Three-dimensional AND flash memory device and manufacturing method thereof

Abstract

The present disclosure provides a three-dimensional AND flash memory device, comprising: a stacked structure disposed on a dielectric substrate, wherein the stacked structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked; a plurality of spacers that separate the stacked structure into a plurality of sub-blocks, wherein the plurality of spacers include: a plurality of stacked walls comprising a plurality of spacer layers and the plurality of insulating layers alternately stacked, wherein the plurality of spacer layers are buried in the plurality of gate layers; a plurality of spacer slits that alternate with the plurality of stacked walls, wherein each spacer slit extends through the stacked structure; a plurality of channel pillars extending through the stacked structure of each sub-block; a plurality of source pillars and a plurality of drain pillars disposed within the plurality of channel pillars; and a plurality of charge storage structures disposed between the plurality of gate layers and the channel pillars.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a three-dimensional AND flash memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory has the advantage of ensuring that stored data persists even after a power outage, and is therefore widely used in personal computers and other electronic devices. Currently, the most commonly used three-dimensional memories include NOR memory and NAND memory. Another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays, offering high integration and area efficiency, as well as fast operation speeds. Therefore, the development of three-dimensional memory devices has become a trend.

[0003] Public content

[0004] The present disclosure provides a three-dimensional AND flash memory device and a manufacturing method thereof, which can reduce the tilting or collapse of the stacked structure.

[0005] One embodiment of the present disclosure provides a three-dimensional AND flash memory device, comprising: a stacked structure disposed on a dielectric substrate, wherein the stacked structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked; a plurality of spacers that separate the stacked structure into a plurality of sub-blocks, the plurality of spacers comprising: a plurality of stacked walls comprising a plurality of spacer layers and the plurality of insulating layers alternately stacked, wherein the plurality of spacer layers are buried in the plurality of gate layers; a plurality of spacer slits that alternate with the plurality of stacked walls, wherein each spacer slit extends through the plurality of gate layers and the plurality of insulating layers of the stacked structure; a plurality of channel pillars extending through the stacked structure of each sub-block; a plurality of source pillars and a plurality of drain pillars disposed within and electrically connected to the plurality of channel pillars; and a plurality of charge storage structures disposed between the plurality of gate layers and the channel pillars.

[0006] One embodiment of the present disclosure provides a three-dimensional AND flash memory device, comprising: forming a stacked structure on a dielectric substrate, wherein the stacked structure includes a plurality of interlayers and a plurality of insulating layers alternately stacked; forming a plurality of channel pillars extending through the stacked structure; forming a plurality of source pillars and a plurality of drain pillars electrically connected to the plurality of channel pillars within the plurality of channel pillars; patterning the stacked structure to form a plurality of separation channels in the stacked structure, each separation channel extending through the plurality of interlayers and the plurality of insulating layers of the stacked structure; and partially removing the plurality of interlayers to form a plurality of horizontal openings, wherein The unremoved portions of the multiple intermediate layers form multiple separation layers, the multiple separation layers and the multiple insulating layers form multiple stacked walls, the multiple separation channels and the multiple stacked walls alternate with each other and separate the stacked structure into multiple sub-blocks; multiple gate layers are formed in the multiple horizontal openings, wherein each separation layer is sandwiched between the multiple gate layers; multiple charge storage structures are formed, located between the multiple gate layers and the channel pillars; and multiple separation slits are formed in the multiple separation channels, wherein the multiple separation slits and the multiple stacked walls alternate with each other and separate the stacked structure into multiple sub-blocks.

[0007] Based on the above, in the embodiment of the present disclosure, the middle layer is left as a separator, which can reduce the number of separation channels, thereby avoiding the collapse of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments is shown.

[0009] Figure 1B A top view of a 3D AND flash memory array is shown in accordance with some embodiments.

[0010] Figure 1C Show Figure 1B A partial 3D view of a simplified portion of the storage array.

[0011] Figure 1D Show Figure 1C Cross-sectional view of the tangent line I-I'.

[0012] Figure 1E Show Figure 1C 、 Figure 1D Top view of the tangent line II-II'.

[0013] Figures 2A to 2G is a schematic cross-sectional view of a three-dimensional AND flash memory device according to an embodiment of the present disclosure. Figures 2C to 2G for Figures 3A to 3E Sectional view along the line IV-IV'.

[0014] Figures 3A to 3E Show Figures 2C to 2G Top view of the tangent line III-III'.

[0015] Figure 4 A top view of a partition of a three-dimensional AND flash memory element is shown.

[0016] Figure 5 A perspective view of a three-dimensional AND flash memory device is shown.

[0017] Description of Reference Numerals

[0018] 10. A (i) 、A (i+1) : Storage Array

[0019] 12: Charge storage layer

[0020] 14, 114: Tunneling layer

[0021] 15, 56, 156: Separation layer

[0022] 16, 116: Channel column

[0023] 20: Storage unit

[0024] 24, 124: Insulation filling layer

[0025] 28, 128: Insulation column

[0026] 32a: Source column / conductor column

[0027] 32b: Drain column / conductor column

[0028] 36, 136: barrier layer

[0029] 38, 138: Gate layer / word line

[0030] 40, 140: Charge storage structure

[0031] 50, 100: dielectric substrate

[0032] 52, 150: Gate stack structure

[0033] 54, 101, 104: Insulation layer

[0034] 60: Arrow

[0035] 102: Stop layer

[0036] 103: Conductor layer

[0037] 106, 106a: Middle layer

[0038] 108: Opening

[0039] 112: Storage layer

[0040] 118: Virtual Column

[0041] 130a, 130b: hole

[0042] 132a, 132b: Conductor columns

[0043] 133: Separation channel

[0044] 133I, 156I: Interface

[0045] 134: Horizontal opening

[0046] 137: Barrier layer

[0047] AR: Array Area

[0048] B、B1、B2、BLOCK、BLOCK (i) 、BLOCK (i+1) :Sub-block

[0049] BL n BL n+1 : Bit line

[0050] C1: Contact window

[0051] D1, D2: distance

[0052] SP (i) n 、SP (i ) n+1 、SP (i+1) n 、SP (i+1) n+1 :Source column

[0053] DP (i) n , DP i) n+1 , DP i+1) n , DP (i+1 ) n+1 :Source column

[0054] H1, H2: height

[0055] X, Y, Z: direction

[0056] L1, L2: length

[0057] NAND, NOR: D

[0058] SC: ladder structure

[0059] SEP: Separator

[0060] SK2, SK2, SK3: laminated structure

[0061] SLT: Separating Slit

[0062] SR: Step Area

[0063] STW: stacked moisture

[0064] TB: Block

[0065] W1, W2: width

[0066] WL (i) m 、WL (i) m+1 、WL (i+1) m 、WL (i+1) m+1 :Word line

[0067] X, Y, Z: direction

[0068] I-I', II-II', III-III', IV-IV': tangent DETAILED DESCRIPTION

[0069] The gate of a three-dimensional flash memory is formed by performing a gate replacement process on the middle layer in a stacked structure of an insulating layer and an intermediate layer. However, after the middle layer is removed, the stacked structure has poor structural properties and insufficient support, and often tilts or collapses, which leads to misalignment when subsequently forming the global bit line (GBL) contact window, thereby causing the formed contact window to short-circuit with the top gate layer. The disclosed embodiment leaves part of the middle layer as a separation layer, which can form a stacked wall together with the insulating layers above and below it. The stacked wall can serve as a supporting structure together with the channel column to prevent the stacked structure from tilting or collapsing, thereby improving the yield and preventing the contact window from short-circuiting with the top gate layer.

[0070] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments is shown. Figure 1B A top view of a 3D AND flash memory array is shown in accordance with some embodiments. Figure 1C Show Figure 1B A partial 3D view of a simplified portion of the storage array. Figure 1D Show Figure 1C Cross-sectional view of the tangent line I-I'. Figure 1E Show Figure 1C 、 Figure 1D Top view of the tangent line II-II'.

[0071] Figure 1A The vertical AND memory array 10 includes two sub-blocks BLOCK arranged in rows and columns. (i) With BLOCK (i+1) Schematic diagram of the sub-block BLOCK (i) Including storage array A (i) Storage Array A (i) A row (for example, the m+1th row) has a common word line (for example, WL (i) m+1 ) of the AND memory cells 20. Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg Dp (i) n With DP (i) n+1 ), so that the AND memory cell 20 is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.

[0072] Storage array A (i) A row (eg, the nth row) has a common source column (eg, Sp (i) n ) and a common drain column (such as DP (i) n ) of the AND storage unit 20. Each row (eg, the nth row) of AND storage units 20 corresponds to a different word line (eg, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ), so that the AND storage unit 20 is along the common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

[0073] exist Figure 1A In the sub-block BLOCK(i) In the storage array A (1) The AND memory cells 20 in the nth row share a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). The AND storage cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ) and coupled to a common bit line (eg BL n+1 ).

[0074] In some embodiments, the sub-block BLOCK (i+1) Including storage array A (i+1) , which is in the sub-block BLOCK (i) Storage array A in (i) Storage array A (i+1) A row (for example, the m+1th row) has a common word line (for example, WL (i +1) m+1 ) of the AND memory cells 20. Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i+1) m+1 ) and coupled to different source columns (eg Sp (i+1) n With Sp (i+1) n+1 ) and the drain column (eg DP (i+1) n With DP (i+1) n+1 Storage array A (i+1) A row (eg, the nth row) has a common source column (eg, SP (i+1) n) and the common drain column (eg Dp (i+1) n ) of the AND storage unit 20. Each row (eg, the nth row) of AND storage units 20 corresponds to a different word line (eg, WL (i+1) m+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (e.g. DP (i+1) n ), so that the AND storage unit 20 is along the common source column (eg Sp (i+1) n) and a common drain column (such as DP (i+1) n ) are logically configured into one row.

[0075] Sub-block BLOCK (i+1) With sub-block BLOCK (i) Shared source line (eg SL n With SL n+1 ) and bit lines (such as BL n With BL n+1 ). Therefore, the source line SL n and bit line BL n Coupled to sub-block BLOCK (i) The AND memory cell 20 in the nth row of the AND memory array is coupled to the sub-block BLOCK (i+1) Similarly, the source line SL n+1 and bit line BL n+1 Coupled to sub-block BLOCK (i) The AND memory cell 20 in the n+1th row of the AND memory array is coupled to the sub-block BLOCK (i+1) The AND storage unit 20 in the n+1th row in the AND storage array.

[0076] Please refer to Figure 1B , the memory array 10 may include a plurality of separators SEP, which divide the gate stack structure 52 into a plurality of sub-blocks B, such as sub-block B1 and sub-block B2. The separator SEP disclosed in the present invention includes a plurality of stacking walls STW and a plurality of separation slits SLT alternately arranged in the Y direction. The stacking walls STW and the separation slits SLT are made of different insulating materials. The insulating material may include an organic insulating material, an inorganic insulating material, or a combination thereof. The stacking wall STW is a stacked structure formed by stacking a plurality of separation layers 56 and a plurality of insulating layers 54, such as Figure 1D As shown. The materials of the separation layer 56 and the insulating layer 54 are, for example, silicon nitride and silicon oxide. The separation slit SLT is, for example, silicon oxide. Each sub-block B1 and B2 may include a gate stack structure 52 disposed on a dielectric substrate 50, a plurality of channel pillars 16, a plurality of conductive pillars (also referred to as source pillars) 32a and a plurality of conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40, as shown. Figure 1C shown.

[0077] Please refer to Figure 1B and Figure 1CMemory array 10 can be disposed in the back-end of line (BEOL) of a semiconductor die. For example, memory array 10 can be disposed within an interconnect structure of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate. Therefore, dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above a metal interconnect structure on a silicon substrate. Dielectric substrate 50 may include an array region AR and a stepped region SR.

[0078] Please refer to Figure 1B and Figure 1C The gate stack structure 52 is formed on the dielectric substrate 50 in the array region AR and the step region SR. The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 vertically stacked on the surface of the dielectric substrate 50 and a plurality of insulating layers 54. In the Z direction, these gate layers 38 are electrically isolated by the insulating layers 54 disposed between them. The gate layers 38 are electrically isolated from the dielectric substrate 50 (shown in FIG. 1 ). Figure 1D ) extends in a direction parallel to the surface of the gate layer 38 in the step region SR. The gate layer 38 may have a step structure SC (shown in FIG. Figure 1B ), so that the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows C1 for connecting to the gate layers 38 can land at the ends of the gate layers 38, thereby connecting each gate layer 38 to each conductive line.

[0079] Please refer to Figures 1B to 1E The memory array 10 further includes a plurality of channel pillars 16. The channel pillars 16 extend continuously through the gate stack structure 52 of the array region AR. In some embodiments, the channel pillars 16 may have an annular profile when viewed from above. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon.

[0080] Please refer to Figures 1C to 1E The memory array 10 further includes an insulating fill layer 24, insulating pillars 28, a plurality of conductive pillars (also referred to as source pillars) 32a, and a plurality of conductive pillars (also referred to as drain pillars) 32b. The conductive pillars 32a and 32b, as well as the insulating pillars 28, are disposed within the channel pillars 16 and extend in a direction perpendicular to the gate layer 38 (i.e., the Z direction). The conductive pillars 32a and 32b are separated by the insulating fill layer 24 and the insulating pillars 28 and are electrically coupled to the channel pillars 16. The conductive pillars 32a and 32b are, for example, doped polysilicon. The insulating pillars 28 are, for example, silicon nitride.

[0081] Please refer to Figure 1D, the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38. The charge storage structure 40 may include a tunneling layer (or called a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14, the charge storage layer 12, and the blocking layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a portion of the charge storage structure 40 (the tunneling layer 14) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (the charge storage layer 12 and the blocking layer 36) surrounds the gate layer 38, as shown in FIG. Figure 1D shown.

[0082] Please refer to Figure 1E The gate layer 38, the surrounding charge storage structure 40, the channel pillar 16, and the source and drain pillars 32a and 32b define the memory cell 20. The memory cell 20 can be operated in a single-bit or dual-bit manner using various operating methods. For example, when a voltage is applied to the source and drain pillars 32a and 32b, electrons are transferred along the channel pillars 16 and stored in the charge storage structure 40 because the source and drain pillars 32a and 32b are connected to the channel pillar 16, thereby enabling a single-bit operation of the memory cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source and drain pillars 32a and 32b. For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32 a and drain pillars 32 b. This allows the memory cell 20 to operate as a single-level cell (SLG, 1 bit) or a multi-level cell (MLC, greater than or equal to 2 bits).

[0083] When operating, a voltage is applied to the selected word line (gate layer) 38, for example, a voltage higher than the corresponding starting voltage (V th ), the channel region of the channel column 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BLn or BL n+1 (Shown in Figure 1C ) enters the drain column 32b and flows through the conductive channel region to the source column 32a (eg, in the direction indicated by arrow 60), and finally flows to the source line SLn or SL n+1 (Shown in Figure 1C ).

[0084] Please refer to Figure 1B Gate layer 38 is formed by removing the middle layer from the stacked structure of insulating layer 54 and the middle layer through a gate replacement process. In the present disclosure, a portion of the middle layer is left as spacer layer 56. Spacer layer 56 and insulating layer 54 are stacked together to form a stacked wall (STW) between sub-blocks B.

[0085] The separation layer 56 and the separation slit SLT of the stacking wall STW extend continuously in the X-direction. In some embodiments, the separation layer 56 of the stacking wall STW extends continuously in the array region AR and into the step region SR. In other embodiments, the separation layer 56 of the stacking wall STW extends continuously in the array region AR but does not extend into the step region SR. In other words, the length L1 of the separation layer 56 of the stacking wall STW in the X-direction is less than or equal to the length L2 of the separation slit SLT in the X-direction.

[0086] Furthermore, the width W1 of the partition layer 56 of the stacking wall STW in the Y direction is less than or equal to the width W2 of the partition slit SLT in the Y direction. The height H1 of the partition layer 56 of the stacking wall STW in the Z direction is less than or equal to the height H2 of the partition slit SLT in the Z direction. Figure 1D In addition, the partition layer 56 of the stacked wall STW and the partition slit SLT have different profiles. From a top view, the partition layer 56 of the stacked wall STW has a curved profile, while the partition slit SLT is generally rectangular, as shown in FIG. Figure 1B shown.

[0087] In the present disclosure, the remaining separation layer 56 can be used together with the insulating layer 54 as the stacking wall STW between the sub-blocks B. Therefore, the separation layer 56 can serve as a supporting structure to reduce the number of separation channels used to form the separation slits SLT, thereby avoiding the stacking structure from tipping over or collapsing due to the removal of the intermediate layer during the gate replacement process.

[0088] The method of forming the stacked wall STW can refer to Figures 2A to 2G as well as Figures 3A to 3E Detailed description. Figures 2A to 2G is a schematic cross-sectional view of a three-dimensional AND flash memory device according to an embodiment of the present disclosure. Figures 2C to 2G for Figures 3A to 3E Sectional view along the line IV-IV'. Figures 3A to 3E Show Figures 2C to 2G Top view of the tangent line III-III'. Figure 4 A top view of a partition of a three-dimensional AND flash memory element is shown. Figure 5 A perspective view of a three-dimensional AND flash memory device is shown.

[0089] Please refer to Figure 2A , providing a dielectric substrate 100. The dielectric substrate 100 is, for example, a dielectric layer of a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 100 includes an array region AR and a step region SR. A stacked structure SK1 is formed on the dielectric substrate 100 in the array region AR and the step region SR. The stacked structure SK1 can also be called an insulating stacked structure SK1. In this embodiment, the stacked structure SK1 is composed of an insulating layer 104 and an intermediate layer 106 sequentially and alternately stacked on the dielectric substrate 100. In other embodiments, the stacked structure SK1 can be composed of an intermediate layer 106 and an insulating layer 104 sequentially and alternately stacked on the dielectric substrate 100. In addition, in this embodiment, the top layer of the stacked structure SK1 is the insulating layer 104. The insulating layer 104 is, for example, a silicon oxide layer. The intermediate layer 106 is, for example, a silicon nitride layer. The intermediate layer 106 can serve as a sacrificial layer and be partially removed in subsequent processes. In this embodiment, the stacked structure SK1 has 8 insulating layers 104 and 7 intermediate layers 106 , but the present disclosure is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 may be formed according to actual needs.

[0090] In some embodiments, before forming the stacked structure SK1, an insulating layer 101, a stop layer 102, and a conductive layer 103 are first formed on a dielectric substrate 100. Insulating layer 101 is, for example, silicon oxide. Stop layer 102 is formed within insulating layer 101. Stop layer 102 is, for example, a conductive pattern, such as a polysilicon pattern. Conductive layer 103 is, for example, a grounded polysilicon layer. Conductive layer 103 can also be referred to as a dummy gate, which can be used to close leakage paths.

[0091] The stacked structure SK1 is patterned to form a stepped structure SC (eg, Figure 3A and Figure 5 shown).

[0092] Next, please refer to Figure 2B and Figure 3A , a plurality of openings 108 are formed in the stacked structure SK1 of the array region AR. In this embodiment, the openings 108 extend through the conductive layer 103, and their bottom surfaces expose the stop layer 102 and the insulating layer 101, but the present disclosure is not limited thereto. In this embodiment, the openings 108 have a circular outline when viewed from above, but the present disclosure is not limited thereto. In other embodiments, the openings 108 may have outlines of other shapes, such as a polygon (not shown).

[0093] Please refer to Figure 2B and Figure 3A, a tunneling layer 114 and a channel column 116 are formed in the opening 108. The tunneling layer is, for example, a silicon oxide layer. The material of the channel column 116 can be a semiconductor, such as undoped polysilicon. The method of forming the tunneling layer 114 and the channel column 116 is, for example, to form a tunneling material layer and a channel material layer on the stacked structure SKI and in the opening 108. Then, an etch-back process is performed to partially remove the tunneling material layer and the channel material layer to form the tunneling layer 114 and the channel column 116. The tunneling layer 114 and the channel column 116 cover the sidewalls of the opening 108, exposing the bottom of the opening 108. The tunneling layer 114 and the channel column 116 can extend through the stacked structure SK1 and extend into the insulating layer 101. The channel column 116 is, for example, annular in top view and can be continuous in its extension direction (for example, in a direction perpendicular to the dielectric substrate 100). In other words, the channel pillar 116 is integral in its extension direction and is not divided into multiple disconnected portions. In some embodiments, the channel pillar 116 may have a circular profile when viewed from above, but the present disclosure is not limited thereto. In other embodiments, the channel pillar 116 may have other shapes (e.g., polygonal) when viewed from above.

[0094] In this embodiment, the tunneling layer 114 of the charge storage structure 140 is formed within the opening 108, and the storage layer 112 and the blocking layer 136 of the charge storage structure 140 are formed within the horizontal opening 134 during the gate replacement process. Figure 2F shown.

[0095] Please refer to Figure 2B and Figure 3A An insulating fill layer 124 and an insulating pillar 128 are formed in the opening 108. The insulating fill layer 124 is made of, for example, silicon oxide; the insulating pillar 128 is made of, for example, silicon nitride. When the insulating fill layer 124 partially fills the opening 108, a void is left behind. An insulating material different from the insulating fill layer 124 is then added to completely seal the opening 108. The insulating material is then etched back through a dry or wet etching process until the surface of the insulating fill layer 124 is exposed. The insulating material remaining in the center of the opening 108 forms the insulating pillar 128.

[0096] Please refer to Figure 2C and Figure 3A, a patterning process, such as a photolithography and etching process, is performed to form holes 130a and 130b in the insulating filling layer 124. During the etching process, the stop layer 102 can be used as an etching stop layer. Therefore, the formed holes 130a and 130b extend from the stacked structure SK1 until the stop layer 102 is exposed. The outline of the hole pattern defined by the patterning process can be tangent to the outline of the insulating pillar 128. The outline of the hole pattern defined by the patterning process can also exceed the outline of the insulating pillar 128. Since the etching rate of the insulating pillar 128 is lower than the etching rate of the insulating filling layer 124, the insulating pillar 128 is hardly damaged by etching and remains. In addition, in some embodiments, the outline of the hole pattern defined by the patterning process will exceed the outline of the opening 108, so that the holes 130a and 130b expose part of the top insulating layer 104 of the stacked structure SKI.

[0097] Please refer to Figure 3A In some embodiments, dummy pillars 118 are further formed in the step region SR. The dummy pillars 118 can serve as support pillars in the subsequent gate replacement process. The dummy pillars 118 can be formed simultaneously when the tunneling layer 114, the channel pillars 116, the insulating filling layer 124, and the insulating pillars 128 are formed. The dummy pillars 118 can also be formed separately. The number of dummy pillars 118 can be determined as needed. In some embodiments, the dummy pillars 118 in the step region SR are staggered with each other, and the distance D2 between the dummy pillars 118 in the step region SR is greater than or equal to the distance D1 between the channel pillars 116, and its density is lower than the density of the channel pillars 116 in the array region AR.

[0098] Reference Figure 2C and Figure 3A , forming conductor pillars 132a and 132b in the holes 130a and 130b. The conductor pillars 132a and 132b can serve as source pillars and drain pillars, respectively, and are electrically connected to the channel pillar 116, respectively. The conductor pillars 132a and 132b can be formed by forming a conductor layer on the insulating filling layer 124 and in the holes 130a and 130b, and then etching back. The conductor pillars 132a and 132b are, for example, doped polysilicon. The radial dimensions of the conductor pillars 132a and 132b can be the same or different. The line connecting the centers of the conductor pillars 132a and 132b can be at an acute angle to the Y direction (such as Figure 3A or parallel to the Y direction (not shown), ie perpendicular to the subsequently formed separation slit SLT (as shown); Figure 3E In addition, the channel pillars 116 in two adjacent rows may be staggered with each other (as shown in FIG. Figures 3A to 3E shown), or aligned with each other (not shown).

[0099] Afterwards, refer to Figures 2D to 2G as well as Figures 3B to 3E, a replacement process is performed to replace the multi-layer intermediate layer 106 with the multi-layer gate layer 138, etc. First, referring to Figure 2D and Figure 3B The stacked structure SK1 is patterned, such as by photolithography and etching, to form a plurality of separation trenches 133. During the etching process, the conductive layer 103 can be used as an etch stop layer, so that the separation trenches 133 expose the conductive layer 103.

[0100] Reference Figure 3B Separation trenches 133 extend along the X-direction, dividing the stacked structure SK1 of the array region AR and the stepped region SR into a plurality of blocks TB. Each block TB includes a stacked structure SK2, a plurality of channel pillars 116, and components within the plurality of channel pillars 116, such as conductive pillars 132a and 132b, tunneling layer 114, insulating filler layer 124, and insulating pillars 128. The area of ​​the block TB disclosed herein is more than twice that of the subsequently formed sub-block B, resulting in a lower aspect ratio.

[0101] Next, please refer to Figure 2E and Figure 3C An etching process, such as a wet etching process, is performed to remove portions of the multilayer interlayer 106. The etching solution (e.g., hot phosphoric acid) used in the etching process is injected into the separation trenches 133 and then removes the exposed portions of the multilayer interlayer 106. Therefore, the multilayer interlayer 106 closer to the separation trenches 133 is removed first, while the multilayer interlayer 106 farther from the separation trenches 133 is removed more slowly. During the etching process, when the multilayer interlayer 106 between the channel pillars 116 and the separation trenches 133 is removed, the tunneling layer 114, made of different materials from the interlayer 106, serves as an etch stop layer to protect the channel pillars 116. The etching process continues, removing most of the multilayer interlayer 106 through time-controlled machining, to form a stacked structure SK3 with multiple horizontal openings 134. Portions of the interlayer 106a farther from the separation trenches 133 remain, forming the separation layer 156. The remaining separation layer 156 is located between the two horizontal openings 134, as shown in FIG. Figure 2E shown.

[0102] In some embodiments, the density of the dummy columns 118 in the step region SR is low, and therefore, the etching rate is high. The density of the channel columns 116 in the array region AR is high, the flow rate of the etching solution is low, and the etching rate is low, so the multi-layer intermediate layer 106a farthest from the separation channel 133 is left. As a result, the width of the separation layer 156 in the step region SR and the array region AR is different (not shown). In addition, in some embodiments, the separation layer 156 has a curved profile. In addition to being able to control the size of the remaining separation layer 156 by the etching time, the etching rate of the intermediate layer 106 in the step region SR and the array region AR can also be controlled by adjusting the size and density of the dummy columns 118 in the step region SR and the size and density of the channel columns 116 in the array region AR.

[0103] The separation layer 156 and the insulating layer 104 are alternately stacked in the Z direction to form a stacking wall STW. Therefore, the stacking wall STW can serve as a supporting structure together with the channel pillar 116 and the dummy pillar 118 to prevent the stacking structure SK3 from tilting or collapsing. Figure 2E and Figure 3C shown.

[0104] Furthermore, since the multi-layer intermediate layer 106a and the insulating layer 104 can serve together as a stacking wall STW, the block TB is divided into two sub-blocks B (e.g., sub-blocks B1 and B2). It is not necessary to form the separation trenches 133 at the locations of the stacking walls STW. Therefore, the number of separation trenches 133 can be reduced, and the block TB with a larger cross-sectional area and a smaller aspect ratio can be retained. This prevents the sub-block B from tilting or collapsing due to the stacking structure having an excessively small cross-sectional area and an excessively large aspect ratio. Figure 4 and Figure 5 shown.

[0105] Please refer to Figure 2F and Figure 3D A multi-layer storage layer 112, a multi-layer barrier layer 136, and a gate layer 138 are formed in the plurality of horizontal openings 134. The storage layer 112 is, for example, silicon nitride. The barrier layer 136 is, for example, a high-k material having a dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. The gate layer 138 is, for example, tungsten. In some embodiments, before forming the multi-layer gate layer 138, a barrier layer 137 is further formed. The material of the barrier layer 137 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0106] The method for forming the storage layer 112, the blocking layer 136, the barrier layer 137 and the gate layer 138 is, for example, to sequentially form a storage material layer, a blocking material layer, a barrier material layer and a conductor material layer in the separation channel 133 and the horizontal opening 134, and then perform an etch-back process to remove the storage material layer, the blocking material layer, the barrier material layer and the conductor material layer in the multiple separation channels 133 to form the storage layer 112, the blocking layer 136, the barrier layer 137 and the gate layer 138 in the multiple horizontal openings 134. The blocking layer 136, the tunneling layer 114 and the storage layer 112 are collectively referred to as the charge storage structure 140. At this point, a gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes multiple gate layers 138 and multiple insulating layers 104 that are alternately stacked. A separation layer 156 is buried in the gate layer 138. Both sides of the separation layer 156 are adjacent to the gate layer 138, as shown in FIG. Figure 2F shown.

[0107] Please refer to Figure 2G and Figure 3E , forming a separation slit SLT in the separation trench 133. The method for forming the separation slit SLT includes filling an insulating material on the gate stack structure 150 and in the separation trench 133, and then removing excess insulating material on the gate stack structure 150 through an etch-back process or a planarization process. The insulating material is, for example, silicon oxide. The separation slit SLT contacts the adjacent storage layer 112, gate layer 138, and insulating layer 104 and has an interface 133I. The separation layer 156 in the stacked wall STW contacts the adjacent storage layer 112 and has an interface 156I; and the insulating layer 104 above and below the stacked wall STW extends continuously to below the storage layer 112. That is, the interface 133I extends continuously in the Z direction; while the interface 156I extends discontinuously in the Z direction. Multiple stacked walls STW and multiple separation slits SLT arranged alternately in the Y direction divide the gate stack structure 150 into multiple sub-blocks B. The plurality of stacked walls STW and the plurality of separation slits SLT together form a spacer SEP. The length of the separation layer 156 in the step region SR is less than or equal to the length of the separation slits SLT in the step region SR. Figure 5 shown.

[0108] Please refer to Figure 3E Then, a contact window C1 is formed in the stepped region SR. The contact window C1 lands at the end of the gate layer 138 in the stepped region SR and is electrically connected thereto.

[0109] The above embodiments are described using 3D NAND flash memory. However, the present disclosure is not limited thereto and can also be applied to 3D NOR flash memory or 3D NAND flash memory.

[0110] In the embodiment of the present disclosure, when performing the gate replacement process, part of the intermediate layer is left as a separation layer. Therefore, it can be integrated with the existing process without adding process steps, and the process variation can be effectively controlled by the etching process. Furthermore, these separation layers can form a stacked wall together with the insulating layer. The stacked wall can serve as a supporting structure together with the channel column to prevent the stacked structure from tilting or collapsing, thereby improving the yield rate, and preventing the subsequent formation of the bit line (GBL) contact window due to the tilt of the stacked structure. The misalignment, which causes the formed contact window to short-circuit with the top gate layer.

Claims

1. A three-dimensional AND flash memory device, comprising: A stacked structure located on a dielectric substrate, wherein the stacked structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked with each other; A plurality of separators, for separating the stacked structure into a plurality of sub-blocks, wherein the plurality of separators include: a plurality of stacked walls, comprising a plurality of spacer layers and the plurality of insulating layers alternately stacked with each other, wherein the plurality of spacer layers are buried in the plurality of gate layers; a plurality of separation slits alternating with the plurality of stacked walls, wherein each separation slit extends through the plurality of gate layers and the plurality of insulating layers of the stacked structure; a plurality of channel pillars extending through the stacked structure of each sub-block; a plurality of source columns and a plurality of drain columns, located in the plurality of channel columns and electrically connected to the plurality of channel columns; and A plurality of charge storage structures are located between the plurality of gate layers and the channel pillars. 2 . The three-dimensional AND flash memory device according to claim 1 , wherein each of the spacer layers has a curved profile.

3. The three-dimensional AND flash memory device according to claim 1, wherein a length of each of the separation layers is less than or equal to a length of each of the separation slits; and a width of each of the separation layers is less than or equal to a width of each of the separation slits. 4 . The three-dimensional AND flash memory device according to claim 1 , wherein a material of the plurality of separation layers is different from a material of the separation slits. 5 . The three-dimensional AND flash memory device according to claim 1 , wherein both sides of each of the spacer layers are adjacent to the plurality of gate layers. 6 . The three-dimensional AND flash memory device according to claim 1 , wherein each sidewall of the plurality of spacer layers is in contact with the charge storage structure.

7. A method for manufacturing a three-dimensional AND flash memory device, comprising: forming a stacked structure on a dielectric substrate, wherein the stacked structure comprises a plurality of intermediate layers and a plurality of insulating layers alternately stacked with each other; forming a plurality of channel pillars extending through the stacked structure; forming a plurality of source pillars and a plurality of drain pillars electrically connected to the plurality of channel pillars within the plurality of channel pillars; patterning the stacked structure to form a plurality of separation trenches in the stacked structure, each separation trench extending through the plurality of intermediate layers and the plurality of insulating layers of the stacked structure; Partially removing the plurality of intermediate layers to form a plurality of horizontal openings, wherein the unremoved portions of the plurality of intermediate layers form a plurality of separation layers, the plurality of separation layers and the plurality of insulating layers form a plurality of stacked walls, the plurality of separation trenches and the plurality of stacked walls alternate with each other, and separate the stacked structure into a plurality of sub-blocks; forming a plurality of gate layers in the plurality of horizontal openings, wherein each spacer layer is sandwiched between the plurality of gate layers; forming a plurality of charge storage structures between the plurality of gate layers and the channel pillars; as well as A plurality of separation slits are formed in the plurality of separation trenches, wherein the plurality of separation slits and the plurality of stack walls alternate with each other and separate the stack structure into a plurality of sub-blocks.

8. The method for manufacturing a three-dimensional AND flash memory device according to claim 7, wherein the length of each separation layer is less than or equal to the length of each separation slit; and the width of each separation layer is less than or equal to the width of each separation slit. 9 . The method for manufacturing a three-dimensional AND flash memory device according to claim 7 , wherein a material of the plurality of separation layers is different from a material of the separation slits. 10 . The method for fabricating a three-dimensional AND flash memory device according to claim 7 , wherein a plurality of sidewalls of each of the spacer layers are exposed at the plurality of horizontal openings.

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