Three-dimensional memory devices and methods of manufacturing the same

Abstract

The application discloses a three-dimensional memory device, comprising a substrate, a stack structure arranged on the substrate, and a memory string structure penetrating through the stack structure. The stack structure comprises a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The memory string structure comprises a conductive pillar and a memory layer between the conductive pillar and the stack structure and surrounding the conductive pillar, wherein the memory layer comprises a plurality of first protrusions respectively filled in a plurality of first recesses at the junctions of the conductive layers and the dielectric layers. The application can improve the electrical isolation between memory cells and reduce the signal interference problem between adjacent memory cells during writing or reading.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to a three-dimensional memory device and a method for fabricating the same. Background Technology

[0002] In modern electronic products, memory plays an indispensable and crucial role. Besides storing user data, memory is also responsible for storing the program code executed by the central processing unit (CPU) and information that needs to be temporarily saved during computation. Memory typically consists of a memory array and peripheral circuits for reading, sensing, writing, or programming information from the memory cells. Binary systems have two logical states for their memory cells, representing logic 1 and logic 0. Other memory systems may have memory cells that can have even more logical states.

[0003] Currently, memory types can be categorized into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM), whose data is lost after power is turned off and must be re-entered upon the next power supply. Non-volatile memory includes read-only memory (ROM) and flash memory, whose stored data persists even when power is cut off, allowing direct retrieval of previously stored valid data upon power restoration. To meet the specifications of various advanced electronic products in terms of area efficiency, read / write speed, reliability, power consumption, and manufacturing cost, the field continues to improve the structure and manufacturing methods of memory. Summary of the Invention

[0004] The present invention aims to provide a three-dimensional storage device and a method for manufacturing the same, wherein the storage cells are vertically disposed on a substrate in a series-connected storage string structure, thereby improving the area efficiency of the storage device. Furthermore, by filling the recesses in the via sidewalls of the storage layer to form protrusions on the upper and lower sides of the storage cells, electrical isolation between storage cells can be improved, reducing signal interference between adjacent storage cells during writing or reading.

[0005] One embodiment of the present invention provides a three-dimensional storage device, including a substrate, a stacked structure disposed on the substrate, and a memory string structure penetrating the stacked structure. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers alternately disposed. The memory string structure includes a conductive pillar and a storage layer between the conductive pillar and the stacked structure and surrounding the conductive pillar, wherein the storage layer includes a plurality of first protrusions that respectively fill a plurality of first recesses at the junction of the conductive layer and the dielectric layer.

[0006] Another embodiment of the present invention provides a method for manufacturing a three-dimensional memory device, comprising the following steps: First, a substrate is provided, and a stacked structure is formed on the substrate, comprising a plurality of conductive layers and a plurality of dielectric layers alternately arranged. Next, an etching process is performed to form a via through the stacked structure, and a plurality of first recesses are formed on the sidewall of the via, respectively located at the junctions of the conductive layers and the dielectric layers. Then, a memory layer is formed to cover the sidewall of the stacked structure and fill the first recesses. Subsequently, a conductive pillar is formed to fill the via. Attached Figure Description

[0007] The accompanying drawings provide a more detailed understanding of this embodiment and are incorporated herein as a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 7 This is a schematic diagram of the manufacturing method steps of a three-dimensional storage device according to an embodiment of the present invention, wherein... Figure 3 for Figure 2 A magnified view of a portion of the structure shown. Figure 7 for Figure 6 A magnified view of a portion of the structure shown.

[0009] Figure 8 for Figure 6 A partial perspective view of the three-dimensional storage device shown.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 12 Stacked Structure

[0012] 100 substrate

[0013] 103 Contact Pad

[0014] 110 Padding Layer

[0015] 112 Metal oxide layer

[0016] 114 Silicon oxide layer

[0017] 120 Conductive-Dielectric Layer Pair

[0018] 122 Interface Layer

[0019] 124 conductive layer

[0020] 126 Dielectric layer

[0021] 132 First Depression

[0022] 134 Second Depression

[0023] 140 Storage Layer

[0024] 142 First protrusion

[0025] 144 Second protrusion

[0026] 150 conductive pillars

[0027] 152 Barrier Layer

[0028] 154 Conductive Materials

[0029] 103a surface

[0030] 124a Vertex

[0031] 124b base angle

[0032] D1 Depth

[0033] D2 Depth

[0034] E1 Etching Process

[0035] E2 etching process

[0036] MC storage unit

[0037] MCL String Storage Structure

[0038] OP through hole

[0039] SW sidewall

[0040] T1 thickness

[0041] T2 thickness

[0042] T3 thickness

[0043] T4 thickness

[0044] T5 thickness

[0045] TL tangent

[0046] W1 width

[0047] W2 width

[0048] W3 width

[0049] W4 width

[0050] W5 width Detailed Implementation

[0051] To enable those skilled in the art to further understand this invention, several preferred embodiments are provided below, along with the accompanying drawings, to explain in detail the composition and desired effects of the invention. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or combine features from the following embodiments to complete other embodiments.

[0052] Figures 1 to 7 This is a schematic diagram illustrating the manufacturing steps of a three-dimensional storage device according to an embodiment of the present invention. First, as... Figure 1 As shown, a substrate 100 is provided, a pad layer 110 is then formed on the substrate 100, and a stacked structure 12 including alternating stacked conductive layers 124 and dielectric layers 126 is then formed on the pad layer 110.

[0053] Substrate 100 may include a semiconductor substrate and circuit elements and interconnect structures fabricated on the semiconductor substrate using semiconductor processes. The semiconductor substrate may be a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Circuit elements may include active or passive elements, such as transistors, diodes, resistors, and capacitors, but are not limited thereto. Interconnect structures may include an interlayer dielectric layer and conductive structures disposed within the interlayer dielectric layer, such as metal interconnects, contact plugs, and conductive pads. In some embodiments, such as Figure 1 As shown, the surface of the substrate 100 may be provided with a plurality of contact pads 103 that are separated from each other, for realizing the circuit elements of the substrate 100 and the components subsequently fabricated on the substrate 100 (e.g., Figure 6 Electrical connections between memory string structures (MCLs) are shown. Contact pads 103 may include conductive materials, such as metals like tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but are not limited thereto. According to one embodiment of the present invention, contact pads 103 primarily comprise tungsten (W).

[0054] The liner layer 110 can be composed of a single layer or multiple layers of dielectric material. Suitable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride (HfSiON), aluminum oxide (AlO), zinc oxide (ZrO2), titanium oxide (TiO2), and other metal oxide dielectrics, or combinations of the above materials, but are not limited thereto. According to one embodiment of the present invention, as Figure 1 As shown, the pad layer 110 includes a multilayer structure consisting of a metal oxide layer 112 (e.g., aluminum oxide) and a silicon oxide layer 114, wherein the metal oxide layer 112 is preferably located in the lower layer and covers the surface of the contact pad 103. In other embodiments, the pad layer 110 may be composed of a single layer of metal oxide.

[0055] Each conductive layer 124 in the stacked structure 12, together with the dielectric layer 126 above it, forms a conductive-dielectric layer pair 120. The number of conductive-dielectric layer pairs 120 included in the stacked structure 12 can be adjusted according to design requirements, for example, it may include 5 to 10 conductive-dielectric layer pairs 120, but is not limited thereto. The conductive layer 124 includes conductive materials, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, silicide, and other metallic or non-metallic conductive materials or any combination thereof, but is not limited thereto. According to one embodiment of the present invention, the material of the conductive layer 124 includes tungsten (W). The dielectric layer 126 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or any combination thereof, but is not limited thereto. According to one embodiment of the invention, the material of the dielectric layer 126 includes silicon oxide (SiO2). In some embodiments, the uppermost conductive layer 124 of the stacked structure 12 may have a thicker thickness, for example, see reference... Figure 1 The conductive layers 124 from the topmost to the bottommost layer have thicknesses T5, T4, T3, T2 and T1, respectively, with T5>T4>T3>T2>T1.

[0056] The pad layer 110 and the conductive layer 124 and dielectric layer 126 of the stacked structure 12 are formed by deposition processes, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, or any suitable deposition process. In some embodiments, the formation step of each conductive layer 124 may include first forming an interface layer 122 on the surface of the dielectric layer 126, and then forming the conductive layer 124 thereon using the interface layer 122 as a seed layer. The interface layer 122 can help adjust the microstructure (e.g., crystal state and grain size) of the conductive layer 124 to achieve the desired resistivity. In some embodiments, the interface layer 122 also functions as a diffusion barrier layer to prevent the reactive gases used in the deposition of the conductive layer 124 from diffusing into the dielectric layer 126 and affecting product reliability. The material of the interface layer 122 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), titanium silicon (TiSi), tungsten nitride (WN), tungsten silicide (WSi), tungsten nitride silicide (WSiN), tungsten carbide nitride (WCN), or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the material of the interface layer 122 may include tungsten silicide (WSi).

[0057] Please refer to Figure 2 and Figure 3 Next, an etching process E1, such as plasma etching or reactive ion etching (RIE), is performed on the stacked structure 12 to form a plurality of vias OP, each aligned with the contact pads 103 and penetrating the stacked structure 12. In some embodiments, the bottom of the via OP may penetrate the pad layer 110 and expose the contact pads 103. In other embodiments, the pad layer 110 may serve as an etch stop layer for the etching process E1, causing the bottom of the via OP to stop in the pad layer 110 (e.g., at the metal oxide layer 112) without exposing the contact pads 103, before being further etched using another etching process (e.g., ...). Figure 5 The etching process E2 is used to remove the remaining pad layer 110 at the bottom of the via OP to expose the contact pad 103. The via OP can be roughly circular (see reference). Figure 8 However, this is not the only possibility. In some embodiments, the through-hole OP may have a tapering dimension from top to bottom, such as a gradually decreasing diameter. For example... Figure 2 As shown, the tangent TL is a tangent line that roughly cuts through the portion of the conductive layer 124 exposed by the sidewall SW of the via OP. It may have a slope relative to the surface of the substrate 100, rather than being perpendicular to the surface of the substrate 100. The widths of the portions of the via OP that pass through each conductive layer 124 are W5, W4, W3, W2, and W1 from top to bottom, and W5>W4>W3>W2>W1.

[0058] It is worth noting that the present invention can adjust the etching process E1 or perform a wet etching process after etching process E1 to produce more obvious lateral etching at the junction of different material layers of the sidewall SW of the via OP, thereby forming a plurality of first recesses 132 and second recesses 134 on the sidewall SW. The first recesses 132 are located at the junctions of the conductive layer 124 and the dielectric layer 126, and the second recesses 134 are located between the bottom surface of the conductive layer 124, the dielectric layer 126, and the interface layer 122. In some embodiments, since a portion of the interface layer 122 is more easily removed by lateral etching, the second recesses 134 are deeper into the stacked structure 12 than the first recesses 132. For example Figure 3 As shown, if the tangent TL is used as the reference line for measuring the depth of the depression, the first depression 132 may have a depth D1, and the second depression 134 may have a depth D2, and the depth D2 may be greater than or equal to the depth D1. The apex 124a exposed from the first depression 132 and the bottom apex 124b exposed from the second depression 134 of the conductive layer 124 may each have a rounded profile.

[0059] Please refer to Figure 4 Next, a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, or any suitable deposition process, is performed to form a storage layer 140 conformally covering the surface of the stacked structure 12 and the sidewalls SW and bottom surface of the vias OP, and filling the first recess 132 and the second recess 134. For example... Figure 4 As shown, if the contact pad 103 has been exposed from the bottom of the via OP after etching process E1, the storage layer 140 is in direct contact with the contact pad 103.

[0060] The material of the storage layer 140 is selected according to the type of storage device and may include a single-layer or multi-layer structure. In some embodiments, the storage layer 140 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride (HfSiON), aluminum oxide (AlO), zinc oxide (ZrO2), titanium oxide (TiO2), or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, if the memory uses the storage layer 140 as a charge storage layer to store data, the storage layer 140 may include a high-k dielectric or an ONO composite layer composed of silicon oxide-silicon nitride-silicon oxide. In other embodiments of the present invention, if applied to a phase change memory (PCM), the storage layer 140 may include a phase change material such as a chalcogenide alloy. If applied to resistive RAM (ReRAM), the storage layer 140 may include a variable resistance material such as transition metal oxide (TMD).

[0061] Please refer to Figure 5 Next, an etching process E2 is performed, such as plasma etching or reactive ion etching (RIE), to etch away the storage layer 140 covering the surface of the stacked structure 12 and the bottom of the via OP, exposing the surface 103a of the contact pad 103.

[0062] Please refer to Figure 6 and Figure 7 and Figure 8Next, a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, or any suitable deposition process, is performed to form a barrier layer 152 conformally covering the storage layer 140 and the surface 103a of the contact pad 103 on the sidewall SW of the via OP. Then, a conductive material 154 is formed to fill the via OP. Next, an etching or polishing removal process is performed to remove excess barrier layer 152 and conductive material 154 outside the via OP, thereby obtaining conductive pillars 150 respectively filled within the via OP. The material of the barrier layer 152 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), titanium silicon (TiSi), tungsten nitride (WN), tungsten silicide (WSi), tungsten nitride nitrosilide (WSiN), tungsten carbide nitrocarbon (WCN), or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the material of the barrier layer 152 may include titanium nitride (TiN). The conductive material 154 may include, but is not limited to, metallic or non-metallic conductive materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, silicide, etc. In one embodiment of the invention, the conductive material 154 includes tungsten (W). In other embodiments of the invention, if applied to a NAND flash memory, the conductive post 150 may include a semiconductor material, such as polysilicon.

[0063] Please continue to refer to this. Figure 6 and Figure 7 and Figure 8 At this point in the process, the three-dimensional memory device of the present invention is obtained, which includes a substrate 100, contact pads 103 disposed in the substrate 100 and exposed from the surface of the substrate 100, a stacked structure 12 disposed on the substrate 100 and including a plurality of alternating conductive layers 124 and a plurality of dielectric layers 126, and a memory column (MCL) that vertically penetrates the stacked structure 12 and is in direct contact with the contact pads 103. Figure 6 As shown, the memory string structure MCL includes conductive pillars 150 and a memory layer 140, wherein the memory layer 140 is located between and surrounds the conductive pillars 150 and the stacked structure 12. The memory string structure MCL may have dimensions that taper from top to bottom, and the width of the top (away from the end of substrate 100) is greater than the width of the bottom (near the end of substrate 100). The portion of the memory layer 140 sandwiched between the conductive layer 124 and the conductive pillars 150 (e.g.) Figure 7The portions indicated by the dashed lines are memory cells MC. An electric field can be applied to the memory cells MC by the conductive layer 124 and the conductive pillars 150 to switch the state of the memory cells MC (e.g., switching between charging / discharging states, or switching between high resistance / low resistance states), thereby achieving the purpose of storing data. By forming a first recess 132 and a second recess 134 on the sidewall SW of the via OP, the subsequently formed storage layer 140 fills the first recess 132 and the second recess 134, thereby obtaining a first protrusion 142 and a second protrusion 144 located on the upper and lower sides of the memory cells MC, respectively. In some embodiments, such as... Figure 8 As shown, the memory cell MC, the first protrusion 142, and the second protrusion 144 can each be a closed annular structure surrounding the conductive pillar 150. The first protrusion 142 and the second protrusion 144 can improve the electrical isolation between memory cells MC and reduce signal interference between adjacent memory cells MC during writing or reading. In addition, the present invention rounds the apex 124a and the bottom 124b of the conductive layer 124 by forming the first recess 132 and the second recess 134, so that the apex 124a and the bottom 124b have rounded contours. This allows the conductive layer 124 to generate a more controllable electric field within the memory layer 140, reducing the possibility of damage defects in the memory layer 140, thereby improving the reliability of the device.

[0064] In summary, the three-dimensional storage device of the present invention has its storage cells vertically arranged on a substrate in a series-connected storage string structure, which improves the area efficiency of the storage device. Furthermore, before forming the storage string structure within the via, the present invention creates a recess at the interface between the conductive layer and the dielectric layer exposed on the sidewall of the via, allowing the storage layer to fill the recess and thus forming protrusions between the storage cells. This improves the electrical isolation between storage cells and reduces signal interference between adjacent storage cells during writing or reading.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-dimensional storage device, characterized in that, include: A substrate; A stacked structure is disposed on the substrate, including a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The stacked structure also includes a plurality of interface layers, which are respectively located between the bottom surface of the conductive layers and the dielectric layers. as well as A storage string structure, running through the stacked structure, and comprising: A conductive pillar; as well as A storage layer is located between and around the conductive pillar and the stacked structure, wherein the storage layer includes a plurality of first protrusions and a plurality of second protrusions, the plurality of first protrusions filling a plurality of first recesses at the junction of the conductive layer and the dielectric layer, and the plurality of second protrusions filling a plurality of second recesses between the conductive layer, the dielectric layer and the interface layer, wherein the depth of the second recesses in the interface layer is greater than the depth of the first recesses.

2. The three-dimensional storage device according to claim 1, characterized in that, The conductive layer and the conductive pillars are made of tungsten, the interface layer is made of tungsten silicide, and the dielectric layer is made of silicon oxide.

3. The three-dimensional storage device according to claim 1, characterized in that, Also includes: A contact pad is disposed in the substrate; as well as A padding layer is disposed between the stacked structure and the substrate, wherein the storage string structure passes through the padding layer and is in direct contact with the contact pad.

4. The three-dimensional storage device according to claim 3, characterized in that, The liner layer includes a metal oxide layer.

5. The three-dimensional storage device according to claim 1, characterized in that, The storage layer includes a high dielectric constant dielectric.

6. The three-dimensional storage device according to claim 1, characterized in that, The portion of the conductive layer that contacts the first protrusion includes a rounded profile.

7. The three-dimensional storage device according to claim 1, characterized in that, The top width of the storage string structure is greater than the bottom width.

8. The three-dimensional storage device according to claim 1, characterized in that, Among the multiple conductive layers, the uppermost layer is the thickest.

9. A method for manufacturing a three-dimensional storage device, characterized in that, include: Provide a substrate; A stacked structure is formed on the substrate, including a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The stacked structure also includes a plurality of interface layers, which are respectively located between the bottom surface of the conductive layers and the dielectric layers. An etching process is performed to form a through-hole that penetrates the stacked structure, and a plurality of first recesses and a plurality of second recesses are formed on the sidewall of the through-hole. The plurality of first recesses are located at the junction of the conductive layer and the dielectric layer, respectively, and the plurality of second recesses are located between the conductive layer, the dielectric layer and the interface layer. A storage layer is formed, covering the sidewalls of the stacked structure and filling the first recess. The storage layer includes a plurality of first protrusions and a plurality of second protrusions. The plurality of first protrusions fill the plurality of first recesses respectively, and the plurality of second protrusions fill the plurality of second recesses respectively. The depth of the second recesses in the interface layer is greater than the depth of the first recesses. as well as A conductive pillar is formed to fill the through hole.

10. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, The conductive layer and the conductive pillars comprise tungsten, the interface layer comprises tungsten silicide, and the dielectric layer comprises silicon oxide.

11. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, Before forming the stacked structure, the method further includes: A contact pad is formed and embedded in the substrate; and A liner layer is formed on the substrate and covers the contact pad, wherein the through-holes pass through the liner layer and expose one surface of the contact pad.

12. The method for manufacturing a three-dimensional storage device according to claim 11, characterized in that, The liner layer includes a metal oxide layer.

13. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, The storage layer includes a high dielectric constant dielectric.

14. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, The portion of the conductive layer exposed from the first recess includes a rounded outline.

15. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, The top width of the through hole is greater than the bottom width.

16. The method for manufacturing a three-dimensional storage device according to claim 9, characterized in that, Among the multiple conductive layers, the uppermost layer is the thickest.

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