A method for manufacturing a laser chip and a laser chip

Abstract

The laser chip fabrication method and laser chip disclosed herein include a light-emitting region and an electro-absorption modulation region. The P-InP layer includes a first region, a second region, and a third region, with a second active region located below the third region. The first and second regions are exposed to the implanted ion beam, forming a first and a second electrically isolated region. The third region, protected by a mask, remains conductive, forming a first P-InP body layer. During ion implantation, the first and second metal layers act as masks for the first P-InP body layer, intercepting ion implantation and preventing ions from penetrating deep into the first P-InP body layer, thus maintaining its conductivity. The narrow linewidths of the first and second metal layers reduce the ion implantation width of the first P-InP body layer, resulting in a narrower linewidth first P-InP body layer, which is beneficial for improving the modulation rate and modulation bandwidth of the electro-absorption modulation region.

Description

Technical Field

[0001] This disclosure relates to the field of optical communication technology, and in particular to a method for fabricating a laser chip and the laser chip itself. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] Laser chips are a crucial component of optical modules. One type of laser chip is the EML laser chip. An EML laser chip comprises a Distributed Feedback Laser (DFB) and an Electro Absorption Modulator (EAM). EML laser chips require higher modulation rates and bandwidths to meet the data transmission rate requirements of optical modules. Summary of the Invention

[0004] Some embodiments provide a method for fabricating a laser chip and a laser chip that achieves narrower electrical isolation, thereby improving the modulation rate and modulation bandwidth of the EML laser chip.

[0005] In some embodiments, a method for fabricating a laser chip is provided, comprising:

[0006] A first active region and a grating layer are grown sequentially along the N-InP layer. A second active region is epitaxially grown outside the first active region and the grating layer. The second active region is located on the side of the first active region. The first active region is the active region corresponding to the light-emitting region, and the second active region is the active region corresponding to the electro-absorption modulation region.

[0007] Etching forms a first buried region and a second buried region, and the two sides of the first buried region and the second buried region are respectively covered; the first buried region is the buried region corresponding to the light-emitting region, and the second buried region is the buried region corresponding to the electro-absorption modulation region;

[0008] A P-InP layer is grown upward along the surfaces of the first burial area and the second burial area. The P-InP layer includes a first region, a second region, and a third region. The third region is located between the first region and the second region, and the second active region is located below the third region.

[0009] The surfaces of the first region and the second region are coated with photoresist; and a first metal layer and a second metal layer are sequentially grown along the surface of the photoresist and the surface of the third region.

[0010] The photoresist and the first and second metal layers on the surface of the photoresist are peeled off to expose the first and second regions; the first and second metal layers are retained on the surface of the third region.

[0011] Ion implantation is performed on the P-InP layer, and the first region and the second region are subjected to ion action to generate a first electrically isolated region and a second electrically isolated region, respectively; the third region is not subjected to ion action to generate a first P-InP bulk layer.

[0012] The above technical solution has the following advantages or beneficial effects: The laser chip includes a light-emitting region and an electro-absorption modulation region. A narrower width of the electrical conduction region above the quantum well region of the electro-absorption modulation region is beneficial for improving the modulation rate and modulation bandwidth. When generating the electrically isolated region through ion implantation, using photoresist as a carrier transport region mask results in a large photoresist spreading area, making it impossible to achieve a narrower width for the electrical conduction region above the quantum well region. Therefore, a specific metal layer is used as a mask for the electrical conduction region during ion implantation to obtain a narrower linewidth electrical conduction, thereby improving the modulation rate and modulation bandwidth. Specifically, a first active region and a grating layer are sequentially grown along the N-InP layer. A second active region is epitaxially grown by connecting the first active region and the grating layer, and the second active region is located to the side of the first active region. The first active region is the active region corresponding to the light-emitting region, and the second active region is the active region corresponding to the electro-absorption modulation region. Etching is performed to form a first buried region and a second buried region, and the sides of the first buried region and the second buried region are covered. The first buried region corresponds to the luminescent region, and the second buried region corresponds to the electroabsorption modulation region. Then, a P-InP layer is grown along the surface of the first buried region and the second buried region. The P-InP layer includes a first region, a second region, and a third region, with a second active region located below the third region. The first, second, and third regions then correspond to the P-InP layer of the electroabsorption modulation region. The first and second regions are exposed to the implanted ion beam to form a first electrically isolated region and a second electrically isolated region. The third region, protected by the mask, remains conductive, forming the first P-InP body layer. During ion implantation, the first and second metal layers act as a mask for the first P-InP body layer, intercepting ion implantation and preventing ions from penetrating deep into the first P-InP body layer, thus maintaining the conductivity of the first P-InP body layer. The process of growing the first and second metal layers includes: coating photoresist on the surfaces of the first and second regions, and then sequentially growing the first and second metal layers along the surface of the photoresist and the surface of the third region. Next, the photoresist on the surfaces of the first and second regions is stripped off, and the first and second metal layers above the photoresist are also stripped off, exposing the first and second regions to the implanted ion beam, while the first and second metal layers remain on the surface of the third region. After the growth of the first and second metal layers is complete, ion implantation is performed. Under the action of the ion beam, defects are generated in the internal crystal structure of the first and second regions, reducing conductivity. After ion implantation, the first region transforms into a first electrically isolated region, and the second region transforms into a second electrically isolated region. The surface of the third region is covered by the first and second metal layers, preventing ions from penetrating deep into the interior, thus maintaining the internal crystal structure and preserving the conductivity of this region, forming the first P-InP body layer.The stacked first and second metal layers act as masks for the first P-InP bulk layer, intercepting the ion beam and preventing ion implantation into the first P-InP bulk layer, thus maintaining its electrical conductivity. The narrow linewidths of the first and second metal layers address the issue of excessively wide ion implantation in the first P-InP bulk layer, reducing its width and resulting in a narrower linewidth first P-InP bulk layer. This is beneficial for improving the modulation rate and bandwidth of the electroabsorption modulation region.

[0013] In some embodiments, the preparation method includes:

[0014] The P-InP layer includes a fourth region, a fifth region, and a sixth region, with the sixth region located between the fourth region and the fifth region, and the first active region located below the sixth region;

[0015] The surfaces of the fourth region and the fifth region are coated with photoresist; and a third metal layer and a fourth metal layer are sequentially grown along the surface of the photoresist and the surface of the sixth region.

[0016] The photoresist and the third and fourth metal layers on the surface of the photoresist are peeled off to expose the fourth and fifth regions; the third and fourth metal layers remain on the surface of the sixth region.

[0017] Ion implantation is performed on the P-InP layer, and the fourth and fifth regions are affected by ions to generate the third and fourth electrically isolated regions, respectively; the sixth region is not affected by ions to generate the first P-InP bulk layer.

[0018] The above technical solution has the following advantages or beneficial effects: The P-InP layer includes a fourth region, a fifth region, and a sixth region, with the sixth region located between the fourth and fifth regions. The first active region is located below the sixth region, thus forming a long P-InP layer corresponding to the light-emitting region. The fourth and fifth regions are exposed to the implanted ion beam, forming a third and a fourth electrically isolated region. The sixth region, protected by a mask, maintains conductivity, forming a second P-InP body layer. During ion implantation, the third and fourth metal layers act as masks for the second P-InP body layer, intercepting ion implantation and preventing ions from penetrating deep into the second P-InP body layer, thereby maintaining the conductivity of the second P-InP body layer. The process of growing the third and fourth metal layers includes: coating photoresist on the surfaces of the fourth and fifth regions, and sequentially growing the third and fourth metal layers along the surface of the photoresist and the surface of the sixth region. Then, the photoresist on the surfaces of the fourth and fifth regions is stripped off, along with the third and fourth metal layers above the photoresist. This exposes the fourth and fifth regions to the implanted ion beam, while the third region retains the third and fourth metal layers. Ion implantation is then performed after the third and fourth metal layers have grown. Under the influence of the ion beam, defects are generated in the internal crystal structure of the fourth and fifth regions, reducing conductivity. After ion implantation, the fourth region transforms into a third electrically isolated region, and the fifth region transforms into a fourth electrically isolated region. The surface of the sixth region is covered by the third and fourth metal layers, preventing ions from penetrating deeper and maintaining the internal crystal structure, thus preserving the conductivity of this region and forming the second P-InP body layer. The stacked third and fourth metal layers act as a mask for the second P-InP body layer, intercepting the ion beam and preventing ion implantation into the second P-InP body layer, thereby maintaining the electrical conductivity of the second P-InP body layer. The narrower linewidths of the third and fourth metal layers solve the problem of excessively large ion implantation width in the second P-InP bulk layer, thereby reducing the ion implantation width of the second P-InP bulk layer and obtaining a second P-InP bulk layer with narrower linewidth, which is beneficial to improving the gain characteristics of the light-emitting region.

[0019] In some embodiments, a first active region and a grating layer are grown along the N-InP layer, and a second active region is epitaxially grown along the first active region and the grating layer, including:

[0020] A quantum well layer is grown upward from the N-InP layer, and a grating is photolithographically fabricated on the surface of the quantum well layer.

[0021] The quantum well layer and the grating of a predetermined width are etched away to form a first active region and a grating layer, wherein the first active region is the active region of the light-emitting region;

[0022] A quantum well layer is grown along the first active region and the epitaxial docking of the grating layer to form a second active region, which is the active region of the electroabsorption modulation region.

[0023] The above technical solution has the following advantages or beneficial effects: A quantum well layer is grown upward from an N-InP layer, and a grating is photolithographically fabricated on the surface of the quantum well layer. The epitaxial growth width of the quantum well layer and the grating is the same as the width of the N-InP layer. Then, a certain width of the quantum well layer and the grating are etched away to form the active region of the light-emitting region and the grating layer. The active region of the light-emitting region is defined as the first active region. In the first active region, stimulated emission causes discrete electron-hole pairs to recombine and generate photons, thereby converting injected carriers into photons. The photons are reflected by the resonant cavity or distributed feedback grating to form positive feedback, generating laser light. By changing the current injected into the grating layer, the effective refractive index of the grating layer can be changed, thereby changing the laser resonant lasing wavelength and achieving output of a specific wavelength. The light emitted from the first active region is signal-free light. In order to modulate the light emitted from the first active region, a quantum well layer is grown laterally along the first active region and the grating layer, thereby forming the active region of the electro-absorption modulation region. The active region of the electro-absorption modulation region is defined as the second active region. The second active region is located in the optical field transmission direction of the first active region. A reverse bias voltage and bias current are provided to the second active region. The light emitted from the first active region has parameters such as phase, intensity, and frequency. Under the action of the reverse bias voltage, one of these parameters changes according to the modulation current signal, thus modulating the parameter and achieving intensity modulation, thereby modulating the light emitted from the first active region into an optical signal.

[0024] In some embodiments, etching forms a first buried area and a second buried area, and both sides of the first buried area and the second buried area are respectively covered, including:

[0025] Inclined etching is performed along the length of the current surface to form a first buried region and a second buried region, wherein the first buried region is the buried region corresponding to the light-emitting region and the second buried region is the buried region corresponding to the electroabsorption modulation region.

[0026] A first N-InP inversion layer and a first P-InP inversion layer are grown epitaxially along one side of the first burial area, and a second N-InP inversion layer and a second P-InP inversion layer are grown epitaxially along the other side of the first burial area to cover the first burial area.

[0027] A third N-InP inversion layer and a third P-InP inversion layer are grown along one side of the second burial area, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are grown along the other side of the second burial area to cover the second burial area.

[0028] The above technical solution has the following advantages or beneficial effects: A first buried region and a second buried region are formed by oblique etching along the length direction. The first buried region is the buried region corresponding to the light-emitting region, and the second buried region is the buried region corresponding to the electro-absorption modulation region. A first N-InP inversion layer and a first P-InP inversion layer are epitaxially grown along one side of the first buried region, and a second N-InP inversion layer and a second P-InP inversion layer are epitaxially grown along the other side of the first buried region to cover the first buried region. The first N-InP inversion layer and the first P-InP inversion layer are stacked vertically, and an inversion PN junction region is formed at their interface. The second N-InP inversion layer and the second P-InP inversion layer are also stacked vertically, and an inversion PN junction region is also formed at their interface. The inversion PN junction region exhibits a large resistance, thus providing greater electrical isolation, enhancing the electric field confinement effect of the first active region, and thereby increasing the carrier concentration injected into the first active region. Similarly, a third N-InP inversion layer and a third P-InP inversion layer are epitaxially grown on one side of the second buried region, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are epitaxially grown on the other side of the second buried region to cover the second buried region. An inversion PN junction region is formed at the junction of the third N-InP inversion layer and the third P-InP inversion layer, and an inversion PN junction region is formed at the junction of the fourth N-InP inversion layer and the fourth P-InP inversion layer, which can also increase the carrier concentration injected into the second active region.

[0029] In some embodiments, the preparation method includes:

[0030] Annealing is performed after ion implantation to restore the conductivity of the first and second metal layers during the annealing process.

[0031] The above technical solution has the following advantages or beneficial effects: the first or second metal layer acts as a mask to intercept ions. Due to the bombardment of the ion beam, the first or second metal layer develops a small number of defects, thereby reducing its conductivity. After ion implantation, annealing is performed. During the annealing process, these defects will find new bonding sites under thermal action and restore conductivity, thus not affecting the conductivity characteristics of the first or second metal layer.

[0032] In some embodiments, the distance between one edge of the first P-InP body layer and one edge of the first metal layer in the first electrical isolation region is less than a preset range, and the distance between another edge of the first P-InP body layer and another edge of the first metal layer in the second electrical isolation region is less than a preset range.

[0033] The above technical solution has the following advantages or beneficial effects: the first metal layer and the second metal layer have narrower linewidths. When used as a mask, the edge of the first electrically isolated region facing the first P-InP body layer is closer to one edge of the first metal layer, and the edge of the second electrically isolated region facing the first P-InP body layer is closer to the other edge of the first metal layer. Therefore, the distance between the edge of the first electrically isolated region closest to the first P-InP body layer and the edge of the first metal layer is less than a preset range, and the distance between the other edge of the second electrically isolated region closest to the first P-InP body layer and the other edge of the first metal layer is also less than a preset range. Consequently, the first and second electrically isolated regions are closer to the first P-InP body layer from both sides, thus shortening the width of the first P-InP body layer, which is beneficial for improving the modulation rate and modulation bandwidth of the electro-absorption modulation region.

[0034] In some embodiments, a laser chip is provided, comprising:

[0035] A light-emitting region, configured to emit light without carrying a signal, includes:

[0036] The first active area is located within the first burial area;

[0037] An electroabsorption modulation region, configured to modulate the signal-free light to generate an optical signal, the electroabsorption modulation region comprising:

[0038] N-InP layer;

[0039] The second active region is located above the N-InP layer and is located within the second buried region; the N-InP layer provides N-type carriers to the second active region;

[0040] A first P-InP body layer is located above the second buried region, and the second P-InP body layer provides P-type carriers to the second active region.

[0041] The first electrically isolated region is located on one side of the first P-InP body layer;

[0042] The second electrical isolation region is located on the other side of the first P-InP body layer;

[0043] The first metal layer is located above the first P-InP body layer;

[0044] The second metal layer is located above the first metal layer; the distance between one edge of the first electrical isolation region near the first P-InP body layer and one edge of the first metal layer is less than a preset range, and the distance between the other edge of the second electrical isolation region near the first P-InP body layer and the other edge of the first metal layer is less than a preset range.

[0045] The above technical solution has the following advantages or beneficial effects: The laser chip includes a light-emitting region and an electro-absorption modulation region. The light-emitting region includes a first active region located within a first buried region. Stimulated emission within the first active region causes discrete electron-hole pairs to recombine, generating photons, thereby converting injected carriers into photons. These photons are reflected by a resonant cavity or a distributed feedback grating to form positive feedback, generating laser light. The electro-absorption modulation region includes an N-InP layer, a second active region, a first P-InP bulk layer, a first electrically isolated region, a second electrically isolated region, a first metal layer, and a second metal layer. The N-InP layer provides N-type carriers to the second active region, and the first P-InP bulk layer provides P-type carriers to the second active region. The first and second electrically isolated regions are located on opposite sides of the first P-InP bulk layer. The first and second electrically isolated regions are formed by ion implantation. Under the action of ions, defects are generated in the internal crystal structure of the first and second electrically isolated regions, resulting in higher resistance and reduced conductivity. The first and second electrically isolated regions have high resistance and provide electrical isolation, thus preventing lateral diffusion of charge carriers and increasing the carrier concentration injected into the second active region. A first metal layer and a second metal layer are sequentially disposed on the surface of the first P-InP body layer. During ion implantation, the first and second metal layers act as masks for the first P-InP body layer, intercepting ion implantation and preventing ions from penetrating deep into the first P-InP body layer, thereby maintaining the conductivity of the first P-InP body layer. The first and second metal layers have narrow linewidths. When used as masks, the edge of the first electrically isolated region facing the first P-InP body layer is closer to one edge of the first metal layer, and the edge of the second electrically isolated region facing the first P-InP body layer is closer to the other edge of the first metal layer. Therefore, the distance between the edge of the first electrically isolated region closest to the first P-InP body layer and the edge of the first metal layer is less than a preset range, and the distance between the other edge of the second electrically isolated region and the other edge of the first metal layer is also less than a preset range. Furthermore, the first and second electrically isolated regions are positioned closer to the first P-InP bulk layer from both sides, thereby shortening the width of the first P-InP bulk layer. This is beneficial for improving the modulation rate and bandwidth of the electro-absorption modulation region. The first and second metal layers have narrower linewidths, thus solving the problem of excessively large ion implantation width in the first P-InP bulk layer. Reducing the ion implantation width of the first P-InP bulk layer results in a first P-InP bulk layer with narrower linewidth, which is beneficial for improving the modulation rate and bandwidth of the electro-absorption modulation region.

[0046] In some embodiments, the light-emitting region includes:

[0047] N-InP layer;

[0048] A first active region is located above the N-InP layer and within a first buried region; the first active region is configured to generate photons by recombination of P-type carriers and N-type carriers, and the N-InP layer provides N-type carriers to the first active region;

[0049] A grating layer is located above the first active region, and the grating layer is located within the first buried region;

[0050] The second P-InP body layer is located above the first buried area, and the second P-InP body layer provides P-type carriers to the first active region.

[0051] The third electrical isolation region is located on one side of the second P-InP body layer;

[0052] The fourth electrical isolation region is located on the other side of the second P-InP body layer;

[0053] The third metal layer is located above the second P-InP body layer;

[0054] The fourth metal layer is located above the third metal layer.

[0055] The above technical solution has the following advantages or beneficial effects: The light-emitting region includes an N-InP layer, a first active region, a grating layer, a second P-InP bulk layer, a third electrically isolated region, a fourth electrically isolated region, a third metal layer, and a fourth metal layer. The N-InP layer and the second P-InP bulk layer respectively provide N-type and P-type charge carriers to the first active region. These N-type and P-type charge carriers recombine within the first active region to generate photons. These photons are reflected by the resonant cavity or distributed feedback grating to form positive feedback, generating laser light. By changing the current injected into the grating layer, the effective refractive index of the grating layer can be changed, thereby altering the laser resonant lasing wavelength and achieving output at a specific wavelength. The third and fourth electrically isolated regions are located on opposite sides of the second P-InP bulk layer. These regions are formed through ion implantation. Under the influence of ions, defects are generated in the internal crystal structure of the third and fourth electrically isolated regions, resulting in higher resistance and reduced conductivity. The third and fourth electrically isolated regions have high resistance, providing electrical isolation and preventing lateral carrier diffusion, thus increasing the carrier concentration injected into the first active region. A third and fourth metal layer are sequentially disposed on the surface of the second P-InP bulk layer. During ion implantation, the interior of the second P-InP bulk layer is protected by the masking effect of the third and fourth metal layers, preventing ions from penetrating deep into the second P-InP bulk layer. This maintains the internal crystal structure and preserves the conductivity of the second P-InP bulk layer. The narrow linewidth of the third and fourth metal layers solves the problem of excessively large ion implantation width in the second P-InP bulk layer. Reducing the ion implantation width of the second P-InP bulk layer results in a second P-InP bulk layer with a narrower linewidth, which is beneficial for improving the gain characteristics of the emitting region.

[0056] In some embodiments, a third N-InP inversion layer and a third P-InP inversion layer are epitaxially grown on one side of the second burial area, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are epitaxially grown on the other side of the second burial area to cover the second burial area;

[0057] A first N-InP inversion layer and a first P-InP inversion layer are epitaxially grown on one side of the first burial area, and a second N-InP inversion layer and a second P-InP inversion layer are epitaxially grown on the other side of the first burial area to cover the first burial area.

[0058] The above technical solution has the following advantages or beneficial effects: A first N-InP inversion layer and a first P-InP inversion layer are epitaxially grown along one side of the first buried region, and a second N-InP inversion layer and a second P-InP inversion layer are epitaxially grown along the other side of the first buried region to cover the first buried region. The first N-InP inversion layer and the first P-InP inversion layer are stacked one on top of the other, and an inversion PN junction region is formed at their junction. The second N-InP inversion layer and the second P-InP inversion layer are also stacked one on top of the other, and an inversion PN junction region is also formed at their junction. The inversion PN junction region exhibits a large resistance, thereby exhibiting greater electrical isolation, further enhancing the electric field confinement factor of the P-InP bulk layer, and thus increasing the carrier concentration injected into the first active region. Similarly, a third N-InP inversion layer and a third P-InP inversion layer are epitaxially grown on one side of the second buried region, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are epitaxially grown on the other side of the second buried region to cover the second buried region. An inversion PN junction region is formed at the junction of the third N-InP inversion layer and the third P-InP inversion layer, and an inversion PN junction region is formed at the junction of the fourth N-InP inversion layer and the fourth P-InP inversion layer, which can also increase the carrier concentration injected into the second active region.

[0059] In some embodiments, a first electrical isolation groove is formed on the outward side of the first electrical isolation region, and a second electrical isolation groove is formed on the outward side of the second electrical isolation region.

[0060] The above technical solution has the following advantages or beneficial effects: the first electrically isolated region and the second electrically isolated region can achieve electrical isolation, preventing lateral diffusion of charge carriers. A first electrically isolated groove is formed on the outward side of the first electrically isolated region, and a second electrically isolated groove is formed on the outward side of the second electrically isolated region, which can further increase the electrical isolation effect, allowing charge carriers to concentrate through the first P-InP body layer, increasing the charge carrier concentration injected into the second active region, and improving the modulation rate and modulation bandwidth of the electro-absorption modulation region. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0062] Figure 1 This is a partial architecture diagram of an optical communication system according to some embodiments;

[0063] Figure 2This is a partial structural diagram of a host computer according to some embodiments;

[0064] Figure 3 This is a structural diagram of an optical module according to some embodiments;

[0065] Figure 4 An exploded view of an optical module according to some embodiments;

[0066] Figure 5 This is a structural diagram of a light emitting component according to some embodiments;

[0067] Figure 6 An exploded view of a light emitting component according to some embodiments;

[0068] Figure 7 This is a structural diagram of a laser chip according to some embodiments;

[0069] Figure 8 This is a cross-sectional view of the light-emitting region in a laser chip according to some embodiments;

[0070] Figure 9 This is a cross-sectional view of the electroabsorption modulation region in a laser chip according to some embodiments;

[0071] Figure 10 This is a schematic diagram of a laser chip fabrication method according to some embodiments;

[0072] Figure 11 This is a schematic diagram illustrating the principle of a laser chip fabrication process according to some embodiments. Detailed Implementation

[0073] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0074] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0075] In optical communication technology, to establish information transmission between information processing devices, information is loaded onto light, and the speed of light propagation is used to transmit the information. This light carrying information is called an optical signal. When optical signals are transmitted in optical information transmission equipment, optical power loss can be reduced, enabling long-distance transmission of optical signals. At the same time, the cost of optical information transmission equipment such as optical fibers is lower than that of electrical information transmission equipment such as copper wires. Therefore, optical communication technology can achieve high-speed, long-distance, and low-cost information transmission.

[0076] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can only recognize and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert between optical and electrical signals.

[0077] An optical module enables the conversion between optical signals and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output terminals of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output terminals of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.

[0078] Since multiple information processing devices can transmit information via electrical signals, at least one of these devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the host computer of the optical module. Furthermore, the optical signal input or output terminal of the optical module is called the optical port, and the electrical signal input or output terminal is called the electrical port.

[0079] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 for optical modules, an optical module 200, an optical fiber 101, and a network cable 103. Among them, the optical fiber 101 is an optical information transmission device, and the network cable 103 is an electrical information transmission device.

[0080] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total internal reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.

[0081] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.

[0082] The host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor or control the working status of the optical module 200.

[0083] The host computer 100 includes a housing for accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0084] The host computer 100 also includes an external power interface that can connect to an electrical signal network. In some embodiments, the external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0085] One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000.

[0086] In some embodiments, a first optical signal from a remote information processing device 1000 is transmitted through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to an optical module 200. The optical module 200 converts the first optical signal into a first electrical signal, and transmits the first electrical signal to a host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to a local information processing device 2000.

[0087] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0088] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.

[0089] Figure 2 This is a partial structural diagram of a host computer according to some embodiments. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. For example... Figure 2As shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed in the receiving cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.

[0090] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.

[0091] In some embodiments, an electrical connector is provided inside the cage 106, which is configured to connect to the electrical port of the optical module 200.

[0092] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 106 and then diffused through the heat sink 107.

[0093] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.

[0094] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0095] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which comprises an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the shell forms an opening that serves as both an electrical port and an optical port.

[0096] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0097] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the above-mentioned devices.

[0098] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200. Figure 3 The opening 205 is also located at the end of the optical module 200 (right end). Figure 3 (The left end). Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.

[0099] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0100] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0101] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0102] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 106 of the host computer 100.

[0103] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0104] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.

[0105] In some implementations, the gold fingers 301 are disposed on one side of the surface of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some implementations, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to situations where the number of pins is required.

[0106] In some implementations, the gold fingers of the circuit board extend from the opening 204 and are inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the gold fingers 301 are connected to the electrical connector inside the cage 106. The gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0107] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0108] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0109] In some embodiments, the optical module includes a light emitting component 400. In some embodiments, the optical module includes a light receiving component 500. In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.

[0110] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0111] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0112] In some embodiments, the light emitting component 400 and the light receiving component 500 are both disposed on a rectangular tube. The light emitting component 400 generates and outputs signal light, and the light receiving component 500 receives signal light from outside the optical module. An optical fiber adapter is disposed on the rectangular tube to connect the optical module to an external optical fiber. A lens assembly is typically disposed within the rectangular tube to change the propagation direction of the signal light output by the light emitting component 400 or the signal light input from the external optical fiber. The light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300. Therefore, it is difficult to directly connect the light emitting component 400 and the light receiving component 500 to the circuit board 300. Thus, in this embodiment, the light emitting component 400 and the light receiving component 500 are electrically connected via flexible circuit boards. However, in this embodiment, the assembly structure of the light emitting component 400 and the light receiving component 500 is not limited to... Figure 3 and Figure 4 The structure shown can also be other assembly and combination structures, such as the light emitting component 400 and the light receiving component 500 being arranged on different tubes. This embodiment is just an example. Figure 3 and Figure 4 The structure shown is an example.

[0113] Figure 5 This is a structural diagram of a light-emitting component according to some embodiments. Figure 5 As shown, in some embodiments, the light emitting component 400 includes a socket 490, a cap 480, and other devices disposed within the cap 480 and the socket 490. The cap 480 covers one end of the socket 490, and the socket 490 includes several pins. The pins are used to realize the electrical connection between the flexible circuit board and other electrical devices within the light emitting component 400, thereby realizing the electrical connection between the light emitting component 400 and the circuit board 300. This embodiment is only used as an example. Figure 5 The structure shown is an example.

[0114] Figure 6 This is an exploded view of a light emitting component according to some embodiments. Figure 6As shown, in some embodiments, the light emitting component 400 includes a laser component 410 that generates signal light and the generated signal light passes through the cap 480.

[0115] In some embodiments, the laser component 410 includes a laser chip 900 and a substrate. Circuitry is laid on the upper surface of the substrate, and the laser chip 900 is connected to corresponding circuitry on the substrate via wire bonding. Exemplarily, the laser chip 900 may be an electro-absorption modulated laser (EML) chip, which is monolithically integrated from a DFB laser and an EAM modulator. By using external modulation technology, the EML laser chip avoids the interaction between photons and electrons in the laser during high-speed modulation, reducing the large chirp caused by direct modulation, thereby enabling higher transmission rates.

[0116] Figure 7 This is a schematic diagram of the structure of a laser chip according to some embodiments. Figure 7 As shown, in some embodiments, the laser chip 900 can be an EML laser chip.

[0117] In some embodiments, the laser chip 900 may include a light-emitting region 910. The light-emitting region 910 is configured to emit light that does not carry a signal.

[0118] In some embodiments, the laser chip 900 may include an electro-absorption modulation region 920. The electro-absorption modulation region 920 is configured to modulate the light emitted from the light-emitting region 910 to generate an optical signal.

[0119] In some embodiments, the light-emitting region 910 and the electro-absorption modulation region 920 are arranged along the light field transmission direction.

[0120] Figure 8 This is a cross-sectional structural diagram of the light-emitting region in a laser chip according to some embodiments. For example... Figure 8 As shown, in some embodiments, the laser chip 900 may include a light-emitting region 910.

[0121] In some embodiments, the light-emitting region 910 may include an N-InP layer 911. The N-InP layer 911 is located at the bottom. The N-InP layer 911 is an N-type doped InP layer. The N-InP layer 911 outputs N-type carriers.

[0122] In some embodiments, the light-emitting region 910 may include a first active region 912. The first active region 912 is located above the N-InP layer 911. The first active region 912 is located within a first buried region 910a. The first active region 912 is configured to generate photons by recombination of P-type carriers and N-type carriers. The N-InP layer 911 provides N-type carriers to the first active region 912.

[0123] In some embodiments, the light-emitting region 910 may include a grating layer 913. The grating layer 913 is located above the first active region 912 and within the first buried region 910a.

[0124] In some embodiments, within the first active region 912, stimulated emission causes discrete P-type and N-type carrier pairs to recombine and generate photons, thereby converting injected carriers into photons. These photons are reflected by the resonant cavity or distributed feedback grating to form positive feedback, generating laser light. By changing the current injected into the grating layer 913, the effective refractive index of the grating layer 913 can be changed, thereby altering the laser resonant lasing wavelength and achieving output at a specific wavelength.

[0125] In some embodiments, the light-emitting region 910 may include a second P-InP body layer 914. The second P-InP body layer 914 is located above the first buried region 910a. The second P-InP body layer 914 is a P-type doped InP layer, and the second P-InP body layer 914 is used to provide P-type carriers to the first active region 912. When the width of the second P-InP body layer 914 is narrower, it has a stronger electric field confinement factor, thereby increasing the gain characteristics of the first active region 912.

[0126] In some embodiments, the light-emitting region 910 may include a third electrical isolation region 915. The third electrical isolation region 915 is located on one side of the second P-InP body layer 914.

[0127] In some embodiments, the light-emitting region 910 may include a fourth electrical isolation region 916. The fourth electrical isolation region 916 is located on the other side of the second P-InP body layer 914.

[0128] In some embodiments, the chip fabrication process includes growing a P-InP layer. The P-InP layer includes a light-emitting region 910 and an electro-absorption modulation region 920.

[0129] In some embodiments, the P-InP layer includes a first region, a second region, and a third region. The first region, the second region, and the third region are the P-InP layer corresponding to the electroabsorption modulation region 920. The third region is located between the first region and the second region.

[0130] In some embodiments, the P-InP layer includes a fourth region, a fifth region, and a sixth region. The fourth, fifth, and sixth regions correspond to the P-InP layer of the light-emitting region 910. The sixth region is located between the fourth and fifth regions.

[0131] In some embodiments, the fourth and fifth regions are exposed to the implanted ion beam to form the third electrically isolated region 915 and the fourth electrically isolated region 916, respectively. The sixth region, protected by a mask, remains conductive and forms the second P-InP body layer 914. The second P-InP body layer 914 is located between the third electrically isolated region 915 and the fourth electrically isolated region 916.

[0132] In some embodiments, the third and fourth electrically isolated regions 915 and 916 are subjected to ion interaction, resulting in defects in their internal crystal structures and thus generating a larger resistance. The third and fourth electrically isolated regions 915 and 916 provide electrical isolation, thereby preventing lateral diffusion of charge carriers and increasing the carrier concentration injected into the first active region 912.

[0133] In some embodiments, the light-emitting region 910 may include a third metal layer 9171. The third metal layer 9171 is located above the second P-InP body layer 914.

[0134] In some embodiments, the light-emitting region 910 may include a fourth metal layer 9172. The fourth metal layer 9172 is located above the third metal layer 9171.

[0135] In some embodiments, a third metal layer 9171 and a fourth metal layer 9172 are sequentially grown on the surface of the second P-InP body layer 914. During ion implantation, the third metal layer 9171 and the fourth metal layer 9172 act as masks for the second P-InP body layer 914, protecting the area, intercepting ion implantation, and preventing ions from penetrating deep into the interior of the second P-InP body layer 914, thereby maintaining the conductivity of the second P-InP body layer 914.

[0136] In some embodiments, the third metal layer 9171 serves as the first metal layer and the fourth metal layer 9172 serves as the second metal layer. The two layers are stacked one on top of the other to serve as a mask for the second P-InP body layer 914 during ion implantation, preventing ions from being implanted into the interior of the second P-InP body layer 914, maintaining the internal crystal structure of the second P-InP body layer 914, thereby maintaining its electrical conductivity characteristics, so as to transport P-type charge carriers to the first active region 912.

[0137] In some embodiments, a third metal layer 9171 and a fourth metal layer 9172 stacked on top of each other are selected as the mask for the second P-InP body layer 914 during ion implantation. Compared with selecting photoresist as the mask for the second P-InP body layer 914 during ion implantation, the second P-InP body layer 914 has a narrower linewidth, thereby enhancing the electric field confinement factor of the second P-InP body layer 914, increasing the carrier concentration transported to the first active region 912, and improving the gain characteristics of the first active region 912.

[0138] In some embodiments, the surface of the first burial area 910a is inclined. A first N-InP inversion layer 9181 and a first P-InP inversion layer 9191 are epitaxially grown on one side of the first burial area 910a, and a second N-InP inversion layer 9182 and a second P-InP inversion layer 9192 are epitaxially grown on the other side of the first burial area 910a to cover the first burial area 910a.

[0139] In some embodiments, a first N-InP inversion layer 9181 and a first P-InP inversion layer 9191 are stacked vertically, with an inversion PN junction region formed at their junction. A second N-InP inversion layer 9182 and a second P-InP inversion layer 9192 are also stacked vertically, with an inversion PN junction region also formed at their junction. The inversion PN junction region exhibits a large resistance, thereby providing greater electrical isolation, further preventing lateral diffusion of charge carriers and enhancing the electric field confinement factor of the second P-InP body layer 914.

[0140] In some embodiments, the fourth metal layer 9172 is thicker than the third metal layer 9171 to enhance the masking effect.

[0141] In some embodiments, the third metal layer 9171 contains Ti / Pt / Au metal, and the fourth metal layer 9172 contains Ti / Au. The Ti atoms have a bonding effect, which helps to strengthen the fixed connection between the third metal layer 9171 and the fourth metal layer 9172. The Pt atoms in the third metal layer 9171 prevent the Au atoms in the third metal layer 9171 and the Au atoms in the fourth metal layer 9172 from penetrating into the underlying first active region 912, thereby avoiding electrochemical reactions between the Au atoms and the elements in the first active region 912.

[0142] In some embodiments, the third metal layer 9171 and the fourth metal layer 9172 act as a mask to intercept ions. Due to the bombardment of the ion beam, the third metal layer 9171 and the fourth metal layer 9172 develop a small number of defects, thereby reducing their conductivity. After ion implantation, annealing is performed. During the annealing process, these defects will find new bonding sites under thermal action and restore conductivity, thus not affecting the conductivity characteristics of the third metal layer 9171 and the fourth metal layer 9172.

[0143] Figure 9 This is a cross-sectional structural diagram of the electroabsorption modulation region in a laser chip according to some embodiments. For example... Figure 9 As shown, in some embodiments, the laser chip 900 may include an electroabsorption modulation region 920.

[0144] In some embodiments, the electroabsorption modulation region 920 may include an N-InP layer 921. The N-InP layer 921 is located in the same layer as the N-InP layer 911. The N-InP layer 921 is an N-type doped InP layer. The N-InP layer 921 outputs N-type carriers.

[0145] In some embodiments, the electroabsorption modulation region 920 may include a second active region 922. The second active region 922 is located above the N-InP layer 921. The second active region 922 is located within the second buried region 920a. The second active region 922 is configured to receive both P-type and N-type carriers. The N-InP layer 921 provides the N-type carriers to the second active region 922.

[0146] In some embodiments, the second active region 922 is located on the side of the first active region 912. Exemplarily, the second active region 922 is formed by growing along the lateral outward edge of the first active region 912 and the grating layer 913.

[0147] In some embodiments, the second active region 922 is located in the optical field transmission direction of the first active region 912. A reverse bias voltage and a bias current are provided to the second active region 922. The light emitted by the first active region 912 has parameters such as phase, intensity, and frequency. Under the action of the reverse bias voltage, one of these parameters changes according to the modulation current signal, thereby modulating the parameter and achieving intensity modulation, thus modulating the light emitted by the first active region 912 into an optical signal.

[0148] In some embodiments, the electroabsorption modulation region 920 may include a first P-InP body layer 923. The first P-InP body layer 923 is located above the second buried region 920a and provides P-type carriers to the second active region 922. An N-InP layer 921 provides the N-type carriers to the second active region 922, and the first P-InP body layer 923 provides P-type carriers to the second active region 922, thereby injecting a bias current into the second active region 922 to modulate the light emitted from the first active region 912.

[0149] In some embodiments, when the first P-InP body layer 923 has a narrower width, it is beneficial to improve the modulation rate and modulation bandwidth of the electroabsorption modulation region 920.

[0150] In some embodiments, the electroabsorption modulation region 920 may include a first electrical isolation region 924. The first electrical isolation region 924 is located on one side of the first P-InP body layer 923.

[0151] In some embodiments, the electroabsorption modulation region 920 may include a second electrical isolation region 925. The second electrical isolation region 925 is located on the other side of the first P-InP body layer 923.

[0152] In some embodiments, the chip fabrication process includes growing a P-InP layer. The P-InP layer includes a light-emitting region 910 and an electro-absorption modulation region 920.

[0153] In some embodiments, the P-InP layer includes a first region, a second region, and a third region. The first region, the second region, and the third region are the P-InP layer corresponding to the electroabsorption modulation region 920. The third region is located between the first region and the second region.

[0154] In some embodiments, the first region and the second region are exposed to the implanted ion beam to form a first electrically isolated region 924 and a second electrically isolated region 925, respectively. A third region, protected by a mask, remains conductive and forms a first P-InP body layer 923. The first P-InP body layer 923 is located between the first electrically isolated region 924 and the second electrically isolated region 925.

[0155] In some embodiments, the first electrically isolated region 924 and the second electrically isolated region 925 are subjected to ion interaction, resulting in defects in the internal crystal structure and thus generating a large resistance. The first electrically isolated region 924 and the second electrically isolated region 925 provide electrical isolation, thereby preventing lateral diffusion of charge carriers and increasing the carrier concentration injected into the second active region 922.

[0156] In some embodiments, the electroabsorption modulation region 920 may include a first metal layer 926. The first metal layer 926 is located above the first P-InP body layer 923.

[0157] In some embodiments, the electroabsorption modulation region 920 may include a second metal layer 927. The second metal layer 927 is located above the first metal layer 926.

[0158] In some embodiments, a first metal layer 926 and a second metal layer 927 are sequentially grown on the surface of the first P-InP body layer 923. During ion implantation, the first metal layer 926 and the second metal layer 927 act as masks for the first P-InP body layer 923, protecting the area, intercepting ion implantation, and preventing ions from penetrating deep into the interior of the first P-InP body layer 923, thereby maintaining the conductivity of the first P-InP body layer 923.

[0159] In some embodiments, the first metal layer 926 serves as the first metal layer and the second metal layer 927 serves as the second metal layer. The two layers are stacked one on top of the other to serve as a mask for the first P-InP body layer 923 during ion implantation, preventing ions from being implanted into the interior of the first P-InP body layer 923, maintaining the internal crystal structure of the first P-InP body layer 923, thereby maintaining its electrical conductivity characteristics, so as to transport P-type charge carriers to the second active region 922.

[0160] In some embodiments, a first metal layer 926 and a second metal layer 927 stacked on top of each other are selected as masks for the first P-InP body layer 923 during ion implantation. Compared with photoresist as a mask for the first P-InP body layer 923 during ion implantation, the first P-InP body layer 923 has a narrower linewidth, thereby enhancing the electric field confinement factor of the first P-InP body layer 923, which is beneficial to improving the modulation rate and modulation bandwidth of the electroabsorption modulation region 920.

[0161] In some embodiments, the surface of the second burial area 920a is inclined. A third N-InP inversion layer 9281 and a third P-InP inversion layer 9291 are epitaxially grown on one side of the second burial area 920a, and a fourth N-InP inversion layer 9282 and a fourth P-InP inversion layer 9292 are epitaxially grown on the other side of the second burial area 920a to cover the second burial area 920a.

[0162] In some embodiments, the third N-InP inversion layer 9281 and the third P-InP inversion layer 9291 are stacked vertically, and an inversion PN junction region is formed at their junction. The fourth N-InP inversion layer 9282 and the fourth P-InP inversion layer 9292 are also stacked vertically, and an inversion PN junction region is also formed at their junction. The inversion PN junction region exhibits a large resistance, thereby providing greater electrical isolation, further enhancing the electric field confinement factor of the first P-InP body layer 923, further increasing the carrier concentration transmitted to the second active region 922, and improving the modulation rate and modulation bandwidth of the electro-absorption modulation region 920.

[0163] In some embodiments, the first metal layer 926 serves as the first metal layer and the second metal layer 927 serves as the second metal layer. Both act as a mask for the first P-InP body layer 923 during ion implantation, preventing ions from being implanted into the first P-InP body layer 923 and maintaining its electrical conductivity, thereby allowing P-type carriers to be transported to the second active region 922. The second metal layer 927 has a narrower linewidth, thus solving the problem of excessively large ion implantation width in the first P-InP body layer 923. Reducing the ion implantation width of the first P-InP body layer 923 results in a narrower width, improving the modulation rate and bandwidth of the electroabsorption modulation region 920.

[0164] In some embodiments, the second metal layer 927 is thicker than the first metal layer 926 to enhance the masking effect.

[0165] In some embodiments, the first metal layer 926 contains Ti / Pt / Au metal, and the second metal layer 927 contains Ti / Au. The Ti atoms have a binding effect, which helps to strengthen the fixed connection between the first metal layer 926 and the second metal layer 927. The Pt atoms in the first metal layer 926 prevent the Au atoms in the first metal layer 926 and the Au atoms in the second metal layer 927 from penetrating into the underlying second active region 922, thereby avoiding electrochemical reactions between the Au atoms and the elements in the second active region 922.

[0166] In some embodiments, the first metal layer 926 or the second metal layer 927 acts as a mask to intercept ions. Due to bombardment by the ion beam, the first metal layer 926 or the second metal layer 927 develops a small number of defects, thereby reducing its conductivity. After ion implantation, annealing is performed. During the annealing process, these defects find new bonding sites under thermal action and restore conductivity, thus not affecting the conductivity characteristics of the first metal layer 926 or the second metal layer 927.

[0167] In some embodiments, the first electrically isolated region 924 and the second electrically isolated region 925 can achieve an electrically isolated effect, preventing lateral diffusion of charge carriers. A first electrically isolated trench 920b is formed on the outward side of the first electrically isolated region 924, and a second electrically isolated trench 920c is formed on the outward side of the second electrically isolated region 925, which can further enhance the electrically isolated effect, allowing charge carriers to concentrate through the first P-InP body layer 923, increasing the charge carrier concentration injected into the second active region 922, and improving the modulation rate and modulation bandwidth of the electrically absorbed modulation region 920.

[0168] In some embodiments, the second metal layer 927 and the first metal layer 926 may have the same width. A narrower linewidth in the metal layer helps reduce the linewidth of the first P-InP body layer 923, thereby increasing the modulation rate and modulation bandwidth of the electro-absorption modulation region 920.

[0169] In some embodiments, the first metal layer 926 and the second metal layer 927 have narrower linewidths. When used as a mask, the edge of the first electrical isolation region 924 facing the first P-InP body layer 923 is closer to one edge of the first metal layer 926, and the edge of the second electrical isolation region 925 facing the first P-InP body layer 923 is closer to the other edge of the first metal layer 926. Therefore, the distance between one edge of the first electrical isolation region 924 closest to the first P-InP body layer 923 and one edge of the first metal layer 926 is less than a preset range, and the distance between the other edge of the second electrical isolation region closest to the first P-InP body layer 923 and the other edge of the first metal layer 926 is also less than a preset range. Consequently, the first electrical isolation region 924 and the second electrical isolation region 925 are closer to the first P-InP body layer 923 from both sides, thus shortening the width of the first P-InP body layer 923, which is beneficial for improving the modulation rate and modulation bandwidth of the electro-absorption modulation region. For example, regarding the parameter "preset range", the "preset range" corresponding to using the first metal layer 926 and the second metal layer 927 as the mask of the first P-InP body layer 923 is smaller than the "preset range" corresponding to using photoresist as the mask of the first P-InP body layer 923.

[0170] In some embodiments, when the first metal layer 926 and the second metal layer 927 are used as the mask for the first P-InP body layer 923, the corresponding "preset range" can be 0. That is, the inner sidewall of the first electrical isolation region 924 can be flush with the sidewall of the second metal layer 927, that is, it extends outward along the axis of the sidewall of the second metal layer 927. The inner sidewall of the second electrical isolation region 925 can be flush with the other sidewall of the second metal layer 927, that is, it extends outward along the axis of that sidewall of the second metal layer 927.

[0171] Based on the laser chip provided in the above embodiments, this disclosure provides a method for fabricating a laser chip. Figure 10 This is a schematic diagram of a laser chip fabrication method according to some embodiments. Figure 10 As shown. This disclosure provides a method for fabricating a laser chip, including:

[0172] S110: A first active region and a grating layer are grown along the N-InP layer. A second active region is epitaxially grown outside the first active region and the grating layer. The second active region is located on the side of the first active region. The first active region is the active region corresponding to the light-emitting region, and the second active region is the active region corresponding to the electro-absorption modulation region.

[0173] In some embodiments, an N-InP layer is grown. Here, the N-InP layer includes N-InP layer 911 and N-InP layer 921.

[0174] In some embodiments, a quantum well layer is grown upward along the N-InP layer, and a grating is photolithographically fabricated on the surface of the quantum well layer. The epitaxial growth width of the quantum well layer and the grating is the same as the width of the N-InP layer. Then, the quantum well layer and the grating of a predetermined width are etched away to form a first active region 912 and a grating layer 913. The first active region 912 is the active region of the light-emitting region 910.

[0175] In some embodiments, a quantum well layer is epitaxially grown along the first active region 912 and the grating layer 913 to form a second active region 922. The second active region 922 is the active region of the electroabsorption modulation region 920.

[0176] In some embodiments, within the first active region 912, stimulated emission causes discrete electron-hole pairs to recombine and generate photons, thereby converting injected carriers into photons. These photons are reflected by the resonant cavity or distributed feedback grating to form positive feedback, generating laser light. By changing the current injected into the grating layer 913, the effective refractive index of the grating layer 913 can be altered, thereby changing the laser resonant lasing wavelength and achieving output at a specific wavelength. The light emitted from the first active region 910 is signal-free. To modulate the light emitted from the first active region 910, a quantum well layer is grown laterally epitaxially along the first active region 912 and the grating layer 913, forming the active region of the electroabsorption modulation region 920, i.e., the second active region 922. The second active region 922 is located in the light field propagation direction of the first active region 912. A reverse bias voltage and bias current are provided to the second active region 922, and the light emitted from the first active region 912 has parameters such as phase, intensity, and frequency. Under the action of reverse bias voltage, one of these parameters changes according to the modulated current signal, so that the parameter is modulated and intensity modulation is achieved, thereby modulating the light emitted by the first active region 912 into an optical signal.

[0177] S120: Etching to form a first buried region and a second buried region, and covering both sides of the first buried region and the second buried region; the first buried region is the buried region corresponding to the light-emitting region, and the second buried region is the buried region corresponding to the electro-absorption modulation region.

[0178] In some embodiments, oblique etching is performed along the length direction of the current surface to form a first buried region 910a and a second buried region 920a, respectively. The first buried region 910a is the buried region corresponding to the light-emitting region 910, and the second buried region 920a is the buried region corresponding to the electroabsorption modulation region 920.

[0179] In some embodiments, the surface of the first burial area 910a is inclined. A first N-InP inversion layer 9181 and a first P-InP inversion layer 9191 are epitaxially grown on one side of the first burial area 910a, and a second N-InP inversion layer 9182 and a second P-InP inversion layer 9192 are epitaxially grown on the other side of the first burial area 910a to cover the first burial area 910a.

[0180] In some embodiments, a first N-InP inversion layer 9181 and a first P-InP inversion layer 9191 are stacked vertically, with an inversion PN junction region formed at their junction. A second N-InP inversion layer 9182 and a second P-InP inversion layer 9192 are also stacked vertically, with an inversion PN junction region also formed at their junction. The inversion PN junction region exhibits a large resistance, thereby providing greater electrical isolation, further enhancing the electric field confinement factor of the second P-InP body layer 914, further increasing the carrier concentration transported to the first active region 912, and improving the gain characteristics of the light-emitting region 910.

[0181] In some embodiments, the surface of the second burial area 920a is inclined. A third N-InP inversion layer 9281 and a third P-InP inversion layer 9291 are epitaxially grown on one side of the second burial area 920a, and a fourth N-InP inversion layer 9282 and a fourth P-InP inversion layer 9292 are epitaxially grown on the other side of the second burial area 920a to cover the second burial area 920a.

[0182] In some embodiments, the third N-InP inversion layer 9281 and the third P-InP inversion layer 9291 are stacked vertically, and an inversion PN junction region is formed at their junction. The fourth N-InP inversion layer 9282 and the fourth P-InP inversion layer 9292 are also stacked vertically, and an inversion PN junction region is also formed at their junction. The inversion PN junction region exhibits a large resistance, thereby providing greater electrical isolation, further enhancing the electric field confinement factor of the first P-InP body layer 923, further increasing the carrier concentration transmitted to the second active region 922, and improving the modulation rate and modulation bandwidth of the electro-absorption modulation region 920.

[0183] S130: A P-InP layer is grown upward along the surface of the first burial area and the second burial area. The P-InP layer includes a first region, a second region and a third region. The third region is located between the first region and the second region, and the second active region is located below the third region.

[0184] In some embodiments, a P-InP layer is epitaxially grown upward along the surfaces of the first buried region 910a and the second buried region 920a. Here, the P-InP layer includes the P-InP layer corresponding to the light-emitting region 910 and the electroabsorption modulation region 920.

[0185] In some embodiments, the P-InP layer includes a first region, a second region, and a third region, with the third region located between the first and second regions, and the second active region 922 located below the third region. The first, second, and third regions then correspond to the P-InP layer of the electroabsorption modulation region 920.

[0186] S140: Photoresist is coated on the surfaces of the first region and the second region; and a first metal layer and a second metal layer are grown sequentially along the surface of the photoresist and the surface of the third region.

[0187] In some embodiments, step S140 corresponds to the preparation step in the electroabsorption modulation region.

[0188] In some embodiments, the first and second regions are exposed to the implanted ion beam to form a first electrically isolated region 924 and a second electrically isolated region 925. The third region remains conductive while being protected by a mask, forming a first P-InP body layer 923.

[0189] In some embodiments, when the first metal layer 926 and the second metal layer 927 are grown on the surface of the third region, it is inevitable that the first metal layer 926 and the second metal layer 927 will be grown simultaneously on the surfaces of the first region and the second region. Therefore, before growing the first metal layer 926 and the second metal layer 927, a certain thickness of photoresist is coated on the surfaces of the first region and the second region respectively, in order to prepare for the subsequent stripping of the first metal layer 926 and the second metal layer 927 from the surfaces of the first region and the second region.

[0190] In some embodiments, a first metal layer 926 and a second metal layer 927 are sequentially grown along the photoresist surface and the surface of the third region. The first metal layer 926 and the second metal layer 927 on the photoresist surface are subsequently stripped away, leaving only the first metal layer 926 and the second metal layer 927 on the surface of the third region.

[0191] In some embodiments, the first metal layer 926 and the second metal layer 927 on the surface of the third region serve as masks during ion implantation, intercepting ion implantation and preventing ions from penetrating into the interior of the third region, thereby maintaining the internal crystal structure of the third region and thus maintaining the conductivity of the third region. Since the third region still maintains conductivity, a first P-InP body layer 923 is formed.

[0192] In some instances, a metal pattern for the first metal layer 926 is etched onto the photoresist surface and the surface of the third region using photolithography, thereby growing the first metal layer 926. A metal pattern for the second metal layer 927 is then etched onto the surface of the first metal layer 926 using photolithography, thereby growing the second metal layer 927.

[0193] S150: The photoresist and the first and second metal layers on the surface of the photoresist are peeled off to expose the first and second regions; the first and second metal layers are retained on the surface of the third region.

[0194] In some embodiments, the photoresist and the first and second metal layers on the photoresist surface are peeled off to expose the first and second regions to the implanted ion beam for effective ion implantation. Exemplarily, when the photoresist is peeled off, the first and second metal layers on the photoresist surface are also peeled off together.

[0195] In some embodiments, the first and second metal layers on the surface of the third region are retained as a mask during ion implantation to intercept ion implantation, preventing ions from penetrating deep into the third region, thereby maintaining the internal crystal structure of the third region and thus maintaining the conductivity of the third region.

[0196] S160: Ion implantation is performed on the P-InP layer. The first and second regions are affected by ions, thereby generating the first and second electrically isolated regions, respectively; the third region is not affected by ions, thereby generating the first P-InP bulk layer.

[0197] In some embodiments, the first region and the second region are exposed to the implanted ion beam, and the internal crystal structure generates defects under the action of ions, thereby generating a large resistance, and respectively generating a first electrical isolation region 924 and a second electrical isolation region 925.

[0198] In some embodiments, the surface of the third region is covered by a first metal layer 926 and a first metal layer 926. The first metal layer 926 intercepts ion implantation and prevents ions from penetrating into the interior of the third region, thereby maintaining the internal crystal structure of the third region and maintaining the conductivity of the third region, thereby forming a first P-InP body layer 923.

[0199] In some embodiments, the first metal layer 926 serves as the first metal layer and the second metal layer 927, stacked one on top of the other to act as a mask for the first P-InP body layer 923 during ion implantation, preventing ions from being implanted into the first P-InP body layer 923. The first metal layer 926 and the second metal layer 927 have narrow linewidths, thus solving the problem of excessively large ion implantation width in the first P-InP body layer 923. Reducing the ion implantation width of the first P-InP body layer 923 results in a narrower width, which is beneficial for improving the modulation rate and modulation bandwidth of the electroabsorption modulation region 920.

[0200] In some embodiments, the first metal layer 926 or the second metal layer 927 acts as a mask to intercept ions. The first metal layer 926 or the second metal layer 927 is bombarded by the ion beam, generating a small number of defects that reduce conductivity. After ion implantation, annealing is performed. During annealing, these defects find new bonding sites under thermal action and restore conductivity, thus not affecting the conductivity characteristics of the first metal layer 926 or the second metal layer 927.

[0201] In some embodiments, the first electrically isolated region 924 and the second electrically isolated region 925 can achieve an electrically isolated effect, preventing lateral diffusion of charge carriers. A first electrically isolated trench 920b is formed on the outward side of the first electrically isolated region 924, and a second electrically isolated trench 920c is formed on the outward side of the second electrically isolated region 925, which can further enhance the electrically isolated effect, allowing charge carriers to concentrate through the first P-InP body layer 923, increasing the charge carrier concentration injected into the second active region 922, and improving the modulation rate and modulation bandwidth of the electrically absorbed modulation region 920.

[0202] Figure 11 This is a schematic diagram illustrating the principle of a laser chip fabrication process according to some embodiments. For example... Figure 11 As shown, in some embodiments, the first metal layer 926 or the second metal layer 927 serves as a mask for the first P-InP body layer 923 during ion implantation.

[0203] In some embodiments, the P-InP layer corresponding to the electroabsorption modulation region 920 includes a first region 930, a second region 940, and a third region 950. The first region 930 and the second region 940 are located on opposite sides of the third region 950.

[0204] In some embodiments, the surfaces of the first region 930 and the second region 940 are respectively coated with photoresist of a certain thickness. When the first metal layer and the second metal layer are grown on the surface of the third region 950, it is inevitable that the first metal layer and the second metal layer will be grown simultaneously on the surfaces of the first region 930 and the second region 940. Therefore, before growing the first metal layer and the second metal layer, a certain thickness of photoresist is first coated on the surfaces of the first region 930 and the second region 940 to prepare for subsequent stripping of the first metal layer and the second metal layer from the surfaces of the first region 930 and the second region 940.

[0205] In some embodiments, a first metal layer 926 and a second metal layer 927 are sequentially grown on the photoresist surface and the third region surface.

[0206] In some embodiments, when the photoresist is stripped, the first metal layer 926 and the second metal layer 927 on the photoresist surface are also stripped. The surfaces of the first region 930 and the second region 940 are then exposed to the implanted ion beam. Only the surface of the third region 950 retains the first metal layer 926 and the second metal layer 927 to serve as a mask during ion implantation.

[0207] In some embodiments, ion implantation is performed. When the surfaces of the first region 930 and the second region 940 are exposed, ions penetrate into the interior of the first region 930 and the second region 940, causing defects in the crystal structure inside the first region 930 and the second region 940, resulting in greater resistance, thereby transforming them into the first electrically isolated region 924 and the second electrically isolated region 925, respectively.

[0208] In some embodiments, the surface of the third region 950 is covered with a first metal layer 926 and a second metal layer 927. This prevents ions from being implanted into the interior of the third region 950, and the internal crystal structure of the third region 950 remains unaffected. Consequently, the conductivity of the third region 950 remains unaffected and is converted into a first P-InP body layer 923. The first P-InP body layer 923 is located between the first electrically isolated region 924 and the second electrically isolated region 925.

[0209] In some embodiments, the P-InP layer corresponding to the light-emitting region 910 includes a fourth region, a fifth region, and a sixth region. The fourth region and the fifth region are located on opposite sides of the sixth region.

[0210] In some embodiments, the surfaces of the fourth and fifth regions are each coated with photoresist of a certain thickness. When the third metal layer 9171 and the fourth metal layer 9172 are grown on the surface of the sixth region, the third metal layer 9171 and the fourth metal layer 9172 will inevitably be grown simultaneously on the surfaces of the fourth and fifth regions. Therefore, before growing the third metal layer 9171 and the fourth metal layer 9172, a certain thickness of photoresist is first coated on the surfaces of the fourth and fifth regions to prepare for subsequent stripping of the third metal layer 9171 and the fourth metal layer 9172 from the surfaces of the fourth and fifth regions.

[0211] In some embodiments, a third metal layer 9171 and a fourth metal layer 9172 are sequentially grown on the photoresist surface and the sixth region surface.

[0212] In some embodiments, when the photoresist is stripped, the third metal layer 9171 and the fourth metal layer 9172 on the photoresist surface are also stripped. The surfaces of the fourth and fifth regions are then exposed to the implanted ion beam. Only the surface of the sixth region retains the third metal layer 9171 and the fourth metal layer 9172 to serve as a mask during ion implantation.

[0213] In some embodiments, ion implantation is performed. With the surfaces of the fourth and fifth regions exposed, ions penetrate deep into the interiors of the fourth and fifth regions, creating defects in the crystal structure and generating greater resistance, thus transforming them into the third electrically isolated region 915 and the fourth electrically isolated region 916, respectively.

[0214] In some embodiments, the surface of the sixth region is covered with a third metal layer and a fourth metal layer, so ions cannot be implanted into the interior of the sixth region. The internal crystal structure of the sixth region is unaffected, and thus the conductivity of the sixth region remains unaffected, maintaining its conductivity and thus transforming into the second P-InP body layer 914. The second P-InP body layer 914 is located between the third electrical isolation region 915 and the fourth electrical isolation region 916.

[0215] In some embodiments, the first metal layer 926 and the second metal layer 927 have narrower linewidths. When used as a mask, the edge of the first electrical isolation region 924 facing the first P-InP body layer 923 is closer to one edge of the first metal layer 926, and the edge of the second electrical isolation region 925 facing the first P-InP body layer 923 is closer to the other edge of the first metal layer 926. Therefore, the distance between one edge of the first electrical isolation region 924 closest to the first P-InP body layer 923 and one edge of the first metal layer 926 is less than a preset range, and the distance between the other edge of the second electrical isolation region closest to the first P-InP body layer 923 and the other edge of the first metal layer 926 is also less than a preset range. Consequently, the first electrical isolation region 924 and the second electrical isolation region 925 are closer to the first P-InP body layer 923 from both sides, thus shortening the width of the first P-InP body layer 923, which is beneficial for improving the modulation rate and modulation bandwidth of the electro-absorption modulation region.

[0216] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of fabricating a laser chip, characterized by, The preparation method includes: A first active region and a grating layer are grown sequentially along the N-InP layer. A second active region is epitaxially grown outside the first active region and the grating layer. The second active region is located on the side of the first active region. The first active region is the active region corresponding to the light-emitting region, and the second active region is the active region corresponding to the electro-absorption modulation region. Etching forms a first buried region and a second buried region, and the two sides of the first buried region and the second buried region are respectively covered; the first buried region is the buried region corresponding to the light-emitting region, and the second buried region is the buried region corresponding to the electro-absorption modulation region; A P-InP layer is grown upward along the surfaces of the first and second buried areas. The P-InP layer includes a first region, a second region, and a third region. The third region is located between the first and second regions and is located above the second active region. The surfaces of the first region and the second region are coated with photoresist, and a first metal layer and a second metal layer are sequentially grown along the surface of the photoresist and the surface of the third region. The photoresist and the first and second metal layers on the surface of the photoresist are peeled off to expose the first and second regions; the first and second metal layers are retained on the surface of the third region. Ion implantation is performed on the P-InP layer, and the first region and the second region are subjected to ion action to generate a first electrically isolated region and a second electrically isolated region, respectively; the third region is not subjected to ion action to generate a first P-InP bulk layer.

2. The method for fabricating a laser chip according to claim 1, characterized in that, The preparation method includes: The P-InP layer includes a fourth region, a fifth region, and a sixth region, wherein the sixth region is located between the fourth region and the fifth region, and is located above the first active region; The surfaces of the fourth region and the fifth region are coated with photoresist; and a third metal layer and a fourth metal layer are sequentially grown along the surface of the photoresist and the surface of the sixth region. The photoresist and the third and fourth metal layers on the surface of the photoresist are peeled off to expose the fourth and fifth regions. Ion implantation is performed on the P-InP layer, and the fourth and fifth regions are affected by ions to generate the third and fourth electrically isolated regions, respectively; the sixth region is not affected by ions to generate the first P-InP bulk layer.

3. The method for fabricating a laser chip according to claim 1, characterized in that, A first active region and a grating layer are sequentially grown along the N-InP layer. A second active region is epitaxially grown outside the first active region and the grating layer, including: A quantum well layer is grown upward from the N-InP layer, and a grating is photolithographically fabricated on the surface of the quantum well layer. The quantum well layer and the grating of a predetermined width are etched away to form a first active region and a grating layer, wherein the first active region is the active region of the light-emitting region; A quantum well layer is grown along the first active region and the epitaxial docking of the grating layer to form a second active region, which is the active region of the electroabsorption modulation region.

4. The method for fabricating a laser chip according to claim 1, characterized in that, Etching forms a first burial area and a second burial area, and both sides of the first burial area and the second burial area are respectively covered, including: Inclined etching is performed along the length of the current surface to form a first buried region and a second buried region, wherein the first buried region is the buried region corresponding to the light-emitting region and the second buried region is the buried region corresponding to the electroabsorption modulation region. A first N-InP inversion layer and a first P-InP inversion layer are grown epitaxially along one side of the first burial area, and a second N-InP inversion layer and a second P-InP inversion layer are grown epitaxially along the other side of the first burial area to cover the first burial area. A third N-InP inversion layer and a third P-InP inversion layer are grown along one side of the second burial area, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are grown along the other side of the second burial area to cover the second burial area.

5. The method for fabricating a laser chip according to claim 1, characterized in that, The preparation method further includes: Annealing is performed after ion implantation to restore the conductivity of the first and second metal layers.

6. The method for fabricating a laser chip according to claim 1, characterized in that, In the first electrically isolated region, the distance between one edge of the first P-InP body layer and one edge of the first metal layer is less than a preset range, and in the second electrically isolated region, the distance between the other edge of the first P-InP body layer and the other edge of the first metal layer is less than a preset range.

7. A laser chip, characterized in that, include: A light-emitting region, configured to emit light without carrying a signal, includes: The first active zone is located within the first burial zone; An electroabsorption modulation region, configured to modulate the signal-free light to generate an optical signal, the electroabsorption modulation region comprising: N-InP layer; The second active region is located above the N-InP layer and is located within the second buried region; the N-InP layer provides N-type carriers to the second active region; A first P-InP body layer is located above the second buried region, and the first P-InP body layer provides P-type carriers to the second active region. The first electrically isolated region is located on one side of the first P-InP body layer; The second electrical isolation region is located on the other side of the first P-InP body layer; The first metal layer is located above the first P-InP body layer; The second metal layer is located above the first metal layer; the distance between one edge of the first electrical isolation region near the first P-InP body layer and one edge of the first metal layer is less than a preset range, and the distance between the other edge of the second electrical isolation region near the first P-InP body layer and the other edge of the first metal layer is less than a preset range.

8. The laser chip according to claim 7, characterized in that, The light-emitting area includes: N-InP layer; A first active region is located above the N-InP layer and within a first buried region; the first active region is configured to generate photons by recombination of P-type carriers and N-type carriers, and the N-InP layer provides N-type carriers to the first active region; A grating layer is located above the first active region, and the grating layer is located within the first buried region; The second P-InP body layer is located above the first buried area, and the second P-InP body layer provides P-type carriers to the first active region. The third electrical isolation region is located on one side of the second P-InP body layer; The fourth electrical isolation region is located on the other side of the second P-InP body layer; The third metal layer is located above the second P-InP body layer; The fourth metal layer is located above the third metal layer.

9. The laser chip according to claim 8, characterized in that, A first N-InP inversion layer and a first P-InP inversion layer are epitaxially grown on one side of the first burial area, and a second N-InP inversion layer and a second P-InP inversion layer are epitaxially grown on the other side of the first burial area to cover the first burial area; A third N-InP inversion layer and a third P-InP inversion layer are epitaxially grown on one side of the second burial area, and a fourth N-InP inversion layer and a fourth P-InP inversion layer are epitaxially grown on the other side of the second burial area to cover the second burial area.

10. The laser chip according to claim 7, characterized in that, A first electrical isolation groove is formed on the outward side of the first electrical isolation region, and a second electrical isolation groove is formed on the outward side of the second electrical isolation region.

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