Sample for atom probe tomography, its preparation method, and chip

Abstract

Embodiments of the present disclosure provide a sample for atom probe tomography, a preparation method thereof, and a chip. The preparation method includes: providing a substrate having an array region and a peripheral region; performing a first semiconductor process in the array region to form a first semiconductor structure, and synchronously performing, in the peripheral region, a process of the material for forming the first semiconductor structure in the first semiconductor process to form a stacked material layer in the peripheral region; extracting the material layer and performing processing, retaining the material layer to be measured, and forming a sample. The sample prepared according to the embodiments of the present disclosure has uniform material distribution, reduces the preparation difficulty, simplifies the process, improves the integrity of the sample and the surface finish, and improves the accuracy of the test result.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor detection technologies, and in particular, to a sample for atom probe tomography, a preparation method thereof, and a chip. Background Art

[0002] APT (Atom Probe Tomography) is a technology that provides three-dimensional tomographic images and chemical identification at the atomic scale, and is a commonly used test method for analyzing the element distribution or doping concentration in different semiconductor regions of semiconductor devices.

[0003] In related technologies, when performing APT tests, the APT sample is prepared by using a part to be measured in a semiconductor device. However, due to the relatively complex structure of the part to be measured, such as a capacitor, there may be a hollow structure, and the distribution of each material layer is uneven, which greatly increases the difficulty of preparing the APT sample. The prepared APT sample is incomplete and has a rough surface, reducing the accuracy of the test results.

[0004] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present disclosure, and therefore it may include information related to technologies that are not known to those of ordinary skill in the art. Summary of the Invention

[0005] Embodiments of the present disclosure provide a sample for atom probe tomography, a preparation method thereof, and a chip, which can reduce the difficulty of preparing the APT sample, improve the integrity of the sample and the smoothness of the surface, and thus improve the accuracy of the test results.

[0006] Embodiments of the present disclosure provide a method for preparing a sample for atom probe tomography, including: providing a substrate, the substrate having an array region and a peripheral region; performing a first semiconductor process in the array region to form a first semiconductor structure, synchronously performing in the peripheral region the process of the material for forming the first semiconductor structure in the first semiconductor process, and forming a stacked material layer in the peripheral region; extracting the material layer and performing processing, and retaining the material layer to be measured to form a sample.

[0007] According to some exemplary embodiments of the disclosure, the substrate is a semiconductor substrate, and before performing the first semiconductor process in the array region, it further includes: forming a conical carrier column on the semiconductor substrate in the peripheral region.

[0008] According to some exemplary embodiments of the disclosure, the material of the carrier column is at least one of a semiconductor material and a conductor material.

[0009] According to some exemplary embodiments disclosed, a stacked material layer is formed in the peripheral region, including: conformally forming the material layer to be measured on the surface of the carrier pillar.

[0010] According to some exemplary embodiments disclosed, the method further includes: forming a protective layer in the peripheral region, the protective layer completely covering the material layer to be measured on the carrier pillar; forming a stacked material layer in the peripheral region, further including: continuously synchronously performing the process of forming the material of the first semiconductor structure in the first semiconductor process on the protective layer, and forming a non-test material layer on the protective layer.

[0011] According to some exemplary embodiments disclosed, the method further includes: removing the non-test material layer to expose the protective layer; extracting the material layer and processing it to retain the material layer to be measured, forming a sample, including: cutting a target region in the peripheral region to obtain the semiconductor substrate of the target region and the carrier pillar, the material layer to be measured, and the protective layer located on the semiconductor substrate; removing the protective layer to expose the conical material layer to be measured, forming the sample.

[0012] According to some exemplary embodiments disclosed, the material of the protective layer is at least one of photoresist, silicon oxide, silicon nitride, and silicon oxynitride.

[0013] According to some exemplary embodiments disclosed, extracting the material layer and processing it to retain the material layer to be measured, forming a sample, including: using a focused ion beam to cut the material layer in the target region to form a sample strip including the material layer to be measured; cutting and fixing a part of the sample strip to the base of an atom probe to form a sample to be circumferentially cut; circumferentially cutting the sample to be circumferentially cut to form the conical sample.

[0014] According to some exemplary embodiments disclosed, the bottom of the sample strip has a first metal layer.

[0015] According to some exemplary embodiments disclosed, before extracting the material layer and processing it, it further includes: forming a second metal layer on the surface of the material layer.

[0016] According to some exemplary embodiments disclosed, the material of the second metal layer is at least one of tungsten, platinum, and nickel.

[0017] According to some exemplary embodiments disclosed, after forming the first semiconductor structure in the array region and forming the stacked material layer in the peripheral region, it further includes: synchronously performing a second semiconductor process in the array region and the peripheral region to respectively form a second semiconductor structure on the first semiconductor structure in the array region and the material layer in the peripheral region.

[0018] According to some exemplary embodiments disclosed, the substrate includes: a semiconductor substrate having the array region and the peripheral region; and a third semiconductor structure located in the array region and the peripheral region of the semiconductor substrate.

[0019] Embodiments of the present disclosure also provide a sample for atom probe tomography. The sample is prepared by the method according to any one of the above embodiments, and the sample includes: a layer of material to be measured stacked in sequence.

[0020] According to some exemplary embodiments disclosed, the sample further includes: a semiconductor substrate and a conical support column. The support column is located on the semiconductor substrate, and the layer of material to be measured conformally covers the surface of the support column.

[0021] Embodiments of the present disclosure also provide a chip having a working area and a reserved sample area. Among them, a first semiconductor structure is formed in the working area by a first semiconductor process; the reserved sample area has stacked material layers formed by the process of the material used to form the first semiconductor structure in the first semiconductor process; among them, the stacked material layers include a layer of material to be measured.

[0022] According to some exemplary embodiments disclosed, the reserved sample area further has a conical support column, and at least the layer of material to be measured conformally covers the surface of the support column.

[0023] As can be seen from the above technical solutions, the method for preparing a sample for atom probe tomography according to the embodiments of the present disclosure has at least one of the following advantages and positive effects:

[0024] In the embodiments of the present disclosure, the substrate is divided into an array region and a peripheral region. In the array region, a first semiconductor process is performed to form a first semiconductor structure, and in the peripheral region, the process of the material used to form the first semiconductor structure in the first semiconductor process is synchronously performed to form stacked material layers. Therefore, the material layers in the peripheral region and the corresponding materials of the first semiconductor structure in the array region are formed synchronously. Therefore, they have the same thickness and element distribution, and each material layer in the peripheral region is a flat layer. The multi-layer stacking has a simple structure and there will be no hollow or other complex structures. Therefore, using the material layers in the peripheral region to prepare APT samples simplifies the preparation process and greatly reduces the difficulty. The distribution of each material layer is uniform, improving the integrity and surface finish of the sample and the accuracy of the test results. Description of the Drawings

[0025] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other features and advantages of the present disclosure will become more apparent.

[0026] Figure 1Flow chart of the preparation method of the sample for atom probe tomography shown in some embodiments of the present disclosure;

[0027] Figure 2 Top view of the substrate shown in some embodiments of the present disclosure;

[0028] Figure 3 Is Figure 2 Cross-sectional view along A-A;

[0029] Figure 4 Schematic diagram of forming carrier columns in the peripheral region shown in some embodiments of the present disclosure;

[0030] Figure 5 Schematic diagram of forming a first semiconductor structure in the array region and forming a layer of material to be tested on the carrier columns in the peripheral region shown in some embodiments of the present disclosure;

[0031] Figure 6 Schematic diagram of forming a protective layer on the layer of material to be tested in the peripheral region shown in some embodiments of the present disclosure;

[0032] Figure 7 Schematic diagram of forming a non-test material layer in the array region and the peripheral region shown in some embodiments of the present disclosure;

[0033] Figure 8 Schematic diagram of the target region for removing the non-test material layer shown in some embodiments of the present disclosure;

[0034] Figure 9 Schematic diagram of the sample formed after removing the protective layer shown in some embodiments of the present disclosure;

[0035] Figure 10 Top view of forming a first semiconductor structure in the array region and forming a material layer in the peripheral region shown in some embodiments of the present disclosure;

[0036] Figure 11 Is Figure 10 Cross-sectional view along B-B;

[0037] Figure 12 Schematic diagram of taking a sample strip in the target region shown in some embodiments of the present disclosure;

[0038] Figure 13 Schematic diagram of fixing the sample strip to the base of the atom probe shown in some embodiments of the present disclosure;

[0039] Figure 14 Schematic diagram of the prepared sample to be circumcised shown in some embodiments of the present disclosure;

[0040] Figure 15 Schematic diagram of forming a conical sample shown in some embodiments of the present disclosure.

[0041] Description of Reference Numerals

[0042] 1. Substrate; 101. Array Region; 102. Peripheral Region; 2. First Semiconductor Structure; 20. Capacitor; 201. Lower Electrode Layer; 202. Dielectric Layer; 203. Upper Electrode Layer; 3. Layer of Material to be Measured; 4. Carrier Post; 5. Protective Layer; 6. Non-Test Material Layer; 7. Sample Strip; 8. Sample to be Cut in a Ring; 9. Sample; 10. Base; 11. First Metal Layer; 12. Tungsten Needle; P. Target Area. Detailed Implementation Modes

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted.

[0044] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure, and in which different exemplary structures capable of implementing various aspects of the present disclosure are shown by way of example. It should be understood that other specific solutions of components, structures, exemplary devices, systems, and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although terms such as "above", "between", "within" etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, for example, according to the directions of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as labels and are not numerical limitations on their objects.

[0045] The flowcharts shown in the accompanying drawings are only illustrative and not necessarily include all the content and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0046] In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0047] Atom Probe Tomography (APT) is a nanoscale material analysis technique that can identify atomic species and visually reconstruct their spatial positions, relatively truly showing the three-dimensional spatial distribution of different elemental atoms in a material, and has become an analytical test method for analyzing the elemental distribution in different semiconductor regions of semiconductor devices.

[0048] APT testing relies on the ionization of individual atoms / atom clusters on the sample surface and subsequent field evaporation. The sample needs to be made in the form of a conical tip with a vertex radius less than 100 nm. When performing 3D (3-Dimensional) APT testing, the sample is connected as the anode to a positive high voltage, making the atoms at the sample tip in a state to be ionized. A pulsed voltage or pulsed laser is superimposed on the sample tip, and the surface atoms will be ionized and evaporated. The mass-to-charge ratio (the ratio of the mass to the charge of the evaporated ions) of the evaporated ions is measured with a time-of-flight mass spectrometer to obtain the mass spectrometry peak of the ion to determine its elemental species. A position-sensitive detector records the two-dimensional coordinates of the flying ions on the surface of the sample tip, and by the layer-by-layer accumulation of the ions in the longitudinal direction, the longitudinal coordinate of the ion is determined, and then the three-dimensional spatial distribution image of different elemental atoms is obtained.

[0049] When preparing APT samples traditionally, the part to be tested is directly taken out from a semiconductor device and processed to form a sample. For example, the part to be tested is a capacitor in a memory cell of a DRAM (Dynamic Random Access Memory). The structure of the capacitor is relatively complex. For example, in a cup-shaped capacitor, there may be a hollow structure in the center of the cup. If a sample is directly taken from this cup-shaped capacitor, the taken sample may also have a hollow structure. When performing circumferential cutting on the sample, due to the existence of the hollow structure, the circumferential cutting will be uneven, resulting in an uneven surface of the finally formed conical sample, and in severe cases, the sample may even break, increasing the difficulty of preparing APT samples. Moreover, there may also be a hollow in the final sample, making the material distribution of the APT sample uneven and reducing the accuracy of the test. In addition, at the same thickness of the sample, there may be multiple material layers in the transverse direction. Still taking the above cup-shaped capacitor as an example, at the same thickness, there may be an upper electrode, a dielectric, and a lower electrode at the same time. There are differences in the evaporation fields between different materials. Metals and semiconductors have different field evaporation voltages, which will seriously affect the accuracy of the atomic probe during testing or even cause the probe to break, resulting in distortion or failure during signal collection and a very low success rate of sample analysis.

[0050] Based on this, the embodiments of the present disclosure provide a method for preparing a sample for atom probe tomography. As Figures 1 to 15 shown, among which, Figure 1 shows a flowchart of the preparation method, Figure 2 andFigure 3 The top view and cross-sectional view of the substrate 1 are respectively shown. Figures 4 to 9 The schematic diagram of the sample preparation process in some embodiments is shown. Figures 10 to 15 The schematic diagram of the sample preparation process in other embodiments is shown.

[0051] As Figure 1 shown, the method for preparing a sample for atom probe tomography according to an embodiment of the present disclosure includes: steps S110 to S130.

[0052] S110: Provide a substrate 1, and the substrate 1 has an array region 101 and a peripheral region 102.

[0053] In some embodiments, as Figure 2 and Figure 3 shown, the substrate 1 may be a semiconductor substrate, and the material of the semiconductor substrate may be silicon, silicon carbide, silicon on insulator, stacked silicon on insulator, stacked silicon germanide on insulator, germanium on insulator, or germanium on insulator, etc. The semiconductor substrate may also be implanted with certain doping particles according to design requirements to change electrical parameters.

[0054] The substrate 1 is divided into an array region 101 and a peripheral region 102, and a semiconductor process is performed on the semiconductor substrate 1 to form a semiconductor structure. After the semiconductor process is completed, cutting is performed, and the semiconductor structure formed in the array region 101 can be used as a semiconductor device. The peripheral region 102 in the embodiment of the present disclosure refers to the region around the array region 101. In the peripheral region 102, the semiconductor process can be performed synchronously with the array region 101, and the semiconductor structure formed in the peripheral region 102 is used to prepare a sample 9 for atom probe tomography (hereinafter referred to as a sample or an APT sample), and the peripheral region 102 can also be called a sample preparation region.

[0055] Step S120: Perform a first semiconductor process in the array region 101 to form a first semiconductor structure 2, and synchronously perform the process of the material for forming the first semiconductor structure 2 in the first semiconductor process in the peripheral region 102 to form a stacked material layer in the peripheral region 102.

[0056] In the embodiment of the present disclosure, the first semiconductor process refers to a semiconductor manufacturing process, and the first semiconductor process may include: deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, etc.; etching processes such as wet etching processes, dry etching processes, etc.; polishing processes such as chemical mechanical polishing; cleaning processes; oxidation processes; doping processes; spin coating processes; planarization processes; lithography processes, etc., that is, the processes required for preparing a semiconductor structure, and no further examples are given here.

[0057] The first semiconductor structure 2 in the embodiments of the present disclosure refers to a semiconductor structure including a part to be measured, which may be a complete semiconductor device. For example, the first semiconductor structure 2 includes a capacitor 20 and a transistor (not shown in the figure). The first semiconductor structure 2 may also be an incomplete semiconductor device. For example, the first semiconductor structure 2 only includes a part of the capacitor 20 or a part of the transistor (not shown in the figure), as long as the first semiconductor structure 2 includes a part capable of preparing an APT sample, and no special limitation is made here.

[0058] In some embodiments, as Figure 4 shown, before performing the first semiconductor process in the array region 101, the method may further include: forming a conical carrier column 4 on the semiconductor substrate in the peripheral region 102.

[0059] In some embodiments, the material of the conical carrier column 4 may be at least one of semiconductor and conductor materials. The carrier column 4 may be a semiconductor doped with metal to improve conductivity. The carrier column 4 may also be a conductor material. For example, the material of the carrier column 4 may be metal, which can improve conductivity while also improving strength and preventing fracture.

[0060] In the embodiments of the present disclosure, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is synchronously performed in the peripheral region 102.

[0061] Taking the semiconductor process of forming the cup-shaped capacitor 20 as an example, a sacrificial layer is deposited and formed on the array region 101 of the substrate 1, a mask layer with a capacitor hole pattern is deposited and formed on the sacrificial layer, the sacrificial layer is etched using the mask layer, and the pattern is transferred to the sacrificial layer to form capacitor holes. A lower electrode layer 201 with a certain thickness is deposited on the inner wall and bottom wall of the capacitor holes, a dielectric layer 202 is deposited and formed on the lower electrode layer 201, and an upper electrode layer 203 is deposited and formed on the dielectric layer 202. As Figure 5 shown, the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203 form the above-mentioned cup-shaped capacitor 20.

[0062] It should be noted that since the semiconductor process of forming the capacitor 20 is well known in the art, the above content only briefly describes the main process steps, and the specific formation process of the capacitor 20 will not be elaborated further.

[0063] If the portion to be tested is a capacitor 20, then while the aforementioned semiconductor process is being performed in the array region 101, only a deposition process may be simultaneously performed in the peripheral region 102. For example, the deposition process may be performed simultaneously to form a sacrificial layer and a mask layer. While the etching process is being performed in the array region 101, the deposition process may be stopped in the peripheral region 102, or a shielding layer may be provided in the peripheral region 102 to prevent the material layers already formed in the peripheral region 102 from being affected. While the array region 101 continues to perform the deposition process to form the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203, the deposition process may be simultaneously performed in the peripheral region 102 to form the material layers of the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203 stacked in a direction perpendicular to the substrate 1. Alternatively, the deposition process may be performed only in the peripheral region 102 to form the stacked material layers of the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203, without the need for performing the deposition process to form the sacrificial layer and the mask layer.

[0064] Based on this, the material layers formed in the peripheral region 102 are stacked flat layers without hollows or other complex structures, such as those that could include multiple different material layers at the same thickness perpendicular to the substrate 1. Furthermore, the material layers in the peripheral region 102 are formed simultaneously with the materials in the array region 101 and are identical to those in the array region 101, ensuring the accuracy of the test results.

[0065] In the embodiment of the present disclosure, forming the stacked material layers in the peripheral area 102 includes: conformally forming the material layer 3 to be tested on the surface of the support pillar 4 .

[0066] The material layer 3 to be tested is conformally formed on the surface of the carrier pillar 4, and a conical sample 9 can be directly formed. If the semiconductor process stops here, that is, the semiconductor process device is completed, the target area in the peripheral area 102 can be directly cut to form the APT sample 9. It should be noted that since the tip of the APT sample 9 is less than 100nm, before the carrier pillar 4 is formed, the size of the carrier pillar 4 can be set according to the thickness of the material layer 3 to be tested to ensure that the total size of the carrier pillar 4 and the material layer 3 to be tested meets the size requirements of the APT sample 9. Compared with directly sampling and processing to form the APT sample 9 in the semiconductor device, the embodiment of the present disclosure does not need to perform circular cutting to prepare the conical shape, the process is simpler, the material layer is uniform, and the test results are more accurate.

[0067] In the embodiment of the present disclosure, if the semiconductor process cannot stop at forming the material layer 3 to be tested, that is, the semiconductor device has not yet been completed or stopping the first semiconductor process at this time to sample the peripheral area 101 is not conducive to the formation of the semiconductor device, then after forming the material layer 3 to be tested, Figure 6 As shown, the preparation method further includes: forming a protective layer 5 in the peripheral area 102 , wherein the protective layer 5 completely covers the material layer 3 to be tested on the support pillar 4 .

[0068] In the embodiments of the present disclosure, the material of the protective layer 5 may be at least one of photoresist, silicon oxide, silicon nitride, and silicon oxynitride layer. As Figure 6 shown, the protective layer 5 fills between each adjacent conical layer of the material to be tested 3 and completely covers the top of the conical shape, so as to completely encapsulate the conical carrier column 4 and the material layer 3 to be tested in the protective layer 5. In this way, the material layer 3 to be tested can be isolated from the outside world. When continuing to perform semiconductor processes, other materials and processes will not contact the material layer 3 to be tested and will not affect the material layer 3 to be tested. In some other embodiments, the protective layer 5 may also be conformally formed on the surface of the material layer 3 to be tested to completely cover the material layer 3 to be tested. In the embodiments of the present disclosure, as long as the protective layer 5 can completely cover the material layer 3 to be tested, no special limitation is made here.

[0069] After forming the protective layer 5, continue to perform the first semiconductor process. Therefore, the stacked material layer formed in the peripheral region 102 further includes: continuing to synchronously perform the process of forming the material of the first semiconductor structure 2 in the first semiconductor process on the protective layer 5, and forming a non-test material layer 6 on the protective layer 5.

[0070] In the embodiments of the present disclosure, as Figure 7 shown, the first semiconductor process can be continued in the array region 101 and the peripheral region 102, and a material layer is continuously deposited and formed on the protective layer 5 in the peripheral region 102. Since the material layer formed at this time does not need to be subjected to APT testing, it is called a non-test material layer 6. Continuing to synchronously perform the process of forming the material of the first semiconductor structure 2 in the first semiconductor process in the array region 101 in the peripheral region 102 is to ensure the continuity of the first semiconductor process in the array region 101 to form a complete semiconductor structure / device.

[0071] Step S130: Extract the material layer and process it, retain the material layer 3 to be tested, and form a sample 9.

[0072] As Figure 8 shown, after the first semiconductor process is completed, the preparation method further includes: removing the non-test material layer to expose the protective layer 5.

[0073] Since the first semiconductor process is completed, for example, a complete structure of the capacitor 20 is formed in the array region. At this time, the required semiconductor structure is formed in the array region 101, and subsequent dicing processing can be performed. For the peripheral region 102 where the sample 9 needs to be extracted, the non-test material layer 6 can be removed by a chemical mechanical polishing process or an etching process to expose the protective layer 5.

[0074] In the embodiments of the present disclosure, S130 further includes: cutting a target area in the peripheral area 102 to obtain a semiconductor substrate of the target area and carrier pillars 4, a material layer to be measured 3, and a protective layer 5 located on the semiconductor substrate. The target area can be understood as a sampling area, and the material layer to be measured 3 of the target area obtained by cutting is used to prepare an APT sample 9.

[0075] In the embodiments of the present disclosure, as Figure 9 shown, S130 further includes: removing the protective layer 5 to expose the conical material layer to be measured 3, thereby forming a sample 9.

[0076] The protective layer 5 can be removed by using an etching process or other chemical methods to expose the material layer to be measured 3. The etching process can be a wet etching process or a dry etching process, and other chemical methods can be to dissolve the protective layer 5 using a specific solvent without damaging the material layer to be measured 3. No matter which process or method is adopted, as long as the protective layer 5 can be removed without damaging the material layer to be measured 3, those skilled in the art can determine how to remove the protective layer 5 according to the material of the material layer to be measured 3 and the material of the protective layer 5, and no special limitation is made here. Additionally, after removing the protective layer 5, the material layer to be measured 3 located on the semiconductor substrate can also be removed, that is, the material layer to be measured 3 located on the semiconductor substrate between multiple cones is removed to ensure that the material layer to be measured 3 is formed into a strict cone shape, making the test more accurate.

[0077] For the sample 9 formed in the above embodiments, since the sample 9 is directly formed on the semiconductor substrate, the sample 9 can be directly placed on the test stage and analyzed by laser-assisted positioning. Therefore, in the above embodiments of the present disclosure, a cone shape can be formed during the execution of the semiconductor process without using a focused ion beam for sampling and then performing a circumferential cut, avoiding by-products generated during focused ion beam sampling and damage to the sample 9 during the circumferential cut process, and there is no need to weld the sample 9 to the silicon pedestal 10 before testing, making the preparation process simpler and greatly improving the sample preparation efficiency. At the same time, in the peripheral area 102, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is synchronously performed, so that the material of the material layer to be measured 3 of the sample 9 is exactly the same as the material corresponding to the first semiconductor structure in the array area 101, ensuring the authenticity of the analysis and test data. And only the process of forming the material in the first semiconductor structure 2 is performed in the peripheral area 102, so that the formed material layer to be measured 3 is stacked layer by layer on the carrier pillars 4, with a more uniform distribution, making the test results more accurate.

[0078] In some other embodiments of the present disclosure, the preparation method includes S110 - S130 in the above embodiments. As Figure 10 and Figure 11As shown, different from the above embodiments, before performing the first semiconductor process on the array region 101, a conical carrier column 4 is not formed on the semiconductor substrate in the peripheral region 102. Instead, when performing the first semiconductor process on the array region 101, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is synchronously performed in the peripheral region 102, and a stacked material layer is formed in the peripheral region 102.

[0079] As Figures 12 to 15 shown, another difference from the above embodiments is that S130 includes: using a focused ion beam to cut the material layer in the target region P to form a sample strip 7 including the material layer 3 to be measured; cutting and fixing a part of the sample strip 7 to the base 10 of the atom probe to form a sample 8 to be circumcised. The sample 8 to be circumcised is circumcised to form a conical sample 9.

[0080] Among them, a focused ion beam (FIB) is to accelerate the ion beam generated by the ion source through an ion gun, and after focusing, it acts on the surface of the sample 9 for cutting or stripping the sample 9. The target region P can be understood as a sampling region, and the material layer obtained by cutting from the target region P is used to prepare the sample strip 7.

[0081] In some embodiments, as Figure 13 shown, the bottom of the sample strip 7 has a first metal layer 11. The first metal layer 11 can be a metal layer formed at the bottom of the material layer 3 to be measured when performing the first semiconductor process. When performing FIB cutting, the cutting reaches the first metal layer 11, so that the bottom of the formed sample 9 is a metal layer. Or, if the bottom of the material layer 3 to be measured is not a metal layer, after performing FIB cutting to form the sample strip 7, the first metal layer 11 can be formed at the bottom of the sample strip 7 by a spraying process. One end of the sample strip 7 is fixed to the base 10 of the atom probe. Since the bottom of the sample strip 7 has the first metal layer 11, the first metal layer 11 can be directly used for welding, which can improve the welding adhesion. In addition, since the metal has good electrical conductivity and thermal conductivity, during the analysis and testing process, it is more conducive to the electric field heat conduction at the tip of the conical sample 9, improving the phenomenon of heat accumulation at the tip, increasing the success rate of the test, and at the same time improving the signal-to-noise ratio of the analysis result.

[0082] In some embodiments, the material of the first metal layer 11 can be at least one of tungsten (W), platinum (Pt), and nickel (Ni).

[0083] In some embodiments, as Figure 12 and Figure 13As shown, the sample strip 7 can be extracted using the tungsten needle 12. Specifically, after the sample strip 7 is cut by FIB, one end of the sample strip 7 is still connected to the material layer 3 in the peripheral area 102, and the other end is a free end. Move the tungsten needle 12 to the surface of the free end, deposit platinum or tungsten between the tungsten needle 12 and the free end, and weld the tungsten needle 12 to the surface of the free end to connect the tungsten needle 12 to the free end of the sample strip 7. Use FIB to cut off one end of the sample strip 7, move the tungsten needle 12, and take out the sample strip 7.

[0084] As Figure 13 shown, fix one end of the taken-out sample strip 7 on the base 10, cut a part of the sample strip 7, move the tungsten needle 12, and remove the cut part, as Figure 14 shown, leave the part to be circumcised on the base 10 to form the sample 8 to be circumcised. As Figure 15 shown, then circumcise the sample 8 to be circumcised to form a conical sample 9, and put the silicon base 10 and the sample 9 into a testing instrument for testing.

[0085] In some embodiments, before extracting the material layer and processing in S130, the preparation method further includes: forming a second metal layer (not shown in the figure) on the surface of the material layer.

[0086] After forming the stacked material layers, it is necessary to determine the target area P for sampling. The determination of the target area P and the cutting using FIB require SEM (Scanning Electron Microscope) imaging for positioning. Forming a second metal layer on the surface of the material layer can improve the surface conductivity of the material layer, which is beneficial for clearer SEM imaging and more accurate positioning of the target area P. In addition, before performing SEM imaging, use carbon tape to fix the substrate 1 of the peripheral area 102 to be observed to a carrier to improve the conductivity of the sample on the peripheral area 102 and improve the imaging quality of SEM.

[0087] Specifically, a second metal layer can be deposited on the surface of the material layer using a deposition process, and the material of the second metal layer can be at least one of tungsten (W), platinum (Pt), and nickel (Ni).

[0088] During testing, since the second metal layer is not the object to be analyzed and tested, in order to avoid the influence of the second metal layer on the APT test results, after obtaining the sample strip 7, the second metal layer on the surface of the sample strip 7 can be removed to expose the surface of the material layer 3 to be tested.

[0089] In some embodiments, after forming the first semiconductor structure 2 in the array region 101 and the stacked material layers in the peripheral region 102 in S130, and before extracting the sample strip 7, it further includes: synchronously performing a second semiconductor process in the array region 101 and the peripheral region 102 to form second semiconductor structures (not shown in the figure) on the first semiconductor structure 2 in the array region 101 and the material layers in the peripheral region 102 respectively.

[0090] Since the material layers to be tested have been formed in the peripheral region 102, while the fabrication of semiconductor devices in the array region 101 has not been completed and the semiconductor process needs to be continued to complete the fabrication of semiconductor devices, the second semiconductor process can be synchronously performed in the array region 101 and the peripheral region 102 to form second semiconductor structures on the first semiconductor structure 2 in the array region 101 and the material layers in the peripheral region 102. For example, the second semiconductor structure can be a conductor part formed on the capacitor 20. Synchronously performing the second semiconductor process in the array region 101 and the peripheral region 102 without selectively synchronously performing the process of forming the second semiconductor material in the peripheral region 102 can simplify the operation process.

[0091] It should be noted that the second semiconductor structure can be a semiconductor structure in a semiconductor device located on the first semiconductor structure 2. The second semiconductor process can include the same processes as those in the first semiconductor process, and no special limitation is made here.

[0092] After forming the second semiconductor structure, before extracting the sample strip 7 in the peripheral region 102, the second semiconductor structure in the peripheral region 102 can be removed first. For example, the second semiconductor structure is removed by a chemical mechanical polishing process to expose the material layer 3 to be tested. The subsequent sampling process is the same as that in the above embodiments and will not be elaborated here.

[0093] In some embodiments, the substrate 1 can include a semiconductor substrate and a third semiconductor structure (not shown in the figure). The semiconductor substrate has an array region 101 and a peripheral region 102, and the third semiconductor structure is located in the array region 101 and the peripheral region 102 of the semiconductor substrate. For example, the third semiconductor structure can be the structure of a transistor located under the capacitor 20. That is to say, before performing the first semiconductor process, the third semiconductor structure has been formed on the semiconductor substrate. Since the material layers in the first semiconductor structure 2 need to be tested, the third semiconductor structure and the semiconductor substrate are jointly regarded as the substrate 1. The first semiconductor process is continued on the third semiconductor structure located in the array region 101, and the process of forming the materials of the first semiconductor structure 2 in the first semiconductor process is performed on the third semiconductor structure located in the peripheral region 102, so that complete semiconductor devices can be formed in the array region 101.

[0094] In summary, for the method of preparing the sample 9 for atom probe tomography according to the embodiments of the present disclosure, the substrate 1 is divided into an array region 101 and a peripheral region 102. In the array region 101, a first semiconductor process is performed to form a first semiconductor structure 2. In the peripheral region 102, a process of forming the material of the first semiconductor structure 2 in the first semiconductor process is synchronously performed to form a stacked material layer. Therefore, the material layer in the peripheral region 102 and the corresponding material of the first semiconductor structure 2 in the array region 101 are formed synchronously. Therefore, they have the same thickness and element distribution, and each material layer in the peripheral region 102 is a flat layer, stacked in multiple layers, with a simple structure, and there will be no hollow or other complex structures. Therefore, using the material layer in the peripheral region 102 to prepare the APT sample 9 simplifies the preparation process and greatly reduces the difficulty. The material layers are evenly distributed, improving the integrity and surface finish of the sample 9, and improving the accuracy of the test results.

[0095] In the embodiments of the present disclosure, a sample 9 for atom probe tomography is also provided. The sample 9 is prepared by the method in any of the above embodiments, and the preparation method will not be elaborated here. The sample 9 includes a material layer 3 to be measured stacked in sequence in a direction perpendicular to the substrate 1.

[0096] In some embodiments, the sample 9 further includes a semiconductor substrate and a conical carrier column 4. The carrier column 4 is located on the semiconductor substrate, and the material layer 3 to be measured conformally covers the surface of the carrier column 4.

[0097] For the above sample 9 according to the embodiments of the present disclosure, the distribution of the material layer 3 to be measured is more uniform, there is no hollow or other complex structure, improving the integrity and surface finish of the sample 9, enabling the improvement of the accuracy of the test results, with a simple preparation process, improving the sample preparation efficiency, and reducing costs.

[0098] The embodiments of the present disclosure also provide a chip, which has a working area and a reserved sample area. As Figure 7 and Figure 11 show, schematic diagrams of chips with different structures are shown. The working area of the chip has a first semiconductor structure 2, and the first semiconductor structure 2 is formed by a first semiconductor process. The reserved sample area has a stacked material layer, and the stacked material layer is formed by the process of forming the material of the first semiconductor structure 2 in the first semiconductor process; wherein, the stacked material layer includes a material layer 3 to be measured.

[0099] In some embodiments, the working area of the chip corresponds to the array region 101 of the substrate 1 in any of the above embodiments, and the reserved sample area corresponds to the peripheral region 102 of the substrate 1 in any of the above embodiments. The first semiconductor process can be the first semiconductor process in any of the above embodiments, and will not be elaborated here.

[0100] In some embodiments, the stacked material layers in the reserved sample area are formed by a process that synchronously forms the materials of the first semiconductor structure 2 in the first semiconductor process.

[0101] In some embodiments, the reserved sample area further has a conical carrier column 4, and at least the material layer to be measured 3 conformally lies on the surface of the carrier column 4.

[0102] In some embodiments, the sample reserved area may further have a protective layer 5, and the protective layer 5 completely covers the material layer 3 to be measured on the carrier column 4.

[0103] For the chip according to the embodiments of the present disclosure, since the stacked material layers in the reserved sample area are exactly the same as the corresponding materials of the first semiconductor structure 2 in the working area, and each material layer in the reserved sample area is a flat layer, with multiple layers stacked, the structure is simple and there will be no hollow or other complex structures. Therefore, using the material layers in the reserved sample area to prepare the APT sample 9 can simplify the preparation process, greatly reduce the difficulty, the distribution of each material layer is uniform, which can improve the integrity and surface smoothness of the prepared sample 9, and further improve the accuracy of the test results.

[0104] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more separate features mentioned or obvious in the text and / or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A method for preparing a sample for atom probe tomography, characterized in that, Comprising: Providing a substrate having an array region and a peripheral region; Performing a first semiconductor process in the array region to form a first semiconductor structure, synchronously performing in the peripheral region the process of the material for forming the first semiconductor structure in the first semiconductor process, and forming a stacked material layer in the peripheral region; Extracting the material layer and processing it, retaining the material layer to be measured, and forming a sample.

2. The method according to claim 1, wherein The substrate is a semiconductor substrate. Before performing the first semiconductor process in the array region, it further includes: forming a conical carrier column on the semiconductor substrate in the peripheral region.

3. The method according to claim 2, characterized in that The material of the carrier column is at least one of a semiconductor material and a conductor material.

4. The method according to claim 2, characterized in that, Forming a stacked material layer in the peripheral region includes: conformally forming the material layer to be measured on the surface of the carrier column.

5. The method according to claim 4, wherein It further includes: Forming a protective layer in the peripheral region, the protective layer completely covering the material layer to be measured on the carrier column; Forming a stacked material layer in the peripheral region further includes: Continuously and synchronously performing in the protective layer the process of the material for forming the first semiconductor structure in the first semiconductor process, and forming a non-test material layer on the protective layer.

6. The method according to claim 5, characterized in that, It further includes: Removing the non-test material layer to expose the protective layer; Extracting the material layer and processing it, retaining the material layer to be measured, and forming a sample, including: Cutting a target region in the peripheral region to obtain the semiconductor substrate of the target region and the carrier column, the material layer to be measured, and the protective layer located on the semiconductor substrate; Removing the protective layer to expose the conical material layer to be measured and form the sample.

7. The method according to claim 5, wherein The material of the protective layer is at least one of photoresist, silicon oxide, silicon nitride, and silicon oxynitride.

8. The method according to claim 1, characterized in that, Extracting the material layer and processing it, retaining the material layer to be measured, and forming a sample, including: Using a focused ion beam to cut the material layer in the target region to form a sample strip containing the material layer to be measured; Cutting off a part of the sample strip and fixing it to the base of an atom probe to form a sample to be circumferentially cut; Circumferentially cutting the sample to be circumferentially cut to form the conical sample.

9. The method according to claim 8, characterized in that, The bottom of the sample strip has a first metal layer.

10. The method according to claim 1, characterized in that, Before extracting the material layer and processing it, it further includes: forming a second metal layer on the surface of the material layer.

11. The method according to claim 10, wherein, The material of the second metal layer is at least one of tungsten, platinum, and nickel.

12. The method according to claim 1, wherein After forming the first semiconductor structure in the array region and forming the stacked material layer in the peripheral region, it further includes: Synchronously performing a second semiconductor process in the array region and the peripheral region to respectively form a second semiconductor structure on the first semiconductor structure in the array region and the material layer in the peripheral region.

13. The method according to claim 1, wherein The substrate includes: A semiconductor substrate having the array region and the peripheral region; A third semiconductor structure located in the array region and the peripheral region of the semiconductor substrate.

14. A sample for atom probe tomography, characterized in that, The sample is prepared by the method according to any one of claims 1 to 13, and the sample includes: a material layer to be measured stacked in sequence.

15. The sample according to claim 14, characterized in that, It further includes: A semiconductor substrate; A conical carrier column located on the semiconductor substrate, and the material layer to be measured is conformally located on the surface of the carrier column.

16. A chip, characterized in that, The chip has a working area and a reserved sample area, wherein, the working area has a first semiconductor structure formed by a first semiconductor process; the reserved sample area has stacked material layers formed by the process of the material for forming the first semiconductor structure in the first semiconductor process; wherein, the stacked material layers include a material layer to be measured.

17. The chip according to claim 16, wherein The reserved sample area further has a conical carrier column, and at least the material layer to be measured conformally lies on the surface of the carrier column.

Images