Linear regulated power supply and power supply system

Abstract

The application discloses a linear voltage stabilizing power supply, which comprises an abnormality control module, a starting module, an adjusting module and an output module. The abnormality control module is connected with a voltage input end, a voltage output end and the starting module respectively; the starting module is connected with a first enable signal end, the voltage input end and a first node respectively; the adjusting module is connected with the voltage input end, a reference voltage end, the first node, a second node and the output module respectively; and the output module is connected with the second node, the voltage input end and the voltage output end respectively. In the linear voltage stabilizing power supply, the abnormality control module detects input voltage and output voltage, and provides a reset signal to the starting module according to the relationship between the input voltage and the output voltage, so as to adjust the first node voltage, the second node voltage and the output voltage. In this way, the overshoot of the voltage output end in the abnormal working state of the linear voltage stabilizing power supply is avoided, and the safety of the voltage output end is protected.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a linear regulated power supply and power supply system. Background Technology

[0002] In recent years, charging electronic devices have been powered by integrated PMICs (Power Management ICs), which places high demands on the transient overshoot voltage of the system. When the battery voltage is at full charge voltage, the transient overshoot of the system should not exceed 100 millivolts, or 2.3%. If this value is exceeded, it may damage or burn out the system chip.

[0003] In the above situation, charging chips using traditional voltage-mode control and current-mode control are prone to transient overshoot, which can greatly affect the operation of the PMIC of mobile smart terminals or even burn them out. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application provides a linear regulated power supply and power supply system.

[0005] This application provides a linear regulated power supply, characterized in that it includes an abnormal control module, a startup module, an adjustment module, and an output module;

[0006] The fault control module is connected to the voltage input terminal, the voltage output terminal and the start-up module respectively. The fault control module is used to provide a reset signal to the start-up module according to the input voltage of the voltage input terminal and the output voltage of the voltage output terminal.

[0007] The startup module is connected to the first enable signal terminal, the voltage input terminal, and the first node respectively. The startup module is used to adjust the voltage of the first node according to the first enable signal of the first enable signal terminal and the input voltage of the voltage input terminal, and to reset the voltage of the first node to zero according to the reset signal.

[0008] The adjustment module is connected to the voltage input terminal, the reference voltage terminal, the first node, the second node, and the output module respectively. The adjustment module is used to adjust the voltage of the second node according to the voltage of the first node, the reference voltage of the reference voltage terminal, and the input voltage of the voltage input terminal.

[0009] The output module is connected to the second node, the voltage input terminal, and the voltage output terminal respectively. The output module is used to provide the output voltage to the voltage output terminal according to the voltage of the second node and the input voltage of the voltage input terminal.

[0010] In some implementations, the anomaly control module includes:

[0011] The comparator has its first input terminal and second input terminal connected to the voltage input terminal and the voltage output terminal, respectively.

[0012] The first transistor has its first and second terminals connected to the startup module and the ground terminal, respectively, and its third terminal connected to the output terminal of the comparator.

[0013] In some implementations, the startup module includes:

[0014] A startup capacitor, wherein the first end of the startup capacitor is connected to the abnormal control module and the first node, and the second end is connected to the ground terminal;

[0015] The first current mirror unit is connected to the voltage input terminal and the first node, respectively;

[0016] The first switch control unit is connected to the first current mirror unit, the second enable signal terminal, the ground terminal, and the first node, respectively.

[0017] In some embodiments, the first current mirror unit includes:

[0018] The second transistor has its first terminal connected to the voltage input terminal, and its second terminal connected to the first switch control unit and its third terminal.

[0019] The third transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the first node, and its third terminal connected to the third terminal of the second transistor.

[0020] The fourth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the adjustment module, and its third terminal connected to the second terminal of the second transistor.

[0021] In some embodiments, the first switch control unit includes:

[0022] The fifth transistor has its first terminal connected to the first current mirror unit, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal.

[0023] The sixth transistor has its first terminal connected to the first node, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal.

[0024] In some embodiments, the adjustment module includes:

[0025] An error amplification unit is connected to the first node, the reference voltage terminal, the first current mirror unit, the output module, and the third node, respectively.

[0026] An active load unit is connected to the error amplification unit, the third node, and the ground terminal;

[0027] The two-stage amplification unit is connected to the voltage input terminal, the second node, the third node, and the ground terminal, respectively.

[0028] In some embodiments, the error amplification unit includes:

[0029] The seventh transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the active load unit, and its third terminal connected to the first node;

[0030] The eighth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the active load unit, and its third terminal connected to the reference voltage terminal.

[0031] The ninth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the third node, and its third terminal connected to the output module.

[0032] In some embodiments, the active load unit includes:

[0033] The tenth transistor has its first terminal connected to the error amplification unit, its second terminal connected to the ground terminal, and its third terminal connected to the first terminal.

[0034] The eleventh transistor has its first terminal connected to the three nodes, its second terminal connected to the ground terminal, and its third terminal connected to the third terminal of the tenth transistor.

[0035] In some embodiments, the secondary amplification unit includes:

[0036] The twelfth transistor has its first terminal connected to the voltage input terminal, and its second and third terminals connected to the second node;

[0037] The thirteenth transistor has its first terminal connected to the second terminal of the twelfth transistor, the second terminal connected to the ground terminal, and its third terminal connected to the third node.

[0038] In some implementations, the output module includes:

[0039] The fourteenth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the output terminal, and its third terminal connected to the second node;

[0040] A first resistor, one end of which is connected to the second terminal of the fourteenth transistor, and the other end of which is connected to the error amplification unit;

[0041] The second resistor has one end connected to the first resistor and the error amplification unit, and the other end connected to the ground terminal;

[0042] The filter capacitors are connected to the output terminal and the ground terminal, respectively.

[0043] In some implementations, the anomaly control module further includes:

[0044] The second current mirror unit is connected to the voltage input terminal, the fourth node, and the ground terminal;

[0045] The control unit is connected to the fourth node, the voltage output terminal, the ground terminal, and the fifth node, respectively.

[0046] The output unit is connected to the fifth node, the startup module, and the grounding terminal, respectively.

[0047] In some embodiments, the linear regulated power supply further includes:

[0048] The step-down module is connected to both the voltage input terminal and the startup module.

[0049] In some embodiments, the second current mirror unit includes:

[0050] The fifteenth transistor, wherein the first terminal of the fifteenth transistor is connected to the voltage input terminal, and the second terminal is connected to the third terminal;

[0051] The sixteenth transistor has its first terminal connected to the voltage input terminal and its third terminal connected to the second terminal of the fifteenth transistor.

[0052] The seventeenth transistor has its first terminal connected to the second terminal of the fifteenth transistor, and its second terminal connected to its third terminal.

[0053] The eighteenth transistor has its first terminal connected to the second terminal of the sixteenth transistor, the second terminal connected to the fourth node, and its third terminal connected to the third terminal of the seventeenth transistor.

[0054] The nineteenth transistor has its first terminal connected to the second terminal of the seventeenth transistor, the second terminal connected to the ground terminal, and its third terminal connected to the buck module.

[0055] In some embodiments, the control unit includes:

[0056] The twentieth transistor has its first terminal connected to the fourth node, its second terminal connected to the ground terminal, and its third terminal connected to the voltage output terminal.

[0057] The 21st transistor has its first terminal connected to the fourth node and its second terminal connected to the fifth node.

[0058] The 22nd transistor has its first terminal connected to the voltage output terminal, its second terminal connected to the ground terminal, and its third terminal connected to the third terminal of the 21st transistor and the ground terminal.

[0059] In some embodiments, the output unit includes:

[0060] Voltage inverter, connected to the fifth node;

[0061] The 23rd transistor has its first terminal connected to the first node, its second terminal connected to ground, and its third terminal connected to the voltage inverter.

[0062] In some implementations, the anomaly control module further includes:

[0063] The second switch control unit is connected to the second enable signal terminal, the step-down module, the ground terminal, and the control unit, respectively.

[0064] In some embodiments, the second switch control unit includes:

[0065] The 24th transistor has its first terminal connected to the buck module, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal.

[0066] The 25th transistor has its first terminal connected to the buck module, its second terminal connected to the ground terminal, and its third terminal connected to the first terminal and the control unit.

[0067] This application provides a power supply system, including the linear regulated power supply described in any of the above claims.

[0068] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0069] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0070] Figure 1 This is a schematic diagram of a linear regulated power supply according to an embodiment of this application;

[0071] Figure 2 This is a schematic diagram of a linear regulated power supply according to an embodiment of this application;

[0072] Figure 3 This is a schematic diagram of a linear regulated power supply according to an embodiment of this application;

[0073] Figure 4 This is a schematic diagram of the power supply system according to an embodiment of this application.

[0074] Explanation of key component symbols:

[0075] Power supply system 1000, linear regulated power supply 100, abnormal control module 10, comparator 11, first transistor T1, second current mirror unit 13, fifteenth transistor T15, sixteenth transistor T16, seventeenth transistor T17, eighteenth transistor T18, nineteenth transistor T19, control unit 14, twentieth transistor T20, twenty-first transistor T21, twenty-second transistor T22, output unit 15, voltage inverter 151, twenty-third transistor T23, second switch control unit 16, twenty-fourth transistor T24, twenty-fifth transistor T25, startup module 20, startup capacitor C1, first current mirror unit 22, second transistor T2, third transistor T3, fourth transistor T4. First switch control unit 23, fifth transistor T5, sixth transistor T6, adjustment module 30, error amplification unit 31, seventh transistor T7, eighth transistor T8, ninth transistor T9, active load unit 32, tenth transistor T10, eleventh transistor T11, second stage amplification unit 33, twelfth transistor T12, thirteenth transistor T13, output module 40, fourteenth transistor T14, first resistor R1, second resistor R2, filter capacitor C2, step-down module 50, voltage input terminal VIN, voltage output terminal VOUT, first node D1, second node D2, third node D3, fourth node D4, fifth node D5, second enable signal terminal E2, ground terminal GND, reference voltage terminal VREF. Detailed Implementation

[0076] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0077] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0078] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0079] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0080] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0081] Currently, in order to avoid the risk of damage to electronic devices due to overshoot during the power supply process, an overshoot protection circuit is usually added to the power supply system. The overshoot protection circuit can make the output voltage of the power supply system rise slowly, thus avoiding output overshoot.

[0082] However, current overshoot protection circuits only mitigate the output process during startup. In practical applications, if the input is continuously powered on and off due to sudden poor contact or other specific conditions, the overshoot protection circuit will still exhibit output overshoot, which can damage the electronic equipment.

[0083] In view of this, please refer to Figure 1 This application provides a linear regulated power supply 100, which includes an abnormal control module 10, a startup module 20, an adjustment module 30, and an output module 40.

[0084] The fault control module 10 is connected to the voltage input terminal VIN, the voltage output terminal VOUT, and the start module 20. The fault control module 10 is used to provide a reset signal to the start module 20 according to the input voltage of the voltage input terminal VIN and the output voltage of the voltage output terminal VOUT.

[0085] The startup module 20 is connected to the first enable signal terminal (not shown), the voltage input terminal VIN, and the first node D1 respectively. The startup module 20 is used to adjust the voltage of the first node D1 according to the first enable signal of the first enable signal terminal and the input voltage of the voltage input terminal VIN, and to reset the voltage of the first node D1 to zero according to the reset signal.

[0086] The adjustment module 30 is connected to the voltage input terminal VIN, the reference voltage terminal VREF, the first node D1, the second node D2 and the output module 40 respectively. The adjustment module 30 is used to adjust the voltage of the second node D2 according to the voltage of the first node D1, the reference voltage of the reference voltage terminal VREF and the input voltage of the voltage input terminal VIN.

[0087] The output module 40 is connected to the second node D2, the voltage input terminal VIN, and the voltage output terminal VOUT, respectively. The output module 40 is used to provide the output voltage to the voltage output terminal VOUT according to the voltage of the second node D2 and the input voltage of the voltage input terminal VIN.

[0088] In the linear regulated power supply 100 of this application, an abnormal control module 10 is set to detect the input voltage and output voltage, and provide a reset signal to the start-up module 20 according to the relationship between the input voltage and output voltage, thereby adjusting the voltage of the first node D1, the voltage of the second node D2 and the output voltage. In this way, the overshoot of the voltage output terminal VOUT of the linear regulated power supply 100 under abnormal working conditions is avoided, which helps to protect the safety of the voltage output terminal VOUT.

[0089] Specifically, the anomaly control module 10 is connected to the voltage input terminal VIN and the voltage output terminal VOUT. The anomaly control module 10 can detect the input voltage at the voltage input terminal VIN and the output voltage at the voltage output terminal VOUT to determine whether the input voltage at the voltage input terminal VIN is abnormal. When the input voltage is abnormal, it generates a reset signal and transmits it to the start-up module 20. For example, in this application, when the input voltage is detected to be greater than the output voltage, it is determined that the input voltage is normal, and the anomaly control module 10 will not provide a reset signal to the start-up module 20. When the anomaly control module 10 detects that the input voltage is less than the output voltage, it can confirm that the input voltage is in an abnormal state, and the anomaly control module 10 generates a reset signal and sends it to the start-up module 20.

[0090] The startup module 20 is connected to the first node D1, the first enable signal terminal, and the voltage input terminal VIN. The first enable signal terminal is the enable signal input terminal, which can control the input of the enable signal. Under normal circumstances, the first enable signal terminal is active at high level. That is, when EN=1 and EN_B=0, the first enable signal terminal can send the first enable signal to the startup module 20. It should be noted that the enable signal can be an operation permission signal. That is, when the startup module 20 receives the first enable signal, the startup module 20 can start, thereby transmitting the input voltage of the voltage input terminal VIN from the first node D1 to the regulation module 30.

[0091] The adjustment module 30 is connected to the voltage input terminal VIN, the reference voltage terminal VREF, the first node D1, and the second node D2, respectively. This allows the adjustment module 30 to adjust the voltage of the second node D2 based on the voltage of the first node D1 and the reference voltage of the reference voltage terminal VREF. The reference voltage of the reference voltage terminal VREF is factory-calibrated and can be configured according to specific circumstances; no limitation is made here. When the first enable signal is high, i.e., when the startup module 20 is enabled, if the voltage of the first node D1 is less than the reference voltage of the reference voltage terminal VREF, the adjustment module 30 can adjust the voltage of the first node D1 and the voltage of the second node D2. That is, the voltage of the second node D2 slowly increases following the voltage of the first node D1. During the operation of the startup module 20, the voltage of the first node D1 continuously increases. When the voltage of the first node D1 exceeds the reference voltage, the startup module 20 enters a failure state, and the adjustment module 30 can begin adjusting the reference voltage and the voltage of the second node D2 until the voltage of the second node D2 stabilizes. The output module 40 is connected to the second node D2, the voltage input terminal VIN, and the voltage output terminal VOUT, respectively. The output module 40 can provide the output voltage to the voltage output terminal VOUT according to the input voltage and the voltage of the second node D2.

[0092] In some examples, when the first enable signal is high (i.e., when the startup module 20 is enabled) and the abnormality control module 10 confirms that the circuit is in a normal state (i.e., when the abnormality control module 10 detects that the input voltage is greater than the output voltage), the startup module 20 operates normally. The adjustment module 30 can adjust the reference voltage at the reference voltage terminal VREF and the voltage of the output module 40, causing the voltage of the output module 40 to rise slowly, thereby causing the output voltage VOUT to rise slowly and avoiding overcharging. When the abnormality control module 10 confirms that the circuit is in an abnormal state (i.e., when the abnormality control module 10 detects that the input voltage is less than the output voltage), the abnormality control module 10 can send a reset signal to the startup module 20. The startup module 20 is connected to the first node D1. The startup module 20 can reset the voltage of the first node D1 to zero according to the reset signal. By adjusting the voltage of the first node D1 and the voltage of the second node D2 through the adjustment module 30, the voltage of the second node D2 can be reduced, thereby reducing the output voltage of the output module 40. When the input voltage returns to normal, that is, when the input voltage is greater than the output voltage, the voltage of the first node D1 slowly increases. Under the action of the regulating module 30, the voltage of the second node D2 slowly increases, thereby slowly increasing the output voltage of the output module 40.

[0093] Please see Figure 2In some embodiments, the abnormal control module 10 includes a comparator 11 and a first transistor T1. The first input terminal and the second input terminal of the comparator 11 are respectively connected to the voltage input terminal VIN and the voltage output terminal VOUT. The first terminal and the second terminal of the first transistor T1 are respectively connected to the startup module 20 and the ground terminal GND, and the third terminal is connected to the output terminal of the comparator 11.

[0094] Specifically, comparator 11 includes a first input terminal, a second input terminal, and an output terminal. Comparator 11 is an electronic component that outputs different voltage results at the output terminal by comparing the voltage magnitudes of the first input terminal and the second input terminal. The first transistor T1 includes a first terminal, a second terminal, and a third terminal. According to the characteristics of transistors, they can be divided into N-type and P-type transistors. In the embodiments disclosed in this application, the first transistor T1 is an N-type transistor, that is, in the embodiments of this application, when the gate of the first transistor T1 receives a high-level signal, the first terminal and the second terminal of the first transistor T1 are turned on.

[0095] Furthermore, comparator 11 can detect the input voltage at voltage input terminal VIN and the output voltage at voltage output terminal VOUT. When the input voltage is less than the output voltage, the abnormal control module 10 can confirm that the circuit is in an abnormal state and send a reset signal to the startup module 20, causing the voltage of the first node D1 to drop to 0V. At the same time, the gate of the first transistor T1 receives a high-level signal, that is, the third terminal of the first transistor T1 receives a high-level signal, and the first and second terminals are turned on. The first terminal is connected to the startup module 20, and the second terminal is connected to the ground terminal GND, which can discharge the remaining power of the startup module 20, so that the voltage of the first node D1 is 0.

[0096] It should be noted that, in the embodiments of this application, the transistors used can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used here can be symmetrical in structure, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole as the second pole. Therefore, in the embodiments of this disclosure, the source and drain of all or some transistors can be interchanged as needed.

[0097] Thus, on the one hand, the abnormal control module 10 can connect the voltage input terminal VIN and the voltage output terminal VOUT by setting the comparator 11, and output different voltages to control the on and off of the first transistor T1. On the other hand, by setting the first transistor T1, the first terminal is connected to the startup module 20 and the second terminal is connected to the ground terminal GND, so that the remaining power of the startup module 20 can be discharged in the event of a circuit abnormality.

[0098] Please see Figure 2 In some embodiments, the startup module 20 includes a startup capacitor C1, a first current mirror unit 22, and a first switch control unit 23. The first end of the startup capacitor C1 is connected to the fault control module 10 and the first node D1, and the second end is connected to the ground terminal GND. The first current mirror unit 22 is connected to the voltage input terminal VIN and the first node D1, respectively. The first switch control unit 23 is connected to the first current mirror unit 22, the second enable signal terminal E2, the ground terminal GND, and the first node D1, respectively.

[0099] Specifically, the startup capacitor C1 can be slowly charged by the current in the circuit. The first end of the startup capacitor C1 is connected to the first transistor T1 and the first node D1, and the second end is connected to the ground terminal GND. When the startup module 20 is operating normally, the startup capacitor C1 charges slowly, which can slow down the rise rate of the voltage of the first node D1. When the startup module 20 is in an abnormal state, the first transistor T1 is connected to the ground terminal GND, which can discharge the charge of the startup capacitor C1, thereby setting the voltage of the first node D1 to zero.

[0100] The first current mirror unit 22 may include multiple transistors; that is, multiple transistors can form the first current mirror unit 22. A current mirror is a standard component commonly found in analog integrated circuits. Its controlled current is equal to the input reference current, meaning the input-output current transfer ratio is equal to 1. Its characteristic is that the output current is a proportional "copy" of the input current, used to generate bias current and as an active load. The first current mirror unit 22 is connected to the voltage input terminal VIN and the first node D1. It can be understood that the current output by the first current mirror unit 22 flows through the first node D1 to the starting capacitor C1, allowing the starting capacitor C1 to charge slowly.

[0101] The first switch control unit 23 may include multiple transistors. The first switch control unit 23 is connected to the first current mirror unit 22, the second enable signal terminal E2, the ground terminal GND and the first node D1 respectively. The first switch control unit 23 can control the current to flow to the ground terminal GND to form a loop according to the enable signal.

[0102] Thus, by setting the startup capacitor C1, the startup module 20 can slow down the rise rate of the voltage of the first node D1, avoiding circuit damage caused by sudden power-up. By setting the first current mirror unit 22, it can generate bias current and act as an active load, so that each circuit receives the same current. By setting the first switch control unit 23, it can control the current flow direction of the startup module 20 according to the enable signal, thereby forming a current loop.

[0103] Please see Figure 2In some embodiments, the first current mirror unit 22 includes a second transistor T2, a third transistor T3, and a fourth transistor T4. The first terminal of the second transistor T2 is connected to the voltage input terminal VIN, the second terminal is connected to the first switch control unit 23 and the third terminal. The first terminal of the third transistor T3 is connected to the voltage input terminal VIN, the second terminal is connected to the first node D1, and the third terminal is connected to the third terminal of the second transistor T2. The first terminal of the fourth transistor T4 is connected to the voltage input terminal VIN, the second terminal is connected to the adjustment module 30, and the third terminal is connected to the second terminal of the second transistor T2.

[0104] Specifically, the second transistor T2, the third transistor T3, and the fourth transistor T4 in this application can be transistors of the same type. Their voltage input terminals VIN are connected to the first terminals of the second transistor T2, the third transistor T3, and the fourth transistor T4, respectively. The second terminal of the second transistor T2 is connected to the third terminals of the second transistor T2, the third transistor T3, and the fourth transistor T4, respectively, allowing all three transistors to be switched on and off simultaneously. The second transistor T2 is connected to the first switch control unit 23, the third transistor T3 is connected to the first node D1, and the fourth transistor T4 is connected to the adjustment module 30. Thus, the first current mirror unit 22 can enable the first switch control unit 23, the first node D1, and the adjustment module 30 to simultaneously form a current loop and obtain the same current.

[0105] Please see Figure 2 In some embodiments, the first switch control unit 23 includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the first current mirror unit 22, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the second enable signal terminal E2. The first terminal of the sixth transistor T6 is connected to the first node D1, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the second enable signal terminal E2.

[0106] Specifically, the fifth transistor T5 can be a P-type transistor. The gate of the fifth transistor T5 is connected to the second enable signal terminal E2. That is, the third terminal of the fifth transistor T5 is connected to the second enable signal terminal E2, the first terminal is connected to the first current mirror unit 22, and the second terminal is connected to the ground terminal GND. The opening and closing of the fifth transistor T5 can be controlled according to the second enable signal, thereby controlling the on and off of the current loop of the startup module 20.

[0107] The sixth transistor T6 can be an N-type transistor. The first and second terminals of the sixth transistor T6 are connected to the first node D1 and the ground terminal GND, respectively, thus forming a circuit with the start-up capacitor C1. The third terminal is connected to the second enable signal terminal E2. The sixth transistor T6 can control the on / off state of the circuit formed by the start-up capacitor C1 and the sixth transistor T6 according to the second enable signal.

[0108] It should be noted that the second enable signal terminal E2 of this application is equipped with an inverter, so that the second enable signal is opposite to the first enable signal.

[0109] It is understood that in this application, the fifth transistor T5 is a P-type transistor and the sixth transistor T6 is an N-type transistor, and the fifth transistor T5 and the sixth transistor T6 are controlled to turn on and off by a second enable signal. When the second enable signal is EN=0 and EN_B=1, the fifth transistor T5 is connected, the sixth transistor T6 is disconnected, and the current loop of the startup module 20 flows, thereby enabling the startup module 20 to start. When the second enable signal is EN=1 and EN_B=0, the fifth transistor T5 is turned off, the current loop of the startup module 20 is disconnected, the sixth transistor T6 is connected, and the startup capacitor C1 can form a loop with the ground terminal GND through the sixth transistor T6, thereby discharging the charge of the startup capacitor C1. Based on the description and teaching of the implementation of the fifth transistor T5 as a P-type transistor and the sixth transistor T6 as an N-type transistor in this disclosure, those skilled in the art can easily conceive of the implementation of the fifth transistor T5 and the sixth transistor T6 as N-type transistors in the embodiments of this disclosure without inventive effort. Therefore, these implementations are also within the protection scope of this disclosure.

[0110] Thus, by setting a fifth transistor T5 and a sixth transistor T6 in the first switch control unit 23, on the one hand, the opening and closing of the fifth transistor T5 can be controlled according to the second enable signal, thereby controlling the on and off of the current loop of the start-up module 20; on the other hand, the opening and closing of the sixth transistor T6 can be controlled according to the second enable signal, thereby discharging the charge of the start-up capacitor C1 when the start-up module 20 is turned off, thereby improving the safety and service life of the circuit.

[0111] Please see Figure 2 In some embodiments, the adjustment module 30 includes an error amplification unit 31, an active load unit 32, and a secondary amplification unit 33. The error amplification unit 31 is connected to the first node D1, the reference voltage terminal VREF, the first current mirror unit 22, the output module 40, and the third node D3. The active load unit 32 is connected to the error amplification unit 31, the third node D3, and the ground terminal GND. The secondary amplification unit 33 is connected to the voltage input terminal VIN, the second node D2, the third node D3, and the ground terminal GND.

[0112] Specifically, the error amplification unit 31 is connected to the first current mirror unit 22 and the active load unit 32, and the active load unit 32 is connected to the ground terminal GND to form the current loop of the adjustment module 30. The error amplification unit 31 is also connected to the first node D1, the output module 40 and the reference voltage terminal VREF. When the startup module 20 has been started, the reference voltage of the reference voltage terminal VREF has been established. The error amplification unit 31 can compensate for the voltage of the first node D1 and the voltage of the output module 40. That is, the voltage of the output module 40 increases slowly following the voltage of the first node D1.

[0113] The active load unit 32 can serve as the output portion of the first current mirror unit 22, and can be ideally represented as a current source. That is, when the voltage of the active load unit 32 changes, the output current remains constant. The active load unit 32 includes a tenth transistor T10 and an eleventh transistor T11. The first terminal of the tenth transistor T10 is connected to the error amplifier unit 31, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the first terminal. The first terminal of the eleventh transistor T11 is connected to a three-node circuit, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the third terminal of the tenth transistor T10.

[0114] The secondary amplifier unit 33, connected to the voltage input terminal VIN and the ground terminal GND, forms a current loop. The secondary amplifier unit 33 is connected to the second node D2 and the third node D3, with the second node D2 connected to the output module 40. During the error amplifier unit 31's compensation of the voltage at the first node D1, the voltage at the third node D3 slowly increases, causing the voltage at the second node D2 to follow suit, thus gradually increasing the voltage of the output module 40. Furthermore, the secondary amplifier unit 33 includes a twelfth transistor T12 and a thirteenth transistor T13. The first terminal of the twelfth transistor T12 is connected to the voltage input terminal VIN, and its second and third terminals are connected to the second node D2. The first terminal of the thirteenth transistor T13 is connected to the second terminal of the twelfth transistor T12, its second terminal is connected to the ground terminal GND, and its third terminal is connected to the third node D3.

[0115] Thus, by setting the error amplification unit 31, the active load, and the secondary amplification unit 33, the adjustment module 30 can compensate for the voltage of the first node D1 and the voltage of the output module 40, thereby causing the voltage of the output module 40 to rise slowly, avoiding overshoot of the voltage of the output module 40, and helping to protect the safety of the voltage output terminal VOUT.

[0116] Please see Figure 2 In some embodiments, the error amplification unit 31 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0117] The first terminal of the seventh transistor T7 is connected to the voltage input terminal VIN, the second terminal is connected to the active load unit 32, and the third terminal is connected to the first node D1. The first terminal of the eighth transistor T8 is connected to the voltage input terminal VIN, the second terminal is connected to the active load unit 32, and the third terminal is connected to the reference voltage terminal VREF. The first terminal of the ninth transistor T9 is connected to the voltage input terminal VIN, the second terminal is connected to the third node D3, and the third terminal is connected to the output module 40.

[0118] Specifically, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type transistors of the same type. That is, when the voltage at the first node D1 is less than the input voltage, the seventh transistor T7 is connected. When the reference voltage is less than the input voltage, the eighth transistor T8 is connected. When the voltage at the output module 40 is less than the input voltage, the ninth transistor T9 is connected.

[0119] Thus, by setting up an error amplification unit 31 consisting of a seventh transistor, an eighth transistor T8, and a ninth transistor T9, it can compensate for the voltage of the first node D1 and the output module 40. On the other hand, in the case of overcharging of the output module 40 voltage, the ninth transistor T9 is disconnected, which can prevent the output module 40 voltage from overshooting.

[0120] Please see Figure 2 In some embodiments, the output module 40 includes a fourteenth transistor T14, a first resistor R1, a second resistor R2, and a filter capacitor C2. The first terminal of the fourteenth transistor T14 is connected to the voltage input terminal VIN, the second terminal is connected to the output terminal, and the third terminal is connected to the second node D2. One end of the first resistor R1 is connected to the second terminal of the fourteenth transistor T14, and the other end is connected to the error amplification unit 31. One end of the second resistor R2 is connected to the first resistor R1 and the error amplification unit 31, and the other end is connected to the ground terminal GND. The filter capacitor C2 is connected to both the output terminal and the ground terminal GND.

[0121] Specifically, when the input voltage is less than the output voltage, the first transistor T1 is connected, the starting capacitor C1 forms a circuit with the ground terminal GND, and the charge of the starting capacitor C1 is discharged. The voltage of the first node D1 is set to zero. After the seventh transistor T7 is connected, the eighth transistor T8 is short-circuited. The error amplification unit 31 will compensate for the voltage difference between the first node D1 voltage and the output module 40 voltage. Since the first node D1 voltage is less than the output module 40 voltage, the third node D3 voltage will be pulled down to zero. The thirteenth transistor T13 is disconnected, and no current flows through the twelfth transistor T12, causing the fourteenth transistor T14 to disconnect. This can prevent a large amount of current from flowing through the fourteenth transistor T14 when the input voltage suddenly increases, which would cause the output terminal to be overcharged.

[0122] Furthermore, when the input voltage is greater than the output voltage, the startup module 20 starts, the voltage of the first node D1 rises slowly, the voltage of the third node D3 also rises slowly, causing the voltage of the second node D2 to drop slowly. At the same time, the fourteenth transistor T14 receives a slowly increasing charging current, which flows to the output terminal.

[0123] The first resistor R1 and the second resistor R2 can be feedback resistors, used to provide feedback signals to the circuit. The feedback signals can be voltage, current, etc. The circuit can adjust the input voltage according to the feedback signals of the first resistor R1 and the second resistor R2.

[0124] The filter capacitor C2 is connected in parallel at the circuit output. It serves as an energy storage device to reduce AC ripple and smooth DC output. The filter capacitor C2 ensures a smooth and stable DC output, reduces the impact of alternating pulsating current on the circuit, and absorbs current fluctuations and interference introduced via AC power during circuit operation, thus making the circuit's performance more stable.

[0125] Thus, by setting the fourteenth transistor T14, the output voltage can be controlled to rise slowly, avoiding overcharging at the output. By setting the first resistor R1 and the second resistor R2, feedback signals from the output module 40 circuit can be obtained, thereby adjusting the input voltage according to the feedback signals. By setting the filter capacitor C2, the influence of alternating pulsating current on the circuit can be reduced, thereby improving the stability of the circuit's operating performance.

[0126] Please combine Figure 2 and Figure 3 In some embodiments, the abnormal control module 10 further includes a second current mirror unit 13, a control unit 14, and an output unit 15. The second current mirror unit 13 is connected to the voltage input terminal VIN, the fourth node D4, and the ground terminal GND. The control unit 14 is connected to the fourth node D4, the voltage output terminal VOUT, the ground terminal GND, and the fifth node D5. The output unit 15 is connected to the fifth node D5, the start-up module 20, and the ground terminal GND.

[0127] In some embodiments, the linear regulated power supply 100 further includes a step-down module 50, which is connected to the voltage input terminal VIN and the startup module 20, respectively.

[0128] Specifically, the second current mirror unit 13 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The first terminal of the fifteenth transistor T15 is connected to the voltage input terminal VIN, and the second terminal is connected to the third terminal. The first terminal of the sixteenth transistor T16 is connected to the voltage input terminal VIN, and the third terminal is connected to the second terminal of the fifteenth transistor T15. The first terminal of the seventeenth transistor T17 is connected to the second terminal of the fifteenth transistor T15, and the second terminal is connected to the third terminal. The first terminal of the eighteenth transistor T18 is connected to the second terminal of the sixteenth transistor T16, and the second terminal is connected to the fourth node D4. The third terminal is connected to the third terminal of the seventeenth transistor T17. The first terminal of the nineteenth transistor T19 is connected to the second terminal of the seventeenth transistor T17, and the second terminal is connected to the ground terminal GND. The third terminal is connected to the buck module 50. Among them, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 can be P-type transistors, and the nineteenth transistor T19 can be an N-type transistor. The eighteenth transistor T18 and the nineteenth transistor T19 can serve to withstand high voltage. Understandably, the specific characteristics of the second current mirror unit 13 are basically the same as those of the first current mirror unit 22, and will not be described in detail here.

[0129] The control unit 14 includes a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22. The first terminal of the twentieth transistor T20 is connected to the fourth node D4, the second terminal is connected to ground GND, and the third terminal is connected to the voltage output terminal VOUT. The first terminal of the twenty-first transistor T21 is connected to the fourth node D4, and the second terminal is connected to the fifth node D5. The first terminal of the twenty-second transistor T22 is connected to the voltage output terminal VOUT, the second terminal is connected to ground GND, and the third terminal is connected to the third terminal of the twenty-first transistor T21 and the ground terminal GND. The twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 can be P-type transistors.

[0130] Output unit 15 includes a voltage inverter 151 and a 23rd transistor T23. Voltage inverter 151 is connected to the fifth node D5. The first terminal of the 23rd transistor T23 is connected to the first node D1, the second terminal is connected to ground GND, and the third terminal is connected to voltage inverter 151. Voltage inverter 151 can invert the voltage signal output; that is, when the voltage signal is high, the output after passing through voltage inverter 151 is low, and when the voltage signal is low, the output after passing through voltage inverter 151 is high. The 23rd transistor T23 can be an N-type transistor.

[0131] When the input voltage is high, the buck module 50 can convert the input voltage to a low voltage supplied internally. The buck module 50 may include a voltage regulator that can subtract excess voltage from the applied input voltage by a transistor or field-effect transistor operating in the saturation region to generate a regulated output voltage.

[0132] Furthermore, when the input voltage is less than the output voltage, that is, when the voltage of the fourth node D4 is less than the output voltage, the voltage of the fifth node D5 is reduced. The voltage signal of the fifth node D5 is converted to a high level by the voltage inverter 151 and output to the twenty-third transistor T23, making the twenty-third transistor T23 connected. The voltage of the first node D1 is set to zero. The error amplification unit 31 compensates for the voltage difference between the first node D1 and the output module 40, causing the twelfth transistor T12 to disconnect, so that no current flows to the voltage output terminal VOUT of the fourteenth transistor T14. When the input voltage recovers to be greater than the output voltage, the voltage of the fifth node D5 slowly increases along with the voltage of the fourth node D4. The voltage signal of the fifth node D5 is converted to a low level by the voltage inverter 151, making the twenty-third transistor T23 disconnect, and starting the module 20 to operate normally.

[0133] Thus, by setting up the second current mirror unit 13, control unit 14, output unit 15, and step-down module 50, when the input voltage is high, the step-down module 50 can reduce the input voltage to a low voltage for internal power supply. The second current mirror unit 13 controls the current of the abnormal control module 10 circuit, the control unit 14 controls the current on and off, and the output module 40 provides a reset signal to the start-up unit. This makes the linear regulated power supply 100 suitable for high input voltage and ensures that the voltage output terminal VOUT of the linear regulated power supply 100 will not overshoot in abnormal operating conditions.

[0134] Please combine Figure 2 and Figure 3 In some embodiments, the abnormal control module 10 further includes a second switch control unit 16, which is connected to the second enable signal terminal E2, the step-down module 50, the ground terminal GND and the control unit 14 respectively.

[0135] Specifically, the second switch control unit 16 includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25. The first terminal of the twenty-fourth transistor T24 is connected to the step-down module 50, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the second enable signal terminal E2. The first terminal of the twenty-fifth transistor T25 is connected to the step-down module 50, the second terminal is connected to the ground terminal GND, and the third terminal is connected to the first terminal and the control unit 14.

[0136] Furthermore, the twenty-fourth transistor T24 and the twenty-fifth transistor T25 can be N-type transistors. When the second enable signal is EN=0 and EN_B=1, the twenty-fourth transistor T24 is off, and the current flowing from the buck module 50 acts on the twenty-fifth transistor T25, controlling the on / off state of the control unit 14 circuit through the twenty-fifth transistor T25. When the second enable signal is EN=1 and EN_B=0, the twenty-fourth transistor T24 is on, and the current flowing from the buck module 50 enters the ground terminal GND through the twenty-fourth transistor T24, forming a loop.

[0137] Thus, by setting up a second switch control unit 16 and connecting it to the second enable signal terminal E2, the step-down module 50, the ground terminal GND, and the control unit 14 respectively, on the one hand, the second switch control unit 16 can control the on / off state of the control unit 14 circuit; on the other hand, it can control the opening and closing of the twenty-fourth transistor T24 according to the second enable signal, thereby connecting the step-down module 50 to the ground terminal GND when the startup module 20 is turned off, thus improving the safety and service life of the circuit.

[0138] Please see Figure 4 This application also provides a power supply system 1000, which includes a linear regulated power supply 100.

[0139] In the power supply system 1000 of this application, the linear regulated power supply 100 detects the input voltage and output voltage by setting an abnormal control module 10, and provides a reset signal to the start-up module 20 according to the relationship between the input voltage and output voltage, thereby adjusting the voltage of the first node D1, the voltage of the second node D2 and the output voltage. In this way, it is ensured that the voltage output terminal VOUT of the linear regulated power supply 100 will not overshoot under abnormal working conditions, which is beneficial to protecting the safety of the voltage output terminal VOUT.

[0140] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0141] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A linear regulated power supply, characterized in that, It includes an exception control module, a startup module, an adjustment module, and an output module; The fault control module is connected to the voltage input terminal, the voltage output terminal and the start-up module respectively. The fault control module is used to provide a reset signal to the start-up module according to the input voltage of the voltage input terminal and the output voltage of the voltage output terminal. The startup module is connected to the first enable signal terminal, the voltage input terminal, and the first node respectively. The startup module is used to adjust the voltage of the first node according to the first enable signal of the first enable signal terminal and the input voltage of the voltage input terminal, and to reset the voltage of the first node to zero according to the reset signal. The adjustment module is connected to the voltage input terminal, the reference voltage terminal, the first node, the second node, and the output module respectively. The adjustment module is used to adjust the voltage of the second node according to the voltage of the first node, the reference voltage of the reference voltage terminal, and the input voltage of the voltage input terminal. The output module is connected to the second node, the voltage input terminal, and the voltage output terminal respectively. The output module is used to provide the output voltage to the voltage output terminal according to the voltage of the second node and the input voltage of the voltage input terminal. The startup module includes a startup capacitor, a first current mirror unit, and a first switch control unit. The first end of the startup capacitor is connected to the abnormal control module and the first node, and the second end of the startup capacitor is connected to the ground terminal. The first current mirror unit is connected to the voltage input terminal and the first node. The first switch control unit is connected to the first current mirror unit, the second enable signal terminal, the ground terminal, and the first node. The adjustment module includes an error amplification unit, an active load unit, and a secondary amplification unit. The error amplification unit is connected to the first node, the reference voltage terminal, the first current mirror unit, the output module, and the third node, respectively. The active load unit is connected to the error amplification unit, the third node, and the ground terminal, respectively. The secondary amplification unit is connected to the voltage input terminal, the second node, the third node, and the ground terminal, respectively. The abnormal control module includes a second current mirror unit, a control unit, and an output unit. The second current mirror unit is connected to the voltage input terminal, the fourth node, and the ground terminal. The control unit is connected to the fourth node, the voltage output terminal, the ground terminal, and the fifth node. The output unit is connected to the fifth node, the startup module, and the ground terminal.

2. The linear regulated power supply according to claim 1, characterized in that, The anomaly control module includes: The comparator has its first input terminal and second input terminal connected to the voltage input terminal and the voltage output terminal, respectively. The first transistor has its first and second terminals connected to the startup module and the ground terminal, respectively, and its third terminal connected to the output terminal of the comparator.

3. The linear regulated power supply according to claim 1, characterized in that, The first current mirror unit includes: The second transistor has its first terminal connected to the voltage input terminal, and its second terminal connected to the first switch control unit and its third terminal. The third transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the first node, and its third terminal connected to the third terminal of the second transistor. The fourth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the adjustment module, and its third terminal connected to the second terminal of the second transistor.

4. The linear regulated power supply according to claim 1, characterized in that, The first switch control unit includes: The fifth transistor has its first terminal connected to the first current mirror unit, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal. The sixth transistor has its first terminal connected to the first node, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal.

5. The linear regulated power supply according to claim 1, characterized in that, The error amplification unit includes: The seventh transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the active load unit, and its third terminal connected to the first node; The eighth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the active load unit, and its third terminal connected to the reference voltage terminal. The ninth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the third node, and its third terminal connected to the output module.

6. The linear regulated power supply according to claim 1, characterized in that, The active load unit includes: The tenth transistor has its first terminal connected to the error amplification unit, its second terminal connected to the ground terminal, and its third terminal connected to the first terminal. The eleventh transistor has its first terminal connected to the three nodes, its second terminal connected to the ground terminal, and its third terminal connected to the third terminal of the tenth transistor.

7. The linear regulated power supply according to claim 1, characterized in that, The secondary amplification unit includes: The twelfth transistor has its first terminal connected to the voltage input terminal, and its second and third terminals connected to the second node; The thirteenth transistor has its first terminal connected to the second terminal of the twelfth transistor, the second terminal connected to the ground terminal, and its third terminal connected to the third node.

8. The linear regulated power supply according to claim 1, characterized in that, The output module includes: The fourteenth transistor has its first terminal connected to the voltage input terminal, its second terminal connected to the output terminal, and its third terminal connected to the second node; A first resistor, one end of which is connected to the second terminal of the fourteenth transistor, and the other end of which is connected to the error amplification unit; The second resistor has one end connected to the first resistor and the error amplification unit, and the other end connected to the ground terminal; The filter capacitors are connected to the output terminal and the ground terminal, respectively.

9. The linear regulated power supply according to claim 8, characterized in that, The linear regulated power supply also includes: The step-down module is connected to both the voltage input terminal and the startup module.

10. The linear regulated power supply according to claim 9, characterized in that, The second current mirror unit includes: The fifteenth transistor, wherein the first terminal of the fifteenth transistor is connected to the voltage input terminal, and the second terminal is connected to the third terminal; The sixteenth transistor has its first terminal connected to the voltage input terminal and its third terminal connected to the second terminal of the fifteenth transistor. The seventeenth transistor has its first terminal connected to the second terminal of the fifteenth transistor, and its second terminal connected to its third terminal. The eighteenth transistor has its first terminal connected to the second terminal of the sixteenth transistor, the second terminal connected to the fourth node, and its third terminal connected to the third terminal of the seventeenth transistor. The nineteenth transistor has its first terminal connected to the second terminal of the seventeenth transistor, the second terminal connected to the ground terminal, and its third terminal connected to the buck module.

11. The linear regulated power supply according to claim 9, characterized in that, The control unit includes: The twentieth transistor has its first terminal connected to the fourth node, its second terminal connected to the ground terminal, and its third terminal connected to the voltage output terminal. The 21st transistor has its first terminal connected to the fourth node and its second terminal connected to the fifth node. The 22nd transistor has its first terminal connected to the voltage output terminal, its second terminal connected to the ground terminal, and its third terminal connected to the third terminal of the 21st transistor and the ground terminal.

12. The linear regulated power supply according to claim 9, characterized in that, The output unit includes: Voltage inverter, connected to the fifth node; The 23rd transistor has its first terminal connected to the first node, its second terminal connected to ground, and its third terminal connected to the voltage inverter.

13. The linear regulated power supply according to claim 9, characterized in that, The anomaly control module also includes: The second switch control unit is connected to the second enable signal terminal, the step-down module, the ground terminal, and the control unit, respectively.

14. The linear regulated power supply according to claim 13, characterized in that, The second switch control unit includes: The 24th transistor has its first terminal connected to the buck module, its second terminal connected to the ground terminal, and its third terminal connected to the second enable signal terminal. The 25th transistor has its first terminal connected to the buck module, its second terminal connected to the ground terminal, and its third terminal connected to the first terminal and the control unit.

15. A power supply system, characterized in that, Includes the linear regulated power supply according to any one of claims 1-14.

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