A circuit system applied to a micro-satellite on-board computer
By employing a 3-CPU redundancy architecture and a bootstrap reconfiguration method, combined with the STM32H743 main control chip and FPGA, the reliability problem caused by single-event upsets in the microsatellite mission computer was solved, achieving a microsatellite design with high reliability and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF SCI & TECH
- Filing Date
- 2022-09-22
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies for satellite-based computers for microsatellites, single-event upsets lead to reduced reliability, and redundant architecture methods suffer from low reliability, high power consumption, complex structure, and are not suitable for miniaturization requirements.
A 3-CPU redundant architecture is adopted, combined with an STM32H743 main control chip and an FPGA. Data updates and error detection and correction are realized through a bootstrap reconfiguration method. The TMR and EDAC functions of the FPGA are used to ensure the reliability of data transmission and storage.
It improves the reliability of the satellite computer for microsatellites, reduces power consumption, simplifies the structure, and is suitable for the design requirements of micro and small satellites.
Smart Images
Figure CN115840668B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of embedded microsatellite mission computer systems, and in particular, a circuit system applied to microsatellite mission computers. Background Technology
[0002] Space is filled with various particles from the vast universe: protons, electrons, alpha particles, heavy ions, gamma rays, etc. When these high-energy particles bombard sensitive semiconductor devices, the device's logic circuits will flip. Some "0"s will flip to "1", and some "1"s will flip to "0", causing data errors. This phenomenon is called single-event upset.
[0003] Single-event upsets (SOME) affect the reliability of spacecraft. If a spacecraft malfunctions in space, it is often beyond repair and generally leads to mission failure. Numerous accidents in the history of international spaceflight have resulted in mission failure due to SOME.
[0004] Currently, teams both domestically and internationally have proposed several solutions to address the issue of electronic device failure caused by single-event upsets in space. For example, SpaceX and Zhejiang University employ a multi-FPGA redundancy scheme, while Harbin Institute of Technology, the 513 and 804 institutions use dual-CPU cold / hot standby, and multiple software fault-tolerant methods are employed within a single CPU.
[0005] In existing redundancy architectures, dual-machine hot standby and TMR have low reliability and are prone to data errors. On the other hand, multi-machine backup and hardware triple redundancy methods have high power consumption and complex structures, resulting in a sharp increase in the size of satellite mission computer modules. This places high demands on design and manufacturing, and is not suitable for the miniaturization requirements of micro and nano satellites. In addition, current mission computer systems generally lack update and reconfiguration functions. Summary of the Invention
[0006] The purpose of this invention is to provide a circuit system for a microsatellite mission computer, which employs 3-CPU redundancy and a method of updating and reconstructing through bootstrapping to solve the problem of reduced reliability of mission computers caused by single-event inversion of electronic devices in space.
[0007] The technical solution to achieve the purpose of this invention is as follows:
[0008] A circuit system for use in a microsatellite satellite mission computer, comprising:
[0009] Analog acquisition module, used to collect data on the Earth's magnetic field and ambient temperature;
[0010] The AD module is used to convert analog quantities of the collected Earth's magnetic field and ambient temperature into digital quantities, and transmit them to the STM32 main control chip via the SPI interface.
[0011] The STM32 main control chip is used to complete on-board data processing; the STM32 main control chip includes CAN pin, SPI pin, RS422 pin, SWD and TTL-232 debug interfaces, and FLASH and SRAM on-chip memory.
[0012] The RS422 module converts the serial port to an RS422 interface and connects it to the RS422 pins.
[0013] It also includes FPGAs and ARM processors;
[0014] The communication unit sends the application program via the CAN bus, and the FPGA stores the application program in the external FLASH.
[0015] The FPGA pulls the BOOT pin of the STM32 main control chip high to set the STM32 main control chip to boot mode.
[0016] When the FPGA sends a RESET signal, the STM32 main control chip resets and enters the bootstrap program.
[0017] During the bootstrapping process, the STM32 master control chip receives the 0x79 transmit acknowledgment byte signal from the FPGA via the CAN bus. Next, the STM32 master control chip generates a receive response, and the FPGA sends the application program to the STM32 chip via the CAN bus.
[0018] After the application is transferred, the FPGA pulls the BOOT pin of the STM32 control chip low. At this time, the RESET signal is sent again, and the STM32 main control chip will start from FLASH. At this time, the RESET signal is sent again, and the STM32 main control chip starts normally.
[0019] The significant advantages of this invention compared to existing technologies are:
[0020] (1) This invention is based on the design of STM32H743 main control chip + FPGA architecture, wherein the FPGA has the EDAC function of real-time maintenance memory, which has high reliability; in terms of hardware design, the STM32H743 main control chip has a triple mode redundancy routing design for FPGA input and output, an EDAC interface design for external SRAM, and an interface design for program update and refactoring; the TMR (triple mode redundancy) and EDAC (error detection and correction) design of FPGA ensure that the data has strong anti-single-event upset capability during storage and transmission.
[0021] (2) The circuit architecture of the present invention is based on the 3CPU redundancy method, which has a simple structure, low power consumption, and is suitable for micro and small satellites.
[0022] (3) The present invention updates the STM32H743 main control chip by reconstructing the STM32H743 main control chip through FPGA, which can meet the performance requirements of error detection and update. Attached Figure Description
[0023] Figure 1 This is the overall design block diagram of the Starship Computer. Detailed Implementation
[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0025] Combination Figure 1 This embodiment describes a circuit system for a microsatellite satellite mission computer, including an MCU module, a power supply module, a clock module, a storage module, an external interface module, an AD converter, an analog signal acquisition module, a magnetic torque converter module, and a voltage acquisition module.
[0026] Power Supply Module: The satellite computer's voltage is supplied by a wide-voltage input from an external power system. A current-limiting module ensures low-power design requirements are met. The wide-voltage input is converted to 5V and 3.3V by an LTM8078 chip, which further converts it to 3.3V, 2.5V, and 1.2V. The 5V supplies power to the voltage acquisition devices. The 3.3V powers the STM32H743 main control chip and its control blocks, the triaxial magnetic field sensor, and the temperature sensor. The 2.5V provides a reference voltage for the AD converter and, along with the 1.2V, powers the FPGA. The current of the power supply module is acquired by an INA3221-Q1 and supplied via I... 2 The C bus transmits data to other modules.
[0027] Clock Module: The system clock consists of two crystal oscillators with frequencies of 25MHz and 32.768kHz, models TXC-25MEEQ-T and CC5V-T1A respectively. Onboard time management is mainly composed of the FPGA's time counting management module and the DS1302 module. The DS1302 includes a clock / calendar register and a 31-byte (8-bit) data buffer register. The real-time clock / calendar provides information including seconds, minutes, hours, date, month, and year, accurately recording time information when the host is offline.
[0028] Storage Module: The STM32H743 main control chip has 2MB of on-chip FLASH and 1060KB of SRAM for storing programs and data during normal operation. It also expands to 8MB of MRAM via the FMC bus for temporary data storage. The ARM core in the MS090 chip has 512KB of on-chip eNVM and 128KB of SRAM. It expands to 8GB of eNVM and 8MB of MRAM via the FPGA module. The eNVM is used to store onboard telemetry data, and the MRAM is used to store spacecraft software. The FPGA also has an EDAC function for real-time memory maintenance to ensure the reliability of memory data.
[0029] External interface module: The peripheral bus of the Starship computer is mainly used for data transmission and control between various subsystems. Through the peripheral bus of the STM32H743IIT6 main control chip, it expands to 2 CAN buses, 4 serial ports, 1 SPI bus, PWM, as well as a debug serial port and an SWD program programming port. Since the chip only contains a CAN bus controller, a CAN bus receiver module needs to be added.
[0030] Meanwhile, because RS422 signals are stable and more suitable for long-distance transmission, a serial-to-RS422 interface module was added. The MS090 chip utilizes the FPGA module to expand one CAN bus for program updates and one SPI interface for programming and debugging.
[0031] AD module: The AD7490 digital-to-analog converter chip is used to collect 11 voltage signals, of which 4 signals are eliminated by the LM24D chip to eliminate the influence of input impedance on the voltage signal.
[0032] Analog signal acquisition module: Includes a triaxial magnetic field sensor and a temperature sensor. The triaxial magnetic field sensor reads the triaxial magnetic field strength using an RM3100 chip and transmits the data to the STM32H743 main control chip via the SPI bus. The temperature sensor reads the temperature using a TMP175 chip and then transmits the data via I... 2 The C bus transmits temperature data to the STM32H743 main control chip.
[0033] Magnetic torque module: Using the DRV8839 chip, the MTQ_PWR voltage is modulated by the PWM wave generated by the CPU. The modulated voltage is connected to both ends of the magnetic rod through the output ports OUTA and OUTB. The magnetic rod generates a magnetic moment that interacts with the Earth's magnetic field to control the attitude of the satellite.
[0034] Voltage acquisition module: Utilizes the INA3221-Q1 chip to acquire the voltage potential at two points, MTQ_C+ and MTQ_C-, on the ferrite rod, and transmits the voltage via I0... 2The C bus sends the collected data to the STM32H743 main control chip, which then calculates the current passing through the magnetic rod.
[0035] The architecture of this invention is a 3-CPU redundant architecture, including one FPGA and two ARM processors. The chips used are an STM32H743 main control chip and an M2S090 chip. The M2S090 chip includes an FPGA and a Cortex-M3 processor. The STM32H743 main control chip is used to perform on-board data processing, the FPGA is used for program updates and refactoring, and the Cortex-M3 processor serves as a backup main control chip, capable of replacing the STM32H743 main control chip to perform basic space mission data processing functions.
[0036] The communication unit sends the application program via the CAN bus, and the FPGA stores the application program in the external FLASH.
[0037] The FPGA pulls the BOOT pin of the STM32 main control chip high to set the STM32 main control chip to boot mode.
[0038] When the FPGA sends a RESET signal, the STM32H743 main control chip resets and enters the bootstrap program.
[0039] During the bootstrapping process, the STM32H743 main control chip receives the 0x7F transmit acknowledgment byte signal from the FPGA via the CAN bus. Next, the STM32H743 main control chip generates a receive response, and the FPGA sends the application program to the STM32H743 chip via the CAN bus.
[0040] After the application is transferred, the FPGA pulls the BOOT pin of the STM32H743 main control chip low. At this time, the RESET signal is sent again, and the STM32H743 main control chip will start from FLASH. At this time, the RESET signal is sent again, and the STM32H743 main control chip starts normally.
Claims
1. A circuit system for use in a microsatellite satellite mission computer, comprising: Analog acquisition module, used to collect data on the Earth's magnetic field and ambient temperature; The AD module is used to convert analog quantities of the collected Earth's magnetic field and ambient temperature into digital quantities, and transmit them to the STM32 main control chip via the SPI interface. The STM32 main control chip is used to perform on-board data processing; the STM32 main control chip includes CAN pins, SPI pins, RS422 pins, SWD and TTL-232 debug interfaces, and on-chip FLASH and SRAM memory; The RS422 module converts the serial port to an RS422 interface and connects it to the RS422 pins. Its distinguishing feature is that it also includes an FPGA and an ARM processor; The communication unit sends the application program via the CAN bus, and the FPGA stores the application program in the external FLASH. The FPGA pulls the BOOT pin of the STM32 main control chip high to set the STM32 main control chip to boot mode. When the FPGA sends a RESET signal, the STM32 main control chip resets and enters the bootstrap program. During the bootstrapping process, the STM32 master control chip receives the 0x79 transmit acknowledgment byte signal from the FPGA via the CAN bus. Next, the STM32 master control chip generates a receive response, and the FPGA sends the application program to the STM32 master control chip via the CAN bus. After the application is transferred, the FPGA pulls the BOOT pin of the STM32 main control chip low. At this time, the RESET signal is sent again, and the STM32 main control chip will start from FLASH. At this time, the RESET signal is sent again, and the STM32 main control chip starts normally.
2. The circuit system applied to a microsatellite mission computer according to claim 1, characterized in that, The STM32 main control chip is an STM32H743 main control chip, and the ARM processor is a Cortex-M3 processor. The STM32H743 main control chip is used to complete on-board data processing. The Cortex-M3 processor serves as a backup main control chip, used to replace the STM32H743 main control chip to complete basic space mission data processing functions.
3. The circuit system applied to a microsatellite mission computer according to claim 1, characterized in that, The analog quantity acquisition module consists of a triaxial magnetic field sensor and a temperature sensor.
4. The circuit system applied to a microsatellite mission computer according to claim 3, characterized in that, The triaxial magnetic field sensor reads the triaxial magnetic field strength using an RM3100 chip and transmits the data to the STM32 main control chip via the SPI bus. The temperature sensor reads the temperature using a TMP175 chip and then transmits the data via I... 2 The C bus transmits temperature data to the STM32H743 main control chip.