SiC DMOSFET device integrated with HJD and preparation method thereof

Abstract

The application discloses a SiC DMOSFET device integrated with HJD and a preparation method thereof, and comprises a metallized drain, an N+ substrate region and an N-epitaxial region which are sequentially arranged from bottom to top; a first P-base region and a second P-base region are arranged in the N-epitaxial region; a first P+ injection region and a fourth P+ injection region are arranged in the first P-base region and the second P-base region respectively; a second P+ injection region and a third P+ injection region are arranged in the N-epitaxial region; a first N+ injection region and a second N+ injection region are arranged in the first P-base region and the second P-base region respectively; an N-PolySi region is arranged on the N-epitaxial region between the second P+ injection region and the third P+ injection region; a first N-PolySi gate and a second N-PolySi gate are arranged in a first gate dielectric layer and a second gate dielectric layer respectively, and the first gate dielectric layer and the second gate dielectric layer are arranged in a designated gate region; and a metallized source is arranged on the upper surface of the device. The application improves the performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a SiC DMOSFET device with integrated HJD and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is a wide bandgap semiconductor material. Compared with traditional silicon materials, it has a wider bandgap, a higher saturated electron drift velocity, and higher thermal conductivity. It is more suitable for high temperature, high pressure, and high frequency environments, and has a broad market development prospect.

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in power electronic systems due to their high integration density, good thermal stability, and strong radiation resistance. SiC MOSFETs, as a new third-generation semiconductor device, offer lower conduction losses, higher voltage withstand capability, and greater power density than Si MOSFETs and even Si insulated-gate bipolar transistors (IGBTs). In other words, SiC MOSFETs have significant performance advantages and enormous development potential. Double-diffused metal-oxide-semiconductor field-effect transistors (DMOSFETs) are a widely used type of MOSFET. SiC MOSFETs primarily function as electronic switches in power electronic systems. When the SiC MOSFET is in the ON state, the minority carrier hole lifetime of the parasitic PIN diode in the drift region increases, and its reverse recovery deteriorates sharply, which leads to increased switching power consumption and reduced energy transfer efficiency. Therefore, it is usually necessary to connect a Schottky barrier diode (SBD) and a junction barrier Schottky diode (JBS) in parallel or integrate them in the SiC MOSFET to improve the performance of the SiC MOSFET body diode, thereby improving the operating efficiency of the SiC MOSFET.

[0004] However, while connecting a reverse parallel diode outside the SiC MOSFET can significantly improve the performance of the SiC MOSFET body diode, it will increase the area of ​​the entire module, increase the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance. On the other hand, integrating the SBD and JBS inside the SiC MOSFET requires a larger turn-on voltage. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a SiC DMOSFET device integrating a heterojunction diode (HJD) and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a SiC DMOSFET device with integrated HJD, comprising:

[0007] The metallized drain, N+ substrate region, and N- epitaxial region are stacked sequentially from bottom to top;

[0008] The first P-base region and the second P-base region are respectively disposed in the N-epitaxial regions at both ends of the device;

[0009] The device comprises a first P+ injection region, a second P+ injection region, a third P+ injection region, and a fourth P+ injection region. The first P+ injection region and the fourth P+ injection region are respectively disposed within the first P-base region and the second P-base region and are located at the left and right ends of the device, respectively. The second P+ injection region and the third P+ injection region are disposed within the N-epitaxy region, with the first P+ injection region being closer to the second P+ injection region and the third P+ injection region being closer to the fourth P+ injection region.

[0010] The first N+ injection region and the second N+ injection region are respectively located in the first P-base region and the second P-base region and are respectively adjacent to the first P+ injection region and the fourth P+ injection region;

[0011] An N-PolySi region is disposed on the N-epitaxial region between the second P+ implantation region and the third P+ implantation region;

[0012] A first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed on the first P-base region, the N-epitaxy region, a portion of the first N+ injection region and a portion of the second P+ injection region, and the second gate dielectric layer is disposed on the second P-base region, the N-epitaxy region, a portion of the second N+ injection region and a portion of the third P+ injection region;

[0013] The first N-PolySi gate and the second N-PolySi gate are respectively disposed in the first gate dielectric layer and the second gate dielectric layer;

[0014] The metallized source is disposed on the first P+ implantation region, the second P+ implantation region, the third P+ implantation region, the fourth P+ implantation region, the first N+ implantation region, the second N+ implantation region, the N-PolySi region, the first gate dielectric layer, and the second gate dielectric layer.

[0015] In one embodiment of the present invention, the parameters of the first P+ injection region, the second P+ injection region, the third P+ injection region, and the fourth P+ injection region are the same; the parameters of the first P-base region and the second P-base region are the same; and the parameters of the first N+ injection region and the second N+ injection region are the same.

[0016] In one embodiment of the present invention, the width and depth of the first P-base region and the second P-base region are the same; the width and depth of the first P+ injection region, the second P+ injection region, the third P+ injection region and the fourth P+ injection region are the same; the width and depth of the first N+ injection region and the second N+ injection region are the same.

[0017] In one embodiment of the present invention, the first P-base region has the same depth as the first P+ injection region; the depth of the first N+ injection region is less than the depth of the first P-base region.

[0018] In one embodiment of the present invention, the sum of the width of the first P+ injection region and the width of the first N+ injection region is less than the width of the first P-base region; the sum of the width of the fourth P+ injection region and the width of the second N+ injection region is less than the width of the second P-base region.

[0019] In one embodiment of the present invention, the N-PolySi region is disposed above the center of the N-epipolar region, and the left side of the N-PolySi region is vertically aligned with the right side of the second P+ implantation region, and the right side of the N-PolySi region is vertically aligned with the left side of the third P+ implantation region.

[0020] In one embodiment of the present invention, the width and depth of the first N-PolySi gate and the second N-PolySi gate are the same.

[0021] In one embodiment of the present invention, the width of the first N-PolySi gate is not less than the interval between the first N+ implantation region and the second P+ implantation region; the width of the second N-PolySi gate is not less than the interval between the second N+ implantation region and the third P+ implantation region.

[0022] In one embodiment of the present invention, the N-PolySi region is made of the same material as the first N-PolySi gate and the second N-PolySi gate.

[0023] Secondly, embodiments of the present invention provide a method for fabricating a SiC DMOSFET device with integrated HJD, comprising:

[0024] Select an N+ substrate region;

[0025] An N-epitaxial region is formed on the upper surface of the N+ substrate region;

[0026] Ion implantation is performed on the surfaces at both ends of the N-epitaxial region to form a first P-base region and a second P-base region;

[0027] Ion implantation is performed on the leftmost surface of the first P-base region, the rightmost surface of the second P-base region, and the central surface of the N-epitaxial region to sequentially form a first P+ implantation region in the first P-base region, a second P+ implantation region and a third P+ implantation region in the N-epitaxial region, and a fourth P+ implantation region in the second P-base region.

[0028] Ion implantation is performed on the surfaces of the first P-base region and the second P-base region to form a first N+ implantation region adjacent to the first P+ implantation region and a second N+ implantation region adjacent to the fourth P+ implantation region;

[0029] Gate dielectric material is deposited on the first P-base region, the N-epipolar region, a portion of the first N+ implantation region and a portion of the second P+ implantation region, and on the second P-base region, the N-epipolar region, a portion of the second N+ implantation region and a portion of the third P+ implantation region;

[0030] A first N-PolySi gate and a second N-PolySi gate are formed on the gate dielectric material, respectively;

[0031] An N-PolySi region is formed on the N-epitaxial region located between the second P+ implantation region and the third P+ implantation region;

[0032] Continue to deposit gate dielectric materials to form a first gate dielectric layer and a second gate dielectric layer on a portion of the first N+ implantation region, a portion of the second P+ implantation region, the first N-PolySi gate, and a portion of the second N+ implantation region, a portion of the third P+ implantation region, and the second N-PolySi gate;

[0033] A metallized drain is formed on the lower surface of the N+ substrate region;

[0034] Metallized sources are formed on the first P+ implantation region, the second P+ implantation region, the third P+ implantation region, the fourth P+ implantation region, the first N+ implantation region, the second N+ implantation region, the N-PolySi region, the first gate dielectric layer, and the second gate dielectric layer.

[0035] The beneficial effects of this invention are:

[0036] The SiC DMOSFET device with integrated HJD proposed in this invention improves device performance. Specifically, the contact between the N-PolySi region and the N-epitaxial region in the device structure is a heterojunction contact, that is, an HJD structure is integrated inside the SiC MOSFET device, replacing the conventional SiC... The SBD or JBS structure integrated within the MOSFET device has a lower turn-on voltage due to the smaller barrier difference between the N-PolySi region and the N-epitaxial region, further reducing switching losses and improving the device's energy conversion efficiency. The second and third P+ injection regions in the N-epitaxial region of the device structure jointly shield the electric field, protecting the N-PolySi region, the first gate dielectric layer, the second gate dielectric layer, the first N-PolySi gate, and the second N-PolySi gate from the influence of high electric fields, thus improving the device's breakdown characteristics and withstand voltage. The gate in the device structure is divided into a first N-PolySi gate and a second N-PolySi gate. Compared to the general DMOSFET structure, this split gate structure forms an HJD structure internally, significantly reducing gate capacitance, effectively lowering switching losses, and improving device area utilization.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a SiC DMOSFET device with integrated HJD provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the fabrication method of the SiC DMOSFET device with integrated HJD provided in the embodiment of the present invention;

[0040] Figure 3 (a)~ Figure 3 (h) is a schematic diagram of the structure corresponding to the fabrication method of the SiC DMOSFET device with integrated HJD provided in the embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1-N+ substrate region; 2-N-epitaxy region; 3-first P-base region; 4-second P-base region; 5-first P+ implantation region; 6-second P+ implantation region; 7-third P+ implantation region; 8-fourth P+ implantation region; 9-first N+ implantation region; 10-second N+ implantation region; 11-N-PolySi region; 12-first gate dielectric layer; 13-first N-PolySi gate; 14-second N-PolySi gate; 15-metallized drain; 16-metallized source; 17-second gate dielectric layer. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0044] Firstly, in order to further improve the performance of the device, this invention proposes a new device structure, please refer to [link to relevant documentation]. Figure 1 This invention provides a SiC DMOSFET device with integrated HJD, comprising:

[0045] The metallized drain 15, the N+ substrate region 1, and the N- epitaxial region 2 are stacked sequentially from bottom to top;

[0046] The first P-base region 3 and the second P-base region 4 are respectively disposed in the N-epitaxial regions 2 at both ends of the device;

[0047] The device is divided into a first P+ injection region 5, a second P+ injection region 6, a third P+ injection region 7, and a fourth P+ injection region 8. The first P+ injection region 5 and the fourth P+ injection region 8 are respectively disposed in the first P-base region 3 and the second P-base region 4 and are located at the left and right ends of the device, respectively. The second P+ injection region 6 and the third P+ injection region 7 are disposed in the N-epitaxy region 2, with the first P+ injection region 5 close to the second P+ injection region 6 and the third P+ injection region 7 close to the fourth P+ injection region 8.

[0048] The first N+ injection region 9 and the second N+ injection region 10 are respectively located in the first P-base region 3 and the second P-base region 4 and are respectively adjacent to the first P+ injection region 5 and the fourth P+ injection region 8.

[0049] The N-PolySi region 11 is disposed on the N-epitaxial region 2 between the second P+ implantation region 6 and the third P+ implantation region 7;

[0050] A first gate dielectric layer 12 and a second gate dielectric layer 17 are disposed on a first P-base region 3, an N-epipolar region 2, a portion of a first N+ implantation region 9 and a portion of a second P+ implantation region 6, and a second gate dielectric layer 17 are disposed on a second P-base region 4, an N-epipolar region 2, a portion of a second N+ implantation region 10 and a portion of a third P+ implantation region 7.

[0051] The first N-PolySi gate 13 and the second N-PolySi gate 14 are respectively disposed in the first gate dielectric layer 12 and the second gate dielectric layer 17;

[0052] The metallized source 16 is disposed on the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, the N-PolySi region 11, the first gate dielectric layer 12, and the second gate dielectric layer 17.

[0053] In this embodiment of the invention, the N+ substrate region 1 has a thickness of 1μm to 100μm and a doping concentration of 4×10⁻⁶. 18 cm -3 ~6×10 18 cm -3 The SiC substrate. More preferably, the N+ substrate region 1 has a thickness of 3 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 SiC substrate.

[0054] In this embodiment of the invention, the N-epitaxial region 2 has a thickness of 10 μm to 500 μm and a doping concentration of 7 × 10⁻⁶. 15 cm -3 ~9×10 15 cm -3 The SiC epitaxial region. More preferably, the N-epitaxial region 2 is a SiC epitaxial region with a thickness of 25 μm and a doping concentration of 8 × 10⁻⁶. 15 cm -3 The SiC epitaxial region.

[0055] In this embodiment of the invention, the parameters of the first P-base region 3 and the second P-base region 4 are the same. The first P-base region 3 and the second P-base region 4 are symmetrically arranged and have the same width and depth. For example, the depth of the first P-base region 3 and the second P-base region 4 within the N-epitaxial region 2 are both 0.5 μm to 5 μm, the width is both 3 μm to 4 μm, the implanted ions are both aluminum ions, and the ion implantation concentration is both 2 × 10⁻⁶. 17 cm -3 ~4×1017 cm -3 More preferably, the first P-base region 3 and the second P-base region 4 both have a depth of 0.8 μm and a width of 3.5 μm within the N-epitaxial region 2, are implanted with aluminum ions, and have an ion implantation concentration of 3 × 10⁻⁶. 17 cm -3 .

[0056] In this embodiment of the invention, the parameters of the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, and the fourth P+ implantation region 8 are the same. The width and depth of the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, and the fourth P+ implantation region 8 are the same. The depth of the first P-base region 3 is the same as that of the first P+ implantation region 5. For example, the depths of the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, and the fourth P+ implantation region 8 within the first P-base region 3, the second P-base region 4, and the N-epitaxial region 2 are all 0.5 μm to 5 μm, the widths are all 1 μm to 2 μm, the implanted ions are all aluminum ions, and the ion implantation concentration is all 0.5 × 10⁻⁶. 19 cm -3 ~1.5×10 19 cm -3 More preferably, the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, and the fourth P+ implantation region 8 are all located within the first P-base region 3, the second P-base region 4, and the N-epipolar region 2, respectively, with a depth of 0.8 μm, a width of 1.5 μm, implanted ions of aluminum ions, and an ion implantation concentration of 1 × 10⁻⁶. 19 cm -3 .

[0057] In this embodiment of the invention, the parameters of the first N+ implantation region 9 and the second N+ implantation region 10 are the same. The width and depth of the first N+ implantation region 9 and the second N+ implantation region 10 are the same. The depth of the first N+ implantation region 9 is less than the depth of the first P-base region 3. For example, the depth of both the first N+ implantation region 9 and the second N+ implantation region 10 is 0.1 μm to 2 μm, the width is both 1 μm to 2 μm, the implanted ions are both phosphorus ions, and the ion implantation concentration is 0.5 × 10⁻⁶. 19 cm -3 ~1.5×10 19 cm -3 More preferably, the depth of the first N+ implantation region 9 and the width of the second N+ implantation region 10 are both 0.2 μm, both are 1.5 μm, both are implanted with phosphorus ions, and both have an ion implantation concentration of 1 × 10⁻⁶. 19 cm -3 .

[0058] In this embodiment of the invention, the sum of the widths of the first P+ injection region 5 and the first N+ injection region 9 is less than the width of the first P-base region 3; the sum of the widths of the fourth P+ injection region 8 and the second N+ injection region 10 is less than the width of the second P-base region 4. For example, if the widths of the first P+ injection region 5, the fourth P+ injection region 8, the first N+ injection region 9, and the second N+ injection region 10 are all 1.5 μm, and the widths of the first P-base region 3 and the second P-base region 4 are both 3.5 μm, then the channel length formed in the first P-base region 3 and the second P-base region 4 is 0.5 μm.

[0059] In this embodiment of the invention, the N-PolySi region 11 is disposed above the center of the N-epitaxial region 2, and the left side of the N-PolySi region 11 is vertically aligned with the right side of the second P+ implantation region 6, and the right side of the N-PolySi region 11 is vertically aligned with the left side of the third P+ implantation region 7. For example, the N-PolySi region 11 has a thickness of 0.1 μm to 5 μm, a width of 0.1 μm to 5 μm, and a doping concentration of 0.5 × 10⁻⁶. 20 cm -3 ~1.5×10 20 cm -3 The N-PolySi is preferred. More preferably, the N-PolySi region 11 has a thickness of 1 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 The N-PolySi region 11 and the N-epitaxial region 2 are heterojunction contacts.

[0060] In this embodiment of the invention, the width and depth of the first N-PolySi gate 13 and the second N-PolySi gate 14 are the same. The N-PolySi region 11 is made of the same material as the first N-PolySi gate 13 and the second N-PolySi gate 14. For example, the thickness of the first N-PolySi gate 13 and the width of the second N-PolySi gate 14 are both 0.1 μm to 5 μm, and the material is doped with a concentration of 0.5 × 10⁻⁶. 20 cm -3 ~1.5×10 20 cm -3 The N-PolySi material. More preferably, the first N-PolySi gate 13 and the second N-PolySi gate 14 both have a thickness of 1 μm and a width of 2 μm, and the material is doped with a concentration of 1 × 10⁻⁶. 20 cm -3The N-PolySi gate 13 has a width not less than the gap between the first N+ implantation region 9 and the second P+ implantation region 6. The left side of the first N-PolySi gate 13 is vertically aligned with the right side of the first N+ implantation region 9, or the left side of the first N-PolySi gate 13 is located on the first N+ implantation region 9, and the right side of the first N-PolySi gate 13 is vertically aligned with the left side of the second P+ implantation region 6, or the right side of the first N-PolySi gate 13 is vertically aligned with the right side of the second P+ implantation region 6. Located on the second P+ implantation region 6; the width of the second N-PolySi gate 14 is not less than the interval between the second N+ implantation region 10 and the third P+ implantation region 7, that is, the right side of the second N-PolySi gate 14 is vertically aligned with the left side of the second N+ implantation region 10, or the right side of the second N-PolySi gate 14 is located on the second N+ implantation region 10, and the left side of the second N-PolySi gate 14 is vertically aligned with the right side of the third P+ implantation region 7, or the left side of the second N-PolySi gate 14 is located on the third P+ implantation region 7.

[0061] In this embodiment of the invention, the first gate dielectric layer 12 and the second gate dielectric layer 17 respectively surround the first N-PolySi gate 13 and the second N-PolySi gate 14. The thickness of the first gate dielectric layer 12 and the second gate dielectric layer 17 surrounding the perimeter is 0.1μm to 2μm and the material is SiO2. More preferably, the thickness of the first gate dielectric layer 12 and the second gate dielectric layer 17 surrounding the perimeter is 0.1μm and the material is SiO2. Since the width of the first N-PolySi gate 13 is not less than the interval between the first N+ implantation region 9 and the second P+ implantation region 6, and the width of the second N-PolySi gate 14 is not less than the interval between the second N+ implantation region 10 and the third P+ implantation region 7, the first gate dielectric layer 12 under the first N-PolySi gate 13 covers the first P-base region 3, the N-epitaxial region 2, part of the first N+ implantation region 9, and part of the second P+ implantation region 6. Similarly, the second gate dielectric layer 17 under the second N-PolySi gate 14 covers the second P-base region 4, the N-epitaxial region 2, part of the second N+ implantation region 10, and part of the third P+ implantation region 7. All structures in contact with the first N-PolySi gate 13 and the second N-PolySi gate 14 are isolated by the first gate dielectric layer 12 and the second gate dielectric layer 17, respectively.

[0062] In this embodiment of the invention, the metal materials of both the metallized drain 15 and the metallized source 16 can be titanium, nickel, molybdenum, or tungsten. The metallized drain 15 has an ohmic contact with the N+ substrate region 1, and the metallized source 16 has ohmic contacts with the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, and the N-PolySi region 11.

[0063] In summary, the SiC DMOSFET device with integrated HJD proposed in this embodiment of the invention improves device performance. Specifically, the contact between the N-PolySi region 11 and the N-epitaxial region 2 in the device structure is a heterojunction contact, meaning that an HJD structure is integrated inside the SiC MOSFET device, replacing the conventional SiC... The SBD or JBS structure integrated inside the MOSFET device has a lower turn-on voltage (0.5V) due to the smaller barrier difference between the N-PolySi region 11 and the N-epitaxial region 2, further reducing switching losses and improving the device's energy conversion efficiency. The second P+ injection region 6 and the third P+ injection region 7 in the N-epitaxial region 2 of the device structure have a joint shielding effect, protecting the N-PolySi region 11, the first gate dielectric layer 12, the second gate dielectric layer 17, the first N-PolySi gate 13, and the second N-PolySi gate 14 from the influence of high electric fields, thus improving the device's breakdown characteristics and withstand voltage capability. The gate in the device structure is divided into the first N-PolySi gate 13 and the second N-PolySi gate 14. Compared with the general DMOSFET structure, a split gate structure is adopted, forming an HJD structure inside, which greatly reduces the gate capacitance, effectively reduces the device's switching losses, and improves the device's area utilization.

[0064] Secondly, please see Figure 2 This invention provides a method for fabricating a SiC DMOSFET device with integrated HJD, comprising the following steps:

[0065] S10, Select N+ substrate region 1.

[0066] In this embodiment of the invention, the N+ substrate region 1 is selected to be 1 μm to 100 μm in size and has a doping concentration of 4 × 10⁻⁶. 18 cm -3 ~6×10 18 cm -3 The SiC substrate was cleaned using RCA standard cleaning.

[0067] S20. An N-epitaxial region 2 is formed on the upper surface of the N+ substrate region 1.

[0068] Please see Figure 3(a) In this embodiment of the invention, metal-organic chemical vapor deposition (MOCVD) is used to epitaxially grow a material with a thickness of 10 μm to 500 μm and a doping concentration of 7 × 10⁻⁶ on N+ substrate region 1. 15 cm -3 ~9×10 15 cm -3 The SiC epitaxial region.

[0069] S30. Ion implantation is performed on the surfaces at both ends of the N-epipolar region 2 to form the first P-base region 3 and the second P-base region 4.

[0070] Please see Figure 3 (b) In this embodiment of the invention, a SiO2 layer is deposited on the surface of the N-epitaxial region 2, and photoresist is coated on it. Masks are placed on both sides of the N-epitaxial region 2, for example, at a depth of 3.5 μm. After exposure, development, etching, and photoresist removal, aluminum ions are implanted into the N-epitaxial region 2. The implantation depth is 0.5 μm to 5 μm, the width is 3 μm to 4 μm, and the ion implantation concentration is 2 × 10⁻⁶. 17 cm -3 ~4×10 17 cm -3 After implantation, annealing is performed to remove the SiO2 layer, ultimately forming the first P-base region 3 and the second P-base region 4 on both sides of the N-epitaxial region 2.

[0071] S40. Ion implantation is performed on the leftmost surface of the first P-base region 3, the rightmost surface of the second P-base region 4, and the central surface of the N-epitaxial region 2 to sequentially form the first P+ implantation region 5 in the first P-base region 3, the second P+ implantation region 6 and the third P+ implantation region 7 in the N-epitaxial region 2, and the fourth P+ implantation region 8 in the second P-base region 4.

[0072] Please see Figure 3 (c) In this embodiment of the invention, a SiO2 layer is deposited on the upper surface of the N-epipolar region 2, the first P-base region 3, and the second P-base region 4. Photoresist is then applied, and photomasks with a length of, for example, 1.5 μm are placed at intervals of, for example, 0.75 μm between the leftmost and rightmost edges of the first P-base region 3 and 0.75 μm between the rightmost and leftmost edges of the second P-base region 4. After exposure, development, etching, and photoresist removal, aluminum ion implantation is performed. The implantation depth is 0.5 μm to 5 μm, the width is 1 μm to 2 μm, and the ion implantation concentration is 0.5 × 10⁻⁶. 19 cm -3 ~1.5×10 19 cm -3After implantation, annealing is performed, and then the SiO2 layer is removed. Finally, the first P+ implantation region 5 is formed on the far left of the first P-base region 3, the second P+ implantation region 6 is formed on the far right of the second P-base region 4, and the second P+ implantation region 6 and the third P+ implantation region 7 are formed in the N-epitaxy region 2.

[0073] S50, Ion implantation is performed on the surfaces of the first P-base region 3 and the second P-base region 4 to form a first N+ implantation region 9 adjacent to the first P+ implantation region 5 and a second N+ implantation region 10 adjacent to the fourth P+ implantation region 8.

[0074] Please see Figure 3 (d) In this embodiment of the invention, a SiO2 layer is deposited on the upper surfaces of the N-epitaxy region 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, and the fourth P+ implantation region 8. Photoresist is then applied, and photomasks with a length of, for example, 1.5 μm are placed on the right side of the first P+ implantation region 5 and the left side of the fourth P+ implantation region 8. After exposure, development, etching, and photoresist removal, phosphorus ion implantation is performed on the first P-base region 3 and the second P-base region 4. The implantation depth is 0.1 μm to 2 μm, the width is 1 μm to 2 μm, and the ion implantation concentration is 0.5 × 10⁻⁶. 19 cm -3 ~1.5×10 19 cm -3 After implantation, annealing is performed, and then the SiO2 layer is removed. Finally, a first N+ implantation region 9 is formed adjacent to the right side of the first P+ implantation region 5, and a second N+ implantation region 10 is formed adjacent to the left side of the fourth P+ implantation region 8.

[0075] S60, deposit gate dielectric material on the first P-base region 3, N-epitaxy region 2, part of the first N+ implantation region 9 and part of the second P+ implantation region 6, and on the second P-base region 4, N-epitaxy region 2, part of the second N+ implantation region 10 and part of the third P+ implantation region 7, and form a first N-PolySi gate 13 and a second N-PolySi gate 14 on the gate dielectric material, respectively, and form an N-PolySi region 11 on the N-epitaxy region 2 located between the second P+ implantation region 6 and the third P+ implantation region 7.

[0076] Please see Figure 3(e) In this embodiment of the invention, a SiO2 layer is deposited on the upper surfaces of the N-epilithographic region 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, and the second N+ implantation region 10. Photoresist is then applied, and after exposure, development, etching, and photoresist removal, the SiO2 layer remains on the first P-base region 3, the N-epilithographic region 2, a portion of the first N+ implantation region 9, and a portion of the second P+ implantation region 6, as well as on the second P-base region 4, the N-epilithographic region 2, a portion of the second N+ implantation region 10, and a portion of the third P+ implantation region 10. The SiO2 layer deposited on region 7 serves as the gate dielectric material. Then, a SiO2 layer is deposited on the surface of the gate dielectric material, the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, and the second N+ implantation region 10. Photoresist is then applied, and after exposure, development, etching, and removal of the photoresist, gaps are left on the gate dielectric material and on the N-epitaxial region 2 between the second P+ implantation region 6 and the third P+ implantation region 7. An N-PolySi layer is then deposited therein, ultimately forming the first N-PolySi gate 13, the N-PolySi region 11, and the second N-PolySi gate 14. It can be seen that the N-PolySi region 11 uses the same material and the same fabrication process as the first N-PolySi gate 13 and the second N-PolySi gate 14, simplifying the fabrication process. The N-PolySi region 11 and the N-epitaxial region 2 form a heterojunction contact.

[0077] S70, continue to deposit gate dielectric material to form a first gate dielectric layer 12 and a second gate dielectric layer 17 on a portion of the first N+ implantation region 9, a portion of the second P+ implantation region 6 and the first N-PolySi gate 13, and on a portion of the second N+ implantation region 10, a portion of the third P+ implantation region 7 and the second N-PolySi gate 14.

[0078] Please see Figure 3 (f) In this embodiment of the invention, a SiO2 layer is deposited on the surface of the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, the first N-PolySi gate 13, the second N-PolySi gate 14, and the N-PolySi region 11. Photoresist is then coated on the surface. After exposure, development, etching, and removal of the photoresist, gate dielectric material is finally deposited on a portion of the first N+ implantation region 9, a portion of the second P+ implantation region 6, and the first N-PolySi gate 13, as well as on a portion of the second N+ implantation region 10, a portion of the third P+ implantation region 7, and the second N-PolySi gate 14 to form the first gate dielectric layer 12 and the second gate dielectric layer 17.

[0079] S80, a metallized drain 15 is formed on the lower surface of the N+ substrate region 1.

[0080] Please see Figure 3 (g) In this embodiment of the invention, an electron beam evaporation process is used to evaporate a drain metal, such as titanium, on the lower surface of the N+ substrate region 1 to form a metallized drain 15. The metallized drain 15 and the N+ substrate region 1 form an ohmic contact.

[0081] S90, a metallized source 16 is formed on the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, the N-PolySi region 11, the first gate dielectric layer 12, and the second gate dielectric layer 17.

[0082] Please see Figure 3 (h) In this embodiment of the invention, an electron beam evaporation process is used to evaporate a drain metal, such as titanium, onto the upper surfaces of the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, the N-PolySi region 11, the first gate dielectric layer 12, and the second gate dielectric layer 17 to form a metallized source 16. The metallized source 16 has ohmic contacts with the first P+ implantation region 5, the second P+ implantation region 6, the third P+ implantation region 7, the fourth P+ implantation region 8, the first N+ implantation region 9, the second N+ implantation region 10, and the N-PolySi region 11.

[0083] Finally, surface planarization of the device is performed to complete the process design.

[0084] As the method embodiments are basically similar to the device embodiments, the description is relatively simple, and relevant parts can be found in the description of the device embodiments.

[0085] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0086] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0087] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An integrated HJD SiC DMOSFET device, characterized by, The application relates to a metalized source and drain electrode semiconductor device. A metalized drain electrode, an N+ substrate region and an N- epitaxial region are sequentially stacked from bottom to top. A first P-base region and a second P-base region are arranged in the N- epitaxial region at both ends of the device. A first P+ implantation region, a second P+ implantation region, a third P+ implantation region and a fourth P+ implantation region are arranged in the first P-base region and the second P-base region at both ends of the device. A first N+ implantation region and a second N+ implantation region are arranged in the first P-base region and the second P-base region and adjacent to the first P+ implantation region and the fourth P+ implantation region. An N-PolySi region is arranged on the N- epitaxial region between the second P+ implantation region and the third P+ implantation region. A first gate dielectric layer and a second gate dielectric layer are arranged on the first P-base region, the N- epitaxial region, part of the first N+ implantation region and part of the second P+ implantation region, and on the second P-base region, the N- epitaxial region, part of the second N+ implantation region and part of the third P+ implantation region. A first N-PolySi gate and a second N-PolySi gate are arranged in the first gate dielectric layer and the second gate dielectric layer. A metalized source electrode is arranged on the first P+ implantation region, the second P+ implantation region, the third P+ implantation region, the fourth P+ implantation region, the first N+ implantation region, the second N+ implantation region, the N-PolySi region, the first gate dielectric layer and the second gate dielectric layer.

2. The integrated HJD SiC DMOSFET device of claim 1, wherein, The first P+ implantation region, the second P+ implantation region, the third P+ implantation region and the fourth P+ implantation region have the same parameters; the first P-base region and the second P-base region have the same parameters; and the first N+ implantation region and the second N+ implantation region have the same parameters.

3. The integrated HJD SiC DMOSFET device of claim 2, wherein, The first P-base region and the second P-base region have the same width and depth; the first P+ implantation region, the second P+ implantation region, the third P+ implantation region and the fourth P+ implantation region have the same width and depth; and the first N+ implantation region and the second N+ implantation region have the same width and depth.

4. The integrated HJD SiC DMOSFET device of claim 3, wherein, The first P-base region has the same depth as the first P+ implantation region; and the first N+ implantation region has a smaller depth than the first P-base region.

5. The integrated HJD SiC DMOSFET device of claim 1, wherein, The sum of the width of the first P+ implantation region and the width of the first N+ implantation region is smaller than the width of the first P-base region; and the sum of the width of the fourth P+ implantation region and the width of the second N+ implantation region is smaller than the width of the second P-base region.

6. The integrated HJD SiC DMOSFET device of claim 1, wherein, The N-PolySi region is disposed above the center of the N-epitaxial region, and the left side of the N-PolySi region is vertically aligned with the right side of the second P+ implant region, and the right side of the N-PolySi region is vertically aligned with the left side of the third P+ implant region.

7. The integrated HJD SiC DMOSFET device of claim 1, wherein, The first N-PolySi gate and the second N-PolySi gate have the same width and depth, respectively.

8. The integrated HJD SiC DMOSFET device of claim 1, wherein, The width of the first N-PolySi gate is not less than the interval between the first N+ implant region and the second P+ implant region, and the width of the second N-PolySi gate is not less than the interval between the second N+ implant region and the third P+ implant region.

9. The integrated HJD SiC DMOSFET device of claim 1, wherein, The N-PolySi region is made of the same material as the first N-PolySi gate and the second N-PolySi gate.

10. A method of fabricating an integrated HJD SiC DMOSFET device, characterized by, Comprising: selecting an N+ substrate region; forming an N-epitaxial region on the upper surface of the N+ substrate region; forming a first P-base region and a second P-base region by ion implantation on the surfaces at both ends of the N-epitaxial region; forming a first P+ implant region in the first P-base region, a second P+ implant region and a third P+ implant region in the N-epitaxial region, and a fourth P+ implant region in the second P-base region in sequence by ion implantation on the leftmost surface of the first P-base region, the rightmost surface of the second P-base region, and the central surface of the N-epitaxial region; forming a first N+ implant region adjacent to the first P+ implant region and a second N+ implant region adjacent to the fourth P+ implant region by ion implantation on the surfaces of the first P-base region and the second P-base region; depositing gate dielectric material on the first P-base region, the N-epitaxial region, part of the first N+ implant region, and part of the second P+ implant region, and on the second P-base region, the N-epitaxial region, part of the second N+ implant region, and part of the third P+ implant region, and forming a first N-PolySi gate and a second N-PolySi gate on the gate dielectric material, respectively, and forming an N-PolySi region on the N-epitaxial region between the second P+ implant region and the third P+ implant region; depositing gate dielectric material on part of the first N+ implant region, part of the second P+ implant region, the first N-PolySi gate, and on part of the second N+ implant region, part of the third P+ implant region, the second N-PolySi gate to form a first gate dielectric layer and a second gate dielectric layer; forming a metalized drain on the lower surface of the N+ substrate region; forming a metalized source on the first P+ implant region, the second P+ implant region, the third P+ implant region, the fourth P+ implant region, the first N+ implant region, the second N+ implant region, the N-PolySi region, the first gate dielectric layer, and the second gate dielectric layer.

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