Semiconductor circuit

Abstract

An embodiment of the present application provides a semiconductor circuit provided with a trans-impedance amplifier capable of converting an input current into a voltage with high precision. The semiconductor circuit of the present embodiment is provided with: a trans-impedance amplifier TIA having a first input terminal, a second input terminal, and a first output terminal, the first input terminal being supplied with a reference voltage VB, the second input terminal being supplied with an input current, the trans-impedance amplifier TIA converting the input current into an output voltage VINP and outputting the output voltage VINP from the first output terminal; and a trans-impedance amplifier TIAr having a third input terminal, a fourth input terminal, and a second output terminal and provided with the same circuit configuration as the trans-impedance amplifier TIA, the third input terminal being supplied with the reference voltage VB, the trans-impedance amplifier TIAr outputting an output voltage VINN from the second output terminal.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-153422 (filed on September 21, 2021). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0002] This invention relates to semiconductor circuits that include a transimpedance amplifier. Background Technology

[0003] It is known that there exists a transimpedance amplifier that converts input current into voltage. Summary of the Invention

[0004] This embodiment provides a semiconductor circuit having a transimpedance amplifier capable of converting input current into voltage with high precision.

[0005] The semiconductor circuit of this embodiment includes: a first transimpedance amplifier having a first input terminal, a second input terminal, and a first output terminal, wherein a reference voltage is supplied to the first input terminal, an input current is supplied to the second input terminal, the first transimpedance amplifier converts the input current into a first output voltage, and outputs the first output voltage from the first output terminal; and a second transimpedance amplifier having a third input terminal, a fourth input terminal, and a second output terminal, and having the same circuit configuration as the first transimpedance amplifier, wherein the reference voltage is supplied to the third input terminal, and the second transimpedance amplifier outputs the second output voltage from the second output terminal. Attached Figure Description

[0006] Figure 1 This is a circuit diagram showing the configuration of the semiconductor circuit in the first embodiment.

[0007] Figure 2 This is a circuit diagram showing the configuration of the variable resistor circuit in the first embodiment.

[0008] Figure 3 This is a circuit diagram showing the configuration of the switching circuit within the variable resistor circuit in the first embodiment.

[0009] Figure 4 This is a circuit diagram showing other configuration examples of the input / output section in the first embodiment.

[0010] Figure 5 This is a graph showing the relationship between the effective resistance value of the variable resistor circuit in the first embodiment and the power supply voltage.

[0011] Figure 6 This is a circuit diagram showing the configuration of the semiconductor circuit in the second embodiment.

[0012] Figure 7 This is a circuit diagram showing the configuration of the semiconductor circuit in the third embodiment.

[0013] Figure 8 This is a circuit diagram showing the configuration of the semiconductor circuit in the fourth embodiment. Detailed Implementation

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having the same function and structure will be given common reference numerals in the accompanying drawings. Furthermore, the embodiments shown below illustrate apparatus and methods for embodying the technical concept of these embodiments, and are not intended to limit the materials, shapes, structures, and arrangements of the constituent components to the embodiments described below.

[0015] Furthermore, functional modules can be implemented as modules composed of either or a combination of hardware and computer software. Functional modules do not necessarily need to be divided as in the following example. For instance, some functions can be executed by functional modules different from those illustrated. Moreover, the illustrated functional modules can be further divided into smaller functional sub-modules.

[0016] 1. First Implementation Method

[0017] The semiconductor circuit of the first embodiment will be described below.

[0018] 1.1 Structure of Semiconductor Circuits

[0019] Figure 1 This is a circuit diagram showing the configuration of the semiconductor circuit in the first embodiment. The semiconductor circuit 1 includes two transimpedance amplifiers TIA and TIAr, two ESD (electro-static discharge) protection input / output sections IO and IOr, a differential input analog-to-digital converter circuit (also referred to as ADC) 11, and an input terminal WE.

[0020] Input current is supplied to the input terminal WE. The transimpedance amplifiers TIA and TIAAr are circuits that convert the input current into voltage. More specifically, they are circuits that amplify the current flowing through the transimpedance amplifier by impedance transformation and output it as a voltage signal. The transimpedance amplifier TIAAr is a replica circuit of the transimpedance amplifier TIA.

[0021] The input / output section IO is an ESD protection circuit that protects the semiconductor circuit 1 from surge voltages such as static electricity entering from the input terminal WE, or prevents malfunctions caused by surge voltages. The input / output section IOr is a replica circuit of the input / output section IO.

[0022] The differential input analog-to-digital converter 11 outputs a digital signal from the two output voltages of the differential input. That is, the analog-to-digital converter 11 receives two output voltages VINP and VINN from the transimpedance amplifiers TIA and TIAr, removes the in-phase signal between the output voltages VINP and VINN, converts it into a digital value, and outputs the output signal DOUT.

[0023] As described above, the transimpedance amplifier TIA and the input / output section IOr are replicas of the transimpedance amplifier TIA and the input / output section IOr. That is, the transimpedance amplifier TIA and the input / output section IOr have the same circuit configuration as the transimpedance amplifier TIA and the input / output section IOr. Specifically, the transimpedance amplifier TIA has the same circuit elements as the transimpedance amplifier TIA. The circuit elements of the transimpedance amplifier TIA have approximately the same circuit constants as the circuit elements of the transimpedance amplifier TIA. The input / output section IOr has the same circuit elements as the input / output section IO. The circuit elements of the input / output section IOr have approximately the same circuit constants as the circuit elements of the input / output section IO.

[0024] From now on, the path consisting of the input terminal WE, the input / output section IO, and the transimpedance amplifier TIA will be called the measurement signal path. In addition, the path consisting of the replication circuit, i.e., the input / output section IOr, and the transimpedance amplifier TIAr will be called the error (or analog) signal path.

[0025] 1.1.1 Structure of a Transimpedance Amplifier

[0026] Next, the structure of the transimpedance amplifiers TIA and TIAr will be explained.

[0027] like Figure 1 As shown, the transimpedance amplifier TIA has an operational amplifier (or operational amplifier) ​​OP, a variable resistor circuit VR, and a voltage source supplying a reference voltage VB. The operational amplifier OP amplifies the input signal and outputs it. The variable resistor circuit VR is a feedback resistor, a circuit whose resistance value can be changed.

[0028] The transimpedance amplifier TIAr consists of an operational amplifier OPr, a variable resistor circuit VRr, and a voltage source supplying a reference voltage VB. The operational amplifier OPr has the same circuit elements and circuit constants as the operational amplifier OP. The variable resistor circuit VRr has the same circuit elements and circuit constants as the variable resistor circuit VR.

[0029] The following section explains the construction of the variable resistor circuits VR and VRr.

[0030] Figure 2This is a circuit diagram showing the configuration of a variable resistor circuit VR (or VRr). The negative input terminal (or inverting input terminal) of the operational amplifier OP is connected in series with a switching circuit S0, resistors R1, R2, ..., Rn (n is a natural number greater than 1) to the output terminal of the operational amplifier OP. A switching circuit S1 is connected between the node between switching circuit S0 and resistor R1 and the node between resistor R1 and resistor R2. A switching circuit S2 is connected between the node between switching circuit S0 and resistor R1 and the node between resistor R2 and resistor R3. Similarly, a switching circuit Sn is connected between the node between switching circuit S0 and resistor R1 and the node between resistor Rn and the output terminal of the operational amplifier OP. Furthermore, the configuration of the variable resistor circuit VRr is the same as that of the variable resistor circuit VR described above.

[0031] exist Figure 3 The diagram shows the configuration of the switching circuit S0 or Sn within the variable resistor circuit VR (or VRr). The switching circuit S0 or Sn includes a p-channel MOS field-effect transistor (hereinafter referred to as a pMOS transistor) T1 and an n-channel MOS field-effect transistor (hereinafter referred to as an nMOS transistor) T2.

[0032] The drain (or source) of pMOS transistor T1 is connected to the source (or drain) of nMOS transistor T2. The source (or drain) of pMOS transistor T1 is connected to the drain (or source) of nMOS transistor T2.

[0033] A control signal CS0 is input to the gate of the nMOS transistor T2 in the switching circuit S0. A control signal CS0b, which is the inverted signal of the control signal CS0, is input to the gate of the pMOS transistor T1 in the switching circuit S0. Furthermore, a power supply voltage VDD is supplied to the back gate of the pMOS transistor T1 in the switching circuit S0. Also, a ground voltage GND is supplied to the back gate of the nMOS transistor T2 in the switching circuit S0.

[0034] A control signal CSn is input to the gate of nMOS transistor T2 in the switching circuit Sn. A signal CSnb, which is the inverted signal of the control signal CSn, is input to the gate of pMOS transistor T1 in the switching circuit Sn. Furthermore, a power supply voltage VDD is supplied to the back gate of pMOS transistor T1 in the switching circuit Sn. Also, a ground voltage GND is supplied to the back gate of nMOS transistor T2 in the switching circuit Sn.

[0035] In such a variable resistor circuit VR, the resistance value RTIA can be changed by setting the switching circuits S0 to Sn to a closed state (or connected state) or an open state (or disconnected state) through the control signals CS0~CSn and CS0b~CSnb.

[0036] As described above, the variable resistor circuit VRr has the same circuit configuration as the variable resistor circuit VR. Control signals CS0 to CSn and CS0b to CSnb are input to the switching circuits S0 to Sn of the variable resistor circuit VRr in the same way as those to the switching circuit of the variable resistor circuit VR. Therefore, the resistance value RTIAr of the variable resistor circuit VRr is set to approximately the same value as the resistance value RTIA of the variable resistor circuit VR.

[0037] In a variable resistor circuit VR, for example, a junction leakage current Isw is generated at the pn junction of pMOS transistors T1 and nMOS transistors T2 in switching circuits S0 to Sn. Similarly, in a variable resistor circuit VRr, a junction leakage current Isw is generated at the pn junction of pMOS transistors T1 and nMOS transistors T2 in switching circuits S0 to Sn.

[0038] Here, the variable resistor circuit VRr has the same circuit configuration as the variable resistor circuit VR. That is, the variable resistor circuit VRr has the same circuit elements and circuit constants as the variable resistor circuit VR. Specifically, both the variable resistor circuits VR and VRr have pMOS transistor T1, nMOS transistor T2, and resistors R1 to Rn. The pMOS transistors T1 and T2, and resistors R1 to Rn of the variable resistor circuit VRr have approximately the same circuit constants as those of the variable resistor circuit VR. Therefore, the leakage current Isw generated in the variable resistor circuits VR and VRr is approximately the same, that is, it has approximately the same current value.

[0039] 1.1.2 Structure of Input / Output Section (ESD Protection Circuit)

[0040] Next, the structure of the input / output (IO) section and IOR will be explained.

[0041] like Figure 1 As shown, in the signal path, the input / output section IO is connected to the negative input terminal of the operational amplifier OP. The input / output section IO includes diodes D1 and D2. Diode D1 is forward-connected from the ground voltage node supplied with ground voltage GND to the node connected to the negative input terminal. Diode D2 is forward-connected from the node of the negative input terminal to the power supply voltage node supplied with power supply voltage VDD.

[0042] On the other hand, in the error signal path, the input / output section IOr is connected to the negative input terminal of the operational amplifier OPr. The input / output section IOr has the same circuit elements and circuit constants as the input / output section IO. That is, the input / output section IOr, like the input / output section IO, has diodes D1 and D2. Diode D1 is forward-connected from the ground voltage node to the node connected to the negative input terminal. Diode D2 is forward-connected from the node of the negative input terminal to the power supply voltage node.

[0043] In the input / output section IO, for example, a leakage current Iio is generated at the pn junction of diodes D1 and D2 present in the input / output section IO. Similarly, in the input / output section IOr, a leakage current Iio is generated at the pn junction of diodes D1 and D2 present in the input / output section IOr.

[0044] Here, the input / output section IOr has the same circuit configuration as the input / output section IO. That is, the input / output section IOr has the same circuit elements and circuit constants as the input / output section IO. Specifically, both the input / output sections IO and IOr have diodes D1 and D2. The diodes D1 and D2 of the input / output section IOr have approximately the same circuit constants as those of the diodes D1 and D2 of the input / output section IO. Therefore, the leakage current Iio generated in the input / output sections IO and IOr is approximately the same, that is, it has approximately the same current value.

[0045] also, Figure 4 This is a circuit diagram illustrating other configuration examples of the input / output section IO and IOr. The input / output section IO can be constructed using an nMOS transistor T3 and a pMOS transistor T4. The gate and drain of the nMOS transistor T3 are connected to the ground voltage node, and the source of the nMOS transistor T3 is connected to the negative input terminal of the operational amplifier OP. Furthermore, the gate and drain of the pMOS transistor T4 are connected to the power supply voltage node, and the source of the pMOS transistor T4 is connected to the negative input terminal of the operational amplifier OP.

[0046] Similarly, the input / output section IOr can also be composed of an nMOS transistor T3 and a pMOS transistor T4. The gate and drain of the nMOS transistor T3 are connected to the ground voltage node, and the source of the nMOS transistor T3 is connected to the negative input terminal of the operational amplifier OPr. Moreover, the gate and drain of the pMOS transistor T4 are connected to the power supply voltage node, and the source of the pMOS transistor T4 is connected to the negative input terminal of the operational amplifier OPr.

[0047] exist Figure 4In the configuration example shown, leakage current Iio is generated, for example, at the junction of nMOS transistor T3 and pMOS transistor T4 present in the input / output section IO. Similarly, leakage current Iio is generated at the junction of nMOS transistor T3 and pMOS transistor T4 present in the input / output section IOr.

[0048] Here, the nMOS transistor T3 and pMOS transistor T4 of the input / output section IOr have approximately the same circuit constants as those of the nMOS transistor T3 and pMOS transistor T4 of the input / output section IO. Therefore, the leakage current Iio generated in the input / output sections IO and IOr are approximately the same, that is, they have approximately the same current value.

[0049] The circuit connections in the semiconductor circuit 1 of the first embodiment will be described below.

[0050] like Figure 1 As shown, the input terminal WE is connected to the negative input terminal of the operational amplifier OP within the transimpedance amplifier TIA. Furthermore, the input terminal WE is connected to the output terminal of the operational amplifier OP via the variable resistor circuit VR within the transimpedance amplifier TIA. An input / output section IO is connected at the node between the negative input terminal of the operational amplifier OP and the input terminal WE.

[0051] The voltage source supplying the reference voltage VB is connected to the positive input terminal (or non-inverting input terminal) of the operational amplifier OP. Furthermore, the output terminal of the operational amplifier OP is connected to the first input terminal of the differential input analog-to-digital converter circuit 11.

[0052] Furthermore, the input / output section IOr is connected to the negative input terminal of the operational amplifier OPr of the transimpedance amplifier TIAr. The negative input terminal of the operational amplifier OPr is connected to the output terminal of the operational amplifier OPr via the variable resistor circuit VRr within the transimpedance amplifier TIAr.

[0053] The voltage source supplying the reference voltage VB is connected to the positive input terminal of the operational amplifier OPr. Furthermore, the output terminal of the operational amplifier OPr is connected to the second input terminal of the differential input analog-to-digital converter circuit 11.

[0054] 1.2 Operation of Semiconductor Circuits

[0055] The operation of the semiconductor circuit 1 in the first embodiment will now be described. Here, the operation when the current output sensor SE is connected to the input terminal WE will be explained.

[0056] If the current output sensor SE starts operating, the sensor current Isen flows through the current output sensor SE, supplying the reference voltage VB to the positive input terminal of the operational amplifier OP. Then, through the virtual short-circuit characteristic of the operational amplifier OP, the voltages at the input terminals WE and WE, and the negative input terminal of the operational amplifier OP, are set to the reference voltage VB supplied to the positive input terminal and stabilized.

[0057] Here, the impedance of the negative input terminal of the operational amplifier OP is very high. Therefore, the sensor current Isen flowing in the current output sensor SE originates from the output side of the operational amplifier OP, passes through the variable resistor circuit VR, and flows into the current output sensor SE. In this case, the output voltage VINP of the operational amplifier OP is set to the voltage obtained by adding the product of the resistance value RTIA of the variable resistor circuit VR and the sensor current Isen to the reference voltage VB.

[0058] Therefore, the output voltage VINP of the operational amplifier OP can be represented by the following equation (1).

[0059] VINP = VB + RTIA·Isen (1)

[0060] exist Figure 1 In the circuit shown, as described above, a leakage current Iio is generated in the input / output section IO, and a leakage current Isw is generated in the variable resistor circuit VR. If leakage currents Iio and Isw are generated, the current flowing in the variable resistor circuit VR decreases. Therefore, due to the error currents of the leakage currents Iio and Isw, the effective resistance value of the variable resistor circuit VR becomes erroneous. In particular, the higher the power supply voltage VDD, the greater the leakage current Isw generated in the switching circuits S0 to Sn of the variable resistor circuit VR. Therefore, the higher the power supply voltage VDD, the greater the error in the effective resistance value of the variable resistor circuit VR.

[0061] If leakage currents Iio and Isw are taken into account, then equation (1) is expressed by equation (2) below.

[0062] VINP=VB+RTIA·Isen-RTIA·(Iio+Isw) (2)

[0063] On the other hand, the output voltage VINN of the operational amplifier OPr in the transimpedance amplifier TIAr in the replication circuit (or error signal path) is as follows.

[0064] In the input / output section IOr and the variable resistor circuit VRr of the replication circuit, leakage currents Iio and Isw are generated in the same way as in the input / output section IO and the variable resistor circuit VRr that determine the signal path.

[0065] Therefore, the output voltage VINN of the operational amplifier OPr can be represented by the following equation (3).

[0066] VINN=VB-RTIA·(Iio+Isw) (3)

[0067] Here, the circuit elements and their constants of the input / output section IOr and the variable resistor circuit VRr in the replication circuit are the same as those of the input / output section IO and the variable resistor circuit VRr in the measurement signal path. Therefore, the leakage currents Iio and Isw generated in the replication circuit are approximately the same as those generated in the measurement signal path, i.e., they are roughly identical.

[0068] Output voltages VINP and VINN are input to a differential input analog-to-digital converter (ADC) 11. The ADC 11 obtains the voltage difference between VINP and VINN, further digitizes it, and outputs the output signal DOUT. That is, the ADC 11 removes the in-phase signal component between VINP and VINN, converts the voltage with the in-phase signal component removed into a digital value, and outputs the output signal DOUT.

[0069] Therefore, the output signal DOUT is represented by the following equation (4) (= equation (2) - equation (3)).

[0070] DOUT=D(VINP-VINN)=D(RTIA·Isen) (4)

[0071] In addition, D(X) represents the value obtained by converting the analog value X into a digital value X.

[0072] Therefore, the error in the effective resistance value of the variable resistor circuit VR caused by the leakage current Iio and Isw can be eliminated, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

[0073] As described above, in this embodiment, the error in the effective resistance value of the variable resistor circuit VR caused by leakage current generated in the input / output section IO and the variable resistor circuit VR can be reduced. Therefore, the effective resistance value of the variable resistor circuit VR, which serves as the frequency conversion gain in the transimpedance amplifier TIA, can be set to a constant independent of the power supply voltage VDD. Figure 5 The diagram shows the relationship between the effective resistance value of the variable resistor circuit VR and the power supply voltage VDD. For example... Figure 5As shown, even if the power supply voltage VDD changes, the effective resistance value of the variable resistor circuit VR remains constant. Because the effective resistance value of the variable resistor circuit VR can be set to constant, the transimpedance amplifier TIA can have high-precision current-to-voltage conversion characteristics.

[0074] 1.3 Effects of the first implementation method

[0075] According to the first embodiment, a semiconductor circuit is provided that has a transimpedance amplifier capable of converting input current into voltage with high precision.

[0076] The effects of the first embodiment will now be explained. In a transimpedance amplifier that converts input current into voltage, in order to convert a small input current into a large output voltage and to make the frequency conversion gain variable, it is necessary to install a resistor circuit with a very large resistance value and a switching circuit for switching the resistance value.

[0077] When a variable resistor circuit with high resistance and variable function is mounted on a semiconductor silicon substrate, a problem arises in the frequency conversion gain that converts the current in the transimpedance amplifier into voltage due to leakage current in the switching circuit used to implement the switching function and leakage current in the input / output section used for ESD damage protection.

[0078] The semiconductor circuit 1 of the first embodiment includes a replicated transimpedance amplifier TIA and an input / output section IOr relative to the transimpedance amplifier TIA and the input / output section IOr. The transimpedance amplifier TIA and the input / output section IOr are circuits that accurately simulate the leakage currents Iio and Isw, which are important factors affecting the error of the frequency conversion gain of the transimpedance amplifier TIA.

[0079] The differential input analog-to-digital converter 11 removes the error component from the output voltage VINP of the transimpedance amplifier TIA by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA and the output voltage VINN of the transimpedance amplifier TIAAr. Furthermore, the differential input analog-to-digital converter 11 converts the voltage with the error component removed into a digital output signal DOUT.

[0080] In the first embodiment, the transimpedance amplifier TIA and the input / output section IOr of the error signal path are configured as replicas of the transimpedance amplifier TIA and the input / output section IOr of the measurement signal path. Therefore, when the power supply voltage VDD changes and the leakage current changes, especially when the power supply voltage VDD increases and the leakage current increases, the leakage current in the error signal path also increases in accordance with the increase in the leakage current in the measurement signal path. In other words, the transimpedance amplifier TIA and the input / output section IOr have the same circuit elements and circuit constants as the transimpedance amplifier TIA and the input / output section IOr. Therefore, when the power supply voltage VDD changes, the leakage current in the error signal path and the leakage current in the measurement signal path also change similarly, and these current quantities are approximately the same.

[0081] Furthermore, when both temperature and leakage current change, the leakage current in the error signal path also changes accordingly, just as the leakage current in the measurement signal path changes. That is, when temperature changes, the leakage current in the error signal path and the leakage current in the measurement signal path change in the same way, and these current quantities are approximately the same.

[0082] Therefore, by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA in the measurement signal path and the output voltage VINN of the transimpedance amplifier TIAar in the error signal path, the error in the effective resistance value of the variable resistor circuit VR caused by leakage current in the measurement signal path can be eliminated, and the effective resistance value of the variable resistor circuit VR can be maintained at a predetermined value. Thus, in the semiconductor circuit 1 of the first embodiment, the input current can be converted into voltage with high accuracy regardless of changes in the power supply voltage VDD and temperature.

[0083] As described above, the semiconductor circuit 1 according to the first embodiment can realize a transimpedance amplifier that can convert input current into voltage with high accuracy. That is, it can realize a transimpedance amplifier with high-precision current-to-voltage conversion characteristics.

[0084] The first embodiment described above is given by way of example and is not intended to limit the scope of the invention. The first embodiment can be implemented in various other ways.

[0085] 2. Second Implementation Method

[0086] The semiconductor circuit of the second embodiment will now be described. In the first embodiment described above, the output voltages of the transimpedance amplifiers TIA and TIA are input to a differential input analog-to-digital converter circuit. However, in the second embodiment, the output voltages of the transimpedance amplifiers TIA and TIA are input to a single-ended input analog-to-digital converter circuit via a differential input / single-ended output converter amplifier. In the second embodiment, the differences from the first embodiment will be mainly described. Other configurations and operations not described are the same as in the first embodiment.

[0087] 2.1 Structure of Semiconductor Circuits

[0088] Figure 6 This is a circuit diagram showing the configuration of the semiconductor circuit in the second embodiment. The semiconductor circuit 2 includes two transimpedance amplifiers TIA and TIAr, two ESD protection input / output sections IO and IOr, a differential input / single-ended output converter amplifier (or differential input amplifier circuit) OPd, a single-ended input analog-to-digital converter circuit 12, and an input terminal WE.

[0089] The transimpedance amplifiers TIA and TIAr, and the input / output units IO and IOr included in semiconductor circuit 2 are the same as in the first embodiment, so their description is omitted.

[0090] The output terminal of operational amplifier OP within transimpedance amplifier TIA is connected to the negative input terminal of differential input / single-ended output converter amplifier OPd via resistor Ra. The output terminal of operational amplifier OPr within transimpedance amplifier TIAr is connected to the positive input terminal of output converter amplifier OPd via resistor Ra. The voltage source supplying the reference voltage VB is connected to the positive input terminal of converter amplifier OPd via resistor Rb. The output terminal of differential input / single-ended output converter amplifier OPd is connected to the negative input terminal of converter amplifier OPd via resistor Rb.

[0091] Furthermore, the output terminal of the differential input / single-ended output converter amplifier OPd is connected to the input terminal of the analog-to-digital converter circuit 12. Moreover, the output signal DOUT is output from the output terminal of the single-ended input analog-to-digital converter circuit 12.

[0092] 2.2 Operation of Semiconductor Circuits

[0093] The operation of the semiconductor circuit 2 in the second embodiment will be described below.

[0094] The operation of the transimpedance amplifier TIA and input / output section IO for measuring the signal path, and the operation of the transimpedance amplifier TIAr and input / output section IOr for the error signal path are the same as in the first embodiment described above. Therefore, the output voltage VINP is output from the operational amplifier OP in the transimpedance amplifier TIA, and the output voltage VINN is output from the operational amplifier OPr in the transimpedance amplifier TIAr.

[0095] The output voltage VINP is input to the negative input terminal of the differential input / single-ended output converter amplifier OPd, and the output voltage VINN is input to the positive input terminal of the converter amplifier OPd. The converter amplifier OPd obtains the voltage difference between the output voltage VINP and the output voltage VINN, and outputs the output voltage VOUT. That is, the converter amplifier OPd removes the in-phase signal component between the output voltage VINP and the output voltage VINN, and outputs the output voltage VOUT with the in-phase signal component removed.

[0096] The analog-to-digital converter circuit 12 converts the output voltage VOUT of the analog signal into a digital value and outputs the output signal DOUT.

[0097] Based on the above, in the second embodiment, the error in the effective resistance value of the variable resistor circuit VR caused by the leakage current Iio and Isw can be removed in the same way as in the first embodiment, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

[0098] 2.3 Effects of the Second Implementation Method

[0099] According to the second embodiment, a semiconductor circuit is provided that has a transimpedance amplifier capable of converting input current into voltage with high precision.

[0100] In the second embodiment, the semiconductor circuit 2 includes a replicated transimpedance amplifier TIA and an input / output section IOr relative to the transimpedance amplifier TIA and the input / output section IOr. The transimpedance amplifier TIA and the input / output section IOr are circuits that accurately simulate the leakage currents Iio and Isw, which are important factors affecting the error of the frequency conversion gain of the transimpedance amplifier TIA.

[0101] The differential input / single-ended output converter amplifier OPd removes the error component from the output voltage VINP of the transimpedance amplifier TIA by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA and the output voltage VINN of the transimpedance amplifier TIA. Furthermore, the analog-to-digital converter circuit 12 converts the output voltage VOUT, from which the error component has been removed, into a digital output signal DOUT.

[0102] In the second embodiment, by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA in the measurement signal path and the output voltage VINN of the transimpedance amplifier TIAar in the error signal path, the error in the effective resistance value of the variable resistor circuit VR caused by leakage current in the measurement signal path can be eliminated, and the effective resistance value of the variable resistor circuit VR can be maintained at a predetermined value. Therefore, in the semiconductor circuit 2 of the second embodiment, the input current can be converted into voltage with high accuracy regardless of variations in the power supply voltage VDD and temperature.

[0103] The second embodiment described above is given by way of example and is not intended to limit the scope of the invention. The second embodiment can be implemented in various other ways.

[0104] 3. Third Implementation Method

[0105] The semiconductor circuit 3 of the third embodiment will now be described. In the third embodiment, a transimpedance amplifier TIA is operated in a time-division multiplexing manner, and the output signals before and after are subtracted, thereby removing the error component from the output voltage of the transimpedance amplifier TIA. In the third embodiment, the differences from the first embodiment will be mainly described. Other configurations and operations not described are the same as in the first embodiment.

[0106] 3.1 Structure of Semiconductor Circuits

[0107] Figure 7 This is a circuit diagram showing the configuration of the semiconductor circuit 3 according to the third embodiment. The semiconductor circuit 3 includes a transimpedance amplifier TIA, an input / output section IO for ESD protection, a single-ended input analog-to-digital converter circuit 12, a switching circuit 31, a storage circuit 32, a subtractor 33, and an input terminal WE.

[0108] The transimpedance amplifier TIA, input / output section IO, and analog-to-digital conversion circuit 12 included in semiconductor circuit 3 are the same as in the first or second embodiment, so their description is omitted.

[0109] A switching circuit 31 is connected between the input terminal WE and the input / output section IO and the transimpedance amplifier TIA. The output terminal of the operational amplifier OP within the transimpedance amplifier TIA is connected to the input terminal of the analog-to-digital converter 12. The output terminal of the analog-to-digital converter 12 is connected to the subtractor 33 via the storage circuit 32. Alternatively, the output terminal of the analog-to-digital converter 12 is connected to the subtractor 33 without going through the storage circuit 32. Furthermore, the output signal DOUT is output from the output terminal of the subtractor 33.

[0110] 3.2 Operation of Semiconductor Circuits

[0111] The operation of the semiconductor circuit 3 in the third embodiment will be described below.

[0112] In the third embodiment, the output signal DOUT is obtained by subtracting the output obtained through the following actions: time-division multiplexing of the transimpedance amplifier TIA, the action when the switch circuit 31 is open (or disconnected), and the action when the switch circuit 31 is on (or connected).

[0113] In the following description, the operation when the switch circuit 31 is open is referred to as "open state operation", and the operation when the switch circuit 31 is closed is referred to as "closed state operation". In addition, the open state operation is equivalent to the operation of the error signal path (or replication circuit) in the first embodiment, and the closed state operation is equivalent to the operation of the measurement signal path in the first embodiment.

[0114] First, the switching circuit 31 is set to the off state and performs the off state operation. During the off state operation, the output voltage VOUT1 of the operational amplifier OP within the transimpedance amplifier TIA is shown as follows.

[0115] Leakage current Iio is generated in the input / output section IO, and leakage current Isw is generated in the variable resistor circuit VR in the transimpedance amplifier TIA.

[0116] Therefore, the output voltage VOUT1 of the operational amplifier OP can be represented by the following equation (5).

[0117] VOUT1=VB+RTIA·(Iio+Isw) (5)

[0118] The output voltage VOUT1 is input to the analog-to-digital converter circuit 12. The output voltage VOUT1 input to the analog-to-digital converter circuit 12 is converted from an analog signal to a digital signal and output as the output signal DOUT1. The output signal DOUT1 is input to the storage circuit 32 and stored in the storage circuit 32. The output signal DOUT1 is represented by the following equation (5a).

[0119] DOUT1 = D(VOUT1)

[0120] =D(VB+RTIA·(Iio+Isw)) (5a)

[0121] Next, following the disconnection state operation, the switching circuit 31 is set to the conduction state and performs the conduction state operation. During the conduction state operation, the output voltage VOUT2 of the operational amplifier OP within the transimpedance amplifier TIA is shown as follows.

[0122] If the switching circuit 31 is set to the ON state, a current Isen flows through the transimpedance amplifier TIA, supplying the reference voltage VB to the positive input terminal of the operational amplifier OP. During ON operation, similar to the OFF operation, a leakage current Iio is generated in the input / output section IO, and a leakage current Isw is generated in the variable resistor circuit VR within the transimpedance amplifier TIA.

[0123] Therefore, the following equation (6) represents the output voltage VOUT2 of the operational amplifier OP.

[0124] VOUT2=VB+RTIA·(Isen+Iio+Isw) (6)

[0125] The output voltage VOUT2 is input to the analog-to-digital converter 12. The output voltage VOUT2 input to the analog-to-digital converter 12 is converted from an analog signal to a digital signal and output as the output signal DOUT2. The output signal DOUT2 is input to the subtractor 33. The output signal DOUT2 is represented by the following equation (6a).

[0126] DOUT2 = D(VOUT2)

[0127] =D(VB+RTIA·(Isen+Iio+Isw)) (6a)

[0128] Next, the output signal DOUT1 is subtracted from the output signal DOUT2 by the subtractor 33, and the output signal DOUT is output. The output signal DOUT is represented by the following equation (7) (= equation (6a) - equation (5a)).

[0129] DOUT=DOUT2-DOUT1=D(RTIA·Isen) (7)

[0130] Therefore, the error in the effective resistance value of the variable resistor circuit VR caused by the leakage current Iio and Isw can be eliminated, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

[0131] 3.3 Effects of the Third Implementation Method

[0132] According to the third embodiment, a transimpedance amplifier that can convert input current into voltage with high accuracy can be provided.

[0133] The semiconductor circuit 3 of the third embodiment includes a switching circuit 31 between the transimpedance amplifier TIA and the input / output section IO and the input terminal WE, and a storage circuit 32 and a subtractor 33 in the output stage of the analog-to-digital converter 12. First, the switching circuit 31 is set to the off state and the transimpedance amplifier TIA is activated. As a result, the output voltage VOUT1 generated by the leakage current Iio and Isw, which are important factors in the error of the frequency conversion gain of the transimpedance amplifier TIA, is output from the transimpedance amplifier TIA. The output voltage VOUT1 is converted into a digital output signal DOUT1 by the analog-to-digital converter 12, and the output signal DOUT1 is stored in the storage circuit 32.

[0134] Next, the switching circuit 31 is set to the ON state, and the transimpedance amplifier TIA is activated. As a result, the output voltage VOUT2 generated by the sensor current Isen, leakage current Iio, and Isw is output from the transimpedance amplifier TIA. The output voltage VOUT2 is converted into a digital output signal DOUT2 by the analog-to-digital converter 12, and the output signal DOUT2 is output to the subtractor 33. Furthermore, the subtractor 33 subtracts the output signal DOUT1 from the output signal DOUT2, removing the error component from the output signal DOUT2. Then, the output signal DOUT2 with the error component removed is output from the subtractor 33.

[0135] In the third embodiment, by subtracting the output signal DOUT1 of the transimpedance amplifier TIA when the switch circuit 31 is off from the output signal DOUT2 of the transimpedance amplifier TIA when the switch circuit 31 is on, the error in the effective resistance value of the variable resistor circuit VR caused by leakage current when the switch circuit 31 is on can be eliminated, and the effective resistance value of the variable resistor circuit VR can be maintained at a predetermined value. Therefore, in the semiconductor circuit 3 of the third embodiment, the input current can be converted into voltage with high accuracy, regardless of variations in the power supply voltage VDD and temperature.

[0136] Furthermore, in the third embodiment, there is no need to provide a replication circuit including the transimpedance amplifier TIAr, thus simplifying the circuit configuration of the semiconductor circuit 3 compared to the first and second embodiments.

[0137] The third embodiment described above is given by way of example and is not intended to limit the scope of the invention. The third embodiment can be implemented in various other ways.

[0138] 4. Fourth Implementation Method

[0139] The semiconductor circuit of the fourth embodiment will now be described. Various circuits for testing the operation of the transimpedance amplifier TIA are connected to the negative input terminal of the operational amplifier OP within the transimpedance amplifier TIA. Here, an example is shown where a fault detection circuit for detecting the presence or absence of a fault in the transimpedance amplifier TIA is connected to the negative input terminal of the operational amplifier OP. In the fourth embodiment, the differences from the first embodiment will be mainly described. Other configurations and operations not described are the same as in the first embodiment.

[0140] 4.1 Structure of Semiconductor Circuits

[0141] Figure 8 This is a circuit diagram showing the configuration of the semiconductor circuit according to the fourth embodiment. In addition to the semiconductor circuit 1 described in the first embodiment, the semiconductor circuit 4 of the fourth embodiment also includes a fault detection circuit 41, and switching circuits SW and SWr. Figure 8 The semiconductor circuit 1 shown is the same as the semiconductor circuit 1 shown in the first embodiment, so the description is omitted.

[0142] like Figure 8 As shown, the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA is connected to the fault detection circuit 41 via the switching circuit SW. The negative input terminal of the operational amplifier OPr in the transimpedance amplifier TIAr is connected to the fault detection circuit 41 via the switching circuit SWr.

[0143] The fault detection circuit 41 detects the voltage at the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA (hereinafter referred to as the first detection voltage) and the voltage at the negative input terminal of the operational amplifier OPr in the transimpedance amplifier TIA (hereinafter referred to as the second detection voltage), and detects the presence or absence of a fault in the transimpedance amplifier TIA based on the detected first detection voltage and second detection voltage.

[0144] The fault detection circuit 41 includes, for example, an analog-to-digital converter and a determination circuit. The analog-to-digital converter detects first and second detection voltages from the transimpedance amplifiers TIA and TIAAr, respectively, converts the first and second detection voltages into digital signals, and outputs first and second output signals. The determination circuit is the stage following the analog-to-digital converter. Based on the first and second output signals from the analog-to-digital converter, the determination circuit determines whether the transimpedance amplifier TIA is operating normally and outputs the determination result.

[0145] A switching circuit SW is connected between the negative input terminal of the operational amplifier OP and the fault detection circuit 41. The switching circuit SW sets the connection between the negative input terminal of the operational amplifier OP and the fault detection circuit 41 to a connected state (or closed state, conducting state) or a cut-off state (or open state, disconnected state).

[0146] A switching circuit SWr is connected between the negative input terminal of the operational amplifier OPr and the fault detection circuit 41. The switching circuit SWr sets the connection between the negative input terminal of the operational amplifier OPr and the fault detection circuit 41 to either a connected state or a disconnected state.

[0147] The switching circuit SWr has the same circuit structure as the switching circuit SW. That is, the switching circuit SWr has the same circuit elements and circuit constants as the switching circuit SW. The switching circuits SW and SWr are respectively constructed, for example, by transistors (e.g., MOS field-effect transistors).

[0148] There exists a situation where leakage current Iswa is generated in both the switching circuit SW and SWr. As mentioned above, the switching circuit SWr has the same circuit structure as the switching circuit SW. Therefore, the leakage current Iswa generated in the switching circuit SW and the switching circuit SWr is approximately the same, that is, it has approximately the same current value.

[0149] 4.2 Operation of Semiconductor Circuits

[0150] The operation of the semiconductor circuit 4 in the fourth embodiment will be described below.

[0151] exist Figure 8 When the semiconductor circuit 1 shown is in operation and is used normally, the switching circuits SW and SWr are set to the cut-off state.

[0152] In semiconductor circuit 4, leakage current Iio is generated in the input / output section IO in the signal measurement path, leakage current Isw is generated in the variable resistor circuit VR, and leakage current Iswa is generated in the switching circuit SW. If leakage currents Iio, Isw, and Iswa are generated, the current flowing in the variable resistor circuit VR decreases. Therefore, due to the leakage currents Iio, Isw, and Iswa, the effective resistance value of the variable resistor circuit VR becomes inaccurate.

[0153] On the other hand, in the input / output section IOr, the variable resistor circuit VRr, and the switching circuit SWr in the replication circuit (or error signal path), leakage currents Iio, Isw, and Iswa are generated in the same way as in the input / output section IO, the variable resistor circuit VR, and the switching circuit SW of the measurement signal path.

[0154] Here, the input / output section IOr, the variable resistor circuit VRr, and the switching circuit SWr in the replication circuit have the same circuit configuration as the input / output section IO, the variable resistor circuit VRr, and the switching circuit SWr in the measurement signal path. For example, the circuit elements and circuit constants of the input / output section IOr, the variable resistor circuit VRr, and the switching circuit SWr in the replication circuit are the same as those of the input / output section IO, the variable resistor circuit VRr, and the switching circuit SW in the measurement signal path. Therefore, the leakage currents Iio, Isw, and Iswa generated in the replication circuit are approximately the same as, or approximately identical to, the leakage currents Iio, Isw, and Iswa generated in the measurement signal path.

[0155] In this case, the output voltages VINP and VINN from operational amplifiers OP and Opr are represented by the following formulas.

[0156] VINP=VB+RTIA·Isen-RTIA·(Iio+Isw+Iswa) (8)

[0157] VINN=VB-RTIA·(Iio+Isw+Iswa) (9)

[0158] Therefore, the output signal DOUT from the differential input analog-to-digital converter 11 is represented by the following equation (10) (= equation (8) - equation (9)).

[0159] DOUT=D(VINP-VINN)=D(RTIA·Isen) (10)

[0160] Therefore, the error in the effective resistance value of the variable resistor circuit VR caused by leakage currents Iio, Isw, and Iswa can be eliminated, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

[0161] On the other hand, when semiconductor circuit 1 is operating and the transimpedance amplifier TIA test is performed, switching circuits SW and SWr are set to the connected state. When switching circuits SW and SWr are set to the connected state, leakage current is generated from both switching circuits SW and SWr. Here, as described above, switching circuit SWr has the same circuit configuration as switching circuit SW. For example, the circuit elements and their circuit constants of switching circuit SWr are the same as those of switching circuit SW. Therefore, the leakage current Iswa generated in switching circuit SWr is approximately the same as the leakage current Iswa generated in switching circuit SW, i.e., approximately identical.

[0162] A first detection voltage is input to the fault detection circuit 41 via the switching circuit SW, representing the negative input terminal of the operational amplifier OP within the transimpedance amplifier TIA. A second detection voltage is input to the fault detection circuit 41 via the switching circuit SWr, representing the negative input terminal of the operational amplifier OPr within the transimpedance amplifier TIA. The fault detection circuit 41 uses the first and second detection voltages to correct the voltage value of the first detection voltage generated by the leakage current Iswa, and based on the corrected first detection voltage, detects whether a fault exists in the transimpedance amplifier TIA.

[0163] 4.3 Effects of the Fourth Implementation Method

[0164] The semiconductor circuit 4 according to the fourth embodiment, like the first embodiment, can provide a transimpedance amplifier capable of converting input current into voltage with high precision.

[0165] Furthermore, in the semiconductor circuit 4 of the fourth embodiment, the switching circuit SWr has the same circuit configuration as the switching circuit SW, thus generating approximately the same leakage current Iswa in both the switching circuit SW and the switching circuit SWr. In the fourth embodiment, the fault detection circuit 41 corrects for errors in the first detection voltage generated by the leakage currents Iio, Isw, and Iswa based on the first detection voltage at the input terminal of the transimpedance amplifier TIA and the second detection voltage at the input terminal of the transimpedance amplifier TIA. Therefore, in the fourth embodiment, based on the corrected first detection voltage, it is possible to accurately detect whether a fault exists in the transimpedance amplifier TIA.

[0166] The fourth embodiment described above is given by way of example and is not intended to limit the scope of the invention. The fourth embodiment can be implemented in various other ways.

[0167] 5. Other variations, etc.

[0168] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor circuit, wherein, have: A first transimpedance amplifier has a first input terminal, a second input terminal, and a first output terminal. The first input terminal is supplied with a reference voltage, and the second input terminal is supplied with an input current. The first transimpedance amplifier converts the input current into a first output voltage and outputs the first output voltage from the first output terminal. The second transimpedance amplifier has a third input terminal, a fourth input terminal and a second output terminal, and has the same circuit configuration as the first transimpedance amplifier. The reference voltage is supplied to the third input terminal, and the second transimpedance amplifier outputs a second output voltage from the second output terminal. as well as The differential input analog-to-digital converter circuit receives the first output voltage and the second output voltage as input, obtains the voltage difference between the first output voltage and the second output voltage, thereby removing the in-phase signal component between the first output voltage and the second output voltage, and converts the third output voltage after removing the in-phase signal component into a digital value and outputs it.

2. The semiconductor circuit according to claim 1, wherein, It also has: The first ESD protection circuit is connected to the second input terminal of the first transimpedance amplifier; as well as The second ESD protection circuit is connected to the fourth input terminal of the second transimpedance amplifier and has the same circuit elements as the first ESD protection circuit. The first transimpedance amplifier has a first variable resistor circuit connected between the second input terminal and the first output terminal, and configured to allow the resistance value to be variable. The second transimpedance amplifier has a second variable resistor circuit connected between the fourth input terminal and the second output terminal, configured to allow the resistance value to be variable, and has the same circuit elements as the first variable resistor circuit.

3. The semiconductor circuit according to claim 2, wherein, Both the first ESD protection circuit and the second ESD protection circuit have a first circuit constant, and both the first variable resistor circuit and the second variable resistor circuit have a second circuit constant.

4. The semiconductor circuit according to claim 2, wherein, The first ESD protection circuit has a first diode and a second diode. The first diode is connected between the ground voltage node supplied with ground voltage and the second input terminal, and the second diode is connected between the second input terminal and the power supply voltage node supplied with power supply voltage. The second ESD protection circuit has a third diode and a fourth diode. The third diode is connected between the ground voltage node and the fourth input terminal, and the fourth diode is connected between the fourth input terminal and the power supply voltage node.

5. The semiconductor circuit according to claim 2, wherein, The first ESD protection circuit has a first transistor and a second transistor. The gate and drain of the first transistor are connected to a ground voltage node supplied with ground voltage, and the source of the first transistor is connected to the second input terminal. The gate and drain of the second transistor are connected to the power supply voltage node, and the source of the second transistor is connected to the second input terminal. The second ESD protection circuit has a third transistor and a fourth transistor. The gate and drain of the third transistor are connected to the ground voltage node, and the source of the third transistor is connected to the fourth input terminal. The gate and drain of the fourth transistor are connected to the power supply voltage node, and the source of the fourth transistor is connected to the fourth input terminal.

6. The semiconductor circuit according to claim 2, wherein, The first variable resistor circuit has a plurality of first resistors and a plurality of first transistors connected to the plurality of first resistors. The second variable resistor circuit has a plurality of second resistors and a plurality of second transistors connected to the plurality of second resistors.

7. The semiconductor circuit according to claim 1, wherein, It also has: The first circuit is connected to the second input terminal of the first transimpedance amplifier; as well as The second circuit is connected to the fourth input terminal of the second transimpedance amplifier and has the same circuit elements as the first circuit.

8. The semiconductor circuit according to claim 7, wherein, The first circuit includes a first switching circuit, and the second circuit includes a second switching circuit. Both the first switching circuit and the second switching circuit have a third circuit constant.

9. The semiconductor circuit according to claim 8, wherein, It also has: The detection circuit is connected to the first switch circuit and the second switch circuit.

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