Phased array system and method with phase shifter

Abstract

The present disclosure provides a phased array system and method having a phase shifter. The present disclosure provides various techniques for improving signal quality. By integrating a phase shift circuit with a transmit / receive (T / R) switch, insertion loss can be reduced while reducing the space occupied on an integrated circuit or printed circuit board. Specifically, the embodiments disclosed herein include a transmitter and a receiver each including one or more differential amplifiers coupled to a first inductor, and a switch network coupled to a second inductor and one or more phase shift circuits. The differential interface of the differential amplifiers can enable integration of a stage (e.g., a 180-degree stage) of the phase shifter with the T / R switch, such that a single circuit can operate as both the phase shifter and the T / R switch. This particular implementation can reduce the number of T / R switches and phase shifter stages in a phased array system, thereby reducing the total insertion loss experienced by the phased array system.

Description

Technical Field

[0001] This disclosure relates in general to wireless communication, and more specifically to transmitter / receiver isolation and phase shifting in wireless communication devices. Background Technology

[0002] The electronic device may include a phased array system, which includes an antenna shared between the transmitter and receiver of the electronic device. However, sharing an antenna between the transmitter and receiver may result in lower signal quality and may negatively affect the linearity of the phased array system. Summary of the Invention

[0003] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects not set forth below.

[0004] In one embodiment, the transceiver may include a transmitter, a receiver, and isolation and phase-shifting circuitry. The transmitter may include a first inductor, and the receiver may include a second inductor. The isolation and phase-shifting circuitry may include: a first switch that couples processing circuitry to a first terminal of the first inductor of the transmitter; a second switch that couples processing circuitry to a second terminal of the first inductor of the transmitter; a third switch that couples processing circuitry to a first terminal of the second inductor of the receiver; and a fourth switch that couples processing circuitry to a second terminal of the second inductor of the receiver.

[0005] In another embodiment, the phased array system may include: a transmitting circuit having a power amplifier; at least one phase shifter that phase-shifts a signal input to the power amplifier; and a switching network. The switching network may include: a first switch and a first shunt switch that couple the processor to a first terminal of an inductor of the power amplifier; and a second switch and a second shunt switch configured to couple the processor to a second terminal of an inductor of the power amplifier.

[0006] In yet another embodiment, a method may include: receiving an indication to receive a signal from a receiver; activating a first switch to couple processing circuitry to a first terminal of an inductor of the receiver, and deactivating a second switch to decouple the processing circuitry from a second terminal of the inductor to apply a first phase shift to the signal; and activating the second switch to couple the processing circuitry to the second terminal of the inductor, and deactivating the first switch to decouple the processing circuitry from the first terminal of the inductor to apply a second phase shift to the signal.

[0007] Various modifications to the above-described features may exist with respect to various aspects of the invention. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, various features discussed below relating to one or more illustrated embodiments may be incorporated individually or in any combination into any of the above aspects of the invention. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of the embodiments disclosed herein and does not limit the claimed subject matter. Attached Figure Description

[0008] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0009] Figure 1 This is a block diagram of an electronic device (such as a user equipment) according to an embodiment of this disclosure;

[0010] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional block diagram of an electronic device;

[0011] Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A simplified block diagram of a transceiver for an electronic device, which has a transmitter and a receiver separated by isolation / phase shift circuitry;

[0012] Figure 4 It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of the transmitter;

[0013] Figure 5 It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of the receiver;

[0014] Figure 6 This is a schematic diagram of an exemplary phased array system, in which Figure 3 The transmitter and receiver share an antenna;

[0015] Figure 7 yes Figure 6 A schematic diagram of an exemplary switching phase shifter for a phased array system;

[0016] Figure 8A It is based on the implementation scheme of this disclosure. Figure 4 A schematic diagram of a transmitter having a multi-stage power amplifier and a switching network arranged to shift the transmitted signal by a certain phase angle;

[0017] Figure 8B It is based on the implementation scheme of this disclosure. Figure 4A schematic diagram of a transmitter having a multi-stage power amplifier (PA) and a switching network arranged to shift the transmitted signal by another phase angle;

[0018] Figure 9 This is a flowchart of a method for selectively applying a phase shift according to an embodiment of the present disclosure;

[0019] Figure 10A It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of a transceiver circuit, which has an isolation / phase shift circuit for phase shifting the transmitted signal;

[0020] Figure 10B It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of a transceiver circuit, which has an isolation / phase shift circuit for phase shifting the received signal;

[0021] Figure 11 It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of a transceiver circuit, which has an isolation / phase shift circuit utilizing a single-ended transmission line;

[0022] Figure 12 It is a Smith chart, which illustrates an embodiment according to this disclosure. Figure 11 The total impedance of the transceiver circuit;

[0023] Figure 13 It is based on the implementation scheme of this disclosure. Figure 3 A schematic diagram of a transceiver circuit, which has an isolation / phase shift circuit utilizing differential transmission lines and an additional inductor;

[0024] Figure 14 It is a Smith chart, which illustrates an embodiment according to this disclosure. Figure 13 The total impedance of the transceiver circuit;

[0025] Figure 15 This is a schematic diagram illustrating an embodiment according to this disclosure. Figure 13 Alternative implementation schemes for the transceiver circuit; and

[0026] Figure 16 It is a Smith chart, which illustrates an embodiment according to this disclosure. Figure 15 The total impedance of the transceiver circuit. Detailed Implementation

[0027] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0028] When describing elements of various embodiments of this disclosure, the articles “an” and “the” are intended to refer to one or more of the elements present. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms “generally,” “nearly,” “about,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.).

[0029] This disclosure relates to isolation circuitry and phase shifting of transceivers within a phased array system for wireless communication devices (e.g., user equipment). The transceiver may include a transmitter and a receiver. In some embodiments, the transmitter and receiver may share the same antenna, which can reduce the size of the phased array system. Smaller phased array systems occupy less space on printed circuit boards (PCBs) or integrated circuits (ICs), while also exhibiting lower design complexity and greater reciprocity. Reciprocity, as used herein, is defined as the voltage conservation between the inputs and outputs of nodes or ports in a phased array system.

[0030] Transmitters and receivers can also share the same phase shifters. A phase shifter can be a passive or active microwave device used to change the phase angle of a radio frequency (RF) signal. Phase shifters can be used in applications such as phase modulators, up-conversion converters, test instruments, or phased array antennas within a phased array system. To use a set of antennas and a set of phase shifters for both transmitter and receiver, a transmit / receive (T / R) switch can be implemented. A T / R switch can connect a common antenna or a set of antennas to either the transmitter or the receiver. In transmit (TX) mode, the T / R switch enables the TX path, allowing the transmitted signal to be sent from a processor (e.g., a baseband processor) to the transmitter; in receive (RX) mode, the T / R switch enables the RX path, allowing the received signal to be sent from the receiver to the processor. While T / R switches allow the receiver and transmitter to share antennas and phase shifters, they can also increase the system's total insertion loss, leading to lower signal quality (e.g., by increasing the system's noise figure (NF)) and negatively impacting system linearity.

[0031] As previously mentioned, phase shifters can be passive (e.g., with zero or negligible power consumption) or active (e.g., with power consumption). Passive phase shifters may be advantageous due to their energy-saving properties. Specifically, switching phase shifters (e.g., phase shifters consisting of multiple phase shift stages) may be advantageous due to their ability to provide large bandwidth and relatively low insertion loss. However, although the insertion loss of switching phase shifters is relatively low, it increases with the addition of additional phase shift stages. For example, if the system requires a 45-degree phase shift, a 90-degree phase shift, and a 180-degree phase shift, each phase shift stage will increase the insertion loss. By implementing a circuit that combines phase shifter functionality with T / R switch functionality, the increase in insertion loss due to the addition of T / R switches and the increase in insertion loss experienced by each stage of the switching phase shifter can be reduced or minimized, thereby reducing the number of T / R switches and phase shifter stages responsible for the increase in insertion loss in the phased array transceiver circuitry.

[0032] The embodiments described herein provide various devices and techniques to reduce insertion loss while minimizing the space occupied on the integrated circuit, PCB, and / or the device as a whole by integrating one or more phase shifters with one or more T / R switches in a phased array transceiver circuit. To this end, the embodiments disclosed herein include: transmitters and receivers, each including one or more differential amplifiers (e.g., differential operational amplifiers) coupled to a first inductor; and a switching network coupled to a second inductor and one or more phase shift circuits. The differential amplifiers can be used for: multi-stage receivers, such as multi-stage low-noise amplifiers (LNAs); and / or multi-stage transmitters, such as multi-stage power amplifiers (PAs) in RF / mmWave circuits. The differential interface of the differential amplifier enables the integration of stages of the switching phase shifter (e.g., 180-degree stages) with the differential ports of the LNA and PA, allowing a single circuit to operate as both a phase shifter and a T / R switch. The T / R switch / phase shifter circuit may include multiple sets of switches (e.g., a switch network). In TX mode, the LNA can be deactivated or effectively removed from the circuit (e.g., all switches coupled to the LNA are open), while at least one set of switches coupled to the PA can be closed. One set of switches in the T / R switch / phase shifter circuit coupled to the PA can be closed so that the signal transmitted by the PA has a 0-degree phase shift, while another set of switches can be closed so that the signal transmitted by the PA has a 180-degree phase shift. Similarly, in RX mode, the PA can be deactivated or effectively removed from the circuit (e.g., all switches coupled to the PA are open), while at least one set of switches coupled to the LNA can be closed. One set of switches in the T / R switch / phase shifter circuit coupled to the LNA can be closed so that the signal received by the LNA has a 0-degree phase shift, while another set of switches can be closed so that the signal received by the LNA has a 180-degree phase shift. This implementation reduces the number of T / R switches and phase shifter stages in the phased array system, thereby reducing the total insertion loss experienced by the phased array system.

[0033] In view of the above, Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and power supply 29. Figure 1The various functional blocks shown may include hardware elements (including circuitry), software elements (including machine-executable instructions), or combinations of hardware and software elements (which may be referred to as logic). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., via or through another component, communication bus, network) to transmit and / or receive data between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0034] For example, electronic device 10 may include any suitable computing device, including desktop computers or laptops (e.g., those available from Apple Inc., Cupertino, California). Pro, MacBook mini or Mac (in the form of) portable electronic devices or handheld electronic devices such as wireless electronic devices or smartphones (e.g., available from Apple Inc. in Cupertino, California). (Model form), tablet computers (for example, those available from Apple in Cupertino, California) (in the form of a model), wearable electronic devices (e.g., Apple products available from Apple Inc. in Cupertino, California) (in the form of) and other similar devices. It should be noted that, Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be embodied wholly or partially in software, hardware, or both. Furthermore, the processor 12 and... Figure 1 Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other manipulations of information. Processor 12 may include one or more application processors, one or more baseband processors, or both, and performs the various functions described herein.

[0035] exist Figure 1In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0036] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0037] The input structure 22 of electronic device 10 allows a user to interact with electronic device 10 (e.g., press a button to increase or decrease the volume level). Like network interface 26, I / O interface 24 enables electronic device 10 to interact with a variety of other electronic devices. In some embodiments, I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. Network interface 26 may include one or more interfaces, for example, for personal area networks (PANs) such as Ultra Wideband (UWB) or... Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN) such as a protocol using one of the IEEE 802.11x series protocols (e.g., Networks; and / or wide area networks (WANs) such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) networks. Cellular networks, Long Term Evolution License Assisted Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or new radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 26 may include, for example, one or more interfaces for using the version 15 cellular communication standard of the 5G specification, which includes millimeter-wave (mmWave) frequency ranges (e.g., 24.25–300 GHz), and / or any other version of the cellular communication standard (e.g., version 16, version 17, any future version) that defines and / or implements frequency ranges for wireless communication. Network interface 26 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0038] Network interface 26 may also include one or more interfaces for, for example, a broadband fixed wireless access network (e.g., Mobile broadband wireless network (mobile) Asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video terrestrial broadcasting (DVB-) Network and its extension DVB handheld (DVB- Networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0039] As shown, network interface 26 may include transceiver 30. In some embodiments, all or part of transceiver 30 may be located within processor 12. Transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and therefore may include transmitters and receivers. Power supply 29 of electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0040] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic device 10. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) may be directly or indirectly communicatively coupled to each other (e.g., through or via another component, communication bus, network) to transmit and / or receive data between each other.

[0041] Electronic device 10 may include transmitter 52 and / or receiver 54, which respectively enable the transmission and reception of data between electronic device 10 and external devices via, for example, a network (e.g., including a base station) or a direct connection. As shown, transmitter 52 and receiver 54 may be combined into transceiver 30. Electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to transceiver 30. Antennas 55A-55N may be configured in omnidirectional or directional configurations, single-beam, dual-beam, or multi-beam arrangements, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in antennas 55A-55N of an antenna group or module may be communicatively coupled to a respective transceiver 30 and each transmits radio frequency signals that can be advantageously and / or destructively combined to form a beam. Applicable to various communication standards, electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas. In some implementations, transmitter 52 and receiver 54 may transmit and receive information via other wired or wired systems or devices.

[0042] As shown in the figure, various components of electronic device 10 can be coupled together via bus system 56. Bus system 56 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 can be coupled together or use some other mechanism to accept or provide input to each other.

[0043] Figure 3 This is a block diagram of a transceiver 30 (e.g., transceiver circuitry) of an electronic device 10 according to an embodiment of the present disclosure. As shown, the transceiver circuitry 30 includes an isolation / phase shifting circuitry 58 disposed between a transmitter (e.g., transmitting circuitry 52) and a receiver (e.g., receiving circuitry 54). The isolation / phase shifting circuitry 58 is communicatively coupled to the transmitter 52 and the receiver 54, and the transmitter 52 and the receiver 54 are coupled to one or more antennas 55. The isolation / phase shifting circuitry 58 prevents signals from being transmitted from the transmitter 52 to the receiver 54, and prevents received signals from being transmitted from the receiver 54 to the transmitter 52. The isolation / phase shifting circuitry 58 may also phase-shift signals, as will be described in further detail below.

[0044] Figure 4This is a schematic diagram of a transmitter 52 (e.g., a transmitting circuit) according to an embodiment of the present disclosure. As shown, the transmitter 52 can receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. A digital-to-analog converter (DAC) 62 of the transmitter 52 can convert the digital signal into an analog signal, and a modulator 64 can combine the converted analog signal with a carrier signal to generate radio waves. A power amplifier (PA) 66 receives the modulated signal from the modulator 64. The power amplifier 66 can amplify the modulated signal to a suitable level to drive the signal to be transmitted via one or more antennas 55. A filter 68 of the transmitter 52 (e.g., filter circuitry and / or software) can then remove unwanted noise from the amplified signal to generate the transmitted data 70 to be transmitted via one or more antennas 55. The filter 68 may include one or more suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise from the amplified signal. Additionally, transmitter 52 may include any suitable additional components not shown, or may exclude some of the components shown, such that transmitter 52 can transmit data 60 via one or more antennas 55. For example, transmitter 52 may include a mixer and / or a digital up-converter. Furthermore, if power amplifier 66 outputs the amplified signal within or substantially within the desired frequency range (so that filtering of the amplified signal is unnecessary), transmitter 52 may not include filter 68.

[0045] Figure 5This is a schematic diagram of a receiver 54 (e.g., a receiving circuit) according to an embodiment of this disclosure. As shown, receiver 54 can receive received data 80 from one or more antennas 55 in the form of an analog signal. A low-noise amplifier (LNA) 82 can amplify the received analog signal to a suitable level for processing by receiver 54. A filter 84 (e.g., filter circuitry and / or software) can remove unwanted noise, such as cross-channel interference, from the received signal. Filter 84 can also remove additional signals received by one or more antennas 55 at frequencies different from the desired signal. Filter 84 may include one or more of any suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise or signals from the received signal. Demodulator 86 can remove the radio frequency envelope from the filtered signal and / or extract the demodulated signal from the filtered signal for processing. Analog-to-digital converter (ADC) 88 can receive the demodulated analog signal and convert it into a digital signal of incoming data 90 for further processing by electronic device 10. Additionally, receiver 54 may include any suitable additional components not shown, or may exclude some of the components shown, such that receiver 54 can receive received data 80 via one or more antennas 55. For example, receiver 54 may include a mixer and / or a digital downconverter.

[0046] Figure 6 This is a schematic diagram of an exemplary phased array system 600, in which receiver 54 and transmitter 52 share an antenna. A T / R switch 606 can be implemented to use a set of antennas and a set of phase shifters for both transmitter and receiver purposes. The phased array system 600 may include transmit / receive (T / R) circuitry 602 that can send and receive signals to and from antenna 55. For example, in receive mode, T / R switch 606A can receive a received signal from the antenna and pass the received signal to LNA 82 (which, as a whole, can represent receiver 54). The received signal can be passed to phase shifter 612 via T / R switch 606B, which can adjust the phase of the received signal by a predetermined phase angle (e.g., 45 degrees, 90 degrees, 180 degrees, etc.). The received signal can then be passed to combiner / splitter 614. T / R switch 606C then enables received data 80 to be passed to intermediate frequency (IF) port 616. It is understood that after switching to transmit mode, T / R switches 606A, 606B, and 606C enable the transmit signal to propagate from IF port 616 through PA 66 to antenna 55. Although two T / R circuits 602 are shown, it should be noted that the phased array system 600 can have any suitable number of T / R circuits 602 (e.g., one, two, ten, one hundred, or several hundred).

[0047] like Figure 6As shown, to allow LNA 82 and PA 66 to share the same antenna 55, the exemplary phased array system 600 can implement three T / R switches 606A, 606B, and 606C. Each T / R switch 606 contributes to increasing the total insertion loss of the phased array system 600. Increased insertion loss leads to lower signal quality (e.g., by increasing the system's noise figure (NF)) and negatively impacts system linearity. Reducing the number of T / R switches 606 can decrease insertion loss.

[0048] Figure 7 This is a schematic diagram of a switching phase shifter 700 according to an embodiment of the present disclosure. The phase shifter (e.g., 612) can be passive (e.g., with zero or negligible power consumption) or active (with power consumption). Passive phase shifters (such as the switching phase shifter 700) may be advantageous due to their energy-saving properties. Specifically, a switching phase shifter 700 with multiple phase shift stages (e.g., 702, 704, and 706) may be advantageous because it can provide a large bandwidth and relatively low insertion loss. However, although the insertion loss of any single stage of the switching phase shifter 700 is relatively low, the insertion loss increases with the addition of additional stages. For example, if the switching phase shifter 700 includes a 45-degree phase shift stage 702, a 90-degree phase shift stage 704, and a 180-degree phase shift stage 706, each stage introduces a certain amount of insertion loss, and the total insertion loss of the switching phase shifter 700 is increased. For example, the insertion loss caused by a 135-degree phase shift (e.g., provided by activating the 45-degree phase shift stage 702 and the 90-degree phase shift stage 704) can have a smaller corresponding insertion loss than that provided by a 315-degree phase shift (e.g., provided by activating the 45-degree phase shift stage 702, the 90-degree phase shift stage 704, and the 180-degree phase shift stage 180). By implementing a circuit that integrates one or more stages of switching phase shifters 700 with the functions of T / R switches 606, the increase in insertion loss due to the additional T / R switches 606 and the increase in insertion loss experienced by each stage of switching phase shifters can be reduced or minimized, thereby reducing the number of T / R switches 606 and eliminating one or more stages of switching phase shifters 700 that may be responsible for the increase in insertion loss in the phased array system 600.

[0049] Figure 8AThis is a schematic diagram of a transmitting circuit 800 (e.g., transmitter 52) according to an embodiment of the present disclosure, having a multi-stage PA 801 and a switching network 802 arranged to phase-shift the transmitted signal by 0 degrees. The multi-stage PA 801 may be a differential power amplifier (e.g., a differential operational amplifier) ​​including multiple PAs 66 and a transformer 810; the transformer 810 includes inductors 812A and 812B. The switching network 802 includes switches 804A and 804B and shunt switches 806A and 806B. Switches 804A and shunt switch 806A may together form group 808A, while switches 804B and shunt switch 806B may together form group 808B. When group 808A is activated (e.g., switch 804A and shunt switch 806A are closed) and group 808B is deactivated (e.g., switch 804B and shunt switch 806B are open), the activated switch network 802 can transmit a transmit signal from processor 12 to the differential port 814A of multistage PA 801 by coupling processor 12 to the first terminal 816A of inductor 812B of transformer 810. This differential port inductively transmits the transmit signal from inductor 812B to inductor 812A coupled to the differential port 814A of multistage PA 801. The activated shunt switch 806A can short-circuit the second terminal 816B of inductor 812B (e.g., converting the differential signal to a single-ended signal when the second terminal 816B can be grounded). By enabling the processor 12 to be coupled to the differential port 814A of the multi-stage PA 801, the switching network 802 can maintain the phase of the transmitted signal to the multi-stage PA 801, or shift the phase of the transmitted signal to the multi-stage PA 801 by 0 degrees.

[0050] Figure 8B This is a schematic diagram of a transmitting circuit 800 according to an embodiment of the present disclosure, having a multi-stage PA 801 and a switching network 802 arranged to produce a 180-degree phase shift. When group 808B of the switching network 802 is activated (e.g., switch 804B and shunt switch 806B are closed) and group 808A is deactivated (e.g., switch 804A and shunt switch 806A are open), processor 12 can be coupled to the differential port 814B of the multi-stage PA 801 via a second terminal 816B coupled to inductor 812B. Coupling processor 12 to the differential port 814B of the multi-stage PA 801 causes the transmitted signal to exchange polarity, thereby inverting the transmitted signal sent from the multi-stage PA 801, resulting in a 180-degree phase shift in the signal destined for the multi-stage PA 801 (e.g., causing...). Figure 8A (180-degree phase shift in the circuit). The activated shunt switch 806B can short-circuit the first terminal 816A of the inductor 812B (e.g., converting the differential signal to a single-ended signal when the first terminal 816A can be grounded).

[0051] By using a switching network 802 to phase-shift the transmitted signal, a phase shifter (e.g., Figure 7 The 180-degree phase shift stage 706 is removed from the switch-type phase shifter 700 (as shown in the switch network 802), thereby reducing the insertion loss of the phased array system (e.g., 600). In the following embodiments, the manner in which a switch network similar to switch network 802 can be used to integrate the stages of the switch-type phase shifter 700 (e.g., the 180-degree phase shift stage 706) and the T / R switch 606 will be discussed. Additionally, although... Figure 8A and Figure 8B The diagram illustrates how switching network 802 generates different phase shifts for multi-stage PA 801. However, it should be noted that a similar switching network to switching network 802 can be implemented to generate one or more phase shifts for signals from LNA 82 (e.g., multi-stage LNA).

[0052] Figure 9 This is a flowchart of a method 900 for applying a phase shift using a transmitting circuit 800 according to an embodiment of the present disclosure. Method 900 can be performed by any suitable device (e.g., a controller) capable of controlling components of electronic device 10 (such as processor 12). In some embodiments, method 900 can be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14 or storage device 16. For example, method 900 can be performed at least in part by one or more software components such as the operating system of electronic device 10, one or more software applications of electronic device 10, etc. Although method 900 is described using a specific order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0053] In processing block 902, processor 12 determines that a signal is being transmitted from processor 12 to the transmitting circuitry of transceiver 30 (e.g., including PA 66), or determines that a signal is being transmitted from the receiving circuitry of transceiver 30 (e.g., including LNA 82) to processor 12. In decision block 904, processor 12 may determine whether a phase shift greater than 180 degrees is desired. If processor 12 determines that a phase shift greater than 180 degrees is desired, then in processing block 906, processor 12 activates a first set of switches (e.g., group 808B) to cause transceiver 30 to apply a 180-degree phase shift to the transmitted or received signal. For example, if processor 12 determines that a 225-degree phase shift of the transmitted signal is desired, processor 12 may activate a 45-degree phase shifter and group 808B (e.g., this group couples processor 12 to the first terminal 816A of inductor 812B) to combine the 45-degree phase shift with the 180-degree phase shift to shift the transmitted signal by 225 degrees.

[0054] However, if processor 12 determines that a phase shift greater than 180 degrees is not desired, then in processing block 908, processor 12 activates a second set of switches (e.g., group 808B) to cause the transceiver to apply a 0-degree phase shift to the transmitted or received signal. For example, if processor 12 determines that a 135-degree phase shift is desired, processor 12 may activate a 45-degree phase shifter, a 90-degree phase shifter, and group 808A to produce a 135-degree phase shift. In this way, method 900 enables processor 12 to apply a phase shift to an input (e.g., transmitted) signal. Although Figure 9 Method 900 describes how to... Figure 8A and Figure 8B The transmitted signal to the multi-stage PA801 is phase-shifted as shown, but method 900 can also be applied to the received signal from an LNA (e.g., 82), as will be discussed in more detail below.

[0055] Figure 10A This is a schematic diagram of a transceiver circuit 1000 according to an embodiment of the present disclosure, which has a switch for an isolation / phase shift circuit 58 configured to phase-shift a transmitted signal. The transceiver circuit 1000 includes a PA 66 (representing transmitter 52), an LNA 82 (representing receiver 54), and the isolation / phase shift circuit 58, which further includes a switch network 802 and a switch network 1002. Figure 8A and Figure 8B As shown, switch network 802 can phase shift the signal destined for PA 66 by 0 degrees (e.g., by activating switch 804A and spooler 806A, and deactivating switch 804B and spooler 806B) or by 180 degrees (e.g., by activating switch 804B and spooler 806B, and deactivating switch 804A and spooler 806A). Switch network 1002 can phase shift the signal from LNA 82 by 180 degrees or 0 degrees. Switch network 1002 includes switches 1004A and 1004B and spoolers 1006A and 1006B. As shown, switch network 802 is activated and switch network 1002 is deactivated (e.g., switches 1004A and 1004B and spoolers 1006A and 1006B are disconnected), thereby putting transceiver circuit 1000 in transmit (TX) mode. When switch 804A and shunt switch 806A are activated and switch 804B and shunt switch 806B are deactivated, isolation / phase shift circuit 58 can couple processor 12 to the first terminal 816A of inductor 812B. This can inductively transmit the transmitted signal from inductor 812B to inductor 812A coupled to differential port 814A of PA 66, thereby maintaining the phase of the transmitted signal or shifting the phase of the transmitted signal by 0 degrees.

[0056] By coupling the processor to either the first terminal 1016A or the second terminal 1016B of the inductor 1012A of the transformer 1010, the isolation / phase shift circuit 58 and the switch network 1002 enable the processor 12 to be coupled to either the differential port 1014A or the differential port 1014B of the LNA 82. When switch 1004A and shunt switch 1006A are activated (e.g., closed) and switch 1004B and shunt switch 1006B are deactivated (e.g., open), the processor 12 can be coupled to the differential port 1014A of the LNA 82, thereby causing a phase shift (e.g., 0-degree phase shift) in the signal from the LNA 82. Similarly, when switch 1004B and shunt switch 1006B are activated (e.g., closed) and switch 1004A and shunt switch 1006A are deactivated (e.g., open), processor 12 can be coupled to differential port 1014B of LNA 82 and decoupled from differential port 1014A, thereby causing a phase shift (e.g., 180-degree phase shift) in the signal from LNA 82. Transceiver circuit 1000 also includes a 45-degree phase shifter 1020 and a 90-degree phase shifter 1018. Although only the 45-degree phase shifter 1020 and the 90-degree phase shifter 1018 are shown in transceiver circuit 1000, it should be noted that transceiver circuit 1000 may include fewer or more phase shifters that can apply any appropriate phase shift (e.g., 30-degree phase shift, 15-degree phase shift, etc.).

[0057] As discussed, Figure 10A The transceiver circuit 1000 is in TX mode. Figure 10BThis is a schematic diagram of a transceiver circuit 1000 according to an embodiment of the present disclosure, which has a switch of an isolation / phase shift circuit 58 configured to apply a phase shift to the received signal. It can be observed that the transceiver circuit 1000 is in RX mode. Switch network 802 is deactivated (e.g., all switches 804 and shunt switches 806 in switch network 802 are open), and switch network 1002 is activated (e.g., switches 1004B and shunt switches 1006B are closed). Activating switch 1004B and shunt switch 1006B and deactivating switch 1004A and shunt switch 1006A allows switch network 1002 to couple processor 12 to the second terminal 1016B of inductor 1012B. This allows the received signal to be inductively transmitted from inductor 1012B to inductor 1012A coupled to the differential port 1014B of LNA 82, thereby shifting the received signal by 180 degrees. In other embodiments, switch 1004A and shunt switch 1006A can be activated, and switch 1004B and shunt switch 1006B can be deactivated to couple processor 12 to the first terminal 1016A of inductor 1012B. Inductor 1012B can inductively transmit the received signal from inductor 102B to inductor 1012A coupled to the differential port 1014A of LNA 82, which can maintain the phase shift of the received signal or shift the phase of the received signal by 0 degrees.

[0058] Figure 11 This is a schematic diagram of a transceiver circuit 1100 utilizing a single-ended transmission line according to an embodiment of this disclosure. Single-ended transmission line 1102 couples switching network 802 to phase shifters 1018 and 1020. Single-ended transmission line 1104 connects switching network 1002 to phase shifters 1018 and 1020. However, at certain frequencies (e.g., 30 GHz and higher), single-ended transmission lines 1102 and 1104 can cause reactive energy (e.g., capacitive reactance) to accumulate at deactivated switching networks (e.g., switching network 802 in receive mode and switching network 1002 in transmit mode). For example, in… Figure 11 In this configuration, transceiver circuit 1100 is in RX mode, therefore switch network 1002 is activated (e.g., one or more switches 1004 and one or more branch switches 1006 are closed), and switch network 802 is deactivated (e.g., switches 804 and branch switches 806 are open). If the signal frequency from LNA 82 is 50 GHz, excessive reactive power (e.g., especially excessive capacitive reactance) will accumulate at switch network 802; and switch network 1002 may not be able to absorb this excessive capacitive reactance. Several implementation schemes for resolving or compensating for excessive capacitive reactance will be discussed below.

[0059] Figure 12The Smith chart 1200 illustrates the total impedance of the transceiver circuit 1100 according to an embodiment of the present disclosure. The Smith chart 1200 shows the impedance of the deactivated switching network (e.g., due to various components in the transceiver circuit 1100, such as the activated switching network 1002, single-ended transmission lines 1102 and 1104, etc.) due to these components. Figure 11 Impedance 1202 is located at 802 in the Smith chart. The top hemisphere 1204 of the Smith chart 1200 represents the inductive reactance of one or more components in the transceiver circuit 1100 (e.g., single-ended transmission lines 1102 and 1104). The bottom hemisphere 1206 represents the capacitive reactance of one or more components in the transceiver circuit 1100. Impedance 1202 indicates the capacitive reactance that cannot be absorbed or dissipated by the rest of the transceiver circuit 1100 and thus accumulates significantly at the switching network 802.

[0060] Figure 13 This is a schematic diagram of a transceiver circuit 1300 utilizing a differential transmission line and an additional inductor according to an embodiment of this disclosure. To address the excessive capacitive reactance problem of the signal at the aforementioned specific frequency, the switching network 802 can be moved from or near the input port 1308 of PA66 and repositioned between the differential transmission line 1302 and the inductor 1306. Similarly, the switching network 1002 can be moved from or near the input port 1310 of LNA 82 and repositioned between the differential transmission line 1304 and the inductor 1306. Branch switches 806A and 806B can be 100 micrometers to 250 micrometers away from input port 1308 of PA 66 and / or inductor 812B, and branch switches 1006A and 1006B can be 100 micrometers to 250 micrometers away from input port 1310 of LNA 82 and / or inductor 1012B. By eliminating single-ended transmission line 1102 and implementing differential transmission lines 1302 and 1304 in transceiver circuit 1300, and utilizing the differential nature of differential transmission lines 1302 and 1304, the deactivated switching network can be reduced (e.g., Figure 13 The capacitive reactance at point 802 is dissipated, rather than being allowed to accumulate. Additionally, inductor 1306 can dissipate all or part of the remaining capacitive reactance. To completely dissipate the remaining capacitive reactance, inductor 1306 can have a range from 100 picohenry to 150 picohenry.

[0061] Figure 14The Smith chart 1400 shows the total impedance of the transceiver circuit 1300 according to an embodiment of the present disclosure. The Smith chart 1400 shows the impedance 1402 within the transceiver circuit 1300 due to components such as differential transmission lines 1302 and 1304, switching networks 802 and 1002, and inductor 1306. It can be observed that the capacitive reactance of the transceiver circuit 1300 (e.g., the capacitive reactance at the differential port of PA 66) has been reduced (e.g., closer to the system impedance 1404).

[0062] Figure 15 This is a schematic diagram of a transceiver circuit 1500 according to an embodiment of the present disclosure, wherein transceiver circuit 1500 is an alternative embodiment of transceiver circuit 1300. Transceiver circuit 1500 can be implemented in the following manner: from Figure 13 Starting from the observed location (e.g., 100 to 250 micrometers from the input port 1308 of PA 66 and / or inductor 812B), shunt switches 806A and 806B are moved and repositioned at or near the input port 1308 of PA 66, such that differential transmission line 1302 is positioned between shunt switches 806A and 806B and switches 804A and 804B. Similarly, it is possible to... Figure 13 The observed locations (e.g., 100 to 250 micrometers from the input port 1310 of LNA 82 and / or inductor 1012B) begin to move shunt switches 1006A and 1006B, repositioning them at or near the input port 1310 of LNA 82, such that differential transmission line 1304 is positioned between shunt switches 1006A and 1006B and switches 1004A and 1004B. By repositioning shunt switches 806A, 806B, 1006A, and 1006B, transceiver circuitry 1500 can further reduce excess capacitive reactance (e.g., as shown in the image) accumulated at the deactivated switch network for specific frequency signals. Figure 11 (See image). Due to the reduced capacitive reactance, the transceiver circuit 1500 may include an inductor 1502 that can be smaller than the inductor 1306. For example, while the inductor 1306 may have a range of 100 picohens to 150 picohens, the inductor 1502 may have a range of 20 picohens to 30 picohens. In one or more other embodiments, the inductor 1502 may be completely eliminated. The arrangement of the transceiver circuit 1500 may also further reduce the insertion loss experienced by the phased array system (e.g., by half dB).

[0063] Figure 16The Smith chart 1600 shows the total impedance of the transceiver circuit 1500 according to an embodiment of the present disclosure. It can be observed that the impedance 1602 of the transceiver circuit 1500 is less than the impedance 1402 of the transceiver circuit 1300. Specifically, it can be observed that the capacitive reactance of impedance 1602 is less than the capacitive reactance component of impedance 1402. As previously stated, this smaller capacitive reactance component of impedance 1602 allows the transceiver circuit 1500 to absorb deactivated switching networks (e.g., using a smaller inductor 1502 or without an inductor) Figure 15 The capacitive reactance at the switch network 802 in the middle.

[0064] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0065] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0066] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature, which significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35U.SC112(f).

Claims

1. A transceiver, comprising: A transmitter, the transmitter including a first transformer; Receiver, the receiver including a second transformer; and Isolation and phase shifting circuitry, the isolation and phase shifting circuitry including... A first switch, configured to at least partially induce a first phase shift by coupling processing circuitry to a first terminal of the first transformer of the transmitter. A second switch, configured to at least partially induce a second phase shift by coupling the processing circuitry to a second terminal of the first transformer of the transmitter. A third switch, configured to at least partially cause the first phase shift by coupling the processing circuitry to a first terminal of the second transformer of the receiver, and A fourth switch is configured to cause at least partially the second phase shift by coupling the processing circuitry to a second terminal of the second transformer of the receiver.

2. The transceiver of claim 1, wherein the first phase offset transmitted from the processing circuit includes 0 degrees.

3. The transceiver of claim 1, wherein the second phase offset transmitted from the processing circuit comprises 180 degrees.

4. The transceiver of claim 1, further comprising a third inductor coupling the isolation and phase shift circuitry to the processing circuitry, the third inductor being configured to absorb reactive power accumulated at the first and second switches, the third and fourth switches, or the first and second switches and the third and fourth switches.

5. The transceiver of claim 4, wherein the third inductor has an inductance of 100 to 150 picohens.

6. The transceiver of claim 1, further comprising one or more phase shifters coupling the isolation and phase shifting circuitry to the processing circuitry, the one or more phase shifters being configured to shift the phase of a signal transmitted from the processing circuitry, shift the phase of a signal transmitted from the receiver, or shift the phases of both a signal transmitted from the processing circuitry and a signal transmitted from the receiver.

7. The transceiver of claim 6, comprising one or more single-ended transmission lines, wherein the one or more single-ended transmission lines couple the first switch to the one or more phase shifters, couple the second switch to the one or more phase shifters, or couple the first switch to the one or more phase shifters and the second switch to the one or more phase shifters.

8. The transceiver of claim 6, comprising one or more differential transmission lines, wherein the one or more differential transmission lines couple the third switch to the one or more phase shifters, couple the fourth switch to the one or more phase shifters, or couple the third switch to the one or more phase shifters and the fourth switch to the one or more phase shifters.

9. A phased array system, comprising: The transmitting circuit includes a power amplifier; At least one phase shifter, the at least one phase shifter being configured to shift the phase of a signal input to the power amplifier; and Switching networks, including A first switch and a first branch switch, the first switch and the first branch switch being configured to couple the processor to a first terminal of the transformer of the power amplifier, and A second switch and a second branch switch are configured to couple the processor to a second terminal of the transformer of the power amplifier. The first switch and the second shunt switch are configured to cause a first phase shift, and The second switch and the first shunt switch are configured to cause a second phase shift.

10. The phased array system of claim 9, further comprising a differential transmission line configured to couple the switching network to a port of the power amplifier.

11. The phased array system of claim 10, wherein the switching network is coupled to another inductor.

12. The phased array system of claim 11, wherein the other inductor has an inductance of 50 to 100 picohens.

13. The phased array system of claim 11, wherein the first shunt switch and the second shunt switch are disposed at a distance of 100 micrometers to 250 micrometers from the port of the power amplifier.

14. The phased array system of claim 9, further comprising a differential transmission line configured to couple the first shunt switch and the second shunt switch to the first switch and the second switch.

15. The phased array system of claim 14, wherein the first shunt switch and the second shunt switch are coupled to the ports of the power amplifier.

16. A method for applying a phase shift, comprising: Receive an indication of receiving a signal from the receiver; Activate a first switch to couple the processing circuitry to a first terminal of the transformer of the receiver, and deactivate a second switch to decouple the processing circuitry from a second terminal of the transformer to apply a first phase shift to the signal; as well as The second switch is activated to couple the processing circuit to the second terminal of the transformer, and the first switch is deactivated to decouple the processing circuit from the first terminal of the transformer, thereby applying a second phase shift to the signal.

17. The method of claim 16, further comprising activating a first shunt switch based on activating the first switch, the first shunt switch being configured to form a short circuit at the second terminal of the transformer.

18. The method of claim 16, further comprising activating a second shunt switch based on activating the second switch, the second shunt switch being configured to form a short circuit at the first end of the transformer.

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