Bandwidth rate limiting module, method and DMA controller

Abstract

The application provides a bandwidth throttling module, a method and a DMA controller. An output end of a quota submodule of the module is connected with a counter and configured to generate an enable sequence. An output end of the counter is connected with an external output device. The counter is configured to count the traffic passing through the bandwidth throttling module according to the enable sequence to determine the current remaining traffic quota of the bandwidth throttling module. An input end of an input switch is connected with an external input device. An output end of the input switch is connected with an input end of the counter. The input switch is configured to be turned on or turned off according to the current remaining traffic quota to control the data input of the external input device. The enable sequence is evenly distributed in m clock cycles at n high voltage levels. The application generates the enable sequence with evenly distributed high voltage levels. The input switch is turned on or turned off evenly by the cooperation of the enable sequence and the counter to realize the uniform throttling of the bandwidth input into the throttling module.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, in particular, relates to a bandwidth throttling module, method and DMA controller. BACKGROUND

[0002] The current common bandwidth throttling method is to increase a certain amount of flow quota to the throttling module every time interval. When the effective data enters, a quota is subtracted from the flow quota, and when the flow quota of the throttling module is 0, no data is input until a new flow quota is obtained. Although this method can limit the flow to achieve the purpose of throttling, the throttling is not uniform enough, and the instantaneous bandwidth may be too large, causing bandwidth congestion. SUMMARY

[0003] Therefore, the purpose of the embodiments of the present application is to provide a bandwidth throttling module, method and DMA controller, which can smooth the bandwidth and prevent bandwidth congestion.

[0004] In a first aspect, the embodiments of the present application provide a bandwidth throttling module, comprising: a quota submodule, a counter and an input switch; the output end of the quota submodule is connected with the counter and is configured to generate an enable sequence; the output end of the counter is connected with an external output device, and the counter is configured to count the flow passing through the bandwidth throttling module according to the enable sequence to determine the current remaining flow quota of the bandwidth throttling module; the input end of the input switch is connected with an external input device, the output end of the input switch is connected with the input end of the counter, and the input switch is configured to turn on or off according to the current remaining flow quota to control the data input of the external input device; wherein the high level of the enable sequence is evenly distributed in m clock cycles.

[0005] In the above implementation process, the quota submodule generates an enable sequence with evenly distributed high level, and sends the enable sequence to the counter. The counter determines the current remaining flow quota of the throttling module by the enable sequence and the data received by the throttling module, and controls the turn-on and turn-off of the input switch according to the current flow quota, thereby controlling the data input of the external input device. Since the high level generated by the enable sequence is evenly distributed in the clock cycle, the throttling of the bandwidth throttling module is uniform, which reduces the instantaneous bandwidth and prevents the instantaneous bandwidth from being too large to cause bandwidth congestion.

[0006] In one embodiment, the quota submodule has a built-in gate circuit, which includes a counting unit, a quota coefficient determination unit and a signal generating unit; the counting unit is connected to the clock signal for obtaining the clock signal; the input end of the quota coefficient determination unit is connected to the output end of the counting unit and is configured to determine the quota coefficient; the input end of the signal generating unit is connected to the output end of the quota coefficient determination unit and is configured to generate an enable signal to form an enable sequence through the enable signal.

[0007] In the above implementation process, a gate circuit is provided in the quota submodule. This gate circuit, through the cooperation between the counting unit, the quota coefficient determination unit, and the signal generation unit, realizes the conversion of the clock signal into an enable signal through a series of logical operations, so as to form an enable sequence through this enable signal to control the input switch. Because the enable signal is formed by this gate circuit, the enable signal can be generated according to demand by modifying each unit in the gate circuit, realizing the adjustability of the enable signal generation, improving the diversity of the enable sequence generated by the quota submodule, and increasing the applicable scenarios of the bandwidth speed limit module.

[0008] In one embodiment, the quota coefficient determination unit includes: multiple NOT gates, multiple first-group AND gates, multiple second-group AND gates, and multiple third-group AND gates; the first input end of each first-group AND gate is respectively connected to the first output end of the counting unit, and the output end of each first-group AND gate is respectively connected to the first input end of the third-group AND gate; the first input end of each second-group AND gate is connected to the output end of the NOT gate, the output end of each second-group AND gate is respectively connected to the second input end of the first-group AND gate, and the output end of the second-group AND gate is sequentially connected to the second input end of the second-group AND gate; the input end of the NOT gate is connected to the first output end of the counting unit; the output end of the third-group AND gate is connected to the input end of the signal generating unit.

[0009] In the above implementation process, a logic unit circuit is formed by multiple AND gates, NOT gates, etc., and the clock sequence output by the counting unit is logically operated through the logic unit circuit to determine the quota coefficient. Because the quota coefficient is determined based on the logic unit circuit in the quota coefficient determination unit, the quota coefficient can be adjusted by modifying the number and connection relationship of the AND gates and NOT gates in the logic unit circuit. This realizes the adjustability of the enable signal generation, improves the diversity of the enable sequence generated by the quota submodule, and expands the applicable scenarios of the bandwidth speed limit module.

[0010] In one embodiment, the signal generating unit includes: multiple first groups or gates, multiple second groups or gates, at least one third group or gate and at least one fourth group or gate; the input end of each first group or gate is connected to the output end of the quota coefficient determination unit; the first input end and the second input end of each second group or gate are respectively connected to the output end of one of the first groups or gates; the first input end and the second input end of each third group or gate are respectively connected to the output end of one of the second groups or gates; the first input end and the second input end of each fourth group or gate are respectively connected to the output end of one of the third group or gates.

[0011] In the above implementation process, multiple quota coefficients determined in the quota coefficient determination unit are calculated by setting multiple OR gates and set calculation rules to obtain an enable signal with a high level evenly distributed within the clock cycle. Then, the bandwidth speed limit module can be evenly allocated quotas through the enable signal, thereby avoiding bandwidth congestion.

[0012] In one embodiment, the counting unit includes: multiple triggers; the multiple triggers are connected in sequence, and the first output end of the previous trigger is connected to the input end of the next trigger; the second output end of each trigger is connected to the input end of the quota coefficient determination unit.

[0013] In the above implementation process, by setting up multiple triggers to form a counting unit, not only can the clock signal be limited to trigger the counting unit to start action in a specific form after the counting unit obtains the clock signal, but the input clock signal can also be cyclically counted through multiple triggers to output the corresponding clock sequence for the quota coefficient determination unit to perform corresponding logical operations to determine the corresponding quota coefficient, thereby realizing the specific triggering of the clock signal and improving the accuracy of the quota sub-module in processing the clock signal.

[0014] In one embodiment, m is an integer power of 2, and the bit width of the counting unit is log2 m.

[0015] In the above implementation process, since the bit width of the counting unit is log2 m, that is, the value of m affects the bit width of the counting unit, the bit width of the counting unit can be adjusted by adjusting the value of m, and the speed limiting accuracy of the bandwidth speed limiting module can be adjusted. This realizes the adjustability of the speed limiting accuracy of the bandwidth speed limiting module and improves the speed limiting accuracy of the bandwidth speed limiting module.

[0016] In one embodiment, the bandwidth rate limiting module is applied to a DMA controller.

[0017] In the above implementation process, by applying the bandwidth speed limit module to the DMA controller, uniform speed limit of the DMA controller is achieved, reducing the pressure on the random access memory caused by the fluctuation of instantaneous bandwidth.

[0018] In a second aspect, an embodiment of the present application also provides a bandwidth speed limiting method, including: obtaining an enable sequence, wherein the enable sequence is n high levels evenly distributed within m clock cycles; wherein n and m are both non-zero natural numbers; counting the traffic passing through the speed limiting device according to the enable sequence to determine the current remaining traffic quota; controlling the conduction or disconnection of the input switch by the current remaining traffic quota to control the data input of the external input device.

[0019] In the above implementation process, the data of the speed limiter is counted by an enable sequence in which n high levels are evenly distributed in m clock cycles, so that the speed limiter can evenly receive n traffic quotas within m clock cycles, thereby making the speed limit of the bandwidth speed limiter module n / m of the total bandwidth, achieving uniform speed limit of the bandwidth speed limiter module, reducing the instantaneous bandwidth, and preventing bandwidth congestion caused by excessive instantaneous bandwidth.

[0020] In one embodiment, counting the traffic passing through the speed limiting device according to the enable sequence to determine the current remaining traffic quota includes: in each clock cycle, if D=1, U=0 and T≠0, then T=T-1; if D=0, U=1 and T<min(n, 255), then T=T+1; wherein D=1 indicates that valid data passes through the bandwidth speed limiting module in the current clock cycle, D=0 indicates that the bandwidth speed limiting module refuses to receive data in the current clock cycle, U represents the enable sequence, U=0 represents a low level, U=1 represents a high level, T represents the remaining traffic quota, and min(n, 255) represents the smaller value of n and 255.

[0021] In the above implementation process, the current remaining traffic quota in the bandwidth limit module is determined by the data quota configured by the quota submodule in the current clock cycle and the actual input data in the current clock cycle. The current traffic quota is determined by the data input in real time by the bandwidth limit module, which is more in line with the actual situation and improves the accuracy of determining the current remaining traffic quota.

[0022] In one embodiment, controlling the on or off of the input switch by the current remaining traffic quota includes: when the current remaining traffic quota is greater than zero, controlling the input switch to be on; when the current remaining traffic quota is equal to zero, controlling the input switch to be off.

[0023] In the above implementation process, by controlling the state of the input switch according to whether the current remaining traffic quota is zero, a large amount of data is prevented from being input into the bandwidth rate limiting module at the same time, ensuring that the data input to the bandwidth rate limiting module is maintained within an appropriate quota range, and preventing bandwidth congestion within the same clock cycle.

[0024] In a third aspect, an embodiment of the present application further provides a DMA controller, comprising: a DMA control module; a bandwidth rate limiting module according to the first aspect mentioned above, or any possible implementation of the first aspect, connected to the DMA control module; wherein the DMA control module is configured to control the bandwidth rate limiting module to perform a rate limiting action according to a read or write request of a peripheral device, so as to limit the data input into the DMA controller.

[0025] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the machine-readable instructions are executed by the processor to perform the steps of the method in the above-mentioned second aspect, or any possible implementation of the second aspect.

[0026] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the bandwidth speed limiting method in the above-mentioned second aspect or any possible implementation method of the second aspect are executed.

[0027] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the following embodiments are given in conjunction with the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic block diagram of a bandwidth limiting module provided in an embodiment of the present application;

[0030] Figure 2 The enabling sequence provided in the embodiment of the present application is a waveform diagram of 48 high levels evenly distributed in 64 cycles;

[0031] Figure 3 The enabling sequence provided in the embodiment of the present application is a waveform diagram in which 10 high levels are evenly distributed in 16 cycles;

[0032] Figure 4 A circuit structure diagram of a gate circuit provided in an embodiment of the present application;

[0033] Figure 5 Flowchart of the bandwidth speed limiting method provided in an embodiment of the present application;

[0034] Figure 6 The function module schematic diagram of the bandwidth throttling device provided in the embodiment of the present application is shown in the following table.

[0035] Reference signs: bandwidth throttling module-10, quota sub-module-100, counting unit-110, quota coefficient determination unit-120, signal generation unit-130, counter-200, input switch-300. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. For example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, functions and operations of the principle structure, system, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, function block, program segment or part of code, which contains one or more executable instructions for implementing the specified simulation functions and logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders from those noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions. In addition, the function modules in the various embodiments of the present application can be integrated together to form a separate part, or each module can exist independently, or two or more modules can be integrated to form a separate part.

[0037] When reading or writing data in the memory, because the bandwidth of the memory is not sufficient to support multiple DMA controllers to access simultaneously, throttling processing needs to be performed at each memory to avoid bandwidth congestion. However, the current throttling module is usually configured with a corresponding traffic quota at a certain time interval, and the throttling module reads or writes data from the DMA controller when there is a traffic quota. This one-time quota method can easily cause uneven throttling and excessive instantaneous bandwidth.

[0038] In light of this, the inventors of this application have proposed a bandwidth limiting module. This module incorporates a quota submodule that, through internal gate circuitry, performs logical operations on clock signals to generate an enable sequence consisting of n high-level signals evenly distributed over m clock cycles, ensuring an average bandwidth of n / m of the total bandwidth. This enable sequence evenly allocates traffic quotas to the bandwidth limiting module within each clock cycle, ensuring uniform speed limiting, reducing instantaneous bandwidth, and preventing bandwidth congestion caused by excessive instantaneous bandwidth.

[0039] See also Figure 1 , is a block diagram of a bandwidth rate limiting module 10 provided in an embodiment of the present application, comprising: a quota submodule 100, a counter 200, and an input switch 300.

[0040] The output of the quota submodule 100 is connected to the counter 200 , the output of the counter 200 is connected to an external output device, the input of the input switch 300 is connected to an external input device, and the output of the input switch 300 is connected to the input of the counter 200 .

[0041] The quota submodule 100 is configured to generate an enable sequence, which is n high levels evenly distributed in m clock cycles, where n and m are both non-zero natural numbers.

[0042] For example, Figure 2 As shown, Figure 2 The enabling sequence provided in the embodiment of the present application is a waveform diagram of 48 high levels evenly distributed in 64 cycles. Figure 2 As shown, the enable sequence is 01110111011101110111011101110111011101110111011101110111011101110111.

[0043] For example, Figure 3 As shown, Figure 3 The enabling sequence provided in the embodiment of the present application is a waveform diagram of 10 high levels evenly distributed in 16 cycles. Figure 3 As shown, the enabling sequence is 0101110101011101. Optionally, m here can also be 32, 128, etc. n can be 20, 64, etc. The values ​​of n and m can be adjusted according to actual conditions, and this application does not impose any specific restrictions.

[0044] It can be understood that the enable sequence may include multiple enable signals, and the enable signals serve as control conditions for turning the input switch 300 on or off.

[0045] The counter 200 is configured to count the traffic passing through the bandwidth limiting module 10 according to the enable sequence to determine the current remaining traffic quota of the bandwidth limiting module 10. The counter 200 can be a multi-bit unsigned counter 200, such as an 8-bit unsigned counter 200, a 16-bit unsigned counter 200, a 32-bit unsigned counter 200, etc. The number of bits of the counter 200 can be adjusted according to actual conditions and is not specifically limited in this application.

[0046] After the quota submodule 100 generates the enable sequence, it sends the enable sequence to the counter 200 . The counter 200 determines the current remaining traffic quota of the bandwidth rate limiting module 10 based on the enable signal in the enable sequence and the data received by the bandwidth rate limiting module 10 in the current cycle.

[0047] It can be understood that the data that a bandwidth limiting module 10 can receive within a clock cycle is limited. By determining the data received by the bandwidth limiting module 10 within the clock cycle, the remaining data that the bandwidth limiting module 10 can receive within the clock cycle can be obtained. The remaining data that the bandwidth limiting module 10 can receive within the clock cycle is the current remaining traffic quota.

[0048] The input switch 300 is configured to be turned on or off according to the current remaining traffic quota to control the data input of the external input device.

[0049] If the current remaining traffic quota is determined to be zero, it indicates that the bandwidth rate limiting module 10 can no longer receive data during the current clock cycle. Therefore, the input switch 300 should be disconnected to prevent data from external input devices from being input into the bandwidth rate limiting module 10. If the current remaining traffic quota is determined to be non-zero, it indicates that the bandwidth rate limiting module 10 can still receive data during the current clock cycle. Therefore, the input switch 300 should be connected to allow data from external input devices to be input into the bandwidth rate limiting module 10.

[0050] Optionally, the input switch 300 may be a switch that can be controlled by an electrical signal, such as a relay or a limit switch.

[0051] In the above implementation, the quota submodule generates an enable sequence with uniformly distributed high levels and sends this enable sequence to a counter. The counter uses this enable sequence and the data already received by the bandwidth limiter module to determine the current remaining traffic quota of the limiter module. Based on this current traffic quota, the counter controls the on and off switching of the input switch, thereby controlling the input of data from the external input device. Because the high levels generated by this enable sequence are uniformly distributed within the clock cycle, the bandwidth limiter module's speed limit is uniform, reducing the instantaneous bandwidth and preventing excessive instantaneous bandwidth from causing bandwidth congestion.

[0052] In a possible implementation, the quota submodule 100 has a built-in gate circuit, which includes a counting unit 110 , a quota coefficient determination unit 120 , and a signal generation unit 130 .

[0053] The counting unit 110 is connected to the clock signal, the input end of the quota coefficient determination unit 120 is connected to the output end of the counting unit 110 , and the input end of the signal generation unit 130 is connected to the output end of the quota coefficient determination unit 120 .

[0054] The counting unit 110 is used to obtain a clock signal and cyclically obtain the clock signal within each clock cycle to output a corresponding binary clock sequence based on the clock signal. The counting unit 110 can be a plurality of unsigned cyclic accumulators composed of multiple flip-flops. For example, an 8-unsigned cyclic accumulator composed of 8 flip-flops, a 16-unsigned cyclic accumulator composed of 16 flip-flops, etc. The following uses an 8-unsigned cyclic accumulator composed of 8 flip-flops as an example to list the clock sequences output by the counting unit 110 from the first clock cycle to the eighth clock cycle.

[0055] Illustratively, the clock sequence output by the counting unit 110 in the first clock cycle may be 00000000, the clock sequence output in the second clock cycle may be 00000001, the clock sequence output in the third clock cycle may be 00000010, the clock sequence output in the fourth clock cycle may be 00000011, the clock sequence output in the fifth clock cycle may be 00000100, the clock sequence output in the sixth clock cycle may be 00000101, the clock sequence output in the seventh clock cycle may be 00000110, the clock sequence output in the eighth clock cycle may be 00000111, and so on.

[0056] The number of triggers of the counting unit 110 can be adjusted according to actual needs, and this application does not impose any specific restrictions. Accordingly, the output sequence of the counting unit 110 can change accordingly according to the structure of the clock unit, and this application does not impose any specific restrictions.

[0057] The quota coefficient determination unit 120 is configured to determine the quota coefficients by using a plurality of logic unit circuits to construct a plurality of quota coefficients using the clock signals in the clock sequence output by the counting unit 110 to determine the enable signal.

[0058] The signal generating unit 130 is configured to generate an enable signal to form an enable sequence through the enable signal. The signal generating unit 130 determines the enable signal according to the quota coefficient and the bandwidth coefficient. The bandwidth coefficient n is an unsigned number of (log2m+1) bits, and n can be 0 to 2.m Any one positive integer between 0 and 2, inclusive m n is represented in binary as n m …n0. Where n0 represents the least significant bit of the m+1 bit unsigned number n, n m represents the most significant bit of the m+1 bit unsigned number n.

[0059] Exemplarily, if the bandwidth coefficient n is a 4-bit unsigned number, and n can take any one positive integer between 0 and 8, inclusive. n is represented in binary as n3n2n1n0. Where n0 represents the least significant bit of the 4-bit unsigned number n, n3 represents the most significant bit of the 4-bit unsigned number n.

[0060] If the bandwidth coefficient n is a 9-bit unsigned number, and n can take any one positive integer between 0 and 256, inclusive. n is represented in binary as n8n7n6n5n4n3n2n1n0. Where n0 represents the least significant bit of the 9-bit unsigned number n, n8 represents the most significant bit of the 9-bit unsigned number n.

[0061] In the implementation process, by setting a gate circuit in the quota submodule, the gate circuit realizes the conversion of the clock signal into an enable signal through a series of logical operations, forms an enable sequence through the enable signal, and controls the input switch. Since the enable signal is formed by the gate circuit, the enable signal can be generated according to the demand by modifying each unit in the gate circuit, the adjustability of the enable signal generation is realized, the diversity of the enable sequence generated by the quota submodule is improved, and the application scenarios of the bandwidth throttling module are increased.

[0062] In a possible implementation manner, as shown in Figure 4 the quota coefficient determination unit 120 includes a plurality of NOT gates, a plurality of first group AND gates, a plurality of second group AND gates, and a plurality of third group AND gates.

[0063] Wherein, the first input end of each first group AND gate is connected with the first output end of the counting unit 110 respectively, and the output end of each first group AND gate is connected with the first input end of the third group AND gate respectively; the first input end of each second group AND gate is connected with the output end of the NOT gate, and the output end of each second group AND gate is connected with the second input end of the first group AND gate respectively, and the output end of the second group AND gate is connected with the second input end of the second group AND gate in turn; the input end of the NOT gate is connected with the first output end of the counting unit 110; and the output end of the third group AND gate is connected with the input end of the signal generation unit 130.

[0064] The plurality of first AND gates, the plurality of second AND gates, the plurality of third AND gates, and the plurality of NOT gates are arranged in a predetermined order. The second input of the first AND gate of the first group is connected to the output of the first NOT gate, and the output of the first NOT gate is also connected to the first input of the first AND gate of the second group. The output of the last AND gate of the second group is connected only to the second input of the last AND gate of the first group.

[0065] The first AND gate of the first group is the AND gate in the first group of AND gates connected to the trigger connected to the clock signal in the counting unit 110, the first NOT gate is the NOT gate in the NOT gate connected to the trigger connected to the clock signal in the counting unit 110, and the last AND gate in the second group is the AND gate in the second group of AND gates that is farthest from the trigger connected to the clock signal in the counting unit 110.

[0066] When determining the enable signal, the clock sequence output by the counting unit 110 is sent to the quota coefficient determination unit 120. The quota coefficient determination unit 120 determines the quota coefficient received by the first input end of each AND gate in the third group of AND gates through the logic unit circuit composed of the above-mentioned AND gates, NOT gates, etc.

[0067] For example, Figure 2 As shown, if eight 1-bit quota coefficients, U0 to U7, are constructed, the calculation method is as follows:

[0068] U0=C0;

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076] Among them, C7C6C5C4C3C2C1C0 is the clock sequence output by the counting unit 110. Indicates a logical NOT on C0. Indicates a logical NOT on C1. Indicates a logical NOT on C6.

[0077] It can be understood that the number, connection relationship and group of AND gates and NOT gates in the quota coefficient determination unit 120 can be adjusted according to actual conditions. When the number, connection relationship and group of AND gates and NOT gates in the quota coefficient determination unit 120 are adjusted, the determination of the corresponding quota coefficient will also change accordingly.

[0078] In the above implementation process, a logic unit circuit is formed by multiple AND gates, NOT gates, etc., and the clock sequence output by the counting unit is logically operated through the logic unit circuit to determine the quota coefficient. Because the quota coefficient is determined based on the logic unit circuit in the quota coefficient determination unit, the quota coefficient can be adjusted by modifying the number and connection relationship of the AND gates and NOT gates in the logic unit circuit. This realizes the adjustability of the enable signal generation, improves the diversity of the enable sequence generated by the quota submodule, and expands the applicable scenarios of the bandwidth speed limit module.

[0079] In a possible implementation, the signal generating unit 130 includes: a plurality of first groups of OR gates, a plurality of second groups of OR gates, at least one third group of OR gates, and at least one fourth group of OR gates.

[0080] The input end of each first group of OR gates is connected to the output end of the quota coefficient determination unit 120; the first input end and the second input end of each second group of OR gates are respectively connected to the output end of a first group of OR gates; the first input end and the second input end of each third group of OR gates are respectively connected to the output end of a second group of OR gates; and the first input end and the second input end of each fourth group of OR gates are respectively connected to the output end of a third group of OR gates.

[0081] It is understood that each OR gate of the signal generating unit 130 includes two input terminals. The number of the first group of OR gates can be determined based on the number of the third group of AND gates in the quota coefficient determining unit 120. The number of the second group of OR gates can be determined based on the number of the first group of OR gates, and the number of the third group of OR gates can be determined based on the number of the second group of OR gates. The number of each group of AND gates can be adjusted based on actual conditions and is not specifically limited in this application.

[0082] When determining the enable signal, the quota coefficient determination unit 120 sends the output quota coefficient to the signal generation unit 130. The signal generation unit 130 determines the enable signal output by the quota submodule 100 through the logic unit circuit composed of the above multiple groups of OR gates.

[0083] For example, if the quota coefficients are:

[0084] U0=C0;

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091]

[0092] Then the enable signal U=n8+n7U0+n6U1+n5U2+n4U3+n3U4+n2U5+n1U6+n0U7;

[0093] Wherein, n is the bandwidth coefficient, n8n7n6n5n4n3n2n1n0 respectively represent a one-bit unsigned number, n7U0 represents the logical AND of n7 and U0, n6U1 represents the logical AND of n6 and U1…n0U7 represents the logical AND of n0 and U7; n8+n7U0 represents the logical OR of n8 and n7U0, n8+n7U0+n6U1 represents the logical OR of n8, n7U0 and n6U1…n8+n7U0+n6U1+n5U2+n4U3+n3U4+n2U5+n1U6+n0U7 represents the logical OR of n8, n1U6…and n7U0.

[0094] The bandwidth factor n mentioned above can be configured through registers.

[0095] In the above implementation process, multiple quota coefficients determined in the quota coefficient determination unit are calculated by setting multiple OR gates and set calculation rules to obtain an enable signal with a high level evenly distributed within the clock cycle. Then, the bandwidth speed limit module can be evenly allocated quotas through the enable signal, thereby avoiding bandwidth congestion.

[0096] In a possible implementation, the counting unit 110 includes: a plurality of triggers.

[0097] Among them, multiple triggers are connected in sequence, and the first output end of the previous trigger is connected to the input end of the next trigger; the second output end of each trigger is connected to the input end of the quota coefficient determination unit 120.

[0098] The triggers here constitute a multi-bit unsigned circular accumulator. The number of bits of the unsigned circular accumulator is related to the number of triggers. For example, if the counting unit 110 includes 8 triggers, the unsigned circular accumulator is an 8-bit unsigned circular accumulator; if the counting unit 110 includes 16 triggers, the unsigned circular accumulator is a 16-bit unsigned circular accumulator; if the counting unit 110 includes 32 triggers, the unsigned circular accumulator is a 32-bit unsigned circular accumulator. The number of bits of the unsigned circular accumulator can be adjusted by adjusting the number of triggers, and this application does not impose any specific restrictions.

[0099] The trigger can be a rising edge trigger or a falling edge trigger. The type of the trigger can be adjusted according to actual conditions, and this application does not impose any specific restrictions.

[0100] When the limit submodule generates an enable sequence, the unsigned number loop accumulator increases by 1 in each clock cycle and loops continuously until it reaches the maximum value and then loops back to 0.

[0101] Exemplarily, the unsigned circular accumulator is an 8-bit unsigned circular accumulator. The value of the unsigned circular accumulator can be represented by C. The binary representation of the 8-bit unsigned circular accumulator is C7C6C5C4C3C2C1C0, where C0 represents the least significant bit of the 8-bit unsigned number C, and C7 represents the most significant bit of the 8-bit unsigned number C. When the limit submodule generates an enable sequence, the 8-bit unsigned circular accumulator cycles from C0 to C7 in each clock cycle, and then cycles back to C0.

[0102] In the above implementation process, by setting up multiple triggers to form a counting unit, not only can the clock signal be limited to trigger the counting unit to start action in a specific form after the counting unit obtains the clock signal, but the input clock signal can also be cyclically counted through multiple triggers to output the corresponding clock sequence for the quota coefficient determination unit to perform corresponding logical operations to determine the corresponding quota coefficient, thereby realizing the specific triggering of the clock signal and improving the accuracy of the quota sub-module in processing the clock signal.

[0103] In a possible implementation, m is an integer power of 2, and the bit width of the counting unit 110 is log2 m.

[0104] Here, m is the number of clock cycles. The bit width of the counting unit 110 can be adjusted by adjusting the number of clock cycles. The bit width of the counting unit 110 affects the speed limiting accuracy of the bandwidth speed limiting module 10. The larger the value of m, the smaller the speed limit adjustment granularity and the more accurate the speed limit can be.

[0105] In some embodiments, the value of m can be adjusted by adjusting the number of bits of a register.

[0106] In the above implementation process, since the bit width of the counting unit is log2 m, that is, the value of m affects the bit width of the counting unit, the bit width of the counting unit can be adjusted by adjusting the value of m, and the speed limiting accuracy of the bandwidth speed limiting module can be adjusted. This realizes the adjustability of the speed limiting accuracy of the bandwidth speed limiting module and improves the speed limiting accuracy of the bandwidth speed limiting module.

[0107] In a possible implementation, the bandwidth rate limiting module 10 is applied to a DMA controller.

[0108] In the above implementation process, by applying the bandwidth speed limit module to the DMA controller, uniform speed limit of the DMA controller is achieved, reducing the pressure on the random access memory caused by the fluctuation of instantaneous bandwidth.

[0109] See also Figure 5 , is a flow chart of the bandwidth speed limiting method provided by the embodiment of the present application. Figure 5 The specific process shown is explained in detail.

[0110] Step 201: Acquire an enabling sequence.

[0111] The enable sequence here is n high levels evenly distributed in m clock cycles; where n and m are both non-zero natural numbers.

[0112] Step 202: Count the data passing through the rate limiting device according to the enabling sequence to determine the current remaining traffic quota.

[0113] The enable sequence includes multiple enable signals, which are used to output a level signal, and the level signal is used to control the value of the counter. For example, if the level signal is high, the value of the counter is increased by 1, and if the level signal is low, the value of the counter is decreased by 1.

[0114] The above-mentioned current remaining traffic quota is the remaining amount of data that can be input by the bandwidth rate limit module in the current clock cycle.

[0115] Step 203: Control the on or off of the input switch by using the current remaining traffic quota to control the data input of the external input device.

[0116] It is understandable that the input switch can be controlled to be turned on or off by the value of the current flow quota. For example, the input switch can be set to be turned on when the current flow quota is greater than or equal to 6, and to be turned off when the current flow quota is less than or equal to 3. The input switch can be set to be turned on when the current flow quota is greater than or equal to 0, and to be turned off when the current flow quota is 0, etc. The control of the input switch by the value of the current remaining flow quota can be adjusted according to actual conditions, and this application does not impose any specific restrictions.

[0117] In the above implementation process, the data of the speed limiter is counted by an enable sequence in which n high levels are evenly distributed in m clock cycles, so that the speed limiter can evenly receive n traffic quotas within m clock cycles, thereby making the speed limit of the bandwidth speed limiter module n / m of the total bandwidth, achieving uniform speed limit of the bandwidth speed limiter module, reducing the instantaneous bandwidth, and preventing bandwidth congestion caused by excessive instantaneous bandwidth.

[0118] In one possible implementation, step 202 includes:

[0119] In each clock cycle, if D=1, U=0 and T≠0, then T=T-1;

[0120] If D=0, U=1 and T<min(n, 255), then T=T+1;

[0121] Wherein, D=1 indicates that valid data passes through the bandwidth limit module in the current clock cycle, D=0 indicates that the bandwidth limit module refuses to receive data in the current clock cycle, U indicates an enable sequence, U=0 indicates a low level, U=1 indicates a high level, T indicates the current remaining traffic quota, and min(n, 255) indicates the smaller value of n and 255.

[0122] In some embodiments, if D=1, U=1 or D=0, U=0, T remains unchanged.

[0123] Understandably, U = 0 indicates that the quota submodule has allocated 0 data quota to the bandwidth limit module, while D = 1 indicates that one valid data item passed through the bandwidth limit module during the current clock cycle. If the traffic quota for the current clock cycle is 0, but another valid data item passes through, one data quota item in the bandwidth limit module is occupied by the valid data item. At this point, the current remaining traffic quota is the remaining traffic quota in the bandwidth limit module minus one.

[0124] If U=1, the quota submodule assigns a data quota of 1 to the bandwidth limit module. If D=0, the bandwidth limit module refuses to accept data during the specified clock cycle. If the traffic quota for the current clock cycle is 1 but valid data input is rejected, the bandwidth limit module's data quota remains unused. The remaining traffic quota is the remaining traffic quota in the bandwidth limit module plus one.

[0125] When U = 1, the quota submodule assigns a data quota of 1 to the bandwidth limit module. D = 1 indicates that one valid data item passed through the bandwidth limit module during the current clock cycle. If the current clock cycle's traffic quota is 1, but another valid data item passes through, the data quota occupied by the valid data item offsets the traffic quota. At this point, the remaining traffic quota is the remaining traffic quota in the bandwidth limit module.

[0126] When U = 0, the quota submodule has assigned a data quota of 0 to the bandwidth limit module. D = 0 indicates that the bandwidth limit module refuses to accept data during the current clock cycle. If the traffic quota for the current clock cycle is 0 and valid data input is rejected, the bandwidth limit module's data quota is unused and has not increased. At this point, the remaining traffic quota is the remaining traffic quota in the bandwidth limit module.

[0127] In the above implementation process, the current remaining traffic quota in the bandwidth limit module is determined by the data quota configured by the quota submodule in the current clock cycle and the actual input data in the current clock cycle. The current traffic quota is determined by the data input in real time by the bandwidth limit module, which is more in line with the actual situation and improves the accuracy of determining the current remaining traffic quota.

[0128] In one possible implementation, step 203 includes:

[0129] When the current remaining flow quota is greater than zero, the control input switch is turned on; when the current remaining flow quota is equal to zero, the control input switch is turned off.

[0130] It can be understood that if the current remaining traffic quota is greater than zero, it means that the bandwidth limit module still has traffic quota for data input. In this case, the input switch can be turned on to input external data into the bandwidth limit module. If the current remaining traffic quota is equal to zero, it means that the bandwidth limit module has no traffic quota for data input. In this case, the input switch needs to be turned off to prevent external data from entering the bandwidth limit module.

[0131] In the above implementation process, by controlling the state of the input switch according to whether the current remaining traffic quota is zero, a large amount of data is prevented from being input into the bandwidth rate limiting module at the same time, ensuring that the data input to the bandwidth rate limiting module is maintained within an appropriate quota range, and preventing bandwidth congestion within the same clock cycle.

[0132] Based on the same application concept, the embodiments of the present application also provide a bandwidth speed limiting device corresponding to the bandwidth speed limiting method. Since the principle of solving the problem by the device in the embodiments of the present application is similar to that of the aforementioned bandwidth speed limiting method embodiment, the implementation of the device in this embodiment can refer to the description in the embodiment of the aforementioned method, and the repeated parts will not be repeated.

[0133] See also Figure 6 , is a functional module diagram of the bandwidth speed limiting device provided in the embodiment of the present application. The various modules in the bandwidth speed limiting device in this embodiment are used to execute the various steps in the above method embodiment. The bandwidth speed limiting device includes an acquisition module 301, a counting module 302, and a control module 303; wherein,

[0134] The acquisition module 301 is used to acquire an enable sequence, where the enable sequence is n high levels evenly distributed in m clock cycles; wherein n and m are both non-zero natural numbers.

[0135] The counting module 302 is configured to count the traffic passing through the speed limiting device according to the enabling sequence to determine the current remaining traffic quota.

[0136] The control module 303 is used to control the on or off of the input switch according to the current remaining traffic quota, so as to control the data input of the external input device.

[0137] In a possible implementation, the control module 303 is specifically configured to: when the current remaining traffic quota is greater than zero, control the input switch to be turned on; and when the current remaining traffic quota is equal to zero, control the input switch to be turned off.

[0138] In a possible implementation, the embodiment of the present application further provides a DMA controller, which includes a DMA control module and the bandwidth rate limiting module in the above embodiment connected to the DMA control module.

[0139] The DMA control module is configured to control the bandwidth limit module to execute a speed limit action according to the read and write requests of the peripheral device, so as to limit the data input into the DMA controller.

[0140] The DMA control module here includes a logic control circuit and a register. The above-mentioned DMA control module may be an integrated circuit chip with signal processing capabilities. The above-mentioned DMA control module may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. In addition, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by the processor, the steps of the bandwidth speed limiting method described in the above method embodiment are executed.

[0141] The computer program product of the bandwidth limiting method provided in the embodiments of the present application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the bandwidth limiting method described in the above method embodiments. For details, please refer to the above method embodiments and will not be repeated here.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0143] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0144] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk. It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0145] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0146] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A bandwidth rate limiting module, characterized in that: include: quota submodule, counters, and input switches; The output end of the quota submodule is connected to the counter and configured to generate an enable sequence; The output end of the counter is connected to an external output device, and the counter is configured to count the traffic passing through the bandwidth rate limiting module according to the enabling sequence to determine the current remaining traffic quota of the bandwidth rate limiting module; The input end of the input switch is connected to the external input device, the output end of the input switch is connected to the input end of the counter, and the input switch is configured to be turned on or off according to the current remaining flow quota to control the data input of the external input device; The enabling sequence is n high levels evenly distributed in m clock cycles; n and m are both non-zero natural numbers.

2. The module according to claim 1, characterized in that The quota submodule has a built-in gate circuit, which includes a counting unit, a quota coefficient determination unit and a signal generation unit; The counting unit is connected to the clock signal and is used to obtain the clock signal; The input end of the quota coefficient determination unit is connected to the output end of the counting unit and is configured to determine the quota coefficient; The input terminal of the signal generating unit is connected to the output terminal of the quota coefficient determining unit, and is configured to generate an enable signal to form an enable sequence through the enable signal.

3. The module according to claim 2, characterized in that The quota coefficient determination unit includes: a plurality of NOT gates, a plurality of first groups of AND gates, a plurality of second groups of AND gates, and a plurality of third groups of AND gates; The first input end of each of the first AND gates is connected to the first output end of the counting unit, and the output end of each of the first AND gates is connected to the first input end of the third AND gate. The first input terminal of each of the second group of AND gates is connected to the output terminal of the NOT gate, the output terminal of each of the second group of AND gates is respectively connected to the second input terminal of the first group of AND gates, and the output terminals of the second group of AND gates are sequentially connected to the second input terminals of the second group of AND gates; The input end of the NOT gate is connected to the first output end of the counting unit; The output end of the third group of AND gates is connected to the input end of the signal generating unit.

4. The module according to claim 2, characterized in that The signal generating unit includes: a plurality of first groups of OR gates, a plurality of second groups of OR gates, at least one third group of OR gates and at least one fourth group of OR gates; An input terminal of each of the first group of OR gates is connected to an output terminal of the quota coefficient determination unit; The first input terminal and the second input terminal of each of the second group of OR gates are respectively connected to an output terminal of the first group of OR gates; The first input terminal and the second input terminal of each of the third group of OR gates are respectively connected to an output terminal of the second group of OR gates; The first input terminal and the second input terminal of each of the fourth groups of OR gates are respectively connected to the output terminal of one of the third groups of OR gates.

5. The module according to claim 2, characterized in that The counting unit includes: a plurality of triggers; The plurality of triggers are connected in sequence, and the first output terminal of a previous trigger is connected to the input terminal of a subsequent trigger; The second output terminal of each trigger is connected to the input terminal of the quota coefficient determination unit.

6. The module according to claim 5, characterized in that m is an integer power of 2, and the bit width of the counting unit is .

7. The module according to any one of claims 1 to 6, characterized in that: The bandwidth rate limiting module is applied to the DMA controller.

8. A bandwidth speed limiting method, characterized in that: include: Obtain an enable sequence, wherein the enable sequence is n high levels evenly distributed in m clock cycles; wherein n and m are both non-zero natural numbers; Counting the flow rate passing through the speed limiting device according to the enabling sequence to determine the current remaining flow rate quota; The current remaining flow quota is used to control the on or off state of the input switch to control data input from an external input device.

9. The method according to claim 8, characterized in that Counting the traffic passing through the speed limiter according to the enabling sequence to determine the current remaining traffic quota includes: In each clock cycle, if D=1, U=0 and T≠0, then T=T-1; If D=0, U=1 and T<min(n,255), then T=T+1; Where D = 1 indicates that valid data passes through the bandwidth limiter module in the current clock cycle. D = 0 indicates that the bandwidth limiter module refuses to receive data in the current clock cycle. U represents the enable sequence. U = 0 indicates a low level, and U = 1 indicates a high level. T represents the remaining traffic quota. Min (n, 255) represents the smaller value of n and 255.

10. A DMA controller, characterized in that: include: A DMA control module and a bandwidth rate limiting module according to any one of claims 1 to 7 connected to the DMA control module; The DMA control module is configured to control the bandwidth rate limiting module to perform a rate limiting action according to a read or write request of a peripheral device, so as to limit data input into the DMA controller.

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