Memory device and manufacturing method thereof

Abstract

The present application relates to a memory device and a method for preparing the same. The memory device comprises: a substrate, and a plurality of memory cells arranged in an array on the substrate. The memory cells in adjacent rows are staggered along the row direction, and the distance between two adjacent memory cells in any row is a first distance. The memory cells in adjacent columns are staggered along the column direction, and the staggered distance is less than the first distance. The memory device and its preparation method can further improve the integration density of the memory cells in the memory device and effectively reduce the contact resistance between the memory cells and the bit lines, so as to ensure that the memory device has good and stable storage performance while having high-density integration capabilities.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a memory device and a method for manufacturing the same. Background Art

[0002] Magnetic random access memory (MRAM), as a non-volatile memory, not only has the high-speed read and write capabilities of static random access memory (SRAM), but also has the high-density integration capabilities of dynamic random access memory (DRAM).

[0003] While MRAM's high-density integration capability helps reduce production costs and serves as a core competitive advantage over traditional non-flash memory, further improving MRAM's high-density integration capability remains a pressing challenge in related technologies. Summary of the Invention

[0004] The embodiments of the present application provide a memory device and a method for preparing the same, which can further improve the integration density of memory cells in the memory device and effectively reduce the contact resistance between the memory cells and the bit lines, thereby ensuring that the memory device has high-density integration capabilities while also having good and stable storage performance.

[0005] Some embodiments of the present application provide a memory device. The memory device includes: a substrate; and a plurality of memory cells arranged in an array on the substrate. The memory cells in adjacent rows are staggered along the row direction, and the distance between two adjacent memory cells in any row is a first distance. The memory cells in adjacent columns are staggered along the column direction, and the staggered distance is less than the first distance.

[0006] In some embodiments, the distance between adjacent columns of memory cells staggered along the column direction is less than or equal to a second distance, which is greater than 0.5 times the first distance and less than the first distance.

[0007] In some embodiments, the distance between adjacent rows of memory cells that are staggered along the row direction is less than or equal to 0.5 times the first distance.

[0008] In some embodiments, the memory device further includes: a common source line disposed between the substrate and the memory cells, and a plurality of gate word lines disposed in parallel and spaced apart and extending along a first direction. The gate word lines are located above the source line and connected to corresponding memory cells.

[0009] In some embodiments, a memory cell includes a wraparound gate transistor and a memory module. The wraparound gate transistor is disposed on and connected to a common source line. The wraparound gate transistor is also connected to a corresponding gate word line. The memory module is disposed on and connected to the wraparound gate transistor.

[0010] Optionally, the storage module includes a magnetic tunnel junction arranged in a columnar shape.

[0011] In some embodiments, a wraparound gate transistor includes a columnar structure, a gate dielectric layer, a source, and a drain. The bottom of the columnar structure contacts the common source line, and the top of the columnar structure passes through the gate word line and extends to the memory module. The gate dielectric layer is located between the columnar structure and the gate word line, and the gate dielectric layer partially covers the columnar structure. The source is located at the bottom of the columnar structure and contacts the common source line. The drain is located at the top of the columnar structure and contacts the memory module.

[0012] Optionally, the material of the columnar structure includes indium gallium zinc oxide.

[0013] In some embodiments, the memory device further includes: a plurality of bit lines arranged in parallel and spaced apart and extending along a second direction. The bit lines are located above the memory cells and are connected to the memory cells accordingly. The second direction intersects the first direction.

[0014] In some embodiments, the memory device further includes a plurality of storage node contact structures. The storage node contact structures are located on the memory cells and at least partially cover the memory cells. The bit lines are located on corresponding storage node contact structures and are connected to the memory cells through the storage node contact structures.

[0015] Some embodiments of the present application further provide a method for preparing a memory device, which is used to prepare the memory device described in some of the above embodiments. The method for preparing the memory device includes the following steps.

[0016] A substrate is provided, and a common source line is formed on the substrate.

[0017] A plurality of gate word lines are formed above the common source line and are arranged in parallel and spaced apart from each other. The gate word lines extend along a first direction.

[0018] A plurality of through holes are formed in an array on the substrate. The through holes penetrate the gate word lines and extend to the upper surface of the common source line. The through holes in adjacent rows are staggered along the row direction, and the through holes in adjacent columns are staggered along the column direction.

[0019] A gate dielectric layer is formed on the sidewall of the through hole, and a columnar structure is formed inside the gate dielectric layer. The bottom of the columnar structure contacts the common source line, and the top of the columnar structure is higher than the upper surface of the gate dielectric layer.

[0020] A storage module is formed on top of the columnar structure.

[0021] A plurality of bit lines are formed above the memory module and are arranged in parallel and spaced apart. The bit lines extend along a second direction and are connected to the memory modules accordingly. The second direction intersects the first direction.

[0022] Optionally, the distance between two adjacent through holes in any row is the first distance, and the staggered distance between the through holes in adjacent columns along the column direction is smaller than the first distance.

[0023] Optionally, the staggered distance between adjacent columns of through holes along the column direction is less than or equal to a second distance, which is greater than 0.5 times the first distance and less than the first distance.

[0024] In some embodiments, a plurality of gate word lines spaced apart and arranged in parallel are formed above a common source line, including the following steps.

[0025] A first dielectric layer is formed on the upper surface of the common source line.

[0026] A plurality of gate word lines arranged in parallel and spaced apart are formed on the first dielectric layer, and a second dielectric layer covering the gate word lines is formed.

[0027] Accordingly, a plurality of through holes are formed in an array on the substrate, including forming a plurality of through holes penetrating the second dielectric layer, the gate word lines and the first dielectric layer, and exposing a portion of the common source line through the through holes.

[0028] In some embodiments, a plurality of bit lines spaced apart in parallel are formed above a memory module, including the following steps.

[0029] A storage node contact structure is formed on the memory cell, and the storage node contact structure at least partially covers the memory cell.

[0030] A plurality of bit lines are formed above the storage node contact structure and are arranged in parallel and spaced apart from each other. The bit lines are connected to the corresponding storage cells through the storage node contact structure.

[0031] In an embodiment of the present application, the storage cells in adjacent rows are staggered along the row direction, the storage cells in adjacent columns are staggered along the column direction, and the staggered distance of the storage cells in adjacent columns along the column direction is less than the first distance. Under the premise of meeting the process processing capabilities, the plane area size required to be occupied by each storage cell can be reasonably reduced, thereby ensuring that multiple storage cells have a higher distribution density.

[0032] Furthermore, in an embodiment of the present application, the bit line is arranged above the memory cell. Thus, when the memory cell has a high distribution density, the bit line can be designed to have a larger line width to effectively reduce the contact resistance between the bit line and the memory cell, thereby avoiding the high resistance of the bit line caused by the buried setting, thereby ensuring that the memory device has good and stable storage performance while having high-density integration capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a schematic structural diagram of a storage device provided in one embodiment;

[0035] Figure 2 A schematic diagram of the distribution of a storage unit provided in one embodiment;

[0036] Figure 3 A schematic diagram of the distribution of another storage unit provided in one embodiment;

[0037] Figure 4 is a cross-sectional schematic diagram of a storage unit provided in one embodiment;

[0038] Figure 5 A schematic diagram of the distribution of a memory cell, a storage node contact structure, and a bit line provided in one embodiment;

[0039] Figure 6 1 is a flow chart of a method for preparing a memory device provided in one embodiment;

[0040] Figure 7 and Figure 8 is a schematic structural diagram of the structure obtained in step S11 provided in one embodiment;

[0041] Figure 9 、 Figure 10 、 Figure 11 and Figure 12 Schematic diagram of the structure obtained in step S12 provided in one embodiment;

[0042] Figure 13 This is a schematic structural diagram of the structure obtained in step S13 provided in one embodiment;

[0043] Figure 14This is a schematic structural diagram of the structure obtained in step S14 provided in one embodiment;

[0044] Figure 15 、 Figure 16 and Figure 17 Schematic diagram of the structure obtained in step S15 provided in one embodiment;

[0045] Figure 18 and Figure 19 Schematic diagram of the structure obtained in step S16 provided in one embodiment.

[0046] Description of reference numerals:

[0047] 100-memory device, 1-substrate, 2-memory cell, 21-surround gate transistor, 211-column structure,

[0048] 212 - gate dielectric layer, 213 - source, 213 - drain, 22 - storage module, 220 - MTJ material layer,

[0049] 3-common source line, 4-gate word line, 41-metal material layer, 30-first dielectric layer, 40-second dielectric layer,

[0050] 50-third dielectric layer, 5-storage node contact structure, 6-bit line,

[0051] D1 - the distance between two adjacent storage cells in any row,

[0052] D2- the offset distance of the memory cells in adjacent columns along the column direction,

[0053] D3- The misalignment distance between adjacent rows of storage cells along the row direction,

[0054] D4-The distance between two storage cells with the same sequence number and corresponding to the misalignment in adjacent rows,

[0055] D5 - the distance between two adjacent storage cells in any column,

[0056] R1~R4-row numbers, L1~L8-column numbers. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0060] It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0061] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0062] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0064] In the field of semiconductor integrated circuit manufacturing, the integration density of various electronic devices can be continuously improved by, for example, reducing the minimum component size and / or placing electronic devices closer together to fit various electronic devices into a specific area. Various electronic devices include transistors, diodes, resistors, or capacitors.

[0065] Currently, MRAM's high-density integration capability can increase MRAM's storage range from megabytes to gigabits. However, further increasing MRAM's storage range from 1 gigabyte to 8 gigabytes or higher remains an urgent issue.

[0066] Based on this, see Figure 1 and Figure 2 Some embodiments of the present application provide a memory device 100. The memory device 100 includes a substrate 1 and a plurality of memory cells 2 arranged in an array on the substrate.

[0067] Please combine Figure 1 and Figure 2 It is understood that the memory cells 2 in adjacent rows are staggered along the row direction, and the distance D1 between two adjacent memory cells 2 in any row is the first distance. The memory cells 2 in adjacent columns are staggered along the column direction, and the staggered distance D2 is less than the first distance. That is, D2 is less than D1.

[0068] Here, the first distance is, for example, twice the minimum process dimension F. The minimum process dimension F refers to the minimum dimension that can be processed by the process, also known as a critical dimension, which can be used as a standard for defining the manufacturing process level.

[0069] In the embodiment of the present application, the offset distance D2 of the memory cells 2 in adjacent columns along the column direction refers to: the distance component along the column direction between the memory cells 2 with the same serial number in adjacent columns. Figure 2 As shown in Figure (a), the columns are numbered from left to right (e.g., L1 to L8), and the memory cells 2 in the same column are numbered from bottom to top. Thus, the offset distance D2 between memory cells 2 in adjacent columns along the column direction is, for example, the distance component along the column direction between the first memory cell 2 in the first column L1 and the first memory cell 2 in the second column L2.

[0070] Similarly, the distance D3 between the storage units 2 of adjacent rows along the row direction refers to the distance component along the row direction between the storage units 2 with the same serial number in adjacent rows. Figure 2 As shown in Figure (b), the rows are numbered from bottom to top (e.g., R1 to R4), and the memory cells 2 in the same row are numbered from left to right. Thus, the offset distance D3 between memory cells 2 in adjacent rows along the row direction is, for example, the distance component along the row direction between the second memory cell 2 in the first row R1 and the second memory cell 2 in the second row R2.

[0071] Based on this, please combine Figure 2 and Figure 3 It is understood that when the memory cells 2 in adjacent rows are offset along the row direction and the memory cells 2 in adjacent columns are offset along the column direction, the distance D4 between two corresponding memory cells 2 with the same serial number in adjacent rows can be as small as 2F based on the manufacturing process level. Thus, the distance D2 between the memory cells 2 in adjacent columns along the column direction can be determined based on the distance D3 between the memory cells 2 in adjacent rows along the row direction. Correspondingly, the distance D5 between two adjacent memory cells 2 in any column is twice D2.

[0072] That is to say, in the embodiment of the present application, the storage cells 2 in adjacent rows are staggered along the row direction, the storage cells 2 in adjacent columns are staggered along the column direction, and the staggered distance of the storage cells 2 in adjacent columns along the column direction is less than the first distance. On the premise of meeting the process processing capabilities, the plane area required to be occupied by each storage cell can be reasonably reduced, thereby ensuring that multiple storage cells 2 have a higher distribution density.

[0073] For examples, please see Figure 2 The distance D2 between adjacent columns of memory cells 2 offset along the column direction is less than or equal to the second distance. The second distance is greater than 0.5 times the first distance and less than the first distance. For example, F<D2<2F.

[0074] Optional, see Figure 3 The distance D2 between adjacent columns of memory cells 2 along the column direction is equal to But it doesn’t stop there.

[0075] Thus, the plane area occupied by each storage unit 2 is Approximately 3.46F 2 Compared with the limit plane area size of 4F that can be achieved in related technologies 2 , the embodiment of the present application effectively improves the integration density of the storage unit 2 in the storage device 100.

[0076] For examples, please see Figure 2 The distance D3 between the memory cells 2 of adjacent rows offset along the row direction is less than or equal to 0.5 times the first distance. For example, D3≤F.

[0077] Optional, see Figure 3 , the distance D3 between adjacent rows of memory cells 2 along the row direction is equal to F; correspondingly, the distance D3 between adjacent columns of memory cells 2 along the column direction is equal to

[0078] Thus, if the distance D1 between two adjacent memory cells 2 in any row is, for example, 2F, and the distance D4 between two corresponding memory cells 2 with the same sequence number but offset in adjacent rows is, for example, 2F, the distance D2 between the memory cells 2 in the column direction can be determined based on the size of the offset distance D3 between the memory cells 2 in the adjacent rows. This facilitates determining the distance between the memory cells 2 in the column direction by designing the distance between the memory cells 2 in adjacent rows along the row direction.

[0079] Please continue reading Figure 1 In some embodiments, the memory device 100 further includes: a common source line 3 disposed between the substrate 1 and the memory cells 2, and a plurality of gate word lines 4 disposed in parallel and spaced apart and extending along the first direction. The gate word lines 4 are located above the source line 3 and are connected to the corresponding memory cells 2.

[0080] Here, the first direction is, for example, a row direction, or a direction that forms an angle with the row direction.

[0081] Optionally, the common source line 3 entirely covers the surface of the substrate 1. The common source line 3 may be, for example, a transparent conductive layer, a molybdenum (Mo) layer, an aluminum (Al) layer, or a stack of titanium (Ti) and gold (Au). The transparent conductive layer may be, for example, an indium tin oxide (ITO) film.

[0082] It is understood that the gate word line 4 is located above the common source line 3, and the gate word line 4 is insulated from the common source line 3. For example, a first dielectric layer 30 is provided between the gate word line 4 and the common source line 3. Optionally, the first dielectric layer 30 is an oxide layer, such as a silicon oxide layer.

[0083] Also, please continue reading Figure 1 Memory device 100 further includes a second dielectric layer 40 covering gate word lines 4. Second dielectric layer 40 is used to insulate adjacent gate word lines 4 and planarize the surface of the structure formed after gate word lines 4 are formed to facilitate subsequent fabrication processes. Optionally, second dielectric layer 40 is an oxide layer, such as a silicon oxide layer. Alternatively, second dielectric layer 40 is an organic insulating layer.

[0084] Optionally, the gate word line 4 extends in the row direction, and one gate word line 4 is connected to a row of memory cells 2. The gate word line 4 is, for example, a metal line and can be formed of a metal material with good conductivity. This embodiment of the application does not limit this.

[0085] Please continue reading Figure 1 In some embodiments, the memory cell 2 includes a wraparound gate transistor 21 and a memory module 22. The wraparound gate transistor 21 is disposed on and connected to the common source line 3. The wraparound gate transistor 21 is also connected to a corresponding gate word line 4. The memory module 22 is disposed on and connected to the wraparound gate transistor 21.

[0086] Here, the memory module 22 and the wrap-around gate transistor 21 have the same size, that is, one memory module 22 is correspondingly disposed on one wrap-around gate transistor 21. This helps ensure that the memory device 100 has a higher density integration capability.

[0087] For example, the storage module 22 is a magnetic random access storage module. For example, the storage module 22 is a magnetic tunnel junction (MTJ) arranged in a columnar shape. Optionally, the MTJ includes a free layer, a fixed layer, and a tunneling oxide layer stacked in a direction away from the substrate. However, this is not limited to this, and other types of storage modules may also be applicable.

[0088] For examples, see Figure 4 The wrap-around gate transistor 21 includes a columnar structure 211, a gate dielectric layer 212, a source 213, and a drain 214. The bottom of the columnar structure 211 contacts the common source line 3, and the top of the columnar structure 211 passes through the gate word line 4 and extends to the memory module 22. The gate dielectric layer 212 is located between the columnar structure 211 and the gate word line 4, and the gate dielectric layer 212 partially covers the columnar structure 211. The source 213 is located at the bottom of the columnar structure 211 and contacts the common source line 3. The drain 214 is located at the top of the columnar structure 211 and contacts the memory module 22.

[0089] Here, the source 213 and drain 214 can be formed from portions of the columnar structure 211, such that the portion of the columnar structure 211 between the source 213 and drain 214 serves as a conductive channel. Thus, the gate dielectric layer 212 at least covers the conductive channel. The gate word line 4 is located outside the gate dielectric layer 212, and a portion of the gate word line 4 can serve as the gate of the wrap-around gate transistor 21.

[0090] For example, the gate dielectric layer 212 may be formed of a material having a high-k dielectric constant. For example, the material of the gate dielectric layer 212 includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0091] For example, the columnar structure 211 may be formed of a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO).

[0092] Optionally, the material of the columnar structure 211 includes indium gallium zinc oxide (IGZO). In this way, the wrap-around gate transistor 21 and the memory device 100 can have a lower process temperature, for example, less than or equal to 300°C, thereby avoiding defects in the memory device 100 caused by the influence of high temperature process. In addition, the columnar structure 211 is formed by IGZO, which can ensure that the wrap-around gate transistor 21 has a higher switching current ratio (I on / I off ), for example, greater than or equal to 10 8 , thereby ensuring that the wrap-around gate transistor 21 has excellent electrical performance to meet the driving requirements of the memory device 100, especially the driving requirements of the MTJ.

[0093] In addition, the columnar structure 211 is formed of IGZO, which is convenient for growth on various surfaces, for example, it can be expanded from a two-dimensional (2D) surface to a three-dimensional (3D) surface to meet the different requirements of a two-dimensional memory device 100 or a three-dimensional memory device.

[0094] It is necessary to add that Figure 1 and Figure 4 It is understood that in some embodiments, with the upper surface of the substrate 1 as a reference plane, the surface of the columnar structure 211 facing away from the substrate 1 is higher than the surface of the gate dielectric layer 212 facing away from the substrate 1. The surface of the gate dielectric layer 212 facing away from the substrate 1 is flush with the surface of the second dielectric layer 40 facing away from the substrate 1, or the surface of the gate dielectric layer 212 facing away from the substrate 1 is higher than the surface of the second dielectric layer 40 facing away from the substrate 1.

[0095] Based on this, the memory device 100 further includes a third dielectric layer 50 covering the second dielectric layer 40 and the surface of the gate dielectric layer 212 facing away from the substrate 1. The surface of the third dielectric layer 50 facing away from the substrate 1 is flush with the surface of the columnar structure 211 facing away from the substrate, which helps simplify the process of forming the memory module 22 on the columnar structure 211 and ensures good contact between the memory module 22 and the columnar structure 211. Optionally, the third dielectric layer 50 is an oxide layer, such as a silicon oxide layer. Alternatively, the third dielectric layer 50 is an organic insulating layer.

[0096] Please combine Figure 1 and Figure 5 It is understood that, in some embodiments, the memory device 100 further includes a plurality of storage node contact structures 5 (SNCs). The storage node contact structures 5 are located on the memory cells 2 and at least partially cover the memory cells 2.

[0097] For example, the storage node contact structure 5 is formed on the upper surface of the storage module 22, i.e., the surface of the storage module 22 facing away from the substrate 1, and contacts the storage module 22. The structure of the storage node contact structure 5 can be selected and configured according to actual needs. Optionally, the storage node contact structure 5 is a metal pad, such as a tungsten pad. This ensures that the storage node contact structure 5 has a low resistance value and high stability.

[0098] For example, the orthographic projection of the storage node contact structure 5 on the substrate 1 is rectangular. Thus, when the storage module 22 is a columnar MTJ, the storage node contact structure 5 is rectangular. The storage node contact structure 5 at least partially covers the MTJ, making it easy for the storage node contact structures 5 in adjacent columns to have portions located on the same straight line or in areas adjacent to the same straight line.

[0099] Please continue reading Figure 1 and Figure 5 In some embodiments, the memory device 100 further includes: a plurality of bit lines 6 arranged in parallel and spaced apart and extending along a second direction. The bit lines 6 are located on corresponding storage node contact structures 5 and are connected to corresponding memory cells 2 through the storage node contact structures 5. The second direction intersects with the first direction, for example, is perpendicular to it.

[0100] Here, the second direction is, for example, a column direction, and may also be a direction that forms an angle with the column direction.

[0101] Optionally, the bit lines 6 extend along the column direction, and one bit line 6 is connected to the storage node contact structures 5 on two adjacent columns of memory cells 2. The bit lines 6 are, for example, metal lines and can be formed of a metal material with good conductivity. This embodiment of the present application does not limit this.

[0102] In the embodiment of the present application, the bit lines 6 are located on top of the memory cells 2, and one bit line 6 is connected to two adjacent columns of memory cells 2. Thus, when the memory cells 2 are densely distributed, the bit lines 6 can be designed to have a larger line width to effectively reduce the contact resistance between the bit lines 6 and the memory cells 2, thereby avoiding the high resistance of the bit lines 6 caused by the buried arrangement. This ensures that the memory device 100 has high-density integration capabilities while also having good and stable storage performance.

[0103] See also Figure 6 Some embodiments of the present application further provide a method for preparing a memory device, which is used to prepare the memory device in some of the above embodiments. The method for preparing the memory device includes the following steps.

[0104] S11, providing a substrate, and forming a common source line on the substrate.

[0105] See also Figure 7 , for example, a substrate 1 is provided, and the substrate 1 includes but is not limited to a silicon substrate or a silicon-based substrate.

[0106] See also Figure 8 For example, a common source line 3 is formed on a substrate 1, and the entire common source line 3 covers the surface of the substrate 1. The common source line 3 may be, for example, a transparent conductive layer, a molybdenum (Mo) layer, an aluminum (Al) layer, or a stack of titanium (Ti) and gold (Au). The transparent conductive layer may be, for example, an indium tin oxide (ITO) thin film.

[0107] Optionally, the common source line 3 is formed by a deposition process, which includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0108] In addition, after forming the common source line 3 , the obtained structure may be subjected to chemical mechanical polishing (CMP) to ensure that the surface of the obtained structure is planarized.

[0109] S12, forming a plurality of gate word lines arranged in parallel and spaced apart above the common source line, wherein the gate word lines extend along a first direction.

[0110] Here, the first direction is, for example, the row direction in the aforementioned embodiment, and may also be a direction that forms an angle with the row direction.

[0111] See also Figure 9 、 Figure 10 and Figure 11 In some embodiments, a plurality of gate word lines 4 arranged in parallel and spaced apart are formed above the common source line 3, including the following steps.

[0112] S121, such as Figure 9 As shown in FIG, a first dielectric layer 30 is formed on the upper surface of the common source line 3.

[0113] Here, the upper surface of the common source line 3 is the surface of the common source line 3 facing away from the substrate 1 .

[0114] Optionally, the first dielectric layer 30 is formed of an oxide material, such as a silicon oxide material.

[0115] S122, such as Figure 10 As shown in FIG, a metal material layer 41 is formed on the first dielectric layer 30 .

[0116] Optionally, the metal material layer 41 is formed by depositing a metal material with good electrical conductivity, such as molybdenum (Mo), titanium (Ti), aluminum (Al), or tungsten (W).

[0117] S123, such as Figure 11 As shown in FIG, the metal material layer 41 is patterned to form a plurality of gate word lines 4 that are arranged in parallel and spaced apart.

[0118] Here, the patterning of the metal material layer 41 may be achieved by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0119] In addition, in some embodiments, see Figure 12 , S12 also includes the following steps.

[0120] S124, such as Figure 12 As shown in FIG, a second dielectric layer 40 is formed on the surface of the gate word line 4 facing away from the substrate 1 and the exposed surface of the first dielectric layer 30 , and the second dielectric layer 40 covers the gate word line 4 .

[0121] The second dielectric layer 40 is used to insulate adjacent gate word lines 4 and planarize the surface of the structure formed after the gate word lines 4 are formed, so as to facilitate subsequent fabrication processes. The surface of the second dielectric layer 40 facing away from the substrate 1 may be planarized.

[0122] Optionally, the second dielectric layer 40 is formed of an oxide material or an organic insulating material, for example, a silicon oxide material.

[0123] S13, forming a plurality of through holes arranged in an array on the substrate. The through holes penetrate the gate word lines and extend to the upper surface of the common source line; wherein the through holes in adjacent rows are staggered along the row direction, and the through holes in adjacent columns are staggered along the column direction.

[0124] See also Figure 13 In some embodiments, a plurality of through holes H arranged in an array are formed on the substrate 1, including: forming a plurality of through holes H penetrating the second dielectric layer 40, the gate word line 4 and the first dielectric layer 30; and the through holes H exposing a portion of the common source line 3.

[0125] The purpose of forming the through hole H is to form a wrap-around gate transistor 21 in the through hole H. Moreover, in the embodiment of the present application, the memory cell 2 is composed of a memory module 22 and a wrap-around gate transistor 21, and the memory module 22 is located on the wrap-around gate transistor 21 in a one-to-one correspondence. Therefore, the staggered distance between the through holes H will determine the staggered distance between the memory cells 2. The distribution diagram of the through holes H can be combined with the distribution diagram of the memory cells 2 in some of the aforementioned embodiments (for example, Figure 2 and Figure 3 The embodiments of the present application will not be described in detail here.

[0126] Based on this, optionally, the distance between two adjacent through holes H in any row is a first distance, and the staggered distance between the through holes H in adjacent columns along the column direction is smaller than the first distance.

[0127] Here, the first distance is, for example, twice the minimum process dimension F. The minimum process dimension F refers to the minimum dimension that can be processed by the process, also known as a critical dimension, which can be used as a standard for defining the manufacturing process level.

[0128] Optionally, the distance between the through holes H of adjacent columns that are offset along the column direction is less than or equal to the second distance. The second distance is greater than 0.5 times the first distance and less than the first distance. For example, the distance between the through holes H of adjacent columns that are offset along the column direction is equal to

[0129] Optionally, the range of the distance between the through holes H of adjacent rows staggered along the row direction includes: a closed interval of 0.5 times the first distance to 0.7 times the first distance. For example, the distance D3 between the storage cells 2 of adjacent rows staggered along the row direction is equal to F; correspondingly, the distance D3 between the storage cells 2 of adjacent columns staggered along the column direction is equal to

[0130] In an embodiment of the present application, the through holes H in adjacent rows are staggered along the row direction, the through holes H in adjacent columns are staggered along the column direction, and the staggered distance of the through holes H in adjacent columns along the column direction is less than the first distance. Under the premise of meeting the process processing capabilities, the plane area size required to be occupied by each storage unit 2 can be reasonably reduced, thereby ensuring that multiple storage units 2 have a higher distribution density.

[0131] S14, forming a gate dielectric layer on the sidewall of the through hole and forming a columnar structure inside the gate dielectric layer, wherein the bottom of the columnar structure contacts the common source line and the top of the columnar structure is higher than the upper surface of the gate dielectric layer.

[0132] Here, see Figure 14 The gate dielectric layer 212 and the columnar structure 211 can be formed using a deposition process, such as an atomic layer deposition process. After the columnar structure 211 is formed, the upper surface of the columnar structure 211 can be chemically mechanically polished to facilitate the subsequent formation of the storage node contact structure 5 on the columnar structure 211, thereby ensuring good electrical contact between the columnar structure 211 and the storage node contact structure 5.

[0133] In addition, optionally, the upper surface of the gate dielectric layer 212 (ie, the surface thereof facing away from the substrate 1 ) is higher than the upper surface of the second dielectric layer 40 , or is flush with the upper surface of the second dielectric layer 40 .

[0134] In some embodiments, the gate dielectric layer 212 may be formed of a material having a high-k dielectric constant. For example, the material of the gate dielectric layer 212 includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0135] In some embodiments, the columnar structure 211 may be formed of a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO).

[0136] Please combine Figure 4 and Figure 14 It is understood that in this step, the gate dielectric layer 212 is located between the columnar structure 211 and the gate word line 4, and the gate dielectric layer 212 partially covers the columnar structure 211. The source electrode 213 is located at the bottom of the columnar structure 211 and contacts the common source line 3. The drain electrode 214 is located at the top of the columnar structure 211 and is used to contact the memory module 22. The drain electrode 214 is the top of the columnar structure 211 that is higher than the upper surface of the gate dielectric layer 212.

[0137] Here, the source 213 and drain 214 can be formed by partial regions of the columnar structure 211, so that the portion of the columnar structure 211 between the source 213 and drain 214 serves as a conductive channel. Thus, the gate dielectric layer 212 at least covers the conductive channel. The gate word line 4 is located on the periphery of the gate dielectric layer 212.

[0138] As described above, the pillar structure 211 , the gate dielectric layer 212 , the source 213 , the drain 214 and a portion of the gate word line 4 may together constitute a wrap-around gate transistor 21 , and the portion of the gate word line 4 is the gate of the wrap-around gate transistor 21 .

[0139] S15, forming a storage module on the top of the columnar structure.

[0140] As can be seen from the aforementioned embodiments, the memory modules 22 and the pillar structures 211 are of the same size. This means that one memory module 22 is disposed on one pillar structure 211 (i.e., on the drain 214 of the wrap-around gate transistor 21). This helps ensure that the memory device 100 has a high density integration capability.

[0141] For example, the storage module 22 is a magnetic random access storage module. For example, the storage module 22 is a magnetic tunnel junction (MTJ) arranged in a columnar shape. Optionally, the MTJ includes a free layer, a fixed layer, and a tunneling oxide layer stacked in a direction away from the substrate. However, this is not limited to this, and other types of storage modules may also be applicable.

[0142] Based on this, see Figure 15 、 Figure 16 and Figure 17 In some embodiments, forming a storage module 22 on top of the columnar structure 211 includes the following steps.

[0143] S151, such as Figure 15 As shown in , a third dielectric layer 50 is formed to cover the second dielectric layer 40 and the surface of the gate dielectric layer 212 facing away from the substrate 1 , and the surface of the third dielectric layer 50 facing away from the substrate 1 is flush with the surface of the columnar structure 211 facing away from the substrate.

[0144] Optionally, the third dielectric layer 50 is an oxide layer, such as a silicon oxide layer. Alternatively, the third dielectric layer 50 is an organic insulating layer.

[0145] S152, such as Figure 16 As shown in , an MTJ material layer 220 is formed on the top of the columnar structure 211 and the upper surface of the third dielectric layer 50 .

[0146] Optionally, the MTJ material layer includes: a free material film, a fixed material film, and an oxidized material film formed in a stacked manner.

[0147] S153, such as Figure 17As shown in FIG, the MTJ material layer 220 is patterned to form an MTJ (ie, the memory module 22 ) arranged in a columnar structure, and one MTJ is correspondingly located on one columnar structure 211 .

[0148] Here, the MTJ material layer 220 may be patterned by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0149] S16, forming a plurality of bit lines arranged in parallel and spaced apart above the memory module. The bit lines extend along a second direction and are connected to the memory modules accordingly. The second direction intersects with the first direction, for example, is perpendicular to the first direction.

[0150] Here, the second direction is, for example, a column direction, and may also be a direction that forms an angle with the column direction.

[0151] See also Figure 18 and Figure 19 In some embodiments, a plurality of bit lines 6 arranged in parallel and spaced apart are formed above the memory module 22, including the following steps.

[0152] S161, such as Figure 18 As shown in FIG, a storage node contact structure 5 is formed on the memory cell 2 , for example, the memory module 22 , and the storage node contact structure 5 at least partially covers the memory module 22 .

[0153] Optionally, the orthographic projection of the storage node contact structure 5 on the substrate 1 includes a rectangular shape. In this way, when the storage module 22 is a columnar MTJ, the storage node contact structure 5 adopts a rectangular structure. The storage node contact structure 5 at least partially covers the MTJ, making it easy for the storage node contact structures 5 in adjacent columns to have portions located on the same straight line or in the area next to the same straight line.

[0154] Optionally, the storage node contact structure 5 is a metal pad, such as a tungsten pad, so as to ensure that the storage node contact structure 5 has a lower resistance value and higher stability.

[0155] S162, such as Figure 19 As shown in FIG, a plurality of bit lines 6 are formed above the storage node contact structure 5 and spaced apart in parallel. The bit lines 6 are connected to the memory cells 2 through the storage node contact structure 5 .

[0156] Optionally, the bit lines 6 extend along the column direction, and one bit line 6 is connected to the storage node contact structures 5 on two adjacent columns of memory cells 2. The bit lines 6 are, for example, metal lines and can be formed of a metal material with good conductivity. This embodiment of the present application does not limit this.

[0157] Furthermore, the bit lines 6 can be formed by first forming a metal material layer and then patterning the metal material layer. The patterning of the metal material layer can be achieved using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0158] In the embodiment of the present application, the bit lines 6 are located on top of the memory cells 2, and one bit line 6 is connected to two adjacent columns of memory cells 2. Thus, when the memory cells 2 are densely distributed, the bit lines 6 can be designed to have a larger line width to effectively reduce the contact resistance between the bit lines 6 and the memory cells 2, thereby avoiding the high resistance of the bit lines 6 caused by the buried arrangement. This ensures that the memory device 100 has high-density integration capabilities while also having good and stable storage performance.

[0159] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A memory device, characterized in that: The invention comprises: a substrate, and a plurality of storage units arranged in an array on the substrate; wherein, The storage cells in adjacent rows are staggered along the row direction, and the distance between two adjacent storage cells in any row is a first distance; The storage units in adjacent columns are staggered along the column direction, and the staggered distance is less than the first distance; a plurality of bit lines arranged in parallel and spaced apart and extending along a second direction; the bit lines are located above the memory cells and are connected to the memory cells accordingly; and a common source line disposed between the substrate and the memory cell.

2. The memory device according to claim 1, wherein: The staggered distance between the storage units in adjacent columns along the column direction is less than or equal to a second distance; the second distance is greater than 0.5 times the first distance and less than the first distance.

3. The memory device according to claim 1, wherein: The staggered distance between the storage units in adjacent rows along the row direction is less than or equal to 0.5 times the first distance.

4. The memory device according to claim 1, wherein: The memory device further includes: a plurality of gate word lines arranged in parallel and spaced apart and extending along a first direction; The gate word line is located above the common source line and is correspondingly connected to the storage unit.

5. The memory device according to claim 4, wherein: The storage unit includes: a wrap-around gate transistor, disposed on and connected to the common source line; the wrap-around gate transistor is also connected to the gate word line; And, a storage module is disposed on the wrap-around gate transistor and connected to the wrap-around gate transistor.

6. The memory device according to claim 5, wherein: The storage module includes a magnetic tunnel junction arranged in a columnar shape.

7. The memory device according to claim 5, wherein: The wrap-around gate transistor comprises: a columnar structure, wherein a bottom of the columnar structure contacts the common source line, and a top of the columnar structure passes through the gate word line and extends to the memory module; a gate dielectric layer, located between the columnar structure and the gate word line; the gate dielectric layer partially covers the columnar structure; a source electrode, located at the bottom of the columnar structure and in contact with the common source line; The drain is located on the top of the columnar structure and contacts the storage module.

8. The memory device according to claim 7, wherein: The material of the columnar structure includes indium gallium zinc oxide.

9. The memory device according to any one of claims 1 to 8, wherein: In a case where the memory device includes a gate word line, and the gate word line extends along a first direction, the second direction intersects with the first direction.

10. The memory device according to claim 9, wherein: The memory device further includes a plurality of storage node contact structures; The storage node contact structure is located on the storage unit and at least partially covers the storage unit; The bit line is located on the corresponding storage node contact structure and is connected to the corresponding storage unit through the storage node contact structure.

11. A method for preparing the memory device according to claim 1, characterized in that: include: providing a substrate, and forming a common source line on the substrate; forming a plurality of gate word lines arranged in parallel and spaced apart above the common source line; The gate word line extends along a first direction; A plurality of through holes are formed in an array on the substrate; the through holes penetrate the gate word lines and extend to the upper surface of the common source line; wherein the through holes in adjacent rows are staggered along the row direction, and the through holes in adjacent columns are staggered along the column direction; forming a gate dielectric layer on the sidewall of the through hole, and forming a columnar structure inside the gate dielectric layer; the bottom of the columnar structure contacts the common source line, and the top of the columnar structure is higher than the upper surface of the gate dielectric layer; forming a storage module on top of the columnar structure; A plurality of bit lines are formed above the memory module and are arranged in parallel and spaced apart. The bit lines extend along a second direction and are connected to the memory modules accordingly. The second direction intersects the first direction.

12. The method for preparing a memory device according to claim 11, wherein: The method of forming a plurality of gate word lines spaced apart and arranged in parallel above the common source line comprises: forming a first dielectric layer on the upper surface of the common source line; forming a plurality of gate word lines arranged in parallel and spaced apart on the first dielectric layer, and a second dielectric layer covering the gate word lines; The method of forming a plurality of through holes arranged in an array on the substrate comprises: A plurality of through holes are formed penetrating the second dielectric layer, the gate word lines and the first dielectric layer; the through holes expose portions of the common source lines.

13. The method for preparing a memory device according to claim 11, wherein: The method comprises forming a plurality of bit lines spaced apart and arranged in parallel above the memory module, comprising: forming a storage node contact structure on the storage module, wherein the storage node contact structure at least partially covers the storage module; A plurality of bit lines are formed above the storage node contact structure and are arranged in parallel and spaced apart from each other; the bit lines are connected to the storage modules correspondingly through the storage node contact structure.

14. The method for preparing a memory device according to any one of claims 11 to 13, wherein: The distance between two adjacent through holes in any row is a first distance; The staggered distance between the through holes in adjacent columns along the column direction is smaller than the first distance.

15. The method for preparing a memory device according to claim 14, wherein: The staggered distance between the through holes in adjacent columns along the column direction is less than or equal to a second distance; the second distance is greater than 0.5 times the first distance and less than the first distance.

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