Shift register and driving method thereof, scanning driving circuit, and display device

Abstract

A shift register comprises an input circuit (1), a first output circuit (2), a first control circuit (3), a second control circuit (4), a third control circuit (5) and a second output circuit (6). The input circuit (1) is electrically connected to a first clock signal terminal (SCI), a first voltage signal terminal (VGH) and a first node (Q1). The first output circuit (2) is electrically connected to a first node (Q1), a second clock signal terminal (CLK) and a scan signal terminal (OUT). The first output circuit (2) transmits a second clock signal (CLK) to the scan signal terminal (OUT). The first control circuit (3) is electrically connected to a third clock signal terminal (XCK), a fourth clock signal terminal (SC3), a fifth clock signal terminal (ST) and a first node (Q1). The second control circuit (4) is electrically connected to a sixth clock signal terminal (SC2), a second voltage signal terminal (VGL), a first node (Q1), a first voltage signal terminal (VGH) and a second node (Q2). The third control circuit (5) is electrically connected to the first node (Q1), the second voltage signal terminal (VGL), the third clock signal terminal (XCK) and the second node (Q2). The second output circuit (6) is electrically connected to the second node (Q2), the second voltage signal terminal (VGL) and the scan signal terminal (OUT). The second output circuit (6) transmits the second voltage signal (VGL) to the scan signal terminal (OUT).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a scan driving circuit, and a display device. Background Art

[0002] The scanning drive circuit is an important component of the display device. The scanning drive circuit may include a multi-stage cascaded shift register, and the multi-stage shift register may be electrically connected to a plurality of wires in the display device. The scanning drive circuit may input scanning signals line by line into a plurality of wires (such as gate lines or enable signal lines, etc.) in the display device so that the display device can display a picture.

[0003] Providing a scan driving circuit in a display device can effectively reduce costs and improve yield. Summary of the invention

[0004] In one aspect, a shift register is provided. The shift register includes: an input circuit, a first output circuit, a first control circuit, a second control circuit, a third control circuit and a second output circuit. The input circuit is electrically connected to a first clock signal terminal, a first voltage signal terminal and a first node. The input circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the first node under the control of a first clock signal transmitted by the first clock signal terminal. The first output circuit is electrically connected to the first node, a second clock signal terminal and a scan signal terminal. The first output circuit is configured to transmit a second clock signal received at the second clock signal terminal to the scan signal terminal under the control of a voltage of the first node, so that the scan signal terminal outputs a scan signal. The first control circuit is electrically connected to a third clock signal terminal, a fourth clock signal terminal, a fifth clock signal terminal and the first node. The first control circuit is configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first node under the common control of a third clock signal transmitted by the third clock signal terminal and a fourth clock signal transmitted by the fourth clock signal terminal, so as to control the voltage of the first node. The second control circuit is electrically connected to the sixth clock signal terminal, the second voltage signal terminal, the first node, the first voltage signal terminal and the second node. The second control circuit is configured to, under the control of the sixth clock signal transmitted by the sixth clock signal terminal, transmit the second voltage signal received at the second voltage signal terminal to the first node to control the voltage of the first node, and transmit the first voltage signal to the second node to control the voltage of the second node. The third control circuit is electrically connected to the first node, the second voltage signal terminal, the third clock signal terminal and the second node. The third control circuit is configured to control the voltage of the second node under the mutual cooperation of the voltage of the first node and the third clock signal. The second output circuit is electrically connected to the second node, the second voltage signal terminal and the scan signal terminal. The second output circuit is configured to, under the control of the voltage of the second node, transmit the second voltage signal to the scan signal terminal so that the scan signal terminal outputs a scan signal.

[0005] In some embodiments, the input circuit includes: a first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the first voltage signal terminal, and a second electrode of the first transistor is electrically connected to the first node.

[0006] In some embodiments, the first output circuit includes: a second transistor and a first capacitor. The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the scan signal terminal. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the scan signal terminal.

[0007] In some embodiments, the first control circuit includes: a third transistor and a fourth transistor. The control electrode of the third transistor is electrically connected to the third clock signal terminal, the first electrode of the third transistor is electrically connected to the fifth clock signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the fourth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0008] In some embodiments, the second control circuit includes: a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is electrically connected to the sixth clock signal terminal, the first electrode of the fifth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node. The control electrode of the sixth transistor is electrically connected to the sixth clock signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the second node.

[0009] In some embodiments, the third control circuit includes: a seventh transistor and an eighth transistor. The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second voltage signal terminal, and the second electrode of the seventh transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third clock signal terminal, the first electrode of the eighth transistor is electrically connected to the third clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node. The width-to-length ratio of the seventh transistor is greater than the width-to-length ratio of the eighth transistor.

[0010] In some embodiments, the second output circuit includes: a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the ninth transistor is electrically connected to the scan signal terminal.

[0011] In some embodiments, the third control circuit is also electrically connected to the seventh clock signal terminal. The third control circuit is also configured to control the voltage of the second node under the cooperation of the seventh clock signal transmitted by the seventh clock signal terminal, the voltage of the first node, and the third clock signal. The seventh clock signal and the third clock signal are mutually inverted signals.

[0012] In some embodiments, the third control circuit further includes: a tenth transistor. The control electrode of the tenth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the tenth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the second node. In the case where the third control circuit includes the seventh transistor, the width-to-length ratio of the seventh transistor is greater than the width-to-length ratio of the tenth transistor.

[0013] In some embodiments, the shift register further includes: a fourth control circuit. The fourth control circuit is electrically connected to the second node, the second voltage signal terminal and the first node; the fourth control circuit is further configured to transmit the second voltage signal to the first node under the control of the voltage of the second node.

[0014] In some embodiments, the fourth control circuit includes: an eleventh transistor, wherein a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0015] In some embodiments, the shift register further includes: a first potential raising circuit. The first potential raising circuit is electrically connected to the scan signal terminal and the third node; the first output circuit is also electrically connected to the third node. The first potential raising circuit is configured to raise the voltage of the first node by using the scan signal when the first output circuit causes the scan signal terminal to output the scan signal.

[0016] In some embodiments, the first potential raising circuit includes: a second capacitor. A first end of the second capacitor is electrically connected to the scan signal end, and a second end of the second capacitor is electrically connected to the third node. In the case where the first output circuit includes a first capacitor, the second end of the first capacitor is electrically connected to the scan signal end through the second capacitor.

[0017] In some embodiments, the shift register further includes: a second potential raising circuit. The second potential raising circuit is electrically connected to the first node, the fourth clock signal terminal, the seventh clock signal terminal and the third node; the second potential raising circuit is configured to, under the common control of the voltage of the first node and the fourth clock signal, transmit the seventh clock signal received at the seventh clock signal terminal to the third node, and use the seventh clock signal to raise the voltage of the first node.

[0018] In some embodiments, the second potential raising circuit includes: a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor. The control electrode of the thirteenth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the third node.

[0019] In some embodiments, the shift register further includes: an anti-leakage circuit. The anti-leakage circuit is electrically connected to the first node, the first voltage signal terminal and the anti-leakage node; the anti-leakage circuit is configured to transmit the first voltage signal to the anti-leakage node under the control of the voltage of the first node. The second control circuit is also electrically connected to the anti-leakage node. In the case where the shift register further includes a fourth control circuit, the fourth control circuit is also electrically connected to the anti-leakage node.

[0020] In some embodiments, the anti-leakage circuit includes: a fourteenth transistor. The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the anti-leakage node. In the case where the second control circuit includes a fifth transistor, the fifth transistor includes a first sub-transistor and a second sub-transistor. The control electrode of the first sub-transistor is electrically connected to the sixth clock signal terminal, the first electrode of the first sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the first sub-transistor is electrically connected to the anti-leakage node. The control electrode of the second sub-transistor is electrically connected to the sixth clock signal terminal, the first electrode of the second sub-transistor is electrically connected to the anti-leakage node, and the second electrode of the second sub-transistor is electrically connected to the first node. In the case where the fourth control circuit includes an eleventh transistor, the eleventh transistor includes a third sub-transistor and a fourth sub-transistor. The control electrode of the third sub-transistor is electrically connected to the second node, the first electrode of the third sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the third sub-transistor is electrically connected to the anti-leakage node. The control electrode of the fourth sub-transistor is electrically connected to the second node, the first electrode of the fourth sub-transistor is electrically connected to the anti-leakage node, and the second electrode of the fourth sub-transistor is electrically connected to the first node.

[0021] On the other hand, a driving method of a shift register as described in any one of the above is provided. The driving method comprises: in a first stage, in response to a first clock signal received at a first clock signal terminal, an input circuit is turned on, and a first voltage signal received at a first voltage signal terminal is transmitted to a first node; under the control of the voltage of the first node, a first output circuit is turned on, and a second clock signal received at a second clock signal terminal is transmitted to a scan signal terminal, so that the scan signal terminal outputs a scan signal; under the control of the voltage of the first node, a third control circuit transmits a second voltage signal received at a second voltage signal terminal to a second node, and controls the voltage of the second node; under the control of the voltage of the second node, the second output circuit is turned off. In a second stage, in response to a sixth clock signal received at a sixth clock signal terminal, a second control circuit is turned on, and the second voltage signal is transmitted to the first node, and the voltage of the first node is controlled, and the first voltage signal is transmitted to the second node, and the voltage of the second node is controlled; under the control of the voltage of the first node, the first output circuit is turned off; under the control of the voltage of the second node, the second output circuit is turned on, and the second voltage signal is transmitted to the scan signal terminal, so that the scan signal terminal outputs a scan signal. In the third stage, in response to the third clock signal received at the third clock signal terminal and the fourth clock signal received at the fourth clock signal terminal, the first control circuit transmits the fifth clock signal received at the fifth clock signal terminal to the first node to control the voltage of the first node; under the control of the voltage of the first node, the first output circuit is turned on and transmits the second clock signal to the scan signal terminal so that the scan signal terminal outputs a scan signal; under the control of the voltage of the first node, the third control circuit transmits the second voltage signal to the second node to control the voltage of the second node; under the control of the voltage of the second node, the second output circuit is turned off. In the fourth stage, in response to the third clock signal and the fourth clock signal, the first control circuit transmits the fifth clock signal to the first node to control the voltage of the first node; under the control of the voltage of the first node, the first output circuit is turned off; in response to the third clock signal, the third control circuit transmits the third clock signal to the second node to control the voltage of the second node; under the control of the voltage of the second node, the second output circuit is turned on and transmits the second voltage signal to the scan signal terminal so that the scan signal terminal outputs a scan signal.

[0022] In another aspect, a scan driving circuit is provided, wherein the scan driving circuit comprises: a plurality of cascaded shift registers as described in any one of the above embodiments.

[0023] In another aspect, a display device is provided, comprising: a scan driving circuit as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0025] Figure 1 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0026] Figure 2 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0027] Figure 3 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0028] Figure 4 According to some embodiments of the present disclosure, Figure 3 The timing control diagram of the sub-pixel shown;

[0029] Figure 5 is a structural diagram of a shift register according to some embodiments of the present disclosure;

[0030] Figure 6 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0031] Figure 7 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0032] Figure 8 is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0033] Fig. 9 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0034] Fig.10 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0035] Fig.11 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0036] Fig.12 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0037] Fig.13 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0038] Fig.14 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0039] Fig.15 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0040] Fig.16 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0041] Fig.17 According to some embodiments of the present disclosure, Fig.16 The timing control diagram of the shift register shown;

[0042] Fig.18 According to some embodiments of the present disclosure, Fig.16 The timing control simulation diagram of the shift register shown;

[0043] Fig.19 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0044] Fig. 20 According to some embodiments of the present disclosure, Fig.19 The scan driving circuit shown is a timing simulation diagram of outputting scan signals. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0052] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0056] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as examples.

[0057] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0058] In the circuits provided in the embodiments of the present disclosure, "nodes" do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.

[0059] In the following, in the circuits provided in the embodiments of the present disclosure, N-type transistors are used as examples for description.

[0060] Some embodiments of the present disclosure provide a shift register 100 and a driving method thereof, a scan driving circuit 1000 , and a display device 2000 . The shift register 100 , the driving method of the shift register 100 , the scan driving circuit 1000 , and the display device 2000 are respectively introduced below.

[0061] Some embodiments of the present disclosure provide a display device 2000, such as Figure 1 As shown. The display device 2000 can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether text or. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0062] In some examples, the display device 2000 includes a frame, a display panel PNL disposed in the frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0063] The above-mentioned display panel PNL can be, for example: an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel or a mini light emitting diode (Mini LED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0064] In the following, some embodiments of the present disclosure are schematically described by taking the display panel PNL as an OLED display panel as an example.

[0065] In some embodiments, Figure 2 As shown, the display panel PNL has a display area A and a frame area B arranged beside the display area A. The "side" refers to one side, two sides, three sides or surrounding sides of the display area A, that is, the frame area B can be located on one side, two sides or three sides of the display area A, or the frame area B can be arranged around the display area A.

[0066] In some examples, such as Figure 2 As shown, the display panel PNL may include: a substrate 200 , and a plurality of sub-pixels P, a plurality of gate lines GL, and a plurality of data lines DL disposed on one side of the substrate 200 .

[0067] There are many types of the substrate 200 , which can be selected according to actual needs.

[0068] Exemplarily, the substrate 200 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0069] Exemplarily, the substrate 200 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display panel PNL may be a flexible display panel.

[0070] Optional, such as Figure 2 As shown, the plurality of sub-pixels P, the plurality of gate lines GL and the plurality of data lines DL may be located in the display area A, and the plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y.

[0071] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. Exemplarily, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92° or 95°, etc.

[0072] In some examples, such as Figure 3 As shown, each of the plurality of sub-pixels P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. When the display panel PNL is an OLED display panel, the light emitting device is an OLED.

[0073] The above-mentioned pixel driving circuit has a variety of structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structures. Among them, "T" represents a transistor, and the number in front of "T" represents the number of transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors.

[0074] For example, the above-mentioned multiple sub-pixels P can be arranged in an array, that is, the multiple sub-pixels P can be arranged in multiple rows along the first direction X, and can be arranged in multiple rows along the second direction Y. Among them, the sub-pixels P arranged in a row along the first direction X can be called the same row of sub-pixels P, and the sub-pixels P arranged in a row along the second direction Y can be called the same column of sub-pixels P. Multiple pixel drive circuits in the same row of sub-pixels P can be electrically connected to at least one gate line GL, and multiple pixel drive circuits in the same column of sub-pixels P can be electrically connected to a data line DL. Among them, the number of gate lines GL electrically connected to the multiple pixel drive circuits in the same row of sub-pixels P can be set according to the structure of the pixel drive circuit. The present disclosure is explained by taking the example of multiple pixel drive circuits in the same row of sub-pixels P being electrically connected to a gate line GL.

[0075] Of course, if Figure 2 As shown, according to different structures of the pixel driving circuit, illustratively, the display panel PNL may further include: a plurality of enable signal lines EL arranged on one side of the substrate 1 and extending along the first direction X.

[0076] Exemplarily, one enable signal line EL may be electrically connected to a plurality of pixel driving circuits in the same row of sub-pixels P. The configuration of the enable signal line EL may be determined according to the structure of the pixel driving circuit.

[0077] During the display of the display panel PNL, the sub-pixel P can receive the scanning signal from the corresponding gate line GL and the data signal from the corresponding data line DL to form a driving voltage to drive the light-emitting device in the sub-pixel P to emit light. Alternatively, the sub-pixel P can receive the scanning signal from the corresponding gate line GL, the data signal from the corresponding data line DL and the enable signal from the corresponding enable signal line EL to form a driving voltage to drive the light-emitting device in the sub-pixel P to emit light. Multiple sub-pixels P cooperate with each other to enable the display panel PNL to display images.

[0078] The following is an example of a pixel driving circuit adopting a "2T1C" structure, where sub-pixels P in the same row are electrically connected to a gate line GL, and sub-pixels P in the same column are electrically connected to a data line DL, to schematically illustrate the structure and working process of the sub-pixel P.

[0079] For example, Figure 3 As shown, the above pixel driving circuit includes: a switch transistor M1, a driving transistor M2, and a storage capacitor Cst. Figure 3 For example, it is represented by the first row of sub-pixels P and the second row of sub-pixels P in the display panel PNL. Gate1 represents a gate signal terminal electrically connected to each pixel driving circuit in the first row of sub-pixels P, and Gate2 represents a gate signal terminal electrically connected to each pixel driving circuit in the second row of sub-pixels P.

[0080] For example, Figure 3 As shown, the control electrode of the switch transistor M1 is electrically connected to the gate signal terminal Gate1, the first electrode of the switch transistor M1 is electrically connected to the data signal terminal Data, and the second electrode of the switch transistor M1 is electrically connected to the fourth node G. The switch transistor M1 is configured to transmit the data signal received at the data signal terminal Data to the fourth node G in response to the gate signal received at the gate signal terminal Gate1.

[0081] For example, Figure 3 As shown, the control electrode of the driving transistor M2 is electrically connected to the fourth node G, the first electrode of the driving transistor M2 is electrically connected to the third voltage signal terminal VDD, and the second electrode of the driving transistor M2 is electrically connected to the fifth node S. The driving transistor M2 is configured to transmit the third voltage signal received at the third voltage signal terminal VDD to the fifth node S under the control of the voltage of the fourth node G.

[0082] For example, Figure 3 As shown, a first end of the storage capacitor Cst is electrically connected to the fourth node G, and a second end of the storage capacitor Cst is electrically connected to the fifth node S. In the process of charging the fourth node G, the switch transistor M1 simultaneously charges the storage capacitor Cst.

[0083] For example, Figure 3 As shown, the anode of the light emitting device is electrically connected to the fifth node S, and the cathode of the light emitting device is electrically connected to the fourth voltage signal terminal VSS. The light emitting device is configured to emit light under the cooperation of the third voltage signal from the fifth node S and the fourth voltage signal transmitted by the fourth voltage signal terminal VSS.

[0084] In this example, in the display phase of one frame, the working process of the sub-pixel P may include, for example: a reset phase, a compensation phase, a data writing phase and a light emitting phase.

[0085] It should be noted that in the display stage of one frame, the multiple rows of sub-pixels P included in the display panel PNL simultaneously perform the reset stage and the compensation stage, then perform the data writing stage row by row, and then the multiple rows of sub-pixels P simultaneously perform the light emitting stage.

[0086] The following takes the first row of sub-pixels P and the second row of sub-pixels P as an example. Figure 3 and Figure 4 , the working process of the first row of sub-pixels P and the second row of sub-pixels P is schematically described. Figure 4 The Gate1 shown in FIG. 1 represents a gate signal received by the pixel driving circuit in the first row of sub-pixels P, and the Gate2 represents a gate signal received by the pixel driving circuit in the second row of sub-pixels P.

[0087] In a frame display stage, the working process of the sub-pixel P may include, for example: a reset stage t1 , a compensation stage t2 , and a data writing stage t3 .

[0088] In the reset phase t1 , the level of the gate signal is a high level, and the level of the third voltage signal is a low level.

[0089] The switch transistor M1 in the first row of sub-pixels P is turned on under the control of the gate signal, and receives and transmits the data signal to the fourth node G. At this time, the level of the data signal is, for example, 3.5V.

[0090] The driving transistor M2 is turned on under the control of the voltage of the fourth node G, receives and transmits the third voltage signal to the fifth node S, and resets the fifth node S and the anode of the light emitting device.

[0091] At this stage, the operation process of the pixel driving circuit in the second row of sub-pixels P is the same as the operation process of the pixel driving circuit in the first row of sub-pixels P, which will not be described again.

[0092] That is, in the reset phase t1 , the pixel driving circuits of the multiple rows of sub-pixels P in the display panel PNL may be reset.

[0093] In the compensation stage t2 , the level of the gate signal is high, and the level of the third voltage signal is high.

[0094] The switch transistor M1 in the first row of sub-pixels P is continuously turned on under the control of the gate signal, and continuously transmits the data signal to the fourth node G.

[0095] The level of the third voltage signal changes from a low level to a high level. At this time, the third voltage signal can be transmitted to the fifth node S by the driving transistor M2 to charge the fifth node S, so that the voltage of the fifth node S increases until the driving transistor M2 is turned off. At this time, the voltage difference Vgs between the fourth node G and the fifth node S is equal to the threshold voltage Vth of the driving transistor T2. In this way, the compensation of the driving transistor M2 is also completed.

[0096] At this stage, the operation process of the pixel driving circuit in the second row of sub-pixels P is the same as the operation process of the pixel driving circuit in the first row of sub-pixels P, which will not be described again.

[0097] That is, in the compensation stage t2, the pixel driving circuits of the multiple rows of sub-pixels P in the display panel PNL may be compensated.

[0098] In the data writing phase t3 , the level of the gate signal first jumps from a low level to a high level, and then jumps from a high level to a low level.

[0099] During the period when the level of the gate signal is low, the switch transistor M1 is in the off state. When the level of the gate signal jumps to a high level, the switch transistor M1 is turned on under the control of the gate signal to transmit the data signal to the fourth node G. After the level of the gate signal jumps to a low level, the switch transistor M1 is turned off under the control of the gate signal.

[0100] Here, the gate signals received by the pixel driving circuits of different rows of sub-pixels P have different times of switching from low level to high level, so that the switch transistors M1 of the pixel driving circuits of different rows of sub-pixels P can be turned on at different times, thereby realizing row-by-row data writing.

[0101] It should be noted that, since the data signals required by the pixel driving circuits in the sub-pixels P in different rows may be different, the waveform of the data signal transmitted to the pixel driving circuits in the sub-pixels in the same column may be irregular.

[0102] Of course, the working process of the sub-pixel P may also include, for example: a light emitting stage.

[0103] After completing the row-by-row data writing to the multiple rows of sub-pixels P in the display panel PNL, the multiple rows of sub-pixels P can be driven to emit light simultaneously.

[0104] In some examples, such as Figure 3 As shown, the display panel PNL may include: the above-mentioned scan driving circuit 1000. The scan driving circuit 1000 and the above-mentioned plurality of sub-pixels P, gate lines GL and data lines DL may be located on the same side of the substrate 200.

[0105] The scan driving circuit 1000 may be disposed at various locations, and may be disposed at any location according to actual needs.

[0106] For example, Figure 3 As shown, the scan driving circuit 1000 may be disposed in the border area B and located at one side of the extending direction of the plurality of gate lines GL.

[0107] For example, at least a portion of the scan driving circuit 1000 may be disposed in the display area A. This is beneficial to reducing the occupied area of ​​the scan driving circuit 1000 in the frame area B, thereby reducing the size of the frame area B, so that the display panel PNL and the display device 2000 can achieve a narrow frame design.

[0108] For example, Fig.19 As shown, the scanning driving circuit 1000 comprises a plurality of cascaded shift registers 100. Each shift register 100 can be electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P, for example.

[0109] Here, in the display stage of one frame, the gate signal transmitted by the gate line GL is provided by the scan driving circuit 1000. That is, each shift register 100 in the scan driving circuit 1000 can be electrically connected to the corresponding gate line GL, and transmit the gate signal to the corresponding scan signal terminal Gate through the gate line GL.

[0110] In the related art, the scanning drive circuit usually includes three shift register groups, one of which is used to generate and transmit a reset signal to multiple rows of sub-pixels in the display panel, one of which is used to generate and transmit a compensation signal to multiple rows of sub-pixels in the display panel, and one of which is used to generate and transmit a gate signal to multiple rows of sub-pixels in the display panel. In this way, in the display stage of one frame, the three shift register groups can be used to simultaneously reset and compensate the pixel driving circuits of multiple rows of sub-pixels, write data to the pixel driving circuits of multiple rows of sub-pixels line by line, and drive the light-emitting devices of multiple rows of sub-pixels to emit light. However, the structure of the scanning drive circuit is relatively complex, and the area occupied in the display panel is relatively large. When the scanning drive circuit is set in the border area, the size of the border area will be larger.

[0111] In the scan driving circuit 1000 provided in some embodiments of the present disclosure, the structure of the shift register 100 includes various structures, which can be selected and set according to actual needs as long as the required functions can be achieved.

[0112] In some embodiments, Figure 5 and Figure 6 As shown, the shift register 100 comprises: an input circuit 1 , a first output circuit 2 , a first control circuit 3 , a second control circuit 4 , a third control circuit 5 and a second output circuit 6 .

[0113] In some examples, such as Figure 5 and Figure 6 As shown, the input circuit 1 is electrically connected to the first clock signal terminal SC1, the first voltage signal terminal VGH and the first node Q1. The input circuit 1 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the first node Q1 under the control of the first clock signal transmitted by the first clock signal terminal SC1.

[0114] Exemplarily, the first voltage signal terminal VGH is configured to transmit a DC high-level signal (eg, higher than or equal to the high-level portion of the clock signal); the DC high-level signal is referred to herein as a first voltage signal.

[0115] Exemplarily, when the level of the first clock signal is high, the input circuit 1 can be turned on under the control of the first clock signal, receive and transmit the first voltage signal to the first node Q1, charge the first node Q1, and increase the voltage of the first node Q1.

[0116] In some examples, such as Figure 5 and Figure 6 As shown, the first output circuit 2 is electrically connected to the first node Q1, the second clock signal terminal CLK and the scan signal terminal OUT. The first output circuit 2 is configured to transmit the second clock signal received at the second clock signal terminal CLK to the scan signal terminal OUT under the control of the voltage of the first node Q1, so that the scan signal terminal OUT outputs the scan signal.

[0117] Exemplarily, when the voltage of the first node Q1 is at a high level, the first output circuit 2 can be turned on under the control of the voltage of the first node Q1, receive and transmit the second clock signal to the scan signal terminal OUT, and output the second clock signal from the scan signal terminal OUT as a scan signal.

[0118] In some examples, such as Figure 5 and Figure 6 As shown, the first control circuit 3 is electrically connected to the third clock signal terminal XCK, the fourth clock signal terminal SC3, the fifth clock signal terminal ST and the first node Q1. The first control circuit 3 is configured to transmit the fifth clock signal received at the fifth clock signal terminal ST to the first node Q1 under the common control of the third clock signal transmitted by the third clock signal terminal XCK and the fourth clock signal transmitted by the fourth clock signal terminal SC3, so as to control the voltage of the first node Q1.

[0119] Here, the fifth clock signal may be referred to as a trigger signal.

[0120] Exemplarily, when the level of the third clock signal and the level of the fourth clock signal are both high, the first control circuit 3 can be turned on under the common control of the third clock signal and the fourth clock signal, and receive and transmit the fifth clock signal to the first node Q1. Here, when the level of the fifth clock signal is high, the fifth clock signal can be used to charge the first node Q1, so that the voltage of the first node Q1 is increased to a high level. When the level of the fifth clock signal is low, the fifth clock signal can be used to pull down the voltage of the first node Q1, so that the voltage of the first node Q1 is a low level.

[0121] It should be noted that, for the level of the third clock signal and the level of the fourth clock signal, when both are at a low level, or one is at a high level and the other is at a low level, the first control circuit 3 is in an off state.

[0122] In some examples, such as Figure 5 and Figure 6 As shown, the second control circuit 4 is electrically connected to the sixth clock signal terminal SC2, the second voltage signal terminal VGL, the first node Q1, the first voltage signal terminal VGH and the second node Q2. The second control circuit 4 is configured to, under the control of the sixth clock signal transmitted by the sixth clock signal terminal SC2, transmit the second voltage signal received at the second voltage signal terminal VGL to the first node Q1 to control the voltage of the first node Q1, and transmit the first voltage signal to the second node Q2 to control the voltage of the second node Q2.

[0123] Here, the second voltage signal terminal VGL is configured to transmit a DC low-level signal (e.g., lower than or equal to the low-level portion of the clock signal); the DC low-level signal is referred to as the second voltage signal. The "high level" and "low level" mentioned in this article are relative, and the voltage value of the "high level" and the voltage value of the "low level" are not limited.

[0124] Illustratively, when the level of the sixth clock signal is high, the second control circuit 4 can be turned on under the control of the sixth clock signal, receive and transmit the second voltage signal to the first node Q1, discharge the first node Q1, so that the voltage of the first node Q1 is pulled down to a low level; the second control circuit 4 can also receive and transmit the first voltage signal to the second node Q2, charge the second node Q2, so that the voltage of the second node Q2 is increased to a high level.

[0125] In some examples, such as Figure 5 and Figure 6 As shown, the third control circuit 5 is electrically connected to the first node Q1, the second voltage signal terminal VGL, the third clock signal terminal XCK and the second node Q2. The third control circuit 5 is configured to control the voltage of the second node Q2 under the cooperation of the voltage of the first node Q1 and the third clock signal.

[0126] Exemplarily, when the voltage of the first node Q1 is at a high level, the third control circuit 5 may receive and transmit the second voltage signal to the second node Q2 to discharge the second node Q2 so that the voltage of the second node Q2 is pulled down to a low level.

[0127] When the voltage of the first node Q1 is at a low level and the level of the third clock signal is at a high level, the third control circuit 5 can receive and transmit the third clock signal to the second node Q2, charge the second node Q2, and increase the voltage of the second node Q2 to a high level.

[0128] Here, it should be noted that when the voltage of the first node Q1 is at a high level, even if the level of the third clock signal is at a high level, the voltage of the second node Q2 is mainly controlled by the second voltage signal, that is, the voltage of the second node Q2 is still at a low level.

[0129] In some examples, such as Figure 5 and Figure 6 As shown, the second output circuit 6 is electrically connected to the second node Q2, the second voltage signal terminal VGL and the scan signal terminal OUT. The second output circuit 6 is configured to transmit the second voltage signal to the scan signal terminal OUT under the control of the voltage of the second node Q2, so that the scan signal terminal OUT outputs the scan signal.

[0130] Exemplarily, when the voltage of the second node Q2 is at a high level, the second output circuit 6 can be turned on under the control of the voltage of the second node Q2, receive and transmit the second voltage signal to the scan signal terminal OUT, and output the second voltage signal from the scan signal terminal OUT as a scan signal.

[0131] It should be noted that the first output circuit 2 and the second output circuit 6 are turned on in different time periods, and the scanning signal is composed of a second clock signal and a second voltage signal. The scanning signal corresponds to the gate signal received by the sub-pixel P.

[0132] The following is Fig.17 As an example, the timing diagram shown in Figure 5 and Figure 6 The structure shown schematically illustrates a driving method of the input circuit 1, the first output circuit 2, the first control circuit 3, the second control circuit 4, the third control circuit 5 and the second output circuit 6 included in the shift register 100.

[0133] like Fig.17 As shown, the working process of the shift register 100 includes: a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4.

[0134] In the first stage S1, first, the level of the first clock signal is high and the level of the second clock signal is low. When the level of the first clock signal changes from high to low, the level of the second clock signal changes from low to high. The level of the sixth clock signal is low.

[0135] In response to the first clock signal received at the first clock signal terminal SC1, the input circuit 1 is turned on and transmits the first voltage signal received at the first voltage signal terminal VGH to the first node Q1. The level of the first voltage signal is a high level. After the input circuit 1 is turned on, the first node Q1 can be charged with the first voltage signal, so that the voltage of the first node Q1 is a high level.

[0136] Under the control of the voltage of the first node Q1, the first output circuit 2 is turned on, and the second clock signal received at the second clock signal terminal CLK is transmitted to the scan signal terminal OUT, so that the scan signal terminal OUT outputs the scan signal. In the time period when the level of the first clock signal is high, the level of the second clock signal is low, so the level of the scan signal output by the scan signal terminal OUT is low. Here, the first output circuit 2 has a voltage storage function, that is, the first output circuit 2 will store the high-level first clock signal. After the level of the first clock signal jumps from a high level to a low level and the input circuit 1 is turned off, the first output circuit 2 can maintain the voltage of the first node Q1 at a high level, thereby keeping the first output circuit 2 in the on state in the first stage S1, at which time, the level of the scan signal output by the scan signal terminal OUT is high.

[0137] Since the level of the sixth clock signal is a low level, the second control circuit 4 is in an off state.

[0138] Under the control of the voltage of the first node Q1, the third control circuit 5 transmits the second voltage signal received at the second voltage signal terminal VGL to the second node Q2 to control the voltage of the second node Q2. Here, when the voltage of the first node Q1 is at a high level, the voltage of the second node Q2 is mainly controlled by the second voltage signal transmitted by the third control circuit 5, that is, no matter whether the level of the third clock signal is at a high level or a low level, the voltage of the second node Q2 is at a low level.

[0139] Since the voltage of the second node Q2 is at a low level, at this time, under the control of the voltage of the second node Q2, the second output circuit 6 is in an off state.

[0140] In the second stage S2, the level of the first clock signal is a low level, and the level of the sixth clock signal is a high level.

[0141] In response to the sixth clock signal received at the sixth clock signal terminal SC2, the second control circuit 4 is turned on, transmits the second voltage signal to the first node Q1, controls the voltage of the first node Q1, and transmits the first voltage signal to the second node Q2, controls the voltage of the second node Q2. At this time, the voltage of the first node Q1 is low level, and the voltage of the second node Q2 is high level.

[0142] Since the voltage of the first node Q1 is at a low level, at this time, under the control of the voltage of the first node Q1, the first output circuit 2 is in an off state, and the third control circuit 5 no longer transmits the second voltage signal to the second node Q2.

[0143] Since the voltage of the second node Q2 is at a high level, at this time, under the control of the voltage of the second node Q2, the second output circuit 6 is turned on and transmits the second voltage signal to the scanning signal terminal OUT, so that the scanning signal terminal OUT outputs the scanning signal. Since the level of the second voltage signal is at a low level, therefore, in the second stage S2, the level of the scanning signal output by the scanning signal terminal OUT is at a low level.

[0144] In the third stage S3, the level of the second clock signal is high, the level of the third clock signal is high, the level of the fourth clock signal is high, the level of the fifth clock signal is high, and the level of the fifth clock signal is low.

[0145] In response to the third clock signal received at the third clock signal terminal XCK and the fourth clock signal received at the fourth clock signal terminal SC3, the first control circuit 3 transmits the fifth clock signal received at the fifth clock signal terminal ST to the first node Q1 to control the voltage of the first node Q1. The level of the fifth clock signal is a high level. After the first control circuit 3 is turned on, the first node Q1 can be charged with the fifth clock signal, so that the voltage of the first node Q1 is a high level.

[0146] Under the control of the voltage of the first node Q1, the first output circuit 2 is turned on and transmits the second clock signal to the scanning signal terminal, so that the scanning signal terminal OUT outputs the scanning signal. Since the level of the second clock signal is high, the level of the scanning signal output by the scanning signal terminal OUT is high. In this stage, even if the level of the third clock signal changes, the first output circuit 2 will remain in the on state under the action of its voltage storage function, so that the scanning signal terminal OUT continues to output a high-level scanning signal.

[0147] Since the level of the sixth clock signal is a low level, the second control circuit 4 is in an off state.

[0148] Under the control of the voltage of the first node Q1, the third control circuit 5 transmits the second voltage signal to the second node Q2 to control the voltage of the second node Q2. Here, when the voltage of the first node Q1 is at a high level, the voltage of the second node Q2 is at a low level.

[0149] Since the voltage of the second node Q2 is at a low level, at this time, under the control of the voltage of the second node Q2, the second output circuit 6 is in an off state.

[0150] In the fourth stage S4 , the level of the third clock signal is firstly high level, the level of the fourth clock signal is high level, the level of the fifth clock signal is low level, and the level of the sixth clock signal is low level.

[0151] In response to the third clock signal and the fourth clock signal, the first control circuit 3 transmits the fifth clock signal to the first node Q1 to control the voltage of the first node Q1. The level of the fifth clock signal is low. After the first control circuit 3 is turned on, the fifth clock signal can be used to discharge the first node Q1, so that the voltage of the first node Q1 is low.

[0152] Since the voltage of the first node Q1 is at a low level, the first output circuit 2 is in an off state under the control of the voltage of the first node Q1. Moreover, at this stage, the third control circuit 5 no longer transmits the second voltage signal to the second node Q2.

[0153] Since the level of the sixth clock signal is a low level, the second control circuit 4 is in an off state.

[0154] In response to the third clock signal, the third control circuit 5 transmits the third clock signal to the second node Q2 to control the voltage of the second node Q2. Since the level of the third clock signal is first high, the third control circuit 5 can use the third clock signal to charge the second node Q2, so that the voltage of the second node Q2 is high. Here, the third clock signal will alternately jump between high and low levels at this stage. Since the second control circuit 4 is in the off state, the second node Q2 basically has no discharge path. Therefore, when the level of the third clock signal jumps from a high level to a low level, the voltage of the second node Q2 basically remains at a high level. After that, after the level of the third clock signal jumps from a low level to a high level, the second node Q2 can be further charged, so that the voltage of the second node Q2 remains at a high level.

[0155] Under the control of the voltage of the second node Q2, the second output circuit 6 is turned on and transmits the second voltage signal to the scan signal terminal OUT, so that the scan signal terminal OUT outputs the scan signal. In this stage, the voltage of the second node Q2 remains at a high level, and the second output circuit 6 remains in a conducting state, so that the scan signal terminal OUT continues to output a low-level scan signal.

[0156] Combination Figure 4 and Fig.17 It can be seen that the waveform of the scan signal output by the shift register 100 in some examples of the present disclosure is the same as the waveform of the gate signal required by the sub-pixel P in the display panel PNL. Fig.18As shown, the waveform of the scanning signal is the same as the waveform of the gate signal required by the sub-pixel P in the display panel PNL. That is, by using the above shift register 100, the gate signal required by the sub-pixel P in the display panel PNL can be obtained.

[0157] By electrically connecting multiple shift registers 100 to multiple rows of sub-pixels P in the display panel PNL, the multiple shift registers 100 can be used to provide the required working timing to the pixel driving circuits in the multiple rows of sub-pixels P, so that the multiple rows of sub-pixels P can simultaneously perform the reset stage and the compensation stage during the display stage of one frame, and then perform the row-by-row data writing stage, and then simultaneously perform the light-emitting stage.

[0158] Thus, the shift register 100 provided in some embodiments of the present disclosure, by setting the input circuit 1, the first output circuit 2, the first control circuit 3, the second control circuit 4, the third control circuit 5 and the second output circuit 6, and electrically connecting each circuit to the corresponding signal terminal, can utilize the mutual cooperation between each circuit and each signal terminal to make the first output circuit 2 and the second output circuit 6 conduct in different time periods, and make the second clock signal output by the first output circuit 2 and the second voltage signal output by the second output circuit 6 together constitute a scanning signal. The waveform of the scanning signal is the same as the waveform of the gate signal required by the sub-pixel P in the display panel PNL, so that the shift register 100 can be used to provide a gate signal to the pixel driving circuit of the sub-pixel P in the display panel PNL, so as to realize the display driving of the corresponding sub-pixel P. Using the above-mentioned shift register 100 to drive the sub-pixel P for display is conducive to increasing the time of the data writing stage and the light emitting stage, and further conducive to improving the resolution and refresh frequency of the display panel PNL and the display device 2000.

[0159] In addition, compared with the related art, the shift register 100 provided by the present disclosure has a simpler structure, which is conducive to reducing the structural complexity of the shift register 100 and the scan drive circuit 1000, improving the manufacturing yield of the shift register 100 and the scan drive circuit 1000, and reducing the area occupied by the shift register 100 and the scan drive circuit 1000. In this way, when the shift register 100 and the scan drive circuit 1000 are arranged in the frame area B, it is conducive to reducing the size of the frame area B, so that the display panel PNL and the display device 2000 can achieve a narrow frame design; when the shift register 100 and the scan drive circuit 1000 are arranged in the display area A, it is conducive to reducing the occupied area of ​​the shift register 100 and the scan drive circuit 1000 in the display area A, which is convenient for planning the setting position of the shift register 100 and the scan drive circuit 1000.

[0160] Combine the following Figure 6, structures of the input circuit 1, the first output circuit 2, the first control circuit 3, the second control circuit 4, the third control circuit 5 and the second output circuit 6 included in the shift register 100 are schematically described.

[0161] In some examples, such as Figure 6 As shown, the input circuit 1 comprises: a first transistor T1.

[0162] For example, Figure 6 As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal SC1, the first electrode of the first transistor T1 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the first node Q1.

[0163] For example, when the level of the first clock signal is high, the first transistor T1 may be turned on under the control of the first clock signal, receive the first voltage signal, and transmit the first voltage signal to the first node Q1 to raise the voltage of the first node Q1.

[0164] In some examples, such as Figure 6 As shown, the first output circuit 2 includes: a second transistor T2 and a first capacitor C1.

[0165] For example, Figure 6 As shown, the control electrode of the second transistor T2 is electrically connected to the first node Q1, the first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the scan signal terminal OUT.

[0166] For example, when the voltage of the first node Q1 is at a high level, the second transistor T2 can be turned on under the control of the voltage of the first node Q1, receive the second clock signal, and transmit the second clock signal to the scan signal terminal OUT. At this time, the second clock signal can be used as a scan signal and output from the scan signal terminal OUT.

[0167] For example, Figure 6 As shown, a first end of the first capacitor C1 is electrically connected to the first node Q1, and a second end of the first capacitor C1 is electrically connected to the scan signal terminal OUT.

[0168] For example, in the process that the first transistor T1 charges the first node Q1 using the first voltage signal, the first capacitor C1 is also charged. When the level of the first clock signal is low, the first transistor T1 can be turned off under the control of the first clock signal, and the first capacitor C1 can be discharged, so that the voltage of the first node Q1 remains at a high level, thereby keeping the second transistor T2 turned on.

[0169] In some examples, such as Figure 6 As shown, the first control circuit 3 includes: a third transistor T3 and a fourth transistor T4.

[0170] For example, Figure 6 As shown, the control electrode of the third transistor T3 is electrically connected to the third clock signal terminal XCK, the first electrode of the third transistor T3 is electrically connected to the fifth clock signal terminal ST, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the fourth clock signal terminal SC3, and the second electrode of the fourth transistor T4 is electrically connected to the first node Q1.

[0171] For example, when the level of the third clock signal is high, the third transistor T3 can be turned on under the control of the third clock signal, and receive and transmit the fifth clock signal to the first electrode of the fourth transistor T4. When the level of the fourth clock signal is high, the fourth transistor T4 can be turned on under the control of the fourth clock signal, and transmit the fifth clock signal to the first node Q1. The voltage of the first node Q1 is determined according to the level of the fifth clock signal.

[0172] Here, only when the levels of the third clock signal and the fourth clock signal are both at high levels, the fifth clock signal can be transmitted to the first node Q1 through the third transistor T3 and the fourth transistor T4 in sequence.

[0173] In some examples, such as Figure 6 As shown, the second control circuit 4 includes: a fifth transistor T5 and a sixth transistor T6.

[0174] For example, Figure 6 As shown, the control electrode of the fifth transistor T5 is electrically connected to the sixth clock signal terminal SC2, the first electrode of the fifth transistor T5 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the first node Q1.

[0175] For example, when the level of the sixth clock signal is high, the fifth transistor T5 can be turned on under the control of the sixth clock signal, receive the second voltage signal, and transmit the second voltage signal to the first node Q1, discharge the first node Q1, and pull the voltage of the first node Q1 down to a low level.

[0176] For example, Figure 6 As shown, the control electrode of the sixth transistor T6 is electrically connected to the sixth clock signal terminal SC2, the first electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the second node Q2.

[0177] For example, when the level of the sixth clock signal is high, the sixth transistor T6 can be turned on under the control of the sixth clock signal, receive the first voltage signal, and transmit the first voltage signal to the second node Q2, charging the second node Q2, so that the voltage of the second node Q2 increases to a high level.

[0178] In some examples, such as Figure 6 As shown, the third control circuit 5 includes: a seventh transistor T7 and an eighth transistor T8.

[0179] For example, Figure 6 As shown, the control electrode of the seventh transistor T7 is electrically connected to the first node Q1, the first electrode of the seventh transistor T7 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the second node Q2.

[0180] For example, when the voltage of the first node Q1 is at a high level, the seventh transistor T7 can be turned on under the control of the voltage of the first node Q1, receive the second voltage signal, and transmit the second voltage signal to the second node Q2, discharge the second node Q2, so that the voltage of the second node Q2 is pulled down to a low level.

[0181] For example, Figure 6 As shown, the control electrode of the eighth transistor T8 is electrically connected to the third clock signal terminal XCK, the first electrode of the eighth transistor T8 is electrically connected to the third clock signal terminal XCK, and the second electrode of the eighth transistor T8 is electrically connected to the second node Q2.

[0182] For example, when the level of the third clock signal is high, the eighth transistor T8 can be turned on under the control of the third clock signal, receive the third clock signal, and transmit the third clock signal to the second node Q2, charging the second node Q2, so that the voltage of the second node Q2 increases to a high level.

[0183] Here, it should be noted that, when the voltage of the first node Q1 is at a high level, the voltage of the second node Q2 is mainly controlled by the second clock signal.

[0184] Exemplarily, the width-to-length ratio of the seventh transistor T7 is greater than the width-to-length ratio of the eighth transistor T8.

[0185] In this way, when the seventh transistor T7 is turned on, it can be ensured that the voltage of the second node Q2 is controlled by the second voltage signal transmitted by the seventh transistor T7. That is, when the seventh transistor T7 is turned on, regardless of whether the eighth transistor T8 is turned on, it can be ensured that the voltage of the second node Q2 is at a low level, which is conducive to preventing the voltage of the second node Q2 from being affected by the third clock signal transmitted by the eighth transistor T8, and ensuring the stability of the voltage of the second node Q2.

[0186] In some examples, such as Figure 6 As shown, the second output circuit 6 includes: a ninth transistor T9.

[0187] For example, Figure 6 As shown, the control electrode of the ninth transistor T9 is electrically connected to the second node Q2, the first electrode of the ninth transistor T9 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the ninth transistor T9 is electrically connected to the scan signal terminal OUT.

[0188] For example, when the voltage of the second node Q2 is at a high level, the ninth transistor T9 can be turned on under the control of the voltage of the second node Q2, receive the second voltage signal, and transmit the second voltage signal to the scan signal terminal OUT. At this time, the second voltage signal can be used as a scan signal and output from the scan signal terminal OUT.

[0189] In some embodiments, Figure 7 and Figure 8 As shown, the third control circuit 5 is also electrically connected to the seventh clock signal terminal CK. The third control circuit 5 is also configured to control the voltage of the second node Q2 under the cooperation of the seventh clock signal transmitted by the seventh clock signal terminal CK, the voltage of the first node Q1, and the third clock signal.

[0190] Exemplarily, when the voltage of the first node Q1 is at a low level, the level of the third clock signal is at a low level, and the level of the seventh clock signal is at a high level, the third control circuit 5 can receive and transmit the seventh clock signal to the second node Q2, charge the second node Q2, and increase the voltage of the second node Q2 to a high level.

[0191] It should be noted that, in this example, when the voltage of the first node Q1 is high, regardless of whether the level of the third clock signal is high or the level of the seventh clock signal is high, the voltage of the second node Q2 is still mainly controlled by the level of the second voltage signal.

[0192] In some examples, such as Fig.17 As shown, the seventh clock signal and the third clock signal are inverted signals to each other.

[0193] Exemplarily, the “inverted signal” here means that, within a certain time period, the level of the seventh clock signal and the level of the third clock signal remain unchanged, and when the level of the seventh clock signal is high, the level of the third clock signal is low; when the level of the seventh clock signal is low, the level of the third clock signal is high.

[0194] For example, Fig.17As shown, when the level of the seventh clock signal changes from high level to low level, the level of the third clock signal changes from low level to high level. When the level of the seventh clock signal changes from low level to high level, the level of the third clock signal changes from high level to low level.

[0195] For another example, in a certain time period, when the level of the seventh clock signal changes from low level to high level, the level of the third clock signal changes from high level to low level. Before the level of the seventh clock signal changes from high level to low level, the level of the third clock signal changes from low level to high level.

[0196] Of course, the level of the seventh clock signal and the level of the third clock signal can also be set in other ways, which can satisfy that within the corresponding time period, the level of at least one of the seventh clock signal and the third clock signal is a high level, so that the third control circuit 5 can transmit the corresponding clock signal to the second node Q2.

[0197] The present disclosure is schematically described by taking the case where the level of the seventh clock signal and the level of the third clock signal change simultaneously as an example.

[0198] As can be seen from the above, during the operation of the third control circuit 5, the third control circuit 5 can transmit one of the seventh clock signal and the third clock signal to the second node Q2. For example, when the voltage of the first node Q1 is at a low level, if the level of the seventh clock signal is at a high level and the level of the third clock signal is at a low level, the third control circuit 5 can transmit the seventh clock signal to the second node Q2 to charge the second node Q2; if the level of the seventh clock signal is at a low level and the level of the third clock signal is at a high level, the third control circuit 5 can transmit the third clock signal to the second node Q2 to charge the second node Q2.

[0199] By electrically connecting the third control circuit 5 to the seventh clock signal terminal CK, and setting the seventh clock signal and the third clock signal as inverted signals, the second node Q2 can be continuously charged when the voltage of the first node Q1 is at a low level, so that the voltage of the second node Q2 is maintained at a high level, that is, the voltage of the second node Q2 is in a controllable state. This is conducive to improving the anti-interference ability of the shift register 100, and is conducive to maintaining the second output circuit 6 electrically connected to the second node Q2 in a stable conduction state, thereby helping to improve the accuracy of the scan signal output by the scan signal terminal OUT.

[0200] In some examples, such as Figure 8 As shown, the third control circuit 5 further includes: a tenth transistor T10.

[0201] For example, Figure 8As shown, the control electrode of the tenth transistor T10 is electrically connected to the seventh clock signal terminal CK, the first electrode of the tenth transistor T10 is electrically connected to the seventh clock signal terminal CK, and the second electrode of the tenth transistor T10 is electrically connected to the second node Q2.

[0202] For example, when the level of the seventh clock signal is high, the tenth transistor T10 can be turned on under the control of the seventh clock signal, receive the seventh clock signal, and transmit the seventh clock signal to the second node Q2, charging the second node Q2, so that the voltage of the second node Q2 increases to a high level.

[0203] Here, since the seventh clock signal and the third clock signal are inverted signals, the eighth transistor T8 and the tenth transistor T10 in the third control circuit 5 can be turned on alternately. In this way, when the voltage of the first node Q1 is at a low level and the seventh transistor T7 is turned off, the eighth transistor T8 and the tenth transistor T10 can be used to alternately transmit the high-level third clock signal and the high-level seventh clock signal to the second node Q2, and then the second node Q2 can be continuously charged, so that the voltage of the second node Q2 is in a stable state.

[0204] This can effectively improve the anti-interference capability of the shift register 100. When the second output circuit 6 is turned on to output the scan signal, the second output circuit 6 can be ensured to be in a stably turned-on state, thereby improving the accuracy of the scan signal outputted by the scan signal terminal OUT.

[0205] Exemplarily, in the case where the third control circuit 5 includes the seventh transistor T7 , the width-to-length ratio of the seventh transistor T7 is greater than the width-to-length ratio of the tenth transistor T10 .

[0206] Similar to the eighth transistor T8, by setting the size relationship between the width-to-length ratio of the seventh transistor T7 and the width-to-length ratio of the tenth transistor T10, when the seventh transistor T7 is turned on, regardless of whether the tenth transistor T10 is turned on, it is possible to ensure that the voltage of the second node Q2 is at a low level, and ensure that the voltage of the second node Q2 is mainly controlled by the second voltage signal transmitted by the seventh transistor T7, which is beneficial to avoid the voltage of the second node Q2 being affected by the seventh clock signal transmitted by the tenth transistor T10, and ensure the stability of the voltage of the second node Q2.

[0207] In some embodiments, Fig. 9 and Fig.10 As shown, the shift register 100 further includes: a fourth control circuit 7 .

[0208] In some examples, such as Fig. 9 and Fig.10As shown, the fourth control circuit 7 is electrically connected to the second node Q2, the second voltage signal terminal VGL and the first node Q1. The fourth control circuit 7 is also configured to transmit the second voltage signal to the first node Q1 under the control of the voltage of the second node Q2.

[0209] Exemplarily, when the voltage at the second node Q2 is at a high level, the fourth control circuit 7 can be turned on under the control of the voltage at the second node Q2, receive and transmit the second voltage signal to the first node Q1, discharge the first node Q1, and pull the voltage of the first node Q1 down to a low level.

[0210] By setting the fourth control circuit 7, when the voltage of the second node Q2 is at a high level, the voltage of the first node Q1 can be pulled down to a low level, so that the first output circuit 2 is in an off state under the control of the voltage of the first node Q1. In this way, when the second output circuit 6 is turned on, it can be ensured that the first output circuit 2 is turned off, and further, it can be avoided that the first output circuit 2 outputs the second clock signal when the second output circuit 6 outputs the second voltage signal as the scanning signal, which is conducive to improving the accuracy of the scanning signal and improving the reliability of the shift register 100.

[0211] Combine the following Fig.10 The structure of the fourth control circuit 7 is schematically described.

[0212] In some examples, such as Fig.10 As shown, the fourth control circuit 7 includes: an eleventh transistor T11.

[0213] For example, Fig.10 As shown, the control electrode of the eleventh transistor T11 is electrically connected to the second node Q2, the first electrode of the eleventh transistor T11 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the eleventh transistor T11 is electrically connected to the first node Q1.

[0214] For example, when the voltage of the second node Q2 is at a high level, the eleventh transistor T11 can be turned on under the control of the voltage of the second node Q2, receive the second voltage signal, and transmit the second voltage signal to the first node Q1, pulling the voltage of the first node Q1 down to a low level.

[0215] By setting the eleventh transistor T11, the voltage of the first node Q1 can be pulled down to a low level when the voltage of the second node Q2 is at a high level, thereby ensuring the stable conduction state of the second output circuit 6 and the accuracy of the scan signal output by the scan signal terminal OUT. The fourth control circuit 7 has a simple structure, which is conducive to simplifying the structure of the shift register 100 and improving the yield of the shift register 100.

[0216] In some embodiments, Fig.11 and Fig.12 As shown, the shift register 100 further includes: a first potential raising circuit 8 .

[0217] In some examples, such as Fig.11 and Fig.12 As shown, the first potential raising circuit 8 is electrically connected to the scan signal terminal OUT and the third node Q3. Based on this, the first output circuit 2 is also electrically connected to the third node Q3. The first potential raising circuit 8 is configured to raise the voltage of the first node Q1 by using the scan signal when the first output circuit 2 causes the scan signal terminal OUT to output the scan signal.

[0218] Exemplarily, when the first node Q1 is at a high level, the first output circuit 2 can be turned on under the control of the voltage of the first node Q1, and the second clock signal is output from the scanning signal terminal OUT as a scanning signal. In this stage, after the input circuit 1 transmits the first voltage signal to the first node Q1, it is usually in an off state, thereby making the first node Q1 in a suspended state.

[0219] When the second clock signal received by the scanning signal terminal OUT changes from a low level to a high level, the voltage of the first node Q1 will be further increased based on the coupling bootstrap effect of the first potential raising circuit 8 .

[0220] By setting up the first potential raising circuit 8, the voltage of the first node Q1 can be further raised when the first output circuit 2 causes the scanning signal terminal OUT to output the scanning signal. This helps to ensure that the second transistor T2 in the first output circuit 2 is in a relatively complete conduction state, and further helps to ensure that the scanning signal terminal OUT can be output without loss, thereby improving the accuracy of the scanning signal and the reliability of the shift register 100.

[0221] Combine the following Fig.12 The structure of the first potential raising circuit 8 is schematically described.

[0222] In some examples, such as Fig.12 As shown, the first potential raising circuit 8 includes: a second capacitor C2.

[0223] For example, Fig.12 As shown, the first end of the second capacitor C2 is electrically connected to the scan signal terminal OUT, and the second end of the second capacitor C2 is electrically connected to the third node Q3. Wherein, in the case where the first output circuit 2 includes the first capacitor C2, the second end of the first capacitor C1 is electrically connected to the scan signal terminal OUT through the second capacitor C2. That is, the second capacitor C2 and the first capacitor C1 are arranged in series.

[0224] For example, when the first output circuit 2 is turned on and the second clock signal received by the scan signal terminal OUT changes from a low level to a high level, the second capacitor C2 can be coupled and bootstrapped during this process to increase the voltage of the first node Q1.

[0225] It should be noted that after the input circuit 1 transmits the first voltage signal to the first node Q1 and is turned off, the first node Q1 is in a suspended state. At this time, the first capacitor C1 in the first output circuit 2 can be discharged so that the voltage of the first node Q1 is maintained at a high level.

[0226] By setting a second capacitor C2 and connecting the second capacitor C2 and the first capacitor C1 in series, when the first output circuit 2 is turned on and the second clock signal received by the scanning signal terminal OUT jumps from a low level to a high level, the second capacitor C2 can be used to further raise the voltage of the first node Q1, so that the second transistor T2 can be in a more completely turned-on state, ensuring that the scanning signal terminal OUT can output without loss.

[0227] In some embodiments, Fig.13 and Fig.14 As shown, the shift register 100 further includes: a second potential raising circuit 9 .

[0228] In some examples, such as Fig.13 and Fig.14 As shown, the second potential raising circuit 9 is electrically connected to the first node Q1, the fourth clock signal terminal SC3, the seventh clock signal terminal CK and the third node Q3. The second potential raising circuit 9 is configured to transmit the seventh clock signal received at the seventh clock signal terminal CK to the third node Q3 under the common control of the voltage of the first node Q1 and the fourth clock signal, and raise the voltage of the first node Q1 by using the seventh clock signal.

[0229] Exemplarily, when the voltage of the first node Q1 is at a high level and the level of the fourth clock signal is at a high level, the second potential raising circuit 9 can be turned on under the common control of the voltage of the first node Q1 and the fourth clock signal, and receive and transmit the seventh clock signal to the third node Q3. When the level of the seventh clock signal is at a high level, the voltage of the first node Q1 can be raised through the coupling bootstrap effect of the first capacitor C1 in the second output circuit 2.

[0230] It should be noted that the level of the third clock signal is also high when the second potential raising circuit 9 is turned on. That is, during the process of the second potential raising circuit 9, the voltage of the first node Q1 is first raised by the fifth clock signal transmitted by the first control circuit 3.

[0231] In this example, the types of the third transistor T3 and the fourth transistor T4 included in the first control circuit 3 are, for example, metal oxide thin film transistors. The threshold voltages of the third transistor T3 and the fourth transistor T4 are both positive values. After the fifth clock signal is transmitted to the first node Q1 through the third transistor T3 and the fourth transistor T4, its voltage value is easily lost to a certain extent, making it difficult for the voltage of the first node Q1 to reach a higher voltage, and further making it difficult for the second transistor T2 in the first output circuit 2 to be fully turned on. After the scan signal terminal OUT outputs the scan signal, the voltage value of the scan signal is also lost to a certain extent.

[0232] By providing the second potential raising circuit 9, the voltage of the first node Q1 can be further raised by the second potential raising circuit 9 when the first control circuit 3 is turned on and transmits the fifth clock signal to the first node Q1 to raise the voltage of the first node Q1. In this way, the second transistor T2 in the first output circuit 2 can be in a relatively complete conducting state, thereby ensuring that the scanning signal terminal OUT can be output without loss, thereby improving the accuracy of the scanning signal and the reliability of the shift register 100.

[0233] Combine the following Fig.14 The structure of the second potential raising circuit 9 is schematically described.

[0234] In some examples, such as Fig.14 As shown, the second potential raising circuit 9 includes: a twelfth transistor T12 and a thirteenth transistor T13.

[0235] Exemplarily, the control electrode of the twelfth transistor T12 is electrically connected to the first node Q1, the first electrode of the twelfth transistor T12 is electrically connected to the seventh clock signal terminal CK, and the second electrode of the twelfth transistor T12 is electrically connected to the first electrode of the thirteenth transistor T13. The control electrode of the thirteenth transistor T13 is electrically connected to the fourth clock signal terminal SC3, and the second electrode of the thirteenth transistor T13 is electrically connected to the third node Q3.

[0236] For example, when the voltage of the first node Q1 is at a high level, the twelfth transistor T12 can be turned on under the control of the voltage of the first node Q1, receive the seventh clock signal, and transmit the seventh clock signal to the first electrode of the thirteenth transistor T13. When the level of the fourth clock signal is at a high level, the thirteenth transistor T13 can be turned on under the control of the fourth clock signal, and transmit the seventh clock signal to the third node Q3. The voltage of the third node Q3 is determined according to the level of the seventh clock signal.

[0237] By providing the twelfth transistor T12 and the thirteenth transistor T13, the voltage of the third node Q3 can be raised by the coupling bootstrap effect of the twelfth transistor T12 and the thirteenth transistor T13, and then the voltage of the first node Q1 can be raised by the coupling bootstrap effect of the first capacitor C1.

[0238] In some embodiments, Fig.15 and Fig.16 As shown, the shift register 100 further includes: an anti-leakage circuit 10 .

[0239] In some examples, such as Fig.15 and Fig.16 As shown, the leakage prevention circuit 10 is electrically connected to the first node Q1, the first voltage signal terminal VGH and the leakage prevention node OFF. The leakage prevention circuit 10 is configured to transmit the first voltage signal to the leakage prevention node OFF under the control of the voltage of the first node Q1.

[0240] Exemplarily, when the voltage of the first node Q1 is at a high level, the leakage protection circuit 10 may be turned on under the control of the voltage of the first node Q1 , and receive and transmit the first voltage signal to the leakage protection node OFF.

[0241] Based on this, Fig.15 and Fig.16 As shown, the second control circuit 4 in the shift register 100 is also electrically connected to the anti-leakage node OFF. In this way, when the voltage of the first node Q1 is at a high level, the anti-leakage circuit 10 can transmit the first voltage signal to the anti-leakage node OFF, so that the voltage of the anti-leakage node OFF increases, reducing the voltage difference between the anti-leakage node OFF and the first node Q1, and preventing the first node Q1 from leaking through the first control circuit 4.

[0242] For example, Fig.15 and Fig.16 As shown, in the case where the shift register 100 further includes the fourth control circuit 7, the fourth control circuit 7 is also electrically connected to the leakage prevention node OFF. In this way, when the voltage of the first node Q1 is at a high level, the leakage prevention circuit 10 can transmit the first voltage signal to the leakage prevention node OFF, so that the voltage of the leakage prevention node OFF increases, and the voltage difference between the leakage prevention node OFF and the first node Q1 is reduced, so as to prevent the first node Q1 from leaking through the fourth control circuit 7.

[0243] Combine the following Fig.16 The structures of the leakage prevention circuit 10 , the second control circuit 4 , and the fourth control circuit 7 are schematically described.

[0244] In some examples, such as Fig.16 As shown, the leakage protection circuit 10 includes: a fourteenth transistor T14.

[0245] For example, Fig.16 As shown, the control electrode of the fourteenth transistor T14 is electrically connected to the first node Q1, the first electrode of the fourteenth transistor T14 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the fourteenth transistor T14 is electrically connected to the leakage prevention node OFF.

[0246] For example, when the voltage of the first node Q1 is at a high level, the fourteenth transistor T14 can be turned on under the control of the voltage of the first node Q1, receive the first voltage signal, and transmit the first voltage signal to the anti-leakage node OFF, charging the anti-leakage node OFF, so that the voltage of the anti-leakage node OFF is a high level.

[0247] In some examples, such as Fig.16 As shown, in the case where the second control circuit 4 includes a fifth transistor T5, the fifth transistor T5 includes a first sub-transistor T51 and a second sub-transistor T52.

[0248] For example, Fig.16 As shown, the control electrode of the first sub-transistor T51 is electrically connected to the sixth clock signal terminal SC2, the first electrode of the first sub-transistor T51 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the first sub-transistor T51 is electrically connected to the anti-leakage node OFF. The control electrode of the second sub-transistor T52 is electrically connected to the sixth clock signal terminal SC2, the first electrode of the second sub-transistor T52 is electrically connected to the anti-leakage node OFF, and the second electrode of the second sub-transistor T52 is electrically connected to the first node Q1.

[0249] For example, when the level of the sixth clock signal is high, the first sub-transistor T51 and the second sub-transistor T52 can be turned on at the same time under the control of the sixth clock signal, the first sub-transistor T51 can receive and transmit the second voltage signal to the anti-leakage node OFF, and the second sub-transistor T52 can transmit the second voltage signal from the anti-leakage node OFF to the first node Q1, pulling the voltage of the first node Q1 down to a low level.

[0250] Here, when the voltage of the first node Q1 is at a high level and the second control circuit 4 is in a working state, the leakage prevention circuit 10 can transmit the first voltage signal to the leakage prevention node OFF, reduce the voltage difference between the leakage prevention node OFF and the first node Q1, and make the voltage difference between the control electrode and the second electrode of the first sub-transistor T51 less than zero, ensuring that the first sub-transistor T51 is completely or relatively completely turned off. In this way, the first node Q1 can be prevented from leaking through the second control circuit 4, so that the first node Q1 can be maintained at a higher and more stable voltage.

[0251] In some examples, such as Fig.16 As shown, in the case where the fourth control circuit 7 includes the eleventh transistor T11, the eleventh transistor T11 includes a third sub-transistor T111 and a fourth sub-transistor T112.

[0252] For example, Fig.16 As shown, the control electrode of the third sub-transistor T111 is electrically connected to the second node Q2, the first electrode of the third sub-transistor T111 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the third sub-transistor T111 is electrically connected to the anti-leakage node OFF. The control electrode of the fourth sub-transistor T112 is electrically connected to the second node Q2, the first electrode of the fourth sub-transistor T112 is electrically connected to the anti-leakage node OFF, and the second electrode of the fourth sub-transistor T112 is electrically connected to the first node Q1.

[0253] For example, when the voltage of the second node Q2 is at a high level, the third sub-transistor T111 and the fourth sub-transistor T112 can be turned on at the same time under the control of the voltage of the second node Q2, the third sub-transistor T111 can receive and transmit the second voltage signal to the anti-leakage node OFF, and the fourth sub-transistor T112 can transmit the second voltage signal from the anti-leakage node OFF to the first node Q1, pulling the voltage of the first node Q1 down to a low level.

[0254] Here, when the voltage of the first node Q1 is at a high level and the fourth control circuit 7 is in a working state, the leakage prevention circuit 10 can transmit the first voltage signal to the leakage prevention node OFF, reduce the voltage difference between the leakage prevention node OFF and the first node Q1, and make the voltage difference between the control electrode and the second electrode of the third sub-transistor T111 less than zero, ensuring that the third sub-transistor T111 is completely or relatively completely turned off. In this way, the first node Q1 can be prevented from leaking through the fourth control circuit 7, so that the first node Q1 can be maintained at a higher and more stable voltage.

[0255] In some embodiments, Fig.19 As shown, the scan driving circuit 1000 further includes a plurality of clock signal lines 300 and a plurality of voltage signal lines 400 .

[0256] Below Fig.19 Taking the structure diagram of the scan driving circuit 1000 shown in FIG. 1 as an example, the signal lines in the scan driving circuit 1000 are schematically described.

[0257] like Fig.19 As shown, the scan driving circuit 1000 includes: a first clock signal line CLK_1.

[0258] The first clock signal terminal SC1 of each shift register 100 is electrically connected to the first clock signal line CLK_1 to receive the first clock signal.

[0259] like Fig.19 As shown, the scan driving circuit 1000 includes: a second clock signal line CLK_2.

[0260] The second clock signal terminal CLK of each shift register 100 is electrically connected to the first clock signal line CLK_2 to receive the second clock signal.

[0261] like Fig.19 As shown, the scan driving circuit 1000 includes: a third clock signal line CLK_3.

[0262] The third clock signal terminal XCK of the 2N-1th shift register 100 is electrically connected to the third clock signal line CLK_3 to receive the third clock signal. The seventh clock signal terminal CK of the 2Nth shift register 100 is electrically connected to the third clock signal line CLK_3 to receive the seventh clock signal.

[0263] like Fig.19 As shown, the scan driving circuit 1000 includes: a fourth clock signal line CLK_4.

[0264] The fourth clock signal terminal SC3 of each shift register 100 is electrically connected to the fourth clock signal line CLK_4 to receive the fourth clock signal.

[0265] like Fig.19 As shown, the scan driving circuit 1000 includes: a fifth clock signal line CLK_5.

[0266] The fifth clock signal terminal ST in the first shift register 100 is electrically connected to the fifth clock signal line CLK_5 to receive the fifth clock signal.

[0267] like Fig.19 As shown, except for the first shift register 100 , the fifth clock signal terminal ST of the other shift registers 100 is electrically connected to the scan signal terminal OUT in the previous shift register 100 .

[0268] like Fig.19 As shown, the scan driving circuit 1000 includes: a sixth clock signal line CLK_6.

[0269] The sixth clock signal terminal SC2 of each shift register 100 is electrically connected to the sixth clock signal line CLK_6 to receive the sixth clock signal.

[0270] like Fig.19 As shown, the scan driving circuit 1000 includes: a seventh clock signal line CLK_7.

[0271] The seventh clock signal terminal CK of the 2N-1th shift register 100 is electrically connected to the seventh clock signal line CLK_7 to receive the seventh clock signal. The third clock signal terminal XCK of the 2Nth shift register 100 is electrically connected to the seventh clock signal line CLK_7 to receive the third clock signal.

[0272] like Fig.19 As shown, the scan driving circuit 1000 includes: a first voltage signal line L1.

[0273] The first voltage signal terminal VGH of each shift register 100 is electrically connected to the first voltage signal line L1 to receive the first voltage signal.

[0274] like Fig.19 As shown, the scan driving circuit 1000 includes: a second voltage signal line L2.

[0275] The second voltage signal terminal VGL of each shift register 100 is electrically connected to the second voltage signal line L2 to receive the second voltage signal.

[0276] It should be noted that Fig.19 The cascading relationship shown in is only an example, and other cascading modes may be adopted according to actual conditions.

[0277] Fig.19 A1, A2, A3, A4, ... AN-1, AN shown in the figure represent the first shift register 100, the second shift register 100, the third shift register 100, the fourth shift register 100, ... the N-1th shift register 100, the Nth shift register 100, respectively. Wherein, N represents the number of rows, and N is a positive integer.

[0278] Combine the following Fig.17 and Fig.19 ,right Fig.16 The driving method of the shift register 100 shown in the figure is schematically illustrated in the display stage of one frame.

[0279] Exemplarily, the driving method for the first shift register 100 (e.g., corresponding to the first row of sub-pixels P of the display panel PNL) is described as follows. The driving method includes a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4. The first stage S1 includes stages ① and ②, the second stage S2 includes stage ③, the third stage S3 includes stages ④ and ⑤, and the fourth stage S4 includes stages ⑥ and ⑦.

[0280] In phase ①, the level of the first clock signal is a high level, the level of the second clock signal is a low level, the level of the fourth clock signal is a low level, and the level of the sixth clock signal is a low level.

[0281] The first transistor T1 in the input circuit 1 is turned on under the control of the first clock signal, and transmits the first voltage signal to the first node Q1, so that the voltage of the first node Q1 is at a high level; at the same time, the first capacitor C1 in the first output circuit 2 is charged.

[0282] The level of the fourth clock signal is low, and the first control circuit 3 is in an off state, which can avoid affecting the voltage of the first node Q1.

[0283] The seventh transistor T7 in the third control circuit 4 is turned on under the control of the voltage of the first node Q1, and transmits the second voltage signal to the second node Q2, so that the voltage of the second node Q2 is at a low level.

[0284] The level of the sixth clock signal is low, and the second control circuit 4 is in an off state, which can avoid affecting the voltage of the second node Q2.

[0285] The ninth transistor T9 in the second output circuit 6 is in a turned-off state under the control of the voltage of the second node Q2.

[0286] The second transistor T2 in the first output circuit 2 is turned on under the control of the voltage of the first node Q1, and transmits the second clock signal to the scanning signal terminal OUT.

[0287] Since the level of the second clock signal is a low level, in phase ①, the level of the scanning signal is a low level.

[0288] In phase ②, the level of the first clock signal is a low level, the level of the second clock signal is a high level, the level of the fourth clock signal is a low level, and the level of the sixth clock signal is a low level.

[0289] The first transistor T1 in the input circuit 1 is turned off under the control of the first clock signal.

[0290] The first capacitor C1 in the first output circuit 2 is discharged, so that the voltage of the first node Q1 is maintained at a high level, and thus the second transistor T2 is kept in the on state.

[0291] In this stage, the level of the second clock signal jumps from a low level to a high level, and the voltage of the first node Q1 continues to rise due to the coupling bootstrap effect of the second capacitor C2 in the first potential raising circuit 8. This will keep the second transistor T2 in a relatively complete conduction state, ensuring that the scanning signal terminal OUT can output a high-level scanning signal without loss in stage ②.

[0292] It should be noted that in stage ① and stage ②, the fourteenth transistor T14 in the anti-leakage circuit 10 is in the on state under the control of the voltage of the first node Q1, and transmits the first voltage signal to the anti-leakage node OFF, thereby preventing the first node Q1 from leaking through the fifth transistor T5 in the second control circuit 4 and the eleventh transistor T11 in the fourth control circuit 7.

[0293] In stage ③, the level of the fourth clock signal is low, the level of the sixth clock signal is high first and then changes to low, and the level of the seventh clock signal is low first and then changes to high.

[0294] The fifth transistor T5 and the sixth transistor T6 in the second control circuit 4 are turned on under the control of the sixth clock signal. The fifth transistor T5 transmits the second voltage signal to the first node Q1, so that the voltage of the first node Q1 is at a low level, thereby turning off the second transistor T2 in the first output circuit 2. The sixth transistor T6 transmits the first voltage signal to the second node Q2, so that the voltage of the second node Q2 is at a high level.

[0295] The eleventh transistor T11 in the fourth control circuit 7 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the first node Q1, and continues to lower the voltage of the first node Q1, so as to further ensure the off state of the second transistor T2.

[0296] The ninth transistor T9 in the second output circuit 6 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the scanning signal terminal OUT.

[0297] In addition, when the level of the sixth clock signal jumps from a high level to a low level, the level of the seventh clock signal jumps from a low level to a high level, and the tenth transistor T10 in the third control circuit 5 transmits the seventh clock signal to the second node Q2, and continues to charge the second node Q2, so that the voltage of the second node Q2 remains at a high level, thereby keeping the ninth transistor T9 in the on state.

[0298] Since the level of the second voltage signal is a low level, in phase ③, the level of the scanning signal is a low level.

[0299] As can be seen from the above, in stages ① to ③, the scan signal outputted by the scan signal terminal OUT corresponds to the reset stage and the compensation stage for the sub-pixel P. The duration of the reset stage and the compensation stage can be adjusted by adjusting the sixth clock signal.

[0300] In stage ④, the level of the first clock signal is low, the level of the second clock signal is high, the level of the third clock signal is high, the level of the fourth clock signal is high, the level of the fifth clock signal is high, and the level of the sixth clock signal is low.

[0301] The first transistor T1 in the input circuit 1 is kept in the off state under the control of the first clock signal.

[0302] The third transistor T3 in the first control circuit 3 is turned on under the control of the third clock signal, and the fourth transistor T4 is turned on under the control of the fourth clock signal, and the third transistor T3 and the fourth transistor T4 jointly transmit the fifth clock signal to the first node Q1. At this time, the first node Q1 can be charged by the fifth clock signal of high level, so that the voltage of the first node Q1 is high level, and at the same time, the first capacitor C1 can also be charged.

[0303] The seventh transistor T7 in the third control circuit 4 is turned on under the control of the voltage of the first node Q1, and transmits the second voltage signal to the second node Q2, so that the voltage of the second node Q2 is at a low level.

[0304] The level of the sixth clock signal is low, and the second control circuit 4 is in an off state, which can avoid affecting the voltage of the second node Q2.

[0305] The ninth transistor T9 in the second output circuit 6 is in a turned-off state under the control of the voltage of the second node Q2.

[0306] The first capacitor C1 in the first output circuit 2 is discharged, so that the voltage of the first node Q1 is maintained at a high level, and thus the second transistor T2 is kept in the on state.

[0307] Since the level of the second clock signal is a high level, in phase ④, the level of the scanning signal is a high level.

[0308] In stage ⑤, the level of the third clock signal is a low level, and the level of the seventh clock signal is a high level.

[0309] The third transistor T3 in the first control circuit 3 is turned off under the control of the third clock signal, thereby turning off the first control circuit 3.

[0310] The first capacitor C1 in the first output circuit 2 is discharged, so that the voltage of the first node Q1 is maintained at a high level, and thus the second transistor T2 is kept in the on state.

[0311] The twelfth transistor T12 in the second potential raising circuit 9 can be turned on under the control of the voltage of the first node Q1, and the thirteenth transistor T13 can be turned on under the control of the fourth clock signal. The twelfth transistor T12 and the thirteenth transistor T13 jointly transmit the seventh clock signal to the third node Q3.

[0312] Since the level of the seventh clock signal jumps to a high level, the first capacitor C1 can couple the voltage of the third node Q3 to the first node Q1, further raising the voltage of the first node Q1. This will keep the second transistor T2 in a relatively complete conduction state, ensuring that the scanning signal terminal OUT can output a high-level scanning signal without loss in stage ⑤.

[0313] It should be noted that the scanning signal outputted by the scanning signal terminal OUT in this stage corresponds to the data writing stage for the sub-pixel P.

[0314] In phase ⑥, the level of the third clock signal is a high level, the level of the fifth clock signal is a low level, and the level of the seventh clock signal is a low level.

[0315] The third transistor T3 and the fourth transistor T4 in the first control circuit 3 transmit the fifth clock signal to the first node Q1 , and pull the voltage of the first node Q1 down to a low level.

[0316] The second transistor T2 in the first output circuit 2 is turned off under the control of the voltage of the first node Q1.

[0317] Under the control of the third clock signal, the eighth transistor T8 in the third control circuit 5 transmits the third clock signal to the second node Q2 to charge the second node Q2, so that the voltage of the second node Q2 is at a high level.

[0318] The eleventh transistor T11 in the fourth control circuit 7 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the first node Q1, further lowering the voltage of the first node Q1.

[0319] The ninth transistor T9 in the second output circuit 6 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the scanning signal terminal OUT.

[0320] Since the level of the second voltage signal is a low level, in phase ⑥, the level of the scanning signal is a low level.

[0321] In phase ⑦, the level of the third clock signal is a low level, and the level of the seventh clock signal is a high level.

[0322] Under the control of the seventh clock signal, the tenth transistor T10 in the third control circuit 5 transmits the seventh clock signal to the second node Q2 to charge the second node Q2 so that the voltage of the second node Q2 is maintained at a high level.

[0323] The eleventh transistor T11 in the fourth control circuit 7 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the first node Q1, further lowering the voltage of the first node Q1.

[0324] The ninth transistor T9 in the second output circuit 6 is turned on under the control of the voltage of the second node Q2, and transmits the second voltage signal to the scanning signal terminal OUT.

[0325] In this stage, the level of the third clock signal alternates between a low level and a high level, and the level of the seventh clock signal alternates between a high level and a low level, which can ensure that the voltage of the first node Q1 remains at a low level, and that the voltage of the second node Q2 remains at a high level, thereby ensuring that the level of the scanning signal output from the scanning signal terminal OUT is maintained at a low level.

[0326] For example, Fig. 20 The scanning signal terminal OUT of the first shift register 100 in the scanning driving circuit 1000 is <1> The output scanning signal, the scanning signal terminal OUT of the second shift register 100 <2> The output scanning signal, the scanning signal terminal OUT of the third shift register 100 <3> The output scanning signal, the scanning signal terminal OUT of the 105th shift register 100 <105> The output scanning signal, the scanning signal terminal OUT of the 106th shift register 100 <106> The output scanning signal, the scanning signal terminal OUT of the 107th shift register 100 <107> The output scanning signal, the scanning signal terminal OUT of the 214th shift register 100 <214> The output scanning signal, the scanning signal terminal OUT of the 215th shift register 100 <215> The output scanning signal, the scanning signal terminal OUT of the 216th shift register 100 <216> The timing diagram of the output scanning signal is as follows: Fig. 20 It can be seen that after passing through 216 shift registers 100, the scanning signal is substantially not attenuated, and the integrity of the scanning signal is good.

[0327] In the above-mentioned embodiments of the present disclosure, the conduction and cut-off (opening and closing) processes of the transistors are explained by taking all the transistors as N-type transistors as an example; in the embodiments of the present disclosure, the transistors may also be P-type. When all the transistors are P-type, it is only necessary to flip each control signal.

[0328] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: The shift register comprises: an input circuit electrically connected to the first clock signal terminal, the first voltage signal terminal and the first node; the input circuit being configured to transmit the first voltage signal received at the first voltage signal terminal to the first node under the control of the first clock signal transmitted by the first clock signal terminal; a first output circuit electrically connected to the first node, the second clock signal terminal and the scan signal terminal; the first output circuit is configured to, under the control of the voltage of the first node, transmit the second clock signal received at the second clock signal terminal to the scan signal terminal, so that the scan signal terminal outputs a scan signal; a first control circuit electrically connected to a third clock signal terminal, a fourth clock signal terminal, a fifth clock signal terminal and the first node; the first control circuit being configured to, under the common control of a third clock signal transmitted by the third clock signal terminal and a fourth clock signal transmitted by the fourth clock signal terminal, transmit a fifth clock signal received at the fifth clock signal terminal to the first node, and control a voltage of the first node; a second control circuit electrically connected to the sixth clock signal terminal, the second voltage signal terminal, the first node, the first voltage signal terminal and the second node; the second control circuit is configured to, under the control of the sixth clock signal transmitted by the sixth clock signal terminal, transmit the second voltage signal received at the second voltage signal terminal to the first node to control the voltage of the first node, and transmit the first voltage signal to the second node to control the voltage of the second node; a third control circuit electrically connected to the first node, the second voltage signal terminal, the third clock signal terminal and the second node; the third control circuit is configured to control the voltage of the second node under the cooperation of the voltage of the first node and the third clock signal; and The second output circuit is electrically connected to the second node, the second voltage signal terminal and the scan signal terminal; the second output circuit is configured to transmit the second voltage signal to the scan signal terminal under the control of the voltage of the second node so that the scan signal terminal outputs a scan signal.

2. The shift register according to claim 1, characterized in that: The input circuit comprises: a first transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first voltage signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

3. The shift register according to claim 1, wherein: The first output circuit includes: a second transistor and a first capacitor; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the scan signal terminal; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the scan signal end.

4. The shift register according to claim 1, wherein: The first control circuit includes: a third transistor and a fourth transistor; The control electrode of the third transistor is electrically connected to the third clock signal terminal, the first electrode of the third transistor is electrically connected to the fifth clock signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; A control electrode of the fourth transistor is electrically connected to the fourth clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the first node.

5. The shift register according to claim 1, characterized in that: The second control circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the sixth clock signal terminal, the first electrode of the fifth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the sixth clock signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the second node.

6. The shift register according to claim 1, characterized in that: The third control circuit includes: a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second voltage signal terminal, and the second electrode of the seventh transistor is electrically connected to the second node; The control electrode of the eighth transistor is electrically connected to the third clock signal terminal, the first electrode of the eighth transistor is electrically connected to the third clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node; The aspect ratio of the seventh transistor is greater than the aspect ratio of the eighth transistor.

7. The shift register according to claim 1, characterized in that: The second output circuit comprises: a ninth transistor; The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the ninth transistor is electrically connected to the scan signal terminal.

8. The shift register according to claim 6, characterized in that: The third control circuit is also electrically connected to the seventh clock signal terminal; The third control circuit is further configured to control the voltage of the second node under the cooperation of the seventh clock signal transmitted by the seventh clock signal terminal, the voltage of the first node, and the third clock signal; The seventh clock signal and the third clock signal are inverted signals to each other.

9. The shift register according to claim 8, characterized in that: The third control circuit further includes: a tenth transistor; The control electrode of the tenth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the tenth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the second node; A width-to-length ratio of the seventh transistor is greater than a width-to-length ratio of the tenth transistor.

10. The shift register according to claim 1, characterized in that: The shift register further includes: a fourth control circuit; The fourth control circuit is electrically connected to the second node, the second voltage signal terminal and the first node; the fourth control circuit is also configured to transmit the second voltage signal to the first node under the control of the voltage of the second node.

11. The shift register according to claim 10, characterized in that: The fourth control circuit comprises: an eleventh transistor; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal, and the second electrode of the eleventh transistor is electrically connected to the first node.

12. The shift register according to claim 1, characterized in that: The shift register further includes: a first potential raising circuit; The first potential raising circuit is electrically connected to the scanning signal terminal and the third node; the first output circuit is also electrically connected to the third node; The first potential raising circuit is configured to raise the voltage of the first node by using the scan signal when the first output circuit causes the scan signal terminal to output the scan signal.

13. The shift register according to claim 12, characterized in that: The first potential raising circuit comprises: a second capacitor; A first end of the second capacitor is electrically connected to the scan signal end, and a second end of the second capacitor is electrically connected to the third node; In the case where the first output circuit includes a first capacitor, a second end of the first capacitor is electrically connected to the scan signal end through the second capacitor.

14. The shift register according to claim 12, characterized in that: The shift register further includes: a second potential raising circuit; The second potential raising circuit is electrically connected to the first node, the fourth clock signal terminal, the seventh clock signal terminal and the third node; the second potential raising circuit is configured to, under the joint control of the voltage of the first node and the fourth clock signal, transmit the seventh clock signal received at the seventh clock signal terminal to the third node, and use the seventh clock signal to raise the voltage of the first node.

15. The shift register according to claim 14, characterized in that: The second potential raising circuit comprises: a twelfth transistor and a thirteenth transistor; The control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; A control electrode of the thirteenth transistor is electrically connected to the fourth clock signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the third node.

16. The shift register according to any one of claims 1 to 15, characterized in that: The shift register further includes: an anti-leakage circuit; The anti-leakage circuit is electrically connected to the first node, the first voltage signal terminal and the anti-leakage node; the anti-leakage circuit is configured to transmit the first voltage signal to the anti-leakage node under the control of the voltage of the first node; Wherein, the second control circuit is also electrically connected to the anti-leakage node; In the case where the shift register further includes a fourth control circuit, the fourth control circuit is also electrically connected to the leakage prevention node.

17. The shift register according to claim 16, characterized in that: The anti-leakage circuit comprises: a fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the anti-leakage node; In the case where the second control circuit includes a fifth transistor, the fifth transistor includes a first sub-transistor and a second sub-transistor; The control electrode of the first sub-transistor is electrically connected to the sixth clock signal terminal, the first electrode of the first sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the first sub-transistor is electrically connected to the anti-leakage node; The control electrode of the second sub-transistor is electrically connected to the sixth clock signal terminal, the first electrode of the second sub-transistor is electrically connected to the anti-leakage node, and the second electrode of the second sub-transistor is electrically connected to the first node; In the case where the fourth control circuit includes an eleventh transistor, the eleventh transistor includes a third sub-transistor and a fourth sub-transistor; The control electrode of the third sub-transistor is electrically connected to the second node, the first electrode of the third sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the third sub-transistor is electrically connected to the anti-leakage node; The control electrode of the fourth sub-transistor is electrically connected to the second node, the first electrode of the fourth sub-transistor is electrically connected to the anti-leakage node, and the second electrode of the fourth sub-transistor is electrically connected to the first node.

18. A method for driving a shift register according to any one of claims 1 to 17, characterized in that: The driving method comprises: In the first stage, in response to a first clock signal received at the first clock signal terminal, the input circuit is turned on to transmit a first voltage signal received at the first voltage signal terminal to the first node; Under the control of the voltage of the first node, the first output circuit is turned on to transmit the second clock signal received at the second clock signal terminal to the scan signal terminal, so that the scan signal terminal outputs a scan signal; Under the control of the voltage of the first node, the third control circuit transmits the second voltage signal received at the second voltage signal terminal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the second output circuit is turned off; In the second stage, in response to the sixth clock signal received at the sixth clock signal terminal, the second control circuit is turned on, transmits the second voltage signal to the first node to control the voltage of the first node, and transmits the first voltage signal to the second node to control the voltage of the second node; Under the control of the voltage of the first node, the first output circuit is turned off; Under the control of the voltage of the second node, the second output circuit is turned on to transmit the second voltage signal to the scan signal terminal, so that the scan signal terminal outputs a scan signal; In the third stage, in response to the third clock signal received at the third clock signal terminal and the fourth clock signal received at the fourth clock signal terminal, the first control circuit transmits the fifth clock signal received at the fifth clock signal terminal to the first node to control the voltage of the first node; Under the control of the voltage of the first node, the first output circuit is turned on to transmit the second clock signal to the scan signal terminal, so that the scan signal terminal outputs a scan signal; Under the control of the voltage of the first node, the third control circuit transmits the second voltage signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the second output circuit is turned off; In the fourth stage, in response to the third clock signal and the fourth clock signal, the first control circuit transmits the fifth clock signal to the first node to control the voltage of the first node; Under the control of the voltage of the first node, the first output circuit is turned off; In response to the third clock signal, the third control circuit transmits the third clock signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the second output circuit is turned on to transmit the second voltage signal to the scan signal terminal, so that the scan signal terminal outputs a scan signal.

19. A scanning driving circuit, characterized in that: The scan driving circuit comprises: a plurality of cascaded shift registers according to any one of claims 1 to 17.

20. A display device, characterized in that: The display device comprises: the scan driving circuit as claimed in claim 19.

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