A current source starting circuit

Abstract

The present invention discloses a current source startup circuit, which relates to the field of current source startup technology. The startup circuit includes: a bias module, a voltage detection module, and a reset module. When the current source circuit is powered on, the bias module provides a current bias to the voltage detection module, which activates the voltage detection module and assists in the power-on startup of the current source circuit. After the current source circuit is powered on, the startup circuit is shut down and the current source circuit is activated. After the current source circuit is powered off, the reset module forms a discharge path and resets the startup circuit. After the current source circuit is powered off and powered on again, the bias module provides a current bias to the voltage detection module, which activates the voltage detection module and assists in the power-on startup of the current source circuit. The present invention can reduce circuit static power consumption, reduce design complexity, and provide a fast circuit response, ensuring normal power-on function.

Description

Technical Field

[0001] The present invention relates to the technical field of current source starting technology, in particular to a current source starting circuit. Background Art

[0002] The startup circuit is an integral part of the current source circuit. Due to design complexity, process fluctuations, and other factors, current source circuits typically have more than one stable state. After power-on, the current source may remain in the wrong stable state, causing system malfunction. To prevent this, a startup circuit module is required to guide the current source circuit to the correct state during power-on, ensuring that the system operates correctly as designed.

[0003] The startup circuit must function during the power-up process, maintain a stable operation of the original circuit, and consume minimal power after power-up. During the power-up process, the current source circuit must function correctly regardless of power supply fluctuations. Therefore, low power consumption, high speed, and stability are key design considerations for startup circuits.

[0004] Referring to relevant patents and prior art (such as JP2012248995A, CN201610786351.9, and JP2013150127A), it can be seen that most existing startup circuit solutions require a fixed bias circuit to be always open, which will result in power loss after the startup is completed; to reduce power consumption, some designs propose using different switching strategies during the power-on and power-off stages to charge and discharge the fixed capacitor, and start the original circuit through the voltage stored in the capacitor, but the power-on / power-off detection increases the complexity of the circuit design; to reduce circuit complexity, some designs propose using RC voltage divider for startup, but the voltage at the RC divider point changes with the power supply, and startup can only be performed at a fixed time. The startup process is unrelated to the original circuit state, and therefore the startup accuracy is low. Summary of the Invention

[0005] In order to overcome the above-mentioned defects in the prior art, the present invention provides a current source startup circuit, which reduces the static power consumption of the circuit, reduces the design complexity, and can quickly respond to the circuit to ensure normal power-on function.

[0006] To achieve the above object, the present invention adopts the following technical solutions, including:

[0007] A current source startup circuit includes: two PMOS transistors, whose sources are both connected to a power supply; two PMOS transistors, whose gates are connected to form a VP node; two NMOS transistors, whose gates are connected to form a VN node; and two NMOS transistors, whose sources are both grounded; and a startup circuit including a bias module, a voltage detection module, and a reset module.

[0008] When the current source circuit is powered on, the bias module provides a current bias to the voltage detection module, the voltage detection module works, and the power-on startup of the auxiliary current source circuit is started; after the current source circuit is powered on, the startup circuit is closed and the current source circuit works; after the current source circuit is powered off, the reset module forms a discharge path to reset the startup circuit; after the current source circuit is powered off and powered on again, the bias module provides a current bias to the voltage detection module, the voltage detection module works, and the power-on startup of the auxiliary current source circuit is started.

[0009] Preferably, the bias module includes a first PMOS transistor PM1, a second PMOS transistor PM2, and a capacitor C0; the voltage detection module includes a first NMOS transistor NM1, a first NMOS transistor NM2; the reset module includes a third PMOS transistor PM3, a sixth PMOS transistor PM6, and a fifth NMOS transistor NM5;

[0010] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply VDD;

[0011] The gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are connected to form a VG node, which is connected to one end of the capacitor C0, and the other end of the capacitor C0 is grounded; the drain of the second PMOS transistor PM2 is also connected to the VG node;

[0012] The drain of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor to form a VD node, the VD node is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded, the drain of the first NMOS transistor is connected to the VP node in the current source circuit, and the gate of the second NMOS transistor is connected to the VN node in the current source circuit;

[0013] The drain of the second PMOS transistor PM2 is connected to the source of the third PMOS transistor PM3, and the drain of the third PMOS transistor PM3 is grounded;

[0014] The source of the sixth PMOS transistor PM6 is connected to the power supply VDD, the drain of the sixth PMOS transistor PM6 is connected to the gate of the third PMOS transistor PM3, the gate of the sixth PMOS transistor PM6 is respectively connected to the drain of the fifth NMOS transistor NM5 and the gate of the fifth NMOS transistor NM5, and the source of the fifth NMOS transistor NM5 is grounded.

[0015] Preferably, the reset module is replaced by a resistor Rs, one end of the resistor Rs is connected to the drain of the second PMOS transistor PM2, and the other end of the resistor Rs is grounded.

[0016] Preferably, the current source circuit includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, and a fourth NMOS transistor NM4;

[0017] The source of the fourth PMOS transistor PM4 is connected to the power supply VDD through the resistor R0 and the source of the fifth PMOS transistor PM5, respectively; the gate of the fourth PMOS transistor PM4 is connected to the gate of the fifth PMOS transistor PM5 to form a VP node, and the drain of the fifth PMOS transistor PM5 is connected to the VP node; the drain of the fourth PMOS transistor PM4 is connected to the drain of the third NMOS transistor NM3; the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4; the gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 to form a VN node, and the drain of the third NMOS transistor NM3 is connected to the VN node; the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both grounded.

[0018] The advantages of the present invention are:

[0019] (1) After completing the startup function, the startup circuit of the present invention automatically shuts down, and |Vgs|-|Vth_p| of PM1 and PM2 = 0. There is no current in the branch, and no additional power consumption is generated. Therefore, the static power consumption of the startup circuit of the present invention is low.

[0020] (2) The minimum operating voltage of the startup circuit of the present invention is min(VDD)>max{|Vth_p|,|Vth_n|}, which is lower than the minimum operating voltage of the current source circuit itself. Therefore, it is suitable for various current source circuits and has a wide range of applications.

[0021] (3) The startup circuit of the present invention has a stable detection process and is insensitive to power supply variations. Since PM1 and PM2 are turned off, VDD fluctuations are not transmitted to the VD node and do not affect the pull-down force of NM1 on the VP voltage. The startup circuit controls the startup force only by the bias value of the current source circuit (VP / VN), and this process is not affected by VDD fluctuations.

[0022] (4) The starting circuit of the present invention has no special requirements for the design of each tube. Through reasonable design, it can be implemented with a very small area, reducing the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a current source startup circuit of the present invention Figure 1 .

[0024] Figure 2 Schematic diagram of the current source circuit of the present invention Figure 1 .

[0025] Figure 3 FIG. 4 is a schematic cross-sectional view of the third PMOS transistor PM3 .

[0026] Figure 4 Schematic diagram of the current source circuit of the present invention Figure 2 .

[0027] Figure 5 A schematic diagram of a current source startup circuit of the present invention Figure 2 .

[0028] Figure 6 This is a schematic diagram of a first current source startup circuit in the prior art.

[0029] Figure 7 This is a schematic diagram of a second current source startup circuit in the prior art. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0031] Depend on Figure 1 As shown, Figure 1 The present invention is a current source startup circuit, comprising a bias module, a voltage detection module, and a reset module. Figure 2 As shown, Figure 2 This is a common current source circuit. During the power-up phase, the bias module provides current bias, the voltage detection module operates normally, and the auxiliary current source circuit enters the designed state, i.e., the auxiliary current source circuit is powered on and started. After power-up, the startup circuit shuts down, and the current source circuit operates normally. After power failure, the reset module resets the startup circuit, facilitating the next power-up, allowing the startup circuit to correctly power on the auxiliary current source circuit again.

[0032] Depend on Figure 2 As shown, the current source circuit includes: a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a resistor R0.

[0033] The source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5 are both connected to the power supply VDD via the resistor R0;

[0034] The gate of the fourth PMOS transistor PM4 is connected to the gate of the fifth PMOS transistor PM5 to form a VP node, and the drain of the fifth PMOS transistor PM5 is connected to the VP node;

[0035] The drain of the fourth PMOS transistor PM4 is connected to the drain of the third NMOS transistor NM3; the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4; the gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 to form a VN node, and the drain of the third NMOS transistor NM3 is connected to the VN node;

[0036] The source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both grounded.

[0037] Depend on Figure 1 As shown, in the current source startup circuit, the bias module includes: a first PMOS transistor PM1, a second PMOS transistor PM2, and a capacitor C0. The voltage detection module includes: a first NMOS transistor NM1, a first NMOS transistor NM2. The reset module includes: a third PMOS transistor PM3, a sixth PMOS transistor PM6, and a fifth NMOS transistor NM5.

[0038] The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the sixth PMOS transistor PM6 are all connected to the power supply VDD;

[0039] The gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are connected to form a VG node. The VG node is connected to one end of the capacitor C0, and the other end of the capacitor C0 is grounded. The drain of the second PMOS transistor PM2 is also connected to the VG node.

[0040] The drain of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor to form a VD node, the VD node is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are grounded, the drain of the first NMOS transistor is connected to the VP node in the current source circuit, and the gate of the second NMOS transistor is connected to the VN node in the current source circuit;

[0041] The drain of the second PMOS transistor PM2 is connected to the source of the third PMOS transistor PM3, and the drain of the third PMOS transistor PM3 is grounded; the drain of the sixth PMOS transistor PM6 is connected to the gate of the third PMOS transistor PM3; the gate of the sixth PMOS transistor PM6 is respectively connected to the drain of the fifth NMOS transistor NM5 and the gate of the fifth NMOS transistor NM5, and the source of the fifth NMOS transistor NM5 is grounded.

[0042] In this embodiment, there is no requirement for the accuracy of capacitor CO, but there is a requirement for the capacitance value. To save chip area, capacitor C0 uses an NMOS capacitor structure. NMOS is used as a capacitor, the gate is connected to the node where the capacitor needs to be added, and the drain, source, and substrate are connected to the "ground".

[0043] The working principles of the current source circuit and the startup circuit of the present invention are as follows:

[0044] The threshold voltages of each NMOS transistor are the same, all being Vth_n, and Vth_n > 0V; the threshold voltages of each PMOS transistor are the same, all being Vth_p, and Vth_p < 0V. The power supply voltage is VDD.

[0045] The working process of the current source circuit and the startup circuit can be divided into 4 stages.

[0046] S1, in the initial stage of power-on, 0 < VDD < |Vth_p|, PM1, PM2, PM4, and PM5 are not turned on, no current flows out from the power supply VDD, and neither the startup circuit nor the current source circuit works;

[0047] S2, in the middle stage of power-on, VDD > |Vth_p|, the startup circuit and the current source circuit conduct current, and the VP and VN bias voltages start to be established. At the initial moment, there is no charge residue in both the startup circuit and the current source circuit, and the VP / VN voltage is 0;

[0048] Assuming there is no startup circuit of the present invention, the current source circuit is established alone, VN = 0, and the path formed by PM5 and NM4 cannot form a current path from the power supply VDD to the ground. As VDD rises, a large amount of charge accumulates at the VP point, causing the VP voltage to rise following VDD, maintaining VP = VDD - |Vth_p|, VN < Vth_n, making the current source circuit unable to work in the correct state;

[0049] After setting the startup circuit of the present invention, NM5 controls PM6 to turn on, and PM6 turning on controls PM3 to turn off. There is no current in the PM2 and PM3 path, and the voltage of the VG node will rise following VDD. And the capacitance C0 can be used to control the rate at which the VG voltage follows the change of VDD, making PM1 and PM2 conduct briefly, that is, |Vgs| > |Vth_P|. Since VN = 0, therefore, the VD node will accumulate charge in a short time and show a high voltage. Further, NM1 will be turned on, thus pulling down the gate voltages of PM4 and PM5, that is, pulling down the voltage of the VP node. A current path from the power supply VDD to the ground appears in the current source circuit, and VP and VN are separated from the previous state. The current source circuit starts to be established towards the correct state, and the current source circuit is started.

[0050] S3, after the current source circuit is successfully started, the VP and VN nodes are at the designed voltage values. After PM1 and PM2 conduct briefly, they are turned off, VG = VDD - |Vth_p|. At this time, the NM2 transistor is turned on, pulling down the VD voltage, and the NM1 transistor is turned off. The startup circuit has no influence on the voltages of the VP and VN nodes of the current source circuit, and the startup process ends, and the startup circuit is turned off.

[0051] S4, after power failure,

[0052] Assuming the reset module (PM3, PM6, NM5) of this invention is missing, after a single current source startup or power failure, VDD = 0, PM2 transistor is non-conductive, and the charge stored at the VG node has no path to release. VG will remain at a high voltage, VG = VDD - |Vth_p|. Upon powering back on, PM1 and PM2 will not turn on, and consequently, the VD voltage will not rise. The startup circuit will be unable to adjust the VP / VN voltage during the power-up process, and startup will fail.

[0053] After the reset module (PM3, PM6, NM5) of the present invention is set, when VDD=0, a charge discharge path is formed for the VG node. Specifically, the cross-sectional view of PM3 is as follows: Figure 3 As shown, VDD = 0, the gate voltage of PM3 is 0. At this time, the PN junction formed between the source of PM3 and the Nwell substrate is turned on, and the source voltage, that is, the voltage of the VG node, is pulled down to Vpn (the minimum bias voltage required to turn on the PN junction, which is generally very low). After power is restored, PM1 and PM2 will be turned on briefly, and the current source can still be successfully started.

[0054] The current source circuit of this embodiment can be replaced by other structural types, such as Figure 4 Cascode current source circuit shown.

[0055] The reset module in the startup circuit of this embodiment can be replaced by another type of charge discharge path to restore the initial VP level after power failure, such as Figure 5 As shown, using resistor Rs instead of the reset module can realize the discharge of the VP node. By increasing the resistance value of resistor Rs, the DC power consumption of the circuit can be reduced.

[0056] Comparing the present invention with the two current source starting circuits in the prior art,

[0057] The first existing current source startup circuit is as follows Figure 6 As shown, for the current source circuit composed of M4, M3, M1, and M2, an M5 transistor is used and the gate of M3 is connected to the gate of M1 using a diode connection method. If the current source circuit does not start normally, the gate of M3 is at a high voltage, equal to VDD-|Vth_p|, and the gate of M1 is at a low voltage. At this time, M5 will turn on, pulling down the VP voltage and increasing the VN voltage, allowing the current source circuit to escape the previous state. When the circuit is established in the correct state, M5 is turned off. To ensure the correct startup process, it is required that current flows through the two branches of M4 and M3 at the beginning of the startup. At the same time, after the circuit is established, there is no leakage between VP and VN. Therefore, the threshold voltage Vth_5 of the M5 transistor is required to be:

[0058] At the initial stage of circuit startup: |Vth_3| + Vth_5 + Vth_1 < VDD

[0059] During the stable establishment stage of the circuit: |Vgs3| + Vth_5 + |Vgs1| > VDD, that is:

[0060] VDD - |Vgs3| - |Vgs1| < Vth_5 < VDD - |Vth_3| - Vth_1;

[0061] The first current source startup circuit has the following disadvantages:

[0062] 1) It is difficult to design the circuit size. For the M5 transistor, the range of its threshold voltage Vth_5 is affected by process, current source current, and body bias effect. Generally, the threshold voltage is fine-tuned by adjusting the transistor size. When the current of the current source is very small, |Vgs3| - |Vth_3| and |Vgs1| - |Vth_1| are both very small, and the range of Vth_5 that meets the design requirements will be very narrow. Adjusting the size of the M5 transistor may still not meet the requirements. The current source cannot start normally.

[0063] 2) The minimum operating power supply voltage is very high. To ensure normal circuit startup, it is required that VDD > Vth_1 + Vth_5 + |Vth_3|. This structure is not suitable for low-voltage application scenarios.

[0064] The existing second current source startup circuit is as Figure 7 shown. P1, P2, P3, P4, N1, N2, and R form a current source circuit, and P5, P6, and N3 are the current source startup circuit. If the current source does not start normally, VP1 and VP0 are at high voltage, that is, VP1 = VDD - |Vthp_1|, VP0 = VDD - |Vthp_1| - |Vthp_3|, and VN is at low voltage, VN < Vthn_2, VN < Vthn_3. This scheme breaks this state by adding the M4 transistor. Specifically, since VN < Vthn_3, the N3 transistor is not conducting, VG is at high voltage, and at this time the N4 transistor is turned on, pulling down the voltage of VP0 and raising the voltage of VN, and VP0, VP1, and VN are re-established.

[0065] The second current source startup circuit has the following disadvantages:

[0066] 1) The circuit size and area are large.

[0067] VG voltage swing design requirements: max(VG) = VDD - |Vthp_5|, min(VG) < |Vgs_n2|. When VG = min(VG), the startup circuit completes the startup of the current source and no longer affects the current source circuit. Transistor N3 turns on, and its current is proportional to that of transistors N1 and N2. When VG < |Vgs_n2|, the |Vgs| of transistor P5 is very large. Transistor P5 is in the saturation region, and its current-voltage relationship can be described by the following first-order model:

[0068]

[0069] Among them, I p Indicates the PMOS tube current, u p It represents the majority carrier (hole) mobility of the PMOS transistor, Cox represents the gate oxide capacitance per unit area of ​​the PMOS transistor gate, W represents the width of the PMOS transistor (perpendicular to the channel direction), L represents the length of the PMOS transistor (parallel to the channel direction), Vgs represents the voltage difference between the source and gate of the PMOS transistor (Vgs<0), and Vth_p represents the threshold voltage of the PMOS transistor (Vth_p<0).

[0070] P5 and N3 are in the same branch, drawing the same current. According to the first-order MOS transistor model, for a given current, the larger the |Vgs|, the smaller the W / L. When the minimum W is fixed, a very large L is required to meet the requirement, resulting in a large circuit area.

[0071] 2) High power consumption. After the startup circuit is completed, there is still current in the P5, P6, and N3 paths, which generates additional static power consumption.

[0072] Through the above comparative analysis, we can know that:

[0073] After completing the startup function, the startup circuit of the present invention automatically shuts down, and |Vgs|-|Vth_p| of PM1 and PM2=0. There is no current in the branch circuit, and no additional power consumption is generated. Therefore, the startup circuit of the present invention has low static power consumption.

[0074] The minimum operating voltage of the startup circuit of the present invention is min(VDD)>|Vth_p|, which is lower than the minimum operating voltage of the current source circuit itself. Therefore, the startup circuit of the present invention is suitable for various current source circuits and has a wide range of applications.

[0075] The startup circuit of the present invention provides a stable detection process and is insensitive to power supply variations. Because PM1 and PM2 are disabled, VDD fluctuations are not transmitted to the VD node, and thus do not affect the pull-down strength of NM1 on the VP voltage. The startup circuit controls the startup strength solely through the bias voltage (VP / VN) of the current source circuit, a process unaffected by VDD fluctuations.

[0076] The starting circuit of the present invention has no special requirements on the design of each tube and can be implemented with a very small area through reasonable design.

[0077] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A current source startup circuit, the current source circuit comprising: The sources of the two PMOS transistors are both connected to the power supply, the gates of the two PMOS transistors are connected to form a VP node, the gates of the two NMOS transistors are connected to form a VN node, and the sources of the two NMOS transistors are both grounded. The startup circuit is characterized in that it includes: a bias module, a voltage detection module, and a reset module; When the current source circuit is powered on, the bias module provides a current bias to the voltage detection module, the voltage detection module works, and the power-on startup of the auxiliary current source circuit is started; after the current source circuit is powered on, the startup circuit is closed and the current source circuit works; after the current source circuit is powered off, the reset module forms a discharge path to reset the startup circuit; after the current source circuit is powered off and powered on again, the bias module provides a current bias to the voltage detection module, the voltage detection module works, and the power-on startup of the auxiliary current source circuit is started; The bias module includes a first PMOS transistor PM1, a second PMOS transistor PM2, and a capacitor C0; the voltage detection module includes a first NMOS transistor NM1, a first NMOS transistor NM2; the reset module includes a third PMOS transistor PM3, a sixth PMOS transistor PM6, and a fifth NMOS transistor NM5; The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply VDD; The gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are connected to form a VG node, which is connected to one end of the capacitor C0, and the other end of the capacitor C0 is grounded; the drain of the second PMOS transistor PM2 is also connected to the VG node; The drain of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor to form a VD node, the VD node is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded, the drain of the first NMOS transistor is connected to the VP node in the current source circuit, and the gate of the second NMOS transistor is connected to the VN node in the current source circuit; The drain of the second PMOS transistor PM2 is connected to the source of the third PMOS transistor PM3, and the drain of the third PMOS transistor PM3 is grounded; The source of the sixth PMOS transistor PM6 is connected to the power supply VDD, the drain of the sixth PMOS transistor PM6 is connected to the gate of the third PMOS transistor PM3, the gate of the sixth PMOS transistor PM6 is respectively connected to the drain of the fifth NMOS transistor NM5 and the gate of the fifth NMOS transistor NM5, and the source of the fifth NMOS transistor NM5 is grounded.

2. A current source starting circuit according to claim 1, characterized in that: The reset module is replaced by a resistor Rs, one end of the resistor Rs is connected to the drain of the second PMOS transistor PM2, and the other end of the resistor Rs is grounded.

3. The current source starting circuit according to claim 1, characterized in that: The current source circuit includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, and a fourth NMOS transistor NM4; The source of the fourth PMOS transistor PM4 is connected to the power supply VDD through the resistor R0 and the source of the fifth PMOS transistor PM5, respectively; the gate of the fourth PMOS transistor PM4 is connected to the gate of the fifth PMOS transistor PM5 to form a VP node, and the drain of the fifth PMOS transistor PM5 is connected to the VP node; the drain of the fourth PMOS transistor PM4 is connected to the drain of the third NMOS transistor NM3; the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4; the gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 to form a VN node, and the drain of the third NMOS transistor NM3 is connected to the VN node; the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both grounded.

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