Chip pin coplanarity detection method based on 3D dynamic scanning imaging technology

Abstract

The present invention discloses a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology, which uses a 3D camera to dynamically scan and collect external images of the chip surface, obtain high-precision point cloud data of the chip, process and transform the point cloud data, generate a depth map of the chip, and then find the chip surface area and the top area of each Pin needle in the depth map of the chip, calculate the depth value of each area, and count the difference between the depth value of the top area of each Pin needle and the depth value of the upper surface. If the depth value difference of a certain Pin needle is not within the normal range, it is considered that it has warping or non-coplanar defects. The present invention can not only improve the accuracy and stability of chip pin coplanarity detection, reduce the failure rate of the chip during use, improve product quality, reduce the repair cost caused by chip problems, but also avoid the occurrence of major safety accidents, major equipment and engineering failures to a certain extent, and has certain application value and application space.

Description

Technical Field

[0001] The present invention relates to chip pin coplanarity detection, and in particular to a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology. Background Art

[0002] In today's society, chips are the engine driving the development of the entire information society and the cornerstone and heart of the entire information industry. Key technologies and projects such as artificial intelligence, big data centers, 5G base stations, and the industrial internet are all based on chips, and the demand for chips is growing. Countries around the world attach great importance to chip manufacturing and quality. Furthermore, with the continuous advancement of technology, chip manufacturing processes are becoming smaller and smaller, and transistor integration is increasing. Chips are gradually becoming miniaturized. While small, chips carry a significant responsibility. For these reasons, chip inspection is essential at every stage, and the coplanarity of chip pins is a key indicator of chip performance. Failure to meet the coplanarity requirement can lead to defects in subsequent soldering.

[0003] Before the chip enters the circuit board assembly line, the coplanarity of the chip pins needs to be tested in order to avoid various problems that may occur in subsequent use. Figure 1 As shown, a normal chip has a certain height difference between the top surface and the top and bottom ends of each pin, within a standard range. If the height difference of some pins exceeds this standard range, the pin is generally considered to have a warpage defect. Generally, the pin height deviation must not exceed the pin thickness, that is, the vertical deviation between the bottom of the lower pin and the bottom of the higher pin. Excessive coplanarity error can cause pin tilting and breakage. This can easily lead to defects such as empty solder joints, cold solder joints, solder joint bridging, and solder joint misalignment and offset during assembly or soldering, ultimately resulting in poor contact and serious impact on chip performance. Sometimes, chip pins can scratch the circuit board, causing serious damage to the entire circuit board and direct scrapping. In severe cases, it can cause malfunctions during use, resulting in serious safety incidents or major project failures. Standardized documents such as "GJB 3243-98 Surface Mounting Requirements for Electronic Components" clearly stipulate that the skew error of component (pin) leads should not exceed 0.08mm, and the coplanarity error of component (pin) leads should not exceed 0.1mm.

[0004] Currently, chip pin coplanarity inspection commonly uses three methods: visual inspection, machine vision, and contact inspection. Manual visual inspection of chip components on the production floor is not only prone to missed detections and false detections due to the operator's limited energy and inattention, but also suffers from slow inspection speeds, impacting production schedules. While traditional machine vision inspection is fast, eliminates missed detections, and offers significantly improved accuracy compared to manual inspection, pin coplanarity accuracy remains low, failing to meet the high-precision requirements of today's chip inspection industry. Contact inspection is not only slow but also prone to damaging chip pins during testing. To overcome the low efficiency and accuracy of existing chip coplanarity inspection methods, chip manufacturers and end-users are seeking high-precision and efficient chip pin coplanarity inspection methods or equipment. Addressing this issue of chip pin coplanarity inspection accuracy is a significant and consequential trend. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology to solve the problems existing in the existing chip pin coplanarity detection method, improve the accuracy and stability of chip pin coplanarity detection, and be able to adapt to the detection accuracy required by standardized documents such as "GJB 3243-98 Surface Installation Requirements for Electronic Components", thereby minimizing the failure rate of the chip during use and preventing major safety accidents, major equipment and engineering failures, etc.

[0006] Technical solution: The present invention provides a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology, comprising the following steps:

[0007] (1) The 3D camera obtains the chip depth map.

[0008] (1.1) Calibrate the 3D camera to obtain the camera parameters (intrinsic and extrinsic).

[0009] (1.2) Using 3D imaging chip, first output the chip's 2D grayscale image and save it as a PNG format image, then use the ranging imaging process to obtain the chip's distance information.

[0010] (1.3) The chip’s distance information and point cloud reconstruction technology are used to obtain the chip’s 3D point cloud, and then the 3D point cloud is denoised to improve the quality level of the 3D point cloud.

[0011] (1.4) Based on the calibration parameters (intrinsic and extrinsic parameters) of the 3D camera, the 3D point cloud of the chip is converted into a 3D depth map.

[0012] (1.5) The coplanarity of the test bench is used to correct the 3D depth map of the chip so that the coplanar areas in the depth map have the same depth value.

[0013] (1.6) Output the corrected 3D depth map and save it as a TIFF format image.

[0014] (1.7) Perform coplanarity test on chip pins.

[0015] (2) Perform coplanarity test on chip pins.

[0016] (2.1) Determine whether the depth map data of the chip obtained by the 3D camera is empty. If it is empty, the camera re-acquires the depth map of the chip; if it is not empty, use the threshold processing method to extract the upper surface area of the chip in the depth map and calculate the average depth value of the upper surface area.

[0017] (2.2) Obtain the minimum circumscribed oblique rectangle of the upper surface area, and use the posture of the minimum circumscribed oblique rectangle and the affine transformation method to align the depth map and the upper surface area so that one side of the upper surface area is horizontal.

[0018] (2.3) Subtract the top surface area from the chip depth map to obtain the pin area, and then count the number of pin areas. If the number is 2, the pin area is divided into two left and right areas. If the number is 4, the pin area is divided into four areas: top, bottom, left and right.

[0019] (2.4) Count the number of pins in each area and calculate the depth values of all pins; if the number of pins in the upper and lower areas or the left and right areas is not equal, it is determined that there are missing pins or a large tilt on this chip, and an error message "There are missing pins or a large tilt" is output; otherwise, the average depth value of the upper surface area is subtracted from the depth value of each pin to obtain the height difference between each pin and the upper surface.

[0020] (2.5) Count the height differences between all pins and the upper surface, referred to as the pin height differences, and calculate their median and maximum values; if the maximum value minus the median value is less than 0.05 mm, set the median value to the value of the maximum value minus 0.05 mm; then count the difference between the height differences of all pins and the median value.

[0021] (2.6) If the difference between the height difference of some pins and the median value is greater than 0.0501mm, these pins are judged to be warped and the error message "warping exists" is output; otherwise, all pins are judged to be not warped, and the defect detection result information "warping does not exist" is output, and the height difference of each pin is displayed.

[0022] A computer storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned chip pin coplanarity detection method based on 3D dynamic scanning imaging technology.

[0023] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method for detecting the coplanarity of chip pins based on 3D dynamic scanning imaging technology is implemented.

[0024] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0025] 1. The present invention adopts 3D dynamic scanning imaging detection technology, which is faster and more accurate than manual detection, more accurate than machine vision detection based on monocular or multi-lens 2D lenses, faster than contact detection, and will not damage chip pins. At the same time, it has strong environmental adaptability and is not affected by ambient light;

[0026] 2. The 3D dynamic scanning imaging technology used in this invention is a relatively mature technology that has been applied in visual guidance, and its accuracy and feasibility have been verified. In addition, 3D camera manufacturers can provide some open source algorithm libraries, which developers can either directly call or conduct secondary development.

[0027] 3. In various situations where high accuracy and high speed are required for coplanarity detection of chip pins, it is only necessary to follow the method described in the present invention to achieve online detection of chip pin coplanarity with good consistency. This method has low hardware requirements, strong adaptability to the use environment, and has a wide range of application space. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the chip coplanarity detection principle;

[0029] Figure 2 Flow chart of obtaining chip depth map for 3D camera;

[0030] Figure 3 Flowchart of coplanarity detection of depth map. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0032] like Figure 2 As shown, a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology includes the following steps:

[0033] (1) According to different chip situations, the box containing the chip is first opened manually and then placed into the transmission mechanism. After reaching a certain position, the encoder triggers the camera to scan the chip and generate the chip's point cloud data for subsequent detection. The specific implementation steps for the 3D camera to obtain the chip depth map are as follows:

[0034] (1.1) Calibrate the 3D camera to obtain the camera parameters (intrinsic and extrinsic).

[0035] (1.2) Using 3D imaging chip, first output the chip's 2D grayscale image and save it as a PNG format image, then use the ranging imaging process to obtain the chip's distance information.

[0036] (1.3) The chip’s distance information and point cloud reconstruction technology are used to obtain the chip’s 3D point cloud, and then the 3D point cloud is denoised to improve the quality level of the 3D point cloud.

[0037] (1.4) Based on the calibration parameters (intrinsic and extrinsic parameters) of the 3D camera, the 3D point cloud of the chip is converted into a 3D depth map.

[0038] (1.5) The coplanarity of the test bench is used to correct the 3D depth map of the chip so that the coplanar areas in the depth map have the same depth value.

[0039] (1.6) Output the corrected 3D depth map and save it as a TIFF format image.

[0040] (1.7) Perform coplanarity test on chip pins.

[0041] (2) Figure 3 As shown in the figure, based on the chip depth map, the coplanarity detection of the chip pins is performed. The specific implementation steps are as follows:

[0042] (2.1) Determine whether the depth map data of the chip obtained by the 3D camera is empty. If it is empty, the camera re-acquires the depth map of the chip; if it is not empty, use the threshold processing method to extract the upper surface area of the chip in the depth map and calculate the average depth value of the upper surface area.

[0043] (2.2) Obtain the minimum circumscribed oblique rectangle of the upper surface area, and use the posture of the minimum circumscribed oblique rectangle and the affine transformation method to align the depth map and the upper surface area so that one side of the upper surface area is horizontal.

[0044] (2.3) Subtract the top surface area from the chip depth map to obtain the pin area, and then count the number of pin areas. If the number is 2, the pin area is divided into two left and right areas. If the number is 4, the pin area is divided into four areas: top, bottom, left and right.

[0045] (2.4) Count the number of pins in each area and calculate the depth values of all pins; if the number of pins in the upper and lower areas or the left and right areas is not equal, it is determined that there are missing pins or a large tilt on this chip, and an error message "There are missing pins or a large tilt" is output; otherwise, the average depth value of the upper surface area is subtracted from the depth value of each pin to obtain the height difference between each pin and the upper surface.

[0046] (2.5) Count the height differences between all pins and the upper surface, referred to as the pin height differences, and calculate their median and maximum values; if the maximum value minus the median value is less than 0.05 mm, set the median value to the value of the maximum value minus 0.05 mm; then count the difference between the height differences of all pins and the median value.

[0047] (2.6) If the difference between the height difference of some pins and the median value is greater than 0.0501mm, these pins are judged to be warped and the error message "warping exists" is output; otherwise, all pins are judged to be not warped, and the defect detection result information "warping does not exist" is output, and the height difference of each pin is displayed.

Claims

1. A chip pin coplanarity detection method based on 3D dynamic scanning imaging technology, characterized in that: The following steps are involved: (1) 3D camera obtains chip depth map; (2) Perform coplanarity detection on the chip pins. The specific steps are as follows: (2.1) Determine whether the depth map data of the chip obtained by the 3D camera is empty. If it is empty, the camera re-acquires the depth map of the chip; if it is not empty, use the threshold processing method to extract the upper surface area of the chip in the depth map and calculate the average depth value of the upper surface area; (2.2) Obtain the minimum circumscribed oblique rectangle of the upper surface area, and use the posture of the minimum circumscribed oblique rectangle and the affine transformation method to align the depth map and the upper surface area so that one side of the upper surface area is horizontal; (2.3) Subtract the top surface area from the chip depth map to obtain the pin area, and then count the number of pin areas. If the number is 2, the pin area is divided into two areas: left and right. If the number is 4, the pin area is divided into four areas: top, bottom, left and right. (2.4) Count the number of pins in each area and calculate the depth of all pins. If the number of pins in the upper and lower areas or the left and right areas is not equal, it is determined that the chip has a missing pin or a large tilt, and an error message "missing pin or large tilt" is output. Otherwise, the average depth value of the upper surface area minus the depth value of each pin is used to obtain the height difference between each pin and the upper surface. (2.5) Count the height differences between all pins and the upper surface, referred to as the pin height differences, and calculate their median and maximum values; if the maximum value minus the median value is less than 0.05 mm, set the median value to the value obtained by subtracting 0.05 mm from the maximum value; then count the difference between the height differences of all pins and the median value; (2.6) If the difference between the height difference of some pins and the median value is greater than 0.0501mm, these pins are judged to be warped and the error message "warping exists" is output; otherwise, all pins are judged to be not warped, and the defect detection result information "warping does not exist" is output, and the height difference of each pin is displayed.

2. The chip pin coplanarity detection method based on 3D dynamic scanning imaging technology according to claim 1 is characterized in that: The step (1) is specifically as follows: (1.1) Calibrate the 3D camera and obtain the camera parameters; (1.2) Using 3D imaging of the chip, first output the chip's 2D grayscale image and save it as a PNG format image. Then, use the ranging imaging process to obtain the chip's distance information. (1.3) Using the chip’s distance information and point cloud reconstruction technology to obtain the chip’s 3D point cloud, and then denoising the 3D point cloud to improve the quality level of the 3D point cloud; (1.4) Based on the calibration parameters of the 3D camera, the 3D point cloud of the chip is converted into a 3D depth map; (1.5) Using the coplanarity of the test bench to calibrate the chip's 3D depth map so that the coplanar areas in the depth map have the same depth value; (1.6) Output the corrected 3D depth map and save it as a TIFF format image; (1.7) Perform coplanarity test on chip pins.

3. The chip pin coplanarity detection method based on 3D dynamic scanning imaging technology according to claim 2, characterized in that: The parameters described in step (1.1) and step (1.4) include internal and external parameters.

4. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip pin coplanarity detection method based on 3D dynamic scanning imaging technology as described in any one of claims 1 to 3 is implemented.

5. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, it implements a chip pin coplanarity detection method based on 3D dynamic scanning imaging technology according to any one of claims 1 to 3.

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