Shutdown control circuit and display device

Abstract

The application discloses a power-off control circuit and a display device. The power-off control circuit comprises a selection circuit and a selection control circuit. The first input end and the second input end of the selection circuit are used for connecting the first preset gate-on voltage and the second preset gate-on voltage respectively. The output end of the selection circuit is connected with a gate drive circuit. The controlled end of the selection control circuit is used for connecting a power-on / off control signal. The output end of the selection control circuit is connected with the controlled end of the selection circuit. The selection control circuit is used for controlling the selection circuit to connect the first preset gate-on voltage or the second preset gate-on voltage according to the signal state of the connected power-on / off control signal, and outputting a corresponding clock signal to the gate drive circuit according to the connected first preset gate-on voltage or second preset gate-on voltage. The second preset gate-on voltage is greater than the first preset gate-on voltage. The technical scheme can better eliminate the power-off residual image phenomenon.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a power-off control circuit and a display device. Background Technology

[0002] Currently, liquid crystal display devices typically integrate a function to eliminate ghosting when the device is powered off, known as power-off ghosting elimination. This function releases residual charges in the liquid crystal panel by controlling the activation of thin-film transistors (TFTs) during power-off. However, due to the power loss of the display device, the gate turn-on voltage used to activate the TFTs is insufficient to fully release the residual charges in the liquid crystal panel, thus failing to eliminate the power-off ghosting phenomenon.

[0003] Application content

[0004] The main purpose of this application is to provide a power-off control circuit that aims to solve the problem of the inability to eliminate the afterimage phenomenon when the device is turned off.

[0005] To achieve the above objectives, the power-off control circuit proposed in this application is applied to a display device, the display device including a display array and a gate driving circuit, the gate driving circuit being used to output a corresponding gate driving voltage to the display array according to an input clock signal, and the power-off control circuit including:

[0006] A selection circuit, wherein a first input terminal and a second input terminal of the selection circuit are respectively connected to a first preset gate enable voltage and a second preset gate enable voltage, and the output terminal of the selection circuit is connected to the gate driving circuit; and...

[0007] The selection control circuit is used to receive the power on / off control signal, and the output terminal of the selection control circuit is connected to the controlled terminal of the selection circuit.

[0008] The selection control circuit is used to control the selection circuit to connect to the first preset gate turn-on voltage or the second preset gate turn-on voltage according to the signal state of the input power-on control signal, and output a corresponding clock signal to the gate drive circuit according to the input first preset gate turn-on voltage or the second preset gate turn-on voltage.

[0009] Wherein, the second preset gate turn-on voltage is greater than the first preset gate turn-on voltage.

[0010] Optionally, the selection control circuit is used to control the selection circuit to access the first preset gate turn-on voltage and output a corresponding clock signal to the gate drive circuit when the power-on control signal in the first signal state is accessed.

[0011] The selection control circuit is used to control the selection circuit to connect to the second preset gate turn-on voltage and output a corresponding clock signal to the gate drive circuit when the power-on control signal in the second signal state is connected.

[0012] Optionally, the output terminal of the selection control circuit includes a first output terminal and a second output terminal. The selection control circuit is used to output a first selection control signal and a second selection control signal respectively from the first output terminal and the second output terminal when receiving a power-on control signal in a first signal state; and to output a third selection control signal and a fourth selection control signal respectively from the first output terminal and the second output terminal when receiving a power-on control signal in a second signal state.

[0013] The controlled terminals of the selection circuit include a first controlled terminal and a second controlled terminal. The first controlled terminal and the second controlled terminal of the selection circuit are respectively connected to the first output terminal and the second output terminal of the selection control circuit. The selection circuit is used to connect the first preset gate turn-on voltage and output a corresponding clock signal to the gate driving circuit when it receives the first selection control signal and the second selection control signal; and to connect the second preset gate turn-on voltage and output a corresponding clock signal to the gate driving circuit when it receives the third selection control signal and the fourth selection control signal.

[0014] Optionally, the selection control circuit includes:

[0015] A voltage conversion circuit, wherein the input terminal of the voltage conversion circuit is used to receive an input voltage and to output the input voltage after voltage conversion;

[0016] A switching circuit is provided, wherein the controlled terminal of the switching circuit is the controlled terminal of the selection control circuit, the first and second input terminals of the switching circuit are used to connect to the input voltage, the third input terminal of the switching circuit is connected to the output terminal of the voltage conversion circuit, and the first and second output terminals of the switching circuit are respectively the first and second output terminals of the selection control circuit.

[0017] Optionally, the voltage conversion circuit includes a first resistor and a second resistor. One end of the first resistor is used to connect to the input voltage, and the other end of the first resistor is grounded through the second resistor. The connection point of the first resistor and the second resistor is the output terminal of the voltage conversion circuit.

[0018] The first resistor and / or the second resistor are variable resistors.

[0019] Optionally, the switching circuit includes a first switching transistor, a second switching transistor, and a third switching transistor;

[0020] The input terminals of the first, second, and third switching transistors are respectively the first, second, and third input terminals of the switching circuit. The controlled terminal of the first switching transistor is connected to the output terminal of the second switching transistor, and the output terminal of the first switching transistor is connected to the output terminal of the third switching transistor. The connection point of the first and third switching transistors is the first output terminal of the switching circuit. The controlled terminal of the second and third switching transistors is connected to the controlled terminal of the third switching transistor. The connection point of the second and third switching transistors is the third input terminal and the second output terminal of the switching circuit.

[0021] Optionally, the shutdown control circuit further includes:

[0022] A voltage regulator circuit is provided, wherein the input terminal of the voltage regulator circuit is used to connect to the second preset gate turn-on voltage, the output terminal of the voltage regulator circuit is connected to the second input terminal of the selection circuit, and the voltage regulator circuit is used to maintain the second preset gate turn-on voltage when the selection circuit is connected to the second preset gate turn-on voltage.

[0023] Optionally, the voltage regulator circuit includes a first capacitor and a second capacitor;

[0024] The first terminal of the first capacitor and the first terminal of the second capacitor are respectively the input terminal and the output terminal of the voltage regulator circuit. The first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminals of the first capacitor and the second voltage regulator circuit are respectively grounded.

[0025] Optionally, the power-on / off control signal is a backlight enable signal.

[0026] This application also proposes a display device, the display device comprising:

[0027] Display array;

[0028] A gate driving circuit, wherein the gate driving circuit is configured to output a gate driving voltage to the display array; and,

[0029] As described above, the power-off control circuit is connected to the gate drive circuit.

[0030] This application's technical solution provides a clock signal to the gate drive circuit by employing a second preset gate turn-on voltage with a higher voltage level when the display device transitions from a power-on state to a power-off state. This allows the gate drive circuit to output an anti-image gate drive voltage with a higher initial voltage level, thereby accelerating the release speed of residual charge and simultaneously extending the release time of residual charge. In other words, this application's solution addresses the problem of inability to eliminate image retention when the display device is off by increasing the release speed and extending the release time of residual charge, thus ensuring more complete release of residual charge in the display panel and effectively improving the user experience of the display device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the power-off control circuit in Embodiment 1 of this application;

[0033] Figure 2 This is a circuit diagram of the shutdown control circuit in Embodiment 1 of this application;

[0034] Figure 3 This is a schematic diagram of the signal waveform of the shutdown control circuit in Embodiment 1 of this application;

[0035] Figure 4 This is a schematic diagram of the display device according to Embodiment 2 of this application.

[0036] Explanation of icon numbers:

[0037]

[0038] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0040] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0041] Example 1:

[0042] This application proposes a power-off control circuit that can be applied to a display device.

[0043] The display device may include a display array 40 and a gate driving circuit 50. The display array 40 may consist of multiple pixel units defined by multiple scan lines and multiple data lines. Multiple output terminals of the gate driving circuit 50 may be connected one-to-one with multiple gate scan lines. The gate driving circuit 50 may output corresponding gate driving voltages (G1 to Gn) to each gate scan line according to the input clock signal to turn on the thin-film transistors in each pixel unit. The turned-on thin-film transistors can then release residual charges in their respective pixel units, thereby eliminating the power-off ghosting effect. However, since the gate driving circuit 50 is in a power-off state when the display device is powered off, the voltage level of the gate driving voltage decreases accordingly, and transmission attenuation occurs. This can easily lead to the thin-film transistors receiving an excessively low voltage level during power-off, resulting in incomplete transistor activation and a short activation time. Consequently, residual charges cannot be fully released, and the power-off ghosting phenomenon still occurs in the display device.

[0044] Reference Figure 1 In Embodiment 1, the shutdown control circuit includes:

[0045] Selection circuit 10, wherein the first input terminal and the second input terminal of selection circuit 10 are respectively connected to a first preset gate turn-on voltage VGH1 and a second preset gate turn-on voltage VGH2, and the output terminal of selection circuit 10 is connected to the gate driving circuit 50; and

[0046] Selection control circuit 20, the controlled terminal of selection control circuit 20 is used to receive power on / off control signal, and the output terminal of selection control circuit 20 is connected to the controlled terminal of selection circuit 10;

[0047] The selection control circuit 20 is used to control the selection circuit 10 to connect to the first preset gate enable voltage VGH1 or the second preset gate enable voltage VGH2 according to the signal state of the input power-on control signal, and output a corresponding clock signal to the gate drive circuit 50 according to the input first preset gate enable voltage VGH1 or the second preset gate enable voltage VGH2.

[0048] In this embodiment, the first preset gate enable voltage VGH1 and the second preset gate enable voltage VGH2 can be obtained from the power management circuit in the display device, and the first preset gate enable voltage VGH1 can be configured to be less than the second preset gate enable voltage VGH2 by 5V. The selection circuit 10 can convert the input first preset gate enable voltage VGH1 or the second preset gate enable voltage VGH2 into a corresponding clock signal and output it to the gate drive circuit 50, so that the gate drive circuit 50 can output a corresponding gate drive voltage to the display array 40 to meet the needs of normal operation of the display array 40 or to release residual charge.

[0049] The power-on / off control signal can be obtained from the timing controller, and different signal states can represent the power-on or power-off state of the display device. When the selection control circuit 20 receives the power-on / off control signal indicating that the display device is in the power-on state, the selection control circuit 20 can output a corresponding control signal to control the selection circuit 10 to connect to the first preset gate turn-on voltage VGH1, and output a clock signal corresponding to the first preset gate turn-on voltage VGH1 so that the gate driving circuit 50 can provide the gate driving voltage for the normal power-on operation of the display array 40, i.e., the normal gate driving voltage. When the selection control circuit 20 receives the power-on / off control signal indicating that the display device is in the power-off state, the selection control circuit 20 can output a corresponding control signal to control the selection circuit 10 to connect to the second preset gate turn-on voltage VGH2, and output a clock signal corresponding to the second preset gate turn-on voltage VGH2 so that the gate driving circuit 50 can provide the gate driving voltage for the release of residual charge of the display array 40, i.e., the shadow-eliminating gate driving voltage.

[0050] It should be noted that, since the voltage level of the second preset gate turn-on voltage VGH2 is higher than that of the first preset gate turn-on voltage VGH1, when the display device switches from the power-on state to the power-off state, the starting voltage level of the anti-reflection gate drive voltage can be higher than that of the normal gate drive voltage. Therefore, under the action of the anti-reflection gate drive voltage, the thin-film transistors in each pixel unit can be turned on more completely, and the residual charge in each pixel unit can be released more quickly. Furthermore, since the starting voltage level of the anti-reflection gate drive voltage is higher, and the decay rate of the gate drive voltage remains unchanged in the power-off state, the time it takes for the voltage level of the anti-reflection gate drive voltage to drop to a point where the thin-film transistors cannot be turned on is longer, i.e., the turn-on time of the thin-film transistors is longer, allowing sufficient time for the residual charge in each pixel unit to be released. In this embodiment, the voltage level of the first preset gate turn-on voltage VGH1 can be 30V, and the voltage level of the second preset gate turn-on voltage VGH2 can be set to 35V.

[0051] In summary, this application's solution provides a clock signal to the gate drive circuit 50 by using a second preset gate turn-on voltage VGH2 with a higher voltage level when the display device transitions from a power-on state to a power-off state. This allows the gate drive circuit 50 to output an anti-image gate drive voltage with a higher initial voltage level, thereby accelerating the release speed of residual charge and simultaneously extending the release time of residual charge. In other words, this application's solution addresses the problem of inability to eliminate image retention when the display is off by increasing the release speed and extending the release time of residual charge, thus ensuring more complete release of residual charge in the display panel and effectively improving the user experience of the display device.

[0052] Optionally, the selection control circuit 20 is used to control the selection circuit 10 to connect to the first preset gate turn-on voltage VGH1 when the power-on control signal in the first signal state is connected, and to output a corresponding clock signal to the gate drive circuit 50.

[0053] The selection control circuit 20 is used to control the selection circuit 10 to connect to the second preset gate turn-on voltage VGH2 when the power-on control signal of the second signal state is connected, and to output a corresponding clock signal to the gate drive circuit 50.

[0054] In this embodiment, the power-on / off control signal can have two signal states: a first signal state and a second signal state. The power-on / off control signal in the first signal state indicates that the display device is in the power-on state, and the power-on / off control signal in the second signal state indicates that the display device is in the power-off state. The signal state can be a level state; specifically, the power-on / off control signal in the first signal state can be a high-level signal, and the power-on / off control signal in the second signal state can be a low-level signal. This effectively avoids the problem of the display device still having a power-off ghosting when the power-on / off control signal in the first signal state is a low-level signal and the power-on / off control signal in the second signal state is a high-level signal. This would cause the timing controller's output voltage level to drop, potentially triggering the selection control circuit 20 to output the clock signal corresponding to the first preset gate turn-on voltage VGH1.

[0055] Furthermore, the output terminal of the selection control circuit 20 includes a first output terminal and a second output terminal. The selection control circuit 20 is used to output a first selection control signal and a second selection control signal respectively from the first output terminal and the second output terminal when receiving a power-on control signal in a first signal state; and to output a third selection control signal and a fourth selection control signal respectively from the first output terminal and the second output terminal when receiving a power-on control signal in a second signal state.

[0056] The controlled terminals of the selection circuit 10 include a first controlled terminal and a second controlled terminal. The first controlled terminal and the second controlled terminal of the selection circuit 10 are respectively connected to the first output terminal and the second output terminal of the selection control circuit 20. The selection circuit 10 is used to connect the first preset gate turn-on voltage VGH1 and output a corresponding clock signal to the gate drive circuit 50 when it receives the first selection control signal and the second selection control signal; and to connect the second preset gate turn-on voltage VGH2 and output a corresponding clock signal to the gate drive circuit 50 when it receives the third selection control signal and the fourth selection control signal.

[0057] In this embodiment, the level signals of the first selection control signal and the third selection control signal are opposite, and the level signals of the second selection control signal and the fourth selection control signal are opposite. In this embodiment, the first selection control signal can be a high-level signal compared to the third level signal, and the second selection control signal can be a low-level signal compared to the fourth selection signal; in other words, the voltage level of the first selection control signal is greater than the voltage level of the third level signal, and the voltage level of the second selection control signal is less than the voltage level of the third level signal.

[0058] This application uses two sets of selection control signals with opposite level correspondences to control the selection circuit 10 to access the first preset gate turn-on voltage VGH1 or the second preset gate turn-on voltage VGH2. This can effectively avoid the selection control circuit 20 from being mistakenly triggered to output a clock signal corresponding to the first preset gate turn-on voltage VGH1 due to fluctuations in a single selection control signal, which would otherwise cause the display device to still have a power-off ghosting problem. This is beneficial to improving the stability of this application.

[0059] Furthermore, the selection control circuit 20 includes:

[0060] Voltage conversion circuit 21, the input terminal of which is used to receive input voltage VIN, and is used to output the input voltage VIN after voltage conversion;

[0061] The switching circuit 22 has a controlled terminal that is the controlled terminal of the selection control circuit 20. The first and second input terminals of the switching circuit 22 are used to connect to the input voltage VIN. The third input terminal of the switching circuit 22 is connected to the output terminal of the voltage conversion circuit 21. The first and second output terminals of the switching circuit 22 are respectively the first and second output terminals of the selection control circuit 20.

[0062] The voltage conversion circuit 21 can be a BUCK circuit, i.e., a step-down converter circuit, to BUCK-convert the input voltage VIN before outputting it. It is understood that the output voltage of the voltage conversion circuit 21 is less than the input voltage VIN. When the switching circuit 22 receives a power-on / power-off control signal in the first signal state, it controls the corresponding switching transistor within itself to turn on / off, so that the switching circuit 22 can output the input voltage VIN and the power-on / power-off control signal in the first signal state as the first selection control signal and the second selection control signal, respectively. When it receives a power-on / power-off control signal in the second signal state, it controls the corresponding switching transistor within itself to turn on / off, so that the switching circuit 22 can output the output voltage of the voltage conversion circuit 21 and the power-on / power-off control signal in the second signal state as the third selection control signal and the fourth selection control signal, respectively.

[0063] Furthermore, the voltage conversion circuit 21 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is used to connect to the input voltage VIN, and the other end of the first resistor R1 is grounded through the second resistor R2. The connection point of the first resistor R1 and the second resistor R2 is the output terminal of the voltage conversion circuit 21.

[0064] According to the principle of resistor voltage division, the voltage V1 at the connection point between the first resistor R1 and the second resistor R2 is R2*VIN / (R1+R2), which is less than the input voltage VIN, thus achieving BUCK conversion. This application uses resistors to implement the voltage conversion circuit 21, which effectively avoids fluctuations in the output voltage V1 of the voltage conversion circuit 21 due to the power-off state.

[0065] exist Figure 2 In the illustrated embodiment, the selection circuit 10 is implemented using a level converter U1. The first input terminal, second input terminal, first controlled terminal, second controlled terminal, and output terminal of the level converter U1 can be the first input terminal, second input terminal, first controlled terminal, second controlled terminal, and output terminal of the selection circuit 10, respectively. The ground terminal of the level converter U1 is used to connect to a -9V DC voltage. Since there is a trigger threshold at the first controlled terminal of the level converter U1, the level converter U1 will only be triggered to switch to the second preset gate turn-on voltage VGH2 when the voltage level of the third selection control signal is less than the trigger threshold. The solution of this application sets a resistor voltage divider circuit so that the output voltage V1 of the voltage conversion circuit 21 can drop to the trigger threshold faster than the input voltage VIN in the power-off state to trigger the level converter U1 to output a clock signal corresponding to the second preset gate turn-on voltage VGH2. This effectively avoids the problem of the starting voltage level of the second preset gate turn-on voltage VGH2 being too low due to the excessively long drop time, thus failing to eliminate the power-off afterimage.

[0066] Furthermore, the first resistor R1 and / or the second resistor R2 are variable resistors.

[0067] The first resistor R1 and / or the second resistor R2 can be programmable variable resistors or manually variable resistors. The resistance value of either resistor R1 or R2 can be configured under the program in the timing controller or manually controlled by the operator, so that the voltage at the connection point between resistor R1 and R2 can present different voltage values, thereby adjusting the output voltage V1 of the voltage conversion circuit 21. This configuration facilitates adjustment of the output voltage V1 of the voltage conversion circuit 21 for different display devices, improving the compatibility of the proposed solution and the production efficiency of display devices.

[0068] The switching circuit 22 includes a first switching transistor Q1, a second switching transistor Q2, and a third switching transistor Q3;

[0069] The input terminals of the first switch Q1, the second switch Q2, and the third switch Q3 are respectively the first input terminal, the second input terminal, and the third input terminal of the switching circuit 22. The controlled terminal of the first switch Q1 is connected to the output terminal of the second switch Q2, and the output terminal of the first switch Q1 is connected to the output terminal of the third switch Q3. The connection point of the first switch Q1 and the third switch Q3 is the first output terminal of the switching circuit 22. The controlled terminals of the second switch Q2 and the third switch Q3 are connected. The connection point of the second switch Q2 and the third switch Q3 is the third input terminal and the second output terminal of the switching circuit 22.

[0070] In this embodiment, the first switch Q1, the second switch Q2, and the third switch Q3 can be P-MOS transistors. When the display device is powered on, the second switch Q2 and the third switch Q3 can be turned off under the action of the power-on control signal in the first signal state, i.e., a high-level signal, so that the first switch Q1 is turned on and outputs the input voltage VIN as the first selection control signal. At this time, the connection point of the second switch Q2 and the third switch Q3 can output the power-on control signal in the first signal state as the second selection control signal, thereby realizing that the control selection circuit 10 outputs a clock signal corresponding to the first preset gate turn-on voltage VGH1. When the display device is in the off state, the second switch Q2 and the third switch Q3 are turned on under the action of the power-on control signal in the second signal state, i.e., the low-level signal, so that the first switch Q1 is turned off. At this time, the third switch Q3, which is turned on, outputs the output voltage V1 of the voltage conversion circuit 21 as the third selection control signal, and the connection point of the second switch Q2 and the third switch Q3 outputs the power-on control signal in the second signal state as the fourth selection control signal, so as to realize that the control selection circuit 10 outputs a clock signal corresponding to the second preset gate turn-on voltage VGH2.

[0071] Reference Figure 2 In Embodiment 1, the shutdown control circuit further includes:

[0072] A voltage regulator circuit 30 is provided, wherein the input terminal of the voltage regulator circuit 30 is used to connect the second preset gate turn-on voltage VGH2, and the output terminal of the voltage regulator circuit 30 is connected to the second input terminal of the selection circuit 10. The voltage regulator circuit 30 is used to maintain the second preset gate turn-on voltage VGH2 when the selection circuit 10 is connected to the second preset gate turn-on voltage VGH2.

[0073] The voltage regulator circuit 30 can be implemented using at least one capacitor. These capacitors can be connected in parallel to form a parallel branch. One end of the parallel branch can be connected to the second preset gate turn-on voltage VGH2 and the second input terminal of the selection circuit 10, while the other end can be grounded. When the selection circuit 10 is not connected to the second preset gate turn-on voltage VGH2, the voltage regulator circuit 30 can charge and store energy using the second preset gate turn-on voltage VGH2. When the selection circuit 10 is connected to the second preset gate turn-on voltage VGH2, it discharges to maintain the voltage level of the second preset gate turn-on voltage VGH2 that has decreased due to the display device being off, thereby extending the duration of the second preset gate turn-on voltage VGH2 maintaining a higher voltage level. This achieves the purpose of extending the high release rate and long release time of residual charge. It should be noted that the more capacitors there are, and the larger the capacitance of each capacitor, the better the voltage regulation effect on the second preset gate turn-on voltage VGH2, but the larger the PCB area occupied will also be. In this embodiment, there can be two capacitors, namely a first capacitor C1 and a second capacitor C2, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are 4.7uF. This can effectively reduce the PCB area occupied by the voltage regulator circuit 30 while meeting the voltage regulation requirements of the second preset gate turn-on voltage VGH2.

[0074] Reference Figure 2 In Embodiment 1, the power-on / off control signal is the backlight enable signal BLU_EN.

[0075] The backlight enable signal BLU_EN is used to control the backlight to turn on or off according to its own signal state. Specifically, the backlight enable signal BLU_EN in the first signal state controls the backlight to turn on, so that the display device is in the power-on state; the backlight enable signal BLU_EN in the second signal state controls the backlight to turn off, so that the display device is in the power-off state. Therefore, the power-on / off control signal of this application can be implemented by using the backlight enable signal BLU_EN. In addition, the backlight enable signal BLU_EN can be in the first signal state at the first moment when the display device is powered on; and in the second signal state at the first moment when the device is powered off. Therefore, the signal timing also matches the timing requirement of the selection circuit 10 outputting the first preset gate turn-on voltage VGH1 or the second preset gate turn-on voltage VGH2 in this application.

[0076] Furthermore, since the selection circuit 10 can only be triggered to output a clock signal corresponding to the second preset gate turn-on voltage VGH2 when the backlight enable signal BLU_EN is in the second signal state, it can effectively avoid the problem of the selection circuit 10 being mistakenly triggered to output a clock signal corresponding to the second preset gate turn-on voltage VGH2 due to fluctuations in the input voltage VIN, thereby affecting the display screen. For example, the input voltage VIN can be obtained by the power management circuit converting the power supply voltage of the display device. However, in actual applications, the display device may experience a large power-on current but a small power supply voltage during the power-on phase, resulting in a small fluctuation in the input voltage VIN and a small output voltage V1 of the voltage conversion circuit 21. Since the backlight enable signal BLU_EN is in the first signal state at this time, and the voltage level of the power supply voltage is lower due to fluctuations and is higher than the trigger threshold of the first controlled terminal of the selection circuit 10, the selection circuit 10 can output a clock signal corresponding to the first preset gate turn-on voltage VGH1 according to the input voltage VIN and the backlight enable signal BLU_EN in the first signal state received by the first and second controlled terminals respectively, instead of outputting a clock signal corresponding to the second preset gate turn-on voltage VGH2, thereby avoiding the output of a clock signal corresponding to the second preset gate turn-on voltage VGH2, which would affect the power-on screen of the display device.

[0077] Existing technology also includes a method that uses a timing controller to detect the voltage level of the input voltage VIN, and only controls the gate drive circuit 50 to provide a gate drive voltage to the display array 40 to release residual charge when the voltage level of the input voltage VIN is determined to be lower than a preset voltage threshold due to power-off. For details, please refer to... Figure 3 , Figure 3 The solid line portion in the CKV signal represents the clock signal waveform provided by the timing controller to the gate drive circuit 50 in the aforementioned prior art solution. It can be understood that T1 is the power-down duration during which the input voltage VIN drops below a preset voltage threshold after power-off, i.e., the trigger duration of the power-off image cancellation function in the existing display device; T2 is the duration of the power-off image cancellation function in the existing display device.

[0078] Figure 3 The dashed line portion in the CKV signal represents the clock signal waveform output by this application, corresponding to the second preset gate turn-on voltage VGH2. It can be understood that T3 is the trigger duration of the power-off cancellation function in this application; T4 is the duration of the power-off cancellation function in this application. Figure 3 It is clear that T3 < T1, meaning that the solution of this application can execute the shutdown image removal function faster after power-off; T4 > T2, meaning that the duration of the shutdown image removal function of the solution of this application is longer than the duration of the prior art solution, and therefore the solution of this application can better eliminate the shutdown image phenomenon.

[0079] Example 2:

[0080] Reference Figure 4 This application also proposes a display device. The display device includes a display array 40, a gate driving circuit 50, and a power-off control circuit. The specific structure of the power-off control circuit is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0081] The display array 40 can be composed of multiple pixel units defined by the intersection of multiple scan lines and multiple data lines. Multiple output terminals of the gate driving circuit 50 can be connected one-to-one with multiple gate scan lines in the display array 40. The gate driving circuit 50 can output a corresponding gate driving voltage to each gate scan line according to the input clock signal to turn on the thin-film transistors in each pixel unit. The power-off control circuit can be connected to the clock input terminal of the gate driving circuit 50 to output a clock signal corresponding to the first preset gate turn-on voltage VGH1, so that the gate driving circuit 50 can provide a normal gate driving voltage for the normal power-on operation of the display array 40; or, it can output a clock signal corresponding to the second preset gate turn-on voltage VGH2, so that the gate driving circuit 50 can provide an anti-aliasing gate driving voltage for the release of residual charge in the display array 40.

[0082] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the content of the specification and drawings of this application under the concept of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A power-off control circuit, applied to a display device, the display device comprising a display array and a gate driving circuit, the gate driving circuit being configured to output a corresponding gate driving voltage to the display array according to an input clock signal, characterized in that, The shutdown control circuit includes: A selection circuit, wherein a first input terminal and a second input terminal of the selection circuit are respectively connected to a first preset gate enable voltage and a second preset gate enable voltage, and the output terminal of the selection circuit is connected to the gate driving circuit; and... The selection control circuit is used to receive the power on / off control signal, and the output terminal of the selection control circuit is connected to the controlled terminal of the selection circuit. The selection control circuit is used to control the selection circuit to connect to the first preset gate turn-on voltage and output a corresponding clock signal to the gate drive circuit when the power-on control signal in the first signal state is connected. The selection control circuit is used to control the selection circuit to access the second preset gate turn-on voltage and output a corresponding clock signal to the gate drive circuit when the power-on control signal in the second signal state is accessed. Wherein, the power-on / off control signal of the first signal state indicates that the display device is in the power-on state, the power-on / off control signal of the second signal state indicates that the display device is in the power-off state, and the second preset gate turn-on voltage is greater than the first preset gate turn-on voltage.

2. The shutdown control circuit as described in claim 1, characterized in that, The output terminals of the selection control circuit include a first output terminal and a second output terminal. When the selection control circuit receives a power-on control signal in a first signal state, it outputs a first selection control signal and a second selection control signal respectively from the first output terminal and the second output terminal; when it receives a power-on control signal in a second signal state, it outputs a third selection control signal and a fourth selection control signal respectively from the first output terminal and the second output terminal. The controlled terminal of the selection circuit includes a first controlled terminal and a second controlled terminal. The first controlled terminal and the second controlled terminal of the selection circuit are respectively connected to the first output terminal and the second output terminal of the selection control circuit. The selection circuit is used to connect the first preset gate turn-on voltage and output a corresponding clock signal to the gate drive circuit when it receives the first selection control signal and the second selection control signal. Upon receiving the third selection control signal and the fourth selection control signal, the second preset gate turn-on voltage is applied and a corresponding clock signal is output to the gate drive circuit.

3. The shutdown control circuit as described in claim 2, characterized in that, The selection control circuit includes: A voltage conversion circuit, wherein the input terminal of the voltage conversion circuit is used to receive an input voltage and to output the input voltage after voltage conversion; A switching circuit is provided, wherein the controlled terminal of the switching circuit is the controlled terminal of the selection control circuit, the first and second input terminals of the switching circuit are used to connect to the input voltage, the third input terminal of the switching circuit is connected to the output terminal of the voltage conversion circuit, and the first and second output terminals of the switching circuit are respectively the first and second output terminals of the selection control circuit.

4. The shutdown control circuit as described in claim 3, characterized in that, The voltage conversion circuit includes a first resistor and a second resistor. One end of the first resistor is used to connect to the input voltage, and the other end of the first resistor is grounded through the second resistor. The connection point of the first resistor and the second resistor is the output terminal of the voltage conversion circuit. The first resistor and / or the second resistor are variable resistors.

5. The shutdown control circuit as described in claim 3, characterized in that, The switching circuit includes a first switching transistor, a second switching transistor, and a third switching transistor; The input terminals of the first, second, and third switching transistors are respectively the first, second, and third input terminals of the switching circuit. The controlled terminal of the first switching transistor is connected to the output terminal of the second switching transistor, and the output terminal of the first switching transistor is connected to the output terminal of the third switching transistor. The connection point of the first and third switching transistors is the first output terminal of the switching circuit. The controlled terminal of the second and third switching transistors is connected to the controlled terminal of the third switching transistor. The connection point of the second and third switching transistors is the third input terminal and the second output terminal of the switching circuit.

6. The shutdown control circuit as described in claim 1, characterized in that, The shutdown control circuit also includes: A voltage regulator circuit is provided, wherein the input terminal of the voltage regulator circuit is used to connect to the second preset gate turn-on voltage, the output terminal of the voltage regulator circuit is connected to the second input terminal of the selection circuit, and the voltage regulator circuit is used to maintain the second preset gate turn-on voltage when the selection circuit is connected to the second preset gate turn-on voltage.

7. The shutdown control circuit as described in claim 6, characterized in that, The voltage regulator circuit includes a first capacitor and a second capacitor; The first terminal of the first capacitor and the first terminal of the second capacitor are respectively the input terminal and the output terminal of the voltage regulator circuit. The first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminals of the first capacitor and the second capacitor are respectively grounded.

8. The shutdown control circuit as described in any one of claims 1-7, characterized in that, The power-on / off control signal is a backlight enable signal.

9. A display device, characterized in that, The display device includes: Display array; A gate driving circuit, wherein the gate driving circuit is configured to output a gate driving voltage to the display array; and, The power-off control circuit according to any one of claims 1-8, wherein the power-off control circuit is connected to the gate drive circuit.

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