Decoding method, memory storage device and memory control circuit unit

Abstract

The present application provides a decoding method, a memory storage device and a memory control circuit unit. The method comprises: sending at least one read instruction sequence, which instructs to read a first physical unit in a rewritable non-volatile memory module; receiving response data of the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect voltage variation of a first bit line in a discharge process, in which the first bit line is located in a first storage unit in the first physical unit; determining a decoding parameter corresponding to the first storage unit according to the plurality of identification bits; and decoding data read from the first storage unit according to the decoding parameter. Thus, the decoding efficiency of data read from the rewritable non-volatile memory module can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory control technique, and more particularly, to a decoding method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] Mobile phones, tablet computers, and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memories) are very suitable for being built into various portable multimedia devices exemplified above due to their data non-volatility, power saving, small size, and lack of mechanical structure.

[0003] To ensure data correctness, data stored in a rewritable non-volatile memory module can be encoded. When data is read from the rewritable non-volatile memory module, the read data can be decoded to correct errors. However, how to improve the decoding efficiency of data read from the rewritable non-volatile memory module is a subject that researchers in the field strive to study. SUMMARY

[0004] The present application provides a decoding method, a memory storage device, and a memory control circuit unit, which can improve the decoding efficiency of data read from a rewritable non-volatile memory module.

[0005] An example embodiment of the present application provides a decoding method for a rewritable non-volatile memory module, the decoding method comprising: sending at least one read instruction sequence, wherein the at least one read instruction sequence indicates reading a first physical unit in the rewritable non-volatile memory module; receiving response data of the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect voltage changes of a first bit line in which a first storage unit in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first storage unit according to the plurality of identification bits; and decoding data read from the first storage unit according to the decoding parameter.

[0006] In an example embodiment of the present application, the plurality of identification bits reflect a plurality of sensing results of voltage states of the first bit line at different time points during the discharge process of the first bit line.

[0007] In an example embodiment of the present application, the discharge process includes a discharge process of the first bit line after pre-charging.

[0008] In an example embodiment of this disclosure, the at least one read instruction sequence has at least one time parameter, and the at least one time parameter is used to control a sensing time point of at least one of the plurality of identification bits.

[0009] In an example embodiment of this disclosure, the plurality of identification bits includes a first identification bit, the at least one time parameter includes a first time parameter, and the first time parameter corresponds to a time difference between a sensing time point of the first identification bit and a discharge starting time point of the first bit line.

[0010] In an example embodiment of this disclosure, a total number of the at least one time parameter is positively correlated with a total number of the plurality of identification bits.

[0011] In an example embodiment of this disclosure, the step of determining the decoding parameter corresponding to the first storage unit according to the plurality of identification bits includes: in response to the plurality of identification bits satisfying a first condition, setting the decoding parameter corresponding to the first storage unit as a first value; and in response to the plurality of identification bits satisfying a second condition, setting the decoding parameter corresponding to the first storage unit as a second value, and the first value is different from the second value.

[0012] In an example embodiment of this disclosure, the step of determining the decoding parameter corresponding to the first storage unit according to the plurality of identification bits includes: in response to the plurality of identification bits satisfying a first condition, setting the decoding parameter corresponding to the first storage unit as a first value; and in response to the plurality of identification bits satisfying a second condition, setting the decoding parameter corresponding to the first storage unit as a second value, and the first value is different from the second value.

[0013] An example embodiment of this disclosure further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: send at least one read instruction sequence, wherein the at least one read instruction sequence indicates to read a first physical unit in the rewritable non-volatile memory module; receive response data of the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect voltage changes of a first bit line in which a first storage unit in the first physical unit is located during a discharge process; determine a decoding parameter corresponding to the first storage unit according to the plurality of identification bits; and decode data read from the first storage unit according to the decoding parameter.

[0014] In an example embodiment of this disclosure, the memory control circuit unit determines the decoding parameter corresponding to the first storage unit according to the plurality of identification bits.

[0015] 5In an example embodiment of this disclosure, the memory control circuit unit determines the decoding parameter corresponding

[0016] The operation of the decoding parameters of the first storage unit includes: in response to the plurality of identification bits meeting a first condition, setting the decoding parameters corresponding to the first storage unit to a first value; and in response to the plurality of identification bits meeting a second condition, setting the decoding parameters corresponding to the first storage unit to a second value, wherein the first value is different from the second value.

[0017] 0. An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling rewritable non-volatile memory.

[0018] The memory module includes a host interface, a memory interface, an error checking and correction circuit, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the memory management module.

[0019] Error checking and correction circuitry. The memory management circuitry is used to: send at least one read instruction sequence, wherein the at least one read instruction sequence indicates reading a first physical cell in the rewritable non-volatile memory module; receive the...

[0020] The response data of the rewritable non-volatile memory module, wherein the response data includes multiple identification bits, and the multiple identification bits reflect the voltage change of the first bit line where the first memory cell in the first physical unit is located during the discharge process;

[0021] The system determines decoding parameters corresponding to the first storage unit based on the plurality of identification bits, and the error checking and correction circuit is used to decode the data read from the first storage unit according to the decoding parameters.

[0022] 0 In an exemplary embodiment of the present invention, the memory management circuit determines the corresponding identifier based on the plurality of identification bits.

[0023] The operation of the decoding parameters of the first storage unit includes: in response to the plurality of identification bits meeting a first condition, setting the decoding parameters corresponding to the first storage unit to a first value; and in response to the plurality of identification bits meeting a second condition, setting the decoding parameters corresponding to the first storage unit to a second value, wherein the first value is different from the second value.

[0024] 5. Based on the above, when sending at least one read instruction sequence to indicate reading the first read instruction in the rewritable non-volatile memory module...

[0025] After the entity unit, response data from the rewritable non-volatile memory module can be received. In particular, the response data can include a plurality of identification bits, and the plurality of identification bits reflect a voltage change of a first bit line in which the first memory cell in the first entity unit is located during the discharging process. According to the plurality of identification bits, a decoding parameter corresponding to the first memory cell can be determined. Then, data read from the first memory cell can be decoded according to the decoding parameter. Thus, the decoding efficiency of data read from the rewritable non-volatile memory module can be effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device shown in accordance with an example embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a threshold voltage distribution of a memory cell shown in accordance with an example embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a voltage change of a bit line in which a target memory cell is located during a discharging process shown in accordance with an example embodiment of the present invention;

[0033] Figure 8 is a schematic diagram of determining a decoding parameter corresponding to a first memory cell according to a plurality of identification bits shown in accordance with an example embodiment of the present invention;

[0034] Figure 9 is a schematic diagram of determining a decoding parameter corresponding to a first memory cell according to a plurality of identification bits shown in accordance with an example embodiment of the present invention;

[0035] Figure 10 is a schematic diagram of determining a decoding parameter corresponding to a first memory cell according to a plurality of identification bits shown in accordance with an example embodiment of the present invention;

[0036] Figure 11 FIG. 1 is a diagram illustrating determining decoding parameters corresponding to a first memory cell according to a plurality of identification bits, according to an example embodiment of the present application;

[0037] Figure 12 FIG. 2 is a flowchart illustrating a decoding method, according to an example embodiment of the present application. DETAILED DESCRIPTION

[0038] Reference will now be made to specific embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0039] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0040] Figure 1 FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input / output (I / O) device, according to an example embodiment of the present application. Figure 2 FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I / O device, according to an example embodiment of the present application.

[0041] Please refer to Figure 1 and Figure 2 The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be connected to a system bus 110.

[0042] In an example embodiment, the host system 11 can be connected to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 through the data transfer interface 114. In addition, the host system 11 can be connected to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 through the system bus 110.

[0043] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 can be disposed on a host board 20 of the host system 11. The number of the data transmission interface 114 can be one or more. Through the data transmission interface 114, the host board 20 can be connected to the memory storage device 10 through wired or wireless manner.

[0044] In an example embodiment, the memory storage device 10 can be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy (BLE) memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board 20 can also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the host board 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0045] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise Figure 3 a memory storage device 30 and a host system 31.

[0046] Figure 3 a schematic diagram of a host system and a memory storage device according to an example embodiment of the present disclosure.

[0047] Please refer to Figure 3The memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, etc. For example, the memory storage device 30 can be a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34, etc. The embedded storage device 34 includes an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc. The embedded storage device 34 is directly connected to a substrate of the host system.

[0048] Figure 4 A schematic diagram of a memory storage device according to an example embodiment of the present application.

[0049] Referring to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0050] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an example embodiment, the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that contains the memory control circuit unit 42.

[0051] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions of the host system 11.

[0052] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), another flash memory module, or another memory module having the same characteristics.

[0053] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0054] In an example embodiment, the memory cells of the rewritable non-volatile memory module 43 can form a plurality of physical program units, and the physical program units can form a plurality of physical erase units. Specifically, the memory cells on the same word line can form one or more physical program units. If one memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0055] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In an example embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can include 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erase unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block.

[0056] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application.

[0057] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read, and erase operations, etc. when the memory storage device 10 is in operation. The operation of the memory management circuit 51 is equivalent to the operation of the memory control circuit unit 42.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read, and erase operations, etc.

[0059] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module that is dedicated for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read, and erase operations, etc.

[0060] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0061] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0062] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written into the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits a corresponding instruction sequence. For example, the instruction sequence can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and a corresponding instruction sequence to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, the identification code of the read, the memory address, etc. information is included.

[0063] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0064] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write instruction, and the memory management circuit 51 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the corresponding error correcting code and / or error detecting code corresponding to the data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0065] The buffer memory 55 is connected to the memory management circuit 51 and is used to buffer data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0066] In an example embodiment, Figure 4 The rewritable non-volatile memory module 43 can comprise a flash memory module. In an example embodiment, Figure 4 The memory control circuit 42 can comprise a flash memory controller. In an example embodiment, Figure 5 The memory management circuit 51 can comprise a flash memory management circuit.

[0067] Figure 6 FIG. 6 is a diagram showing a threshold voltage distribution of a memory cell according to an example embodiment of the present application.

[0068] Please refer to Figure 6 The horizontal axis represents the threshold voltage of a memory cell, and the vertical axis represents the number of memory cells. For example, Figure 6 may represent the threshold voltage of each memory cell in one physical unit (also referred to as a first physical unit) in the rewritable non-volatile memory module 43. For example, the first physical unit can comprise one or more physical program units.

[0069] Assume that state 610 corresponds to bit "1" and state 620 corresponds to bit "0". When the threshold voltage of a memory cell belongs to state 610, the memory cell stores bit "1". Conversely, if the threshold voltage of a memory cell belongs to state 620, the memory cell stores bit "0". Note that in the present example embodiment, one state in the threshold voltage distribution corresponds to one bit value, and the threshold voltage distribution of a memory cell has two possible states. However, in other example embodiments, each state in the threshold voltage distribution can correspond to multiple bit values and the threshold voltage distribution of a memory cell can have four, eight or any other number of states. Furthermore, the present application does not limit the bit represented by each state. For example, in another example embodiment of the present application, state 610 can correspond to bit "0" and state 620 can correspond to bit "1". Figure 6

[0070] When data is to be read from the rewritable non-volatile memory module 43, the memory management circuit 51 can send a read instruction sequence to the rewritable non-volatile memory module 43. The read instruction sequence instructs the rewritable non-volatile memory module 43 to read the first physical unit using at least one read voltage level to obtain the data stored in the first physical unit. For example, according to the read instruction sequence, the rewritable non-volatile memory module 43 can use Figure 6 ​The memory management circuit 51 reads at least one memory cell in the first physical unit by using a read voltage level 601. If the threshold voltage of a memory cell is less than the read voltage level 601, the memory cell can be turned on, and the memory management circuit 51 can read bit "1". Alternatively, if the threshold voltage of a memory cell is greater than the read voltage level 601, the memory cell can be turned off, and the memory management circuit 51 can read bit "0".

[0071] Figure 7 This is a schematic diagram illustrating the voltage change of the bit line where the target memory cell is located during the discharge process, as shown in an exemplary embodiment of the present invention.

[0072] Please refer to Figure 7 Generally, upon receiving a read instruction sequence, the rewritable non-volatile memory module 43 can first perform pre-charging on the bit line (also called the target bit line) where the memory cell to be read (also called the target memory cell) is located, to charge the voltage (also called the bit line voltage) of the bit line (also called the bit line voltage) where the memory cell (i.e., the target memory cell) indicated by the read instruction sequence is located to a preset voltage value V (BL). After completing the pre-charging of the target bit line, at time point T (0), the rewritable non-volatile memory module 43 can apply a read voltage (e.g., ... Figure 6 The read voltage level 601 is applied to the word line (also called the target word line) where the target memory cell is located. Simultaneously, the rewritable non-volatile memory module 43 can discharge the target bit line. During the discharge process, the voltage of the target bit line may gradually decrease. Generally, if the applied read voltage is less than the threshold voltage of the target memory cell, the target memory cell will not be turned on by this read voltage. If the target memory cell is not turned on by this read voltage, the voltage of the target bit line may slowly decrease during the discharge process due to leakage current (e.g., ...). Figure 7 (As shown in curve 710). However, if the applied read voltage is not less than the threshold voltage of the target memory cell, the target memory cell can be turned on by this read voltage. When the target memory cell is turned on by this read voltage, the voltage of the target bit line may drop rapidly during the discharge process (e.g., Figure 7 (As shown in curve 720). In an exemplary embodiment, time point T(0) is also referred to as the discharge start time point of the bit line.

[0073] After discharging for a period of time (e.g., ΔΤ(5)), at time point T(S), the rewritable nonvolatile memory module 43 can perform a voltage state sensing on the target bit line and obtain a sensing result. In particular, the sensing result can reflect the voltage state of the target bit line after discharging for a period of time (e.g., ΔΤ(5)). For example, the sensing result can reflect whether the voltage of the target bit line is greater than the decision voltage (also referred to as sensing voltage) V(jud) after discharging for a period of time (e.g., ΔΤ(5)). Then, the rewritable nonvolatile memory module 43 can send back response data corresponding to the sensing result to the memory management circuit 51. According to the response data, the memory management circuit 51 can obtain the current data storage state (e.g., whether storing bit "0" or "1") of the target storage unit.

[0074] In an example embodiment, assume that the voltage variation of the target bit line during discharging is represented by curve 710. After performing a voltage state sensing on the target bit line at time point T(S), the obtained sensing result can reflect that the voltage of the target bit line at time point T(S) is greater than the decision voltage V(jud) (equivalent to the target storage unit not being turned on by the read voltage). According to the sensing result, the rewritable nonvolatile memory module 43 can send back response data with bit "0" to the memory management circuit 51. According to the response data, the memory management circuit 51 can determine that the threshold voltage of the target storage unit belongs to state 620 and the target storage unit can be storing bit "0". Figure 6

[0075] Alternatively, in an example embodiment, assume that the voltage variation of the target bit line during discharging is represented by curve 720. After performing a voltage state sensing on the target bit line at time point T(S), the obtained sensing result can reflect that the voltage of the target bit line at time point T(S) is less than the decision voltage V(jud) (equivalent to the target storage unit being turned on by the read voltage). According to the sensing result, the rewritable nonvolatile memory module 43 can send back response data with bit "1" to the memory management circuit 51. According to the response data, the memory management circuit 51 can determine that the threshold voltage of the target storage unit belongs to state 610 and the target storage unit can be storing bit "1". Figure 6

[0076] Please refer back to Figure 6 In an example embodiment, there is an overlapping region 630 between state 610 and state 620 (in the range of V(jud) - ΔV to V(jud) + ΔV). Figure 6 ​​The overlap region 630 represents some memory cells in the first physical unit that are supposed to store bit "1" (belonging to state 610) but have a threshold voltage greater than the applied read voltage level 601; and some memory cells in the first physical unit that are supposed to store bit "0" (belonging to state 620) but have a threshold voltage less than the applied read voltage level 601. In other words, some bits of the data read by applying the read voltage level 601 can be erroneous.

[0077] Generally, if most of the memory cells in the first physical unit are used for a short time (e.g., data is stored in the first physical unit for a short time) and / or most of the memory cells in the first physical unit are used infrequently (e.g., the memory cells have a low read count, a low write count, and / or a low erase count), the area of the overlap region 630 is typically small, and the overlap region 630 can not exist (i.e., states 610 and 620 do not overlap). Alternatively, if the memory storage device 10 is just out of the factory, the overlap region 630 typically does not exist. If the area of the overlap region 630 is small, the number of erroneous bits in the data read from the first physical unit by applying the read voltage level 601 is typically small.

[0078] However, as the use time and / or the use frequency of the rewritable non-volatile memory module 43 increases, the area of the overlap region 630 can gradually increase. For example, if the first physical unit is used for a long time (e.g., data is stored in the first physical unit for a long time) and / or most of the memory cells in the first physical unit are used frequently (e.g., the memory cells have a high read count, a high write count, and / or a high erase count), the area of the overlap region 630 can increase (e.g., states 610 and 620 become more flat and / or states 610 and 620 are closer to each other). If the area of the overlap region 630 is large, the number of erroneous bits in the data read from the first physical unit by applying the read voltage level 601 can be large.

[0079] In an example embodiment, after receiving the read data from the rewritable non-volatile memory module 43, the error checking and correction circuit 54 can decode the read data to attempt to correct errors in the data. For example, the error checking and correction circuit 54 can support low-density parity-check (LDPC) codes. For example, the error checking and correction circuit 54 can encode and decode data using low-density parity-check codes. However, in another example embodiment, the error checking and correction circuit 54 can also support BCH codes, convolutional codes, turbo codes, and the like, without limitation.

[0080] In one exemplary embodiment, the error checking and correction circuit 54 may use specific decoding parameters to assist in decoding the data. Taking low-density parity-checking codes as an example, this decoding parameter may include the log-likelihood ratio (LLR). For instance, during the decoding operation, the error checking and correction circuit 54 may use the log-likelihood ratio to decode the read data. Alternatively, in another exemplary embodiment, the error checking and correction circuit 54 may use other types of decoding parameters to decode the data; this invention is not limited thereto.

[0081] In one exemplary embodiment, the decoding parameters may include reliability information. Using the log-likelihood ratio as an example, a larger absolute value of the log-likelihood ratio (which may be positive or negative) corresponding to a data bit indicates a higher reliability for that data bit, and a higher probability that the current bit value of that data bit is considered correct. Conversely, a smaller absolute value of the log-likelihood ratio corresponding to a data bit indicates a lower reliability for that data bit, and a higher probability that the current bit value of that data bit is considered incorrect. If a data bit is considered incorrect, the error checking and correction circuit 54 can correct the error in the current decoding operation, for example, by changing the bit value of that data bit. It should be noted that the decoding parameters may also include other types of reliability information, depending on the encoding / decoding algorithm used by the error checking and correction circuit 54.

[0082] It should be noted that as the usage time and frequency of the rewritable non-volatile memory module 43 increase, Figure 6 Changes in the overlapping area 630 or variations in ambient temperature can cause a decrease in the decoding capability, error correction capability, and / or decoding efficiency of the error checking and correction circuit 54 if the preset decoding parameters are continuously used for data decoding. Therefore, it is necessary to dynamically adjust the decoding parameters to improve the decoding capability, error correction capability, and / or decoding efficiency of the error checking and correction circuit 54, given that both the internal and external environments may change.

[0083] In an example embodiment, the memory management circuit 51 can send at least one read instruction sequence to the rewritable non-volatile memory module 43. The at least one read instruction sequence can instruct the rewritable non-volatile memory module 43 to perform a data read on a particular physical cell (i.e., a first physical cell). After sending the at least one read instruction sequence, the memory management circuit 51 can receive a response data from the rewritable non-volatile memory module 43. The response data can include a plurality of identification bits. In particular, the identification bits can reflect a voltage variation of a bit line (also referred to as a first bit line) on which a particular memory cell (also referred to as a first memory cell) in the first physical cell is located during a discharging process. Alternatively, from another perspective, the identification bits can also reflect a read result of the first memory cell at different time points during the discharging process of the first bit line.

[0084] After obtaining the plurality of identification bits, the memory management circuit 51 can determine a decoding parameter corresponding to the first memory cell according to the plurality of identification bits. Then, the error checking and correction circuit 54 can decode the data read from the first memory cell according to the decoding parameter. In particular, by dynamically determining (e.g., updating or adjusting) the decoding parameter, the decoding capability, error correction capability and / or decoding efficiency of the error checking and correction circuit 54 on the data read from the first memory cell can be effectively improved.

[0085] In an example embodiment, the plurality of identification bits can reflect a plurality of sensing results of the voltage state of the first bit line at different time points during the discharging process of the first bit line. For example, the sensing results can be completely identical, partially identical or completely different, depending on the data storage state or program state of the current first memory cell.

[0086] In an example embodiment, before sensing the voltage state of the first bit line or reading the data storage state of the first memory cell, the rewritable non-volatile memory module 43 can first pre-charge the first bit line. After completing the pre-charge of the first bit line, the rewritable non-volatile memory module 43 can apply a read voltage (e.g., a read voltage level 601 of Figure 6 ) to a word line (also referred to as a first word line) on which the first memory cell is located. At the same time, the rewritable non-volatile memory module 43 can discharge the first bit line. In other words, in an example embodiment, the discharging process includes the discharging process of the pre-charged first bit line. The implementation details of the pre-charge and discharge procedures have been described in the example embodiment of Figure 7 , and are not repeated here.

[0087] In an example embodiment, the at least one read instruction sequence carries at least one time parameter. In particular, the at least one time parameter is used to control the sensing time point of at least one of the plurality of identification bits. In an example embodiment, the at least one time parameter is used to control the sensing time point of at least one of the plurality of identification bits can also be considered as the at least one time parameter can be used to affect, determine, change, adjust or update the sensing time point of at least one of the plurality of identification bits.

[0088] In an example embodiment, assuming one of the plurality of identification bits is referred to as a first identification bit, and one of the at least one time parameter is referred to as a first time parameter, the first time parameter can correspond to a time difference between the sensing time point of the first identification bit and the discharge start time point of the first bit line. For example, the first time parameter can be used to control, affect, determine, change, adjust or update the time difference between the sensing time point of the first identification bit and the discharge start time point of the first bit line.

[0089] In an example embodiment, assuming another one of the plurality of identification bits is referred to as a second identification bit, and another one of the at least one time parameter is referred to as a second time parameter, the second time parameter can correspond to a time difference between the sensing time point of the second identification bit and the discharge start time point of the first bit line. For example, the second time parameter can be used to control, affect, determine, change, adjust or update the time difference between the sensing time point of the second identification bit and the discharge start time point of the first bit line.

[0090] By the same token, according to the time parameter carried by the read instruction sequence, after the first bit line starts discharging, the rewritable non-volatile memory module 43 can sense the voltage state of the first bit line at the specified time point and obtain the corresponding sensing result. Then, the rewritable non-volatile memory module 43 can return the sensing result to the memory management circuit 51 in the form of a plurality of identification bits through the response data.

[0091] In an example embodiment, the read instruction sequence carrying the time parameter can mean that one or more time parameters are included in a read instruction sequence. Thus, after receiving the read instruction sequence, the rewritable non-volatile memory module 43 can directly obtain the time parameter from the read instruction sequence.

[0092] In an example embodiment, the read instruction sequence carries a time parameter, or one or more time parameters can be included in a set instruction sequence, and the set instruction sequence can be transmitted to the rewritable non-volatile memory module 43 together with the corresponding read instruction sequence. Thus, upon receiving the read instruction sequence and the corresponding set instruction, the rewritable non-volatile memory module 43 can obtain the time parameter corresponding to the read instruction sequence from the set instruction.

[0093] In an example embodiment, the total number of time parameters carried by the read instruction sequence can be positively correlated to the total number of identification bits. For example, assuming that the total number of time parameters carried by a read instruction sequence is three (i.e., a read instruction sequence carries three time parameters), upon the discharge of the first bit line, the rewritable non-volatile memory module 43 can sense the voltage state of the first bit line at three specified time points according to the three time parameters respectively and obtain the corresponding sensing results. Then, the rewritable non-volatile memory module 43 can return the sensing results to the memory management circuit 51 in the form of three identification bits through the response data. In particular, the three identification bits can respectively reflect the voltage state of the first bit line at the above-mentioned three specified time points.

[0094] In an example embodiment, the memory management circuit 51 can set the decoding parameter of the first storage unit according to whether the received identification bits meet a specific condition. For example, in response to the identification bits meeting a certain condition (also referred to as a first condition), the memory management circuit 51 can set the decoding parameter corresponding to the first storage unit to a certain value (also referred to as a first value). Alternatively, in response to the identification bits meeting another condition (also referred to as a second condition), the memory management circuit 51 can set the decoding parameter corresponding to the first storage unit to another value (also referred to as a second value). The first condition is different from the second condition, and the first value is different from the second value. By analogy, the decoding parameter of the first storage unit can be dynamically determined, updated or adjusted according to the condition met by the received identification bits.

[0095] Figure 8 is a schematic diagram illustrating the determination of the decoding parameter corresponding to the first storage unit according to the identification bits, according to an example embodiment of the present application.

[0096] Please refer to Figure 8, it is assumed that one or more read instruction sequences can carry three time parameters, and the three time parameters correspond to time differences ΔT(l), ΔT(2) and ΔT(3), respectively. In particular, the time difference ΔT(l) corresponds to the time difference between a time point T(l) (also referred to as the sensing time point of the identification bit B(l)) and a time point T(0) (i.e., the discharge starting time point of the first bit line), the time difference ΔT(2) corresponds to the time difference between a time point T(2) (also referred to as the sensing time point of the identification bit B(2)) and the time point T(0), and the time difference ΔT(3) corresponds to the time difference between a time point T(3) (also referred to as the sensing time point of the identification bit B(3)) and the time point T(0).

[0097] After the first bit line completes the pre-charge, the first bit line can start discharging at the time point T(0). According to the three time parameters, after the time differences ΔT(l), ΔT(2) and ΔT(3) elapse, respectively, at the time points T(l), T(2) and T(3), the re-writable non-volatile memory module 43 can perform the sensing of the voltage state of the first bit line and generate the identification bits B(l), B(2) and B(3) according to the sensing results. In particular, the identification bit B(i) can reflect whether the voltage of the first bit line is greater than the decision voltage V(jud) at the time point T(i).

[0098] It should be noted that, in the example embodiment of Figure 8 , the curve 810 can represent the voltage variation of the first bit line during the discharging process. According to the relative relationship between the curve 810 and the decision voltage V(jud), the sensing results of the first bit line at the time points T(l), T(2) and T(3) are all that the voltage of the first bit line is less than the decision voltage V(jud). Therefore, the bit values of the identification bits B(l), B(2) and B(3) can all be determined as "1" to reflect the sensing results at the time points T(l), T(2) and T(3).

[0099] After receiving the response data from the re-writable non-volatile memory module 43, according to the bit values of the identification bits B(l), B(2) and B(3), the memory management circuit 51 can determine the decoding parameter corresponding to the first storage unit as a parameter (also referred to as the first decoding parameter) LLR(l). The parameter LLR(l) includes a specific log-likelihood ratio. Then, the error checking and correction circuit 54 can use the parameter LLR(l) to decode the data read from the first storage unit.

[0100] Figure 9 is a schematic diagram illustrating the determination of a decoding parameter corresponding to a first storage unit according to a plurality of identification bits according to an example embodiment of the present application.

[0101] Please refer to Figure 9, assume that the one or more read instruction sequences can also carry three time parameters, and the three time parameters correspond to time differences ΔT(l), ΔT(2), and ΔT(3), respectively. After the first bit line is completed with the pre-charge, the first bit line can start to discharge at time point T(0). According to the three time parameters, after time differences ΔT(l), ΔT(2), and ΔT(3), respectively, at time points T(l), T(2), and T(3), the rewritable non-volatile memory module 43 can perform sensing of the voltage state of the first bit line and generate identification bits B(l), B(2), and B(3) according to the sensing results.

[0102] It is noted that, in the example embodiment of Figure 9 , the curve 910 can represent the voltage variation of the first bit line during the discharging process. According to the relative relationship between the curve 910 and the decision voltage V(jud), the sensing result of the first bit line at time point T(l) is that the voltage of the first bit line is greater than the decision voltage V(jud), and the sensing results of the first bit line at time points T(2) and T(3) are that the voltage of the first bit line is less than the decision voltage V(jud). Therefore, the bit values of the identification bits B(l), B(2), and B(3) can be determined as "0", "1", and "1", respectively, to reflect the sensing results at time points T(l), T(2), and T(3). Then, according to the bit values of the identification bits B(l), B(2), and B(3), the memory management circuit 51 can determine the decoding parameter corresponding to the first storage unit as a parameter (also referred to as a second decoding parameter) LLR(2). For example, the parameter LLR(2) can include a specific log-likelihood ratio. Then, the error checking and correction circuit 54 can use the parameter LLR(2) to decode the data read from the first storage unit.

[0103] Figure 10 is a schematic diagram illustrating determination of a decoding parameter corresponding to a first storage unit according to a plurality of identification bits, according to an example embodiment of the present application.

[0104] Please refer to Figure 10 , assume that the one or more read instruction sequences can also carry three time parameters, and the three time parameters correspond to time differences ΔT(l), ΔT(2), and ΔT(3), respectively. After the first bit line is completed with the pre-charge, the first bit line can start to discharge at time point T(0). According to the three time parameters, after time differences ΔT(l), ΔT(2), and ΔT(3), respectively, at time points T(l), T(2), and T(3), the rewritable non-volatile memory module 43 can perform sensing of the voltage state of the first bit line and generate identification bits B(l), B(2), and B(3) according to the sensing results.

[0105] It is noted that, in the example embodiment of Figure 10In the example embodiment, curve 1010 can represent the voltage variation of the first bit line during the discharging process. According to the relative relationship between curve 1010 and the decision voltage V(jud), the sensing result of the first bit line at time points T(l) and T(2) is that the voltage of the first bit line is greater than the decision voltage V(jud), and the sensing result of the first bit line at time point T(3) is that the voltage of the first bit line is less than the decision voltage V(jud). Therefore, the bit values of the identified bits B(l), B(2) and B(3) can be determined as "0", "0" and "1", respectively, to reflect the sensing results at time points T(l), T(2) and T(3). Then, according to the bit values of the identified bits B(l), B(2) and B(3), the memory management circuit 51 can determine the decoding parameter corresponding to the first memory cell as a parameter (also referred to as a third decoding parameter) LLR(3). For example, the parameter LLR(3) can include a specific log-likelihood ratio. Then, the error checking and correction circuit 54 can use the parameter LLR(3) to decode the data read from the first memory cell.

[0106] Figure 11 FIG. 10 is a diagram illustrating determining a decoding parameter corresponding to a first memory cell according to a plurality of identified bits, according to an example embodiment of the present disclosure.

[0107] Please refer to Figure 11 , it is assumed that one or more read instruction sequences can also carry three time parameters, and the three time parameters correspond to time differences ΔT(l), ΔT(2) and ΔT(3), respectively. After the first bit line completes the pre-charge, the first bit line can start discharging at time point T(0). According to the three time parameters, after time differences ΔT(l), ΔT(2) and ΔT(3) elapse, respectively, at time points T(l), T(2) and T(3), the rewritable non-volatile memory module 43 can perform voltage state sensing on the first bit line and generate identified bits B(l), B(2) and B(3) according to the sensing results.

[0108] It should be noted that, in Figure 11In an example embodiment, the curve 1110 can represent the voltage variation of the first bit line during the discharging process. According to the relative relationship between the curve 1110 and the decision voltage V(jud), the sensing result of the first bit line at the time points T(l), T(2), and T(3) is that the voltage of the first bit line is greater than the decision voltage V(jud). Therefore, the bit values of the identified bits B(l), B(2), and B(3) can be determined as "0" to reflect the sensing result at the time points T(l), T(2), and T(3). Then, according to the bit values of the identified bits B(l), B(2), and B(3), the memory management circuit 51 can determine the decoding parameter corresponding to the first memory cell as a parameter (also referred to as a fourth decoding parameter) LLR(4). For example, the parameter LLR(4) can include a specific log-likelihood ratio. Then, the error checking and correction circuit 54 can use the parameter LLR(4) to decode the data read from the first memory cell.

[0109] In an example embodiment, the memory management circuit 51 can obtain the parameters LLR(l) to LLR(4) by looking up a table or using a specific algorithm. For example, the memory management circuit 51 can look up a data table according to the bit values of the identified bits B(l), B(2), and B(3) to obtain the decoding parameters corresponding to the identified bits B(l), B(2), and B(3). Alternatively, the memory management circuit 51 can input the bit values of the identified bits B(l), B(2), and B(3) into a specific algorithm and obtain the corresponding decoding parameters according to the output of the algorithm.

[0110] It should be noted that, in the example embodiment, Figure 8 to Figure 11 In an example embodiment, the total number of time parameters carried by a read instruction sequence can also be more (e.g., five) or less (e.g., two). According to the time parameters, more identified bits (e.g., the identified bits B(l) to B(5)) can be obtained and used to determine the decoding parameters corresponding to the first memory cell. The details of the related operations have been described above and will not be repeated here.

[0111] In an example embodiment, the first memory cell can be used to represent any one of the memory cells in the first physical cell. According to the foregoing example embodiment, the decoding parameters corresponding to at least part or all of the memory cells in the first physical cell can be determined and used to decode the data read from the first physical cell. In this way, the decoding capability, error correction capability, and / or decoding efficiency of the data read from the first physical cell can be effectively improved.

[0112] In an example embodiment, the time parameter is a pre-set value. In an example embodiment, the memory management circuit 51 can dynamically determine, adjust or update the time parameter. For example, the memory management circuit 51 can determine, adjust or update the time parameter according to a risk state or a health state of the rewritable non-volatile memory module 43 or the first physical unit. For example, the memory management circuit 51 can determine the risk state or the health state of the rewritable non-volatile memory module 43 or the first physical unit according to a bit error rate, a program count, an erase count, a read count or a temperature of the rewritable non-volatile memory module 43 or the first physical unit. The bit error rate can reflect a proportion of error bits in a piece of data. The program count, the erase count and the read count can respectively reflect a number of times that one physical management unit (e.g., one or more physical units) is programmed, erased and read. In addition, more parameters that can reflect the risk state or the health state of the rewritable non-volatile memory module 43 or the first physical unit can be used to determine, adjust or update the time parameter, and the present application is not limited thereto.

[0113] In an example embodiment, in response to the adjustment of a time parameter, a time difference (or a sensing time point) corresponding to the time parameter can be changed. For example, Figure 8 In response to the adjustment of a time parameter, one of the time differences ΔT(l), ΔT(2) and ΔT(3) can be increased or decreased.

[0114] Figure 12 A flowchart of a decoding method according to an example embodiment of the present application is shown.

[0115] Please refer to Figure 12 In step S1201, at least one read instruction sequence is sent, wherein the at least one read instruction sequence instructs to read a first physical unit in a rewritable non-volatile memory module. In step S1202, response data of the rewritable non-volatile memory module is received, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage change of a bit line (i.e., a first bit line) in which a first storage unit in the first physical unit is located during a discharging process. In step S1203, a decoding parameter corresponding to the first storage unit is determined according to the plurality of identification bits. In step S1204, data read from the first storage unit is decoded according to the decoding parameter.

[0116] However, Figure 12 The steps in the above method have been described in detail, and thus will not be repeated here. It is worth noting that Figure 12 The steps in the above method can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 12 The method of the above embodiment can be used in combination with the above example embodiments, or can be used alone, and the present application is not limited thereto.

[0117] In summary, the decoding method, the memory storage device and the memory control circuit unit provided by the example embodiments of the present application can dynamically determine the decoding parameters corresponding to the first memory cell according to the voltage state of the bit line where the first memory cell is located at different time points in the discharge process. By using the dynamically determined decoding parameters to decode the data read from the first memory cell, the decoding efficiency of the data can be effectively improved.

[0118] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A decoding method, comprising: A decoding method for a rewritable non-volatile memory module, the decoding method comprising: sending at least one read instruction sequence, wherein the at least one read instruction sequence instructs reading a first physical unit in the rewritable non-volatile memory module; receiving response data of the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect voltage variations of a first bit line in a discharge process of a first storage unit in the first physical unit; determining a decoding parameter corresponding to the first storage unit according to the plurality of identification bits; and decoding data read from the first storage unit according to the decoding parameter.

2. The decoding method of claim 1, wherein the plurality of identification bits reflect a plurality of sensing results of voltage states of the first bit line at different time points in the discharge process of the first bit line.

3. The decoding method of claim 1, wherein the discharge process comprises a discharge process of the first bit line after a pre-charge.

4. The decoding method of claim 1, wherein the at least one read instruction sequence is with at least one time parameter, and the at least one time parameter is used to control a sensing time point of at least one of the plurality of identification bits.

5. The decoding method of claim 4, wherein the plurality of identification bits comprises a first identification bit, the at least one time parameter comprises a first time parameter, and the first time parameter corresponds to a time difference between the sensing time point of the first identification bit and a discharge start time point of the first bit line.

6. The decoding method of claim 4, wherein a total number of the at least one time parameter is positively related to a total number of the plurality of identification bits.

7. The decoding method of claim 1, wherein the step of determining the decoding parameter corresponding to the first storage unit according to the plurality of identification bits comprises: in response to the plurality of identification bits satisfying a first condition, setting the decoding parameter corresponding to the first storage unit as a first value; and in response to the plurality of identification bits satisfying a second condition, setting the decoding parameter corresponding to the first storage unit as a second value, and the first value is different from the second value.

8. A memory storage device, characterized by, comprising: a connection interface unit connected to a host system; a rewritable non-volatile memory module; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to: send at least one read instruction sequence, wherein the at least one read instruction sequence instructs reading a first physical unit in the rewritable non-volatile memory module; receive response data of the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect voltage variations of a first bit line in a discharge process of a first storage unit in the first physical unit; determine a decoding parameter corresponding to the first storage unit according to the plurality of identification bits; and decode data read from the first storage unit according to the decoding parameter. decoding the data read from the first memory cell according to the decoding parameter.

9. The memory storage device of claim 8, wherein the plurality of identification bits reflect a plurality of sensing results of voltage states of the first bit line at different time points in the discharging process of the first bit line.

10. The memory storage device of claim 8, wherein the discharging process comprises a discharging process of the first bit line after a pre-charge.

11. The memory storage device of claim 8, wherein the at least one read instruction sequence is with at least one time parameter, and the at least one time parameter is used to control a sensing time point of at least one of the plurality of identification bits.

12. The memory storage device of claim 11, wherein the plurality of identification bits comprises a first identification bit, the at least one time parameter comprises a first time parameter, and the first time parameter corresponds to a time difference between the sensing time point of the first identification bit and a starting time point of the discharging of the first bit line.

13. The memory storage device of claim 11, wherein a total number of the at least one time parameter is positively related to a total number of the plurality of identification bits.

14. The memory storage device of claim 8, wherein the operation of determining the decoding parameter corresponding to the first memory cell according to the plurality of identification bits by the memory control circuitry comprises: setting the decoding parameter corresponding to the first memory cell to a first value in response to the plurality of identification bits satisfying a first condition; and setting the decoding parameter corresponding to the first memory cell to a second value in response to the plurality of identification bits satisfying a second condition, and the first value is different from the second value. A memory control circuitry for controlling a rewritable non-volatile memory module, the memory control circuitry comprising:

15. A memory control circuit unit, characterized by a host interface connected to a host system; a memory interface connected to the rewritable non-volatile memory module; an error checking and correction circuit; and a memory management circuit connected to the host interface, the memory interface and the error checking and correction circuit, wherein the memory management circuit is configured to: send at least one read instruction sequence, wherein the at least one read instruction sequence instructs to read a first physical cell in the rewritable non-volatile memory module; receive response data of the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect voltage variations of a first bit line in which a first memory cell of the first physical cell is located in a discharging process; and determine a decoding parameter corresponding to the first memory cell according to the plurality of identification bits, and the error checking and correction circuit is configured to decode data read from the first memory cell according to the decoding parameter.

16. The memory control circuitry of claim 15, wherein the plurality of identification bits reflect a plurality of sensing results of voltage states of the first bit line at different time points in the discharging process of the first bit line. ​ 17. The memory control circuit unit of claim 15, wherein the discharging process comprises a discharging process of the first bit line after a pre-charge.

18. The memory control circuit unit of claim 15, wherein the at least one read instruction sequence is with at least one time parameter, and the at least one time parameter is used to control a sensing time point of at least one of the plurality of identification bits.

19. The memory control circuit unit of claim 18, wherein the plurality of identification bits comprises a first identification bit, the at least one time parameter comprises a first time parameter, and the first time parameter corresponds to a time difference between the sensing time point of the first identification bit and a discharging start time point of the first bit line.

20. The memory control circuit unit of claim 18, wherein a total number of the at least one time parameter is positively related to a total number of the plurality of identification bits.

21. The memory control circuit unit of claim 15, wherein the operation of determining, by the memory management circuit, the decoding parameter corresponding to the first memory cell according to the plurality of identification bits comprises: in response to the plurality of identification bits satisfying a first condition, setting the decoding parameter corresponding to the first memory cell as a first value; and in response to the plurality of identification bits satisfying a second condition, setting the decoding parameter corresponding to the first memory cell as a second value, and the first value is different from the second value. ​

Images