A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure. In the semiconductor structure preparation method, during epitaxial growth of source and drain crystal structures in source and drain grooves, epitaxial growth is stopped before different orientation crystal surfaces intersect, then isotropic metal material is used to fill the gap between the different orientation crystal surfaces, and the source and the drain of the all-surrounding gate transistor are formed in the source and drain grooves respectively. Compared with the prior art, the source and the drain are formed by combining the epitaxial thin layer and the filling metal, which not only reduces the existing all-epitaxial semiconductor material source and drain material, but also avoids the defects such as dislocation caused by the intersection of different orientation crystal surfaces, reduces the parasitic resistance in the source and the drain, improves the driving capacity of the device, and reduces the power consumption of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] As CMOS (Complementary Metal Oxide Semiconductor) devices continue to shrink along Moore's Law, mass production has entered the 5-3nm technology node. The use of all-around gate transistors effectively suppresses short-channel effects. To control short-channel effects, forming inner sidewalls on the gate is a necessary process module. Simultaneously, a crucial step involves using pure epitaxial growth of SiGe or Si materials to form the source and drain electrodes. Specifically, SiGe or Si materials are epitaxially grown in the source and drain trenches. Because source and drain epitaxy requires growth from multiple single crystal planes in various directions, and the contact and merging of these planes to form the source and drain materials, defects such as stacking faults can occur at the intersections of different orientations within the source and drain materials. This easily leads to a large number of stacking faults and other defects at the growth junctions of single crystal planes, thereby increasing the parasitic resistance of the source and drain, reducing the device's driving capability, and increasing power consumption. Summary of the Invention

[0003] This invention provides a method for preparing a semiconductor structure and a semiconductor structure that avoids defects such as stacking faults caused by the intersection of crystal planes with different orientations.

[0004] In a first aspect, the present invention provides a method for fabricating a semiconductor structure, the method comprising:

[0005] A substrate is provided, on which an active region trench is formed. Within the active region trench, a channel stack structure for a gate transistor is formed, a sacrificial layer structure is formed between the channel stack structures, a dummy gate structure is formed on the channel stack structure, and sidewalls are formed on the sidewalls of the sacrificial layer structure and the dummy gate structure. The channel stack structure divides the active region trench into a source trench and a drain trench.

[0006] Epitaxial growth of source and drain crystal structures is carried out inside and outside the source trench and drain trench respectively, and epitaxial growth is stopped before the crystal planes with different orientations intersect during the growth of the source and drain crystal structures.

[0007] Isotropic metallic materials are used to fill the gaps between the crystal planes of the source crystal structure and the crystal planes of different orientations in the source crystal structure, and the source and drain of the fully surrounding gate transistor are formed in the source trench and drain trench, respectively.

[0008] In the above scheme, during the epitaxial growth of the source and drain crystal structures inside and outside the source and drain trenches, epitaxial growth is stopped before the crystal planes with different orientations intersect. Then, isotropic metal material is used to fill the gaps between the crystal planes with different orientations, forming the source and drain of the all-around gate transistor in the source and drain trenches, respectively. Compared to existing technologies, forming the source and drain by combining epitaxial thin layers with filling metal not only reduces the amount of existing all-epitaxy semiconductor source and drain material, but also avoids defects such as stacking faults that occur when crystal planes with different orientations intersect, reduces parasitic resistance inside the source and drain, improves the device's driving capability, and reduces device power consumption.

[0009] In one specific embodiment, the epitaxial growth of source and drain crystal structures inside and outside the source and drain trenches, respectively, includes: using depressurized vapor deposition epitaxy (DVA) to epitaxially grow a source crystal structure on the bottom and sidewalls of the source trench, as well as on the surfaces of the channel stack and sidewalls, and stopping the epitaxial growth before the crystal planes of different orientations intersect during the growth of the source crystal structure; and using depressurized vapor deposition epitaxy (DVA) to epitaxially grow a drain crystal structure on the bottom and sidewalls of the drain trench, as well as on the surfaces of the channel stack and sidewalls, and stopping the epitaxial growth before the crystal planes of different orientations intersect during the growth of the drain crystal structure. This facilitates control over the growth and cessation of the epitaxially grown source and drain crystal structures, and also improves the quality of the grown source and drain crystal structures.

[0010] In one specific implementation, the source crystal structure and the drain crystal structure are made of silicon or silicon-germanium materials to improve the quality of the grown source crystal structure and drain crystal structure.

[0011] In one specific implementation, the growth thickness of the source crystal structure and the drain crystal structure is between 1 and 20 nm, thereby improving the quality of the grown source crystal structure and drain crystal structure.

[0012] In one specific embodiment, after epitaxially growing source crystal structures and drain crystal structures inside and outside the source trench and drain trench respectively, the preparation method further includes: epitaxially growing in-situ doping on the surfaces of the source crystal structures and drain crystal structures respectively.

[0013] In one specific implementation, isotropic metallic materials are deposited using atomic layer deposition to fill the gaps between different oriented crystal planes in the source crystal structure. This facilitates filling the gaps between different oriented crystal planes and improves the quality of the final source and drain electrodes.

[0014] In one specific implementation, the isotropic metallic material is cobalt, titanium, tungsten, or titanium nitride, which improves the quality of the final source and drain electrodes.

[0015] In one specific embodiment, after filling the gaps between the source crystal structure and the crystal planes with different orientations in the source crystal structure, the fabrication method further includes: planarizing the isotropic metal material using a chemical mechanical polishing (CMP) planarization process; etching the isotropic metal material to a predetermined depth using a metal etch-back process; growing a first dielectric layer on the surface of the isotropic metal material and chemically mechanically polishing the first dielectric layer until the upper surface of the dummy gate structure is exposed; removing the sacrificial layer structure and the dummy gate structure; and filling the gaps formed after removing the sacrificial layer structure and the dummy gate structure with metal gate material to form the gate of the all-around gate transistor. This facilitates the formation of the gate of the all-around gate transistor.

[0016] In one specific embodiment, the fabrication method further includes: forming a second dielectric layer on a first dielectric layer; and forming a source lead-out structure, a drain lead-out structure, and a gate lead-out structure in the second dielectric layer, wherein the source lead-out structure is electrically connected to the source, the drain lead-out structure is electrically connected to the drain, and the gate lead-out structure is electrically connected to the gate. This protects the gate, source, and drain of the all-around gate transistor.

[0017] Secondly, the present invention also provides a semiconductor structure, which is a semiconductor structure prepared by the preparation method according to any one of claims 1 to 9. During the epitaxial growth of the source and drain crystal structures inside and outside the source and drain trenches, epitaxial growth is stopped before the crystal planes with different orientations intersect. Then, an isotropic metal material is used to fill the gaps between the crystal planes with different orientations, and the source and drain of a fully encircling gate transistor are formed in the source and drain trenches, respectively. Compared with the prior art, forming the source and drain by combining an epitaxial thin layer with a filling metal not only reduces the amount of source and drain material required in existing fully epitaxial semiconductor materials, but also avoids defects such as stacking faults that occur when crystal planes with different orientations intersect, reduces the parasitic resistance inside the source and drain, improves the driving capability of the device, and reduces the power consumption of the device. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0019] Figures 2-8 The images show cross-sectional views of various steps in a semiconductor structure fabrication method provided in this embodiment of the invention.

[0020] Figure label:

[0021] 10 - Substrate; 20 - Channel stacked structure; 21 - Source trench; 211 - Source crystal structure; 212 - Source electrode

[0022] 213 - Source pinout structure; 22 - Drain trench; 221 - Drain crystal structure; 222 - Drain.

[0023] 223 - Drain lead structure; 23 - Gate; 231 - Gate lead structure; 31 - Sacrificial layer structure

[0024] 32-Dummy gate structure; 33-Sidewall; 34-Hard mask; 41-First dielectric layer; 42-Second dielectric layer Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] To facilitate understanding of the semiconductor structure fabrication method provided in the embodiments of the present invention, the application scenario of the fabrication method provided in the embodiments of the present invention will be described first. This fabrication method is applied to the fabrication process of the source and drain of a fully all-around gate transistor. The fabrication method of the semiconductor structure will now be described in detail with reference to the accompanying drawings.

[0027] refer to Figures 1 to 8 The method for preparing the semiconductor structure provided in this embodiment of the invention includes:

[0028] Step 10: Provide a substrate 10, on which an active region trench is formed. Within the active region trench, a channel stack structure 20 that surrounds the gate 23 transistor is formed, a sacrificial layer structure 31 is formed between the channel stack structures 20, a dummy gate structure 32 is formed on the channel stack structure 20, and sidewalls 33 are formed on the sidewalls of the sacrificial layer structure 31 and the dummy gate structure 32; wherein, the channel stack structure 20 divides the active region trench into a source trench 21 and a drain trench 22.

[0029] Step 20: Epitaxially grow source crystal structure 211 and drain crystal structure 221 inside and outside source trench 21 and drain trench 22 respectively, and stop epitaxial growth before the crystal planes of different orientations of source crystal structure 211 and drain crystal structure 221 intersect during the growth process.

[0030] Step 30: Fill the gaps between the crystal planes with different orientations in the source crystal structure 211 with an isotropic metal material, and form the source 212 and drain 222 of the fully surrounding gate 23 transistor in the source trench 21 and drain trench 22, respectively.

[0031] In the above scheme, during the epitaxial growth of source crystal structure 211 and drain crystal structure 221 inside and outside source trench 21 and drain trench 22, epitaxial growth is stopped before the crystal planes with different orientations intersect. Then, isotropic metal material is used to fill the gaps between the crystal planes with different orientations, and the source 212 and drain 222 of the all-around gate 23 transistor are formed in source trench 21 and drain trench 22, respectively. Compared with the prior art, forming the source and drain 222 by combining an epitaxial thin layer with filling metal not only reduces the existing all-epitaxy semiconductor source and drain material, but also avoids defects such as stacking faults that occur when crystal planes with different orientations intersect, reduces the parasitic resistance inside the source and drain 222, improves the device's driving capability, and reduces device power consumption. The following describes each step in detail with reference to the accompanying drawings.

[0032] First, such as Figure 1 and Figure 2 As shown, a substrate 10 is provided, on which an active region trench is formed. A channel stack structure 20, encompassing a gate transistor 23, is formed within the active region trench. The channel stack structure 20 includes multiple channels, which are formed in a spaced-apart stacked manner, as shown in the diagram. Figure 2 The channel stack structure 20 is shown. The material of the channel stack structure 20 can be silicon, silicon germanium, or other materials; no specific limitation is made in this invention. A sacrificial layer structure 31 is also formed between the channel stack structures 20; specifically, the space between two adjacent channels is filled with the sacrificial layer structure 31. A dummy gate structure 32 is also formed above the channel stack structure 20. The dummy gate structure 32 is not a true gate 23, but an intermediate transitional sacrificial structure used in the fabrication of the all-around gate 23 transistor. Furthermore, sidewalls 33 are formed on the sidewalls of the sacrificial layer structure 31 and the dummy gate structure 32, serving as sidewalls to protect the gate 23. (Continue referring to...) Figure 2 The channel stack structure 20 divides the active region trench into a source trench 21 and a drain trench 22. The source trench 21 is for forming the source 212 of a transistor with a fully surrounding gate 23, and the drain trench 22 is for forming the drain 222 of a transistor with a fully surrounding gate 23. Additionally, refer to... Figure 2 Furthermore, a hard mask 34 can be formed above the dummy gate structure 32 to prevent damage to the dummy gate structure 32 during subsequent processing, thereby affecting the quality of the final fabricated gate 23.

[0033] Next, refer to Figure 1 and Figure 3Source crystal structures 211 and drain crystal structures 221 are epitaxially grown inside and outside source trench 21 and drain trench 22, respectively. Epitaxial growth is stopped before the crystal planes of source crystal structures 211 and drain crystal structures 221 with different orientations intersect during their growth process to avoid defects such as stacking faults caused by the intersection of crystal planes with different orientations. Since the materials grown on the bottom wall and sidewalls are different, the crystal plane orientations are different during the epitaxial growth process. By stopping the epitaxial growth before the crystal planes of source crystal structures 211 and drain crystal structures 221 with different orientations intersect, the crystal planes with different orientations do not come into contact, thus preventing the intersection of crystal planes with different orientations and avoiding defects such as stacking faults caused by the intersection of crystal planes with different orientations.

[0034] Specifically, when epitaxially growing the source crystal structure 211 inside and outside the source trench 21, for example, depressurized vapor deposition epitaxy can be used to epitaxially grow the source crystal structure 211 on the bottom and sidewalls of the source trench 21, as well as on the surfaces of the channel stack structure 20 and sidewalls 33. Epitaxial growth is stopped before the crystal planes of different orientations intersect during the growth of the source crystal structure 211. Similarly, when epitaxially growing the drain crystal structure 221 inside and outside the drain trench 22, depressurized vapor deposition epitaxy can also be used to epitaxially grow the drain crystal structure 221 on the bottom and sidewalls of the drain trench 22, as well as on the surfaces of the channel stack structure 20 and sidewalls 33. Epitaxial growth is stopped before the crystal planes of different orientations intersect during the growth of the drain crystal structure 221. This facilitates control over the growth and cessation of the epitaxial growth of the source crystal structure 211 and drain crystal structure 221, and also improves the quality of the grown source crystal structure 211 and drain crystal structure 221.

[0035] The source crystal structure 211 and the drain crystal structure 221 can be made of silicon or silicon-germanium materials to improve the quality of the grown source crystal structure 211 and drain crystal structure 221. The growth thickness of the source crystal structure 211 and drain crystal structure 221 can be between 1 and 20 nm. Specifically, the growth thickness of the source crystal structure 211 and drain crystal structure 221 can be any thickness between 1 and 20 nm, such as 1 nm, 5 nm, 10 nm, 15 nm, and 20 nm, to improve the quality of the grown source crystal structure 211 and drain crystal structure 221.

[0036] Furthermore, after epitaxially growing source crystal structure 211 and drain crystal structure 221 inside and outside source trench 21 and drain trench 22 respectively, the fabrication method may further include: epitaxially growing in-situ doping on the surfaces of source crystal structure 211 and drain crystal structure 221 respectively. The in-situ doping uses different elements depending on the transistor type. Specifically, for PMOS, B is used for in-situ doping; for NMOS, P is used for in-situ doping.

[0037] Next, refer to Figure 1 and Figure 3 An isotropic metal material is used to fill the gaps between the source crystal structure 211 and the crystal planes with different orientations within it. The source 212 and drain 222 of the fully surrounding gate 23 transistor are then formed in the source trench 21 and drain trench 22, respectively. For example, when filling the gaps between the source crystal structure 211 and the crystal planes with different orientations using an isotropic metal material, atomic layer deposition of the isotropic metal material can be used. This facilitates filling the gaps between the crystal planes with different orientations, improving the quality of the finally formed source 212 and drain 222. The isotropic metal material can be cobalt, titanium, tungsten, or titanium nitride, further enhancing the quality of the finally formed source 212 and drain 222.

[0038] refer to Figure 3 After filling the gaps between the source crystal structure 211 and the crystal planes with different orientations in the source crystal structure 211, the fabrication method may further include: planarizing the isotropic metallic material using a chemical mechanical polishing planarization process, for example, such as... Figure 3 As shown, a chemical mechanical polishing planarization process can be used, and polishing can be stopped once the upper surface of the hard mask 34 is exposed. Afterwards, as... Figure 4 As shown, a metal etching process is used to etch the isotropic metal material to a preset depth. Then, as... Figure 5 As shown, a first dielectric layer 41 is grown on the surface of an isotropic metallic material, and the first dielectric layer 41 is chemically and mechanically polished until the upper surface of the dummy gate structure 32 is exposed. Then, as... Figure 6 As shown, the sacrificial layer structure 31 and the dummy gate structure 32 are removed. Then, as... Figure 7 As shown, the gap formed after removing the sacrificial layer structure 31 and the dummy gate structure 32 is filled with metal gate material to form the gate 23 of the all-around gate 23 transistor. This facilitates the formation of the gate 23 of the all-around gate 23 transistor.

[0039] like Figure 8 As shown, the fabrication method may further include: forming a second dielectric layer 42 on the first dielectric layer 41, and then forming a source lead-out structure 213, a drain lead-out structure 223, and a gate lead-out structure 231 in the second dielectric layer 42, wherein the source lead-out structure 213 is electrically connected to the source 212, the drain lead-out structure 223 is electrically connected to the drain 222, and the gate lead-out structure 231 is electrically connected to the gate 23. This protects the gate 23, source 212, and drain 222 of the all-around gate 23 transistor. The source lead-out structure 213, drain lead-out structure 223, and gate lead-out structure 231 may specifically be metal conductive pillar structures, etc.

[0040] In the various embodiments shown above, during the epitaxial growth of the source crystal structure 211 and the drain crystal structure 221 inside and outside the source trench 21 and the drain trench 22, the epitaxial growth is stopped before the crystal planes with different orientations intersect. Then, an isotropic metal material is used to fill the gaps between the crystal planes with different orientations, and the source 212 and drain 222 of the all-around gate 23 transistor are formed in the source trench 21 and the drain trench 22, respectively. Compared with the prior art, forming the source and drain 222 by combining an epitaxial thin layer with a filling metal not only reduces the amount of existing all-epitaxy semiconductor source and drain material, but also avoids defects such as stacking faults that occur when crystal planes with different orientations intersect, reduces the parasitic resistance inside the source and drain 222, improves the device's driving capability, and reduces device power consumption.

[0041] In addition, embodiments of the present invention also provide a semiconductor structure, see reference. Figure 1 and Figure 8 The semiconductor structure is fabricated using any of the above-mentioned methods. During the epitaxial growth of the source crystal structure 211 and drain crystal structure 221 inside and outside the source trench 21 and drain trench 22, epitaxial growth is stopped before the crystal planes with different orientations intersect. Then, isotropic metal material is used to fill the gaps between the crystal planes with different orientations, and the source 212 and drain 222 of the fully surrounding gate 23 transistor are formed in the source trench 21 and drain trench 22, respectively. Compared with existing technologies, forming the source and drain 222 by combining an epitaxial thin layer with filling metal not only reduces the amount of existing all-epitaxy semiconductor source and drain material, but also avoids defects such as stacking faults that occur when crystal planes with different orientations intersect, reduces the parasitic resistance inside the source and drain 222, improves the device's driving capability, and reduces device power consumption.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which an active region trench is formed. Within the active region trench, a channel stack structure for a gate transistor is formed, a sacrificial layer structure is formed between the channel stack structures, a dummy gate structure is formed on the channel stack structures, and sidewalls are formed on the sidewalls of the sacrificial layer structure and the dummy gate structure. The channel stack structure divides the active region trench into a source trench and a drain trench. Source crystal structures and drain crystal structures are epitaxially grown inside and outside the source trench and drain trench, respectively, and the epitaxial growth is stopped before the crystal planes with different orientations intersect during the growth of the source crystal structure and drain crystal structure; the material of the source crystal structure and drain crystal structure is silicon or silicon-germanium material. An isotropic metallic material is used to fill the gaps between crystal planes with different orientations in the source and drain crystal structures, and the source and drain of the all-around gate transistor are formed in the source trench and drain trench, respectively.

2. The preparation method according to claim 1, characterized in that, The epitaxial growth of source and drain crystal structures inside and outside the source and drain trenches, respectively, includes: A depressurized vapor deposition epitaxial growth technique is used to epitaxially grow a source crystal structure on the bottom and sidewalls of the source trench, as well as on the surface of the trench stack structure and the sidewalls; and the epitaxial growth is stopped before the crystal planes of different orientations intersect during the growth process of the source crystal structure. A drain crystal structure is epitaxially grown on the bottom and sidewalls of the drain trench, as well as on the surface of the channel stack and the sidewalls, using depressurized vapor deposition epitaxy. The epitaxial growth is stopped before the crystal planes of different orientations intersect during the growth of the drain crystal structure.

3. The preparation method according to claim 1, characterized in that, The growth thickness of the source and drain crystal structures is between 1 and 20 nm.

4. The preparation method according to claim 2, characterized in that, After epitaxially growing source and drain crystal structures inside and outside the source and drain trenches, respectively, the fabrication method further includes: In-situ doping was performed on the surface of the source and drain crystal structures, respectively.

5. The preparation method according to claim 1, characterized in that, The isotropic metallic material is deposited using atomic layer deposition to fill the gaps between the source crystal structure and the crystal planes with different orientations in the source crystal structure.

6. The preparation method according to claim 5, characterized in that, The isotropic metallic material is cobalt, titanium, tungsten, or titanium nitride.

7. The preparation method according to claim 1, characterized in that, After filling the gaps between crystal planes with different orientations in the source and drain crystal structures, the fabrication method further includes: The isotropic metallic material is planarized using a chemical mechanical polishing planarization process. The isotropic metal material is etched to a preset depth using a metal etching process. A first dielectric layer is grown on the surface of the isotropic metallic material, and the first dielectric layer is chemically and mechanically polished until the upper surface of the dummy gate structure is exposed. Remove the sacrificial layer structure and the dummy gate structure; The gap formed after removing the sacrificial layer structure and the dummy gate structure is filled with metal gate material to form the gate of the all-around gate transistor.

8. The preparation method according to claim 7, characterized in that, Also includes: A second dielectric layer is formed on the first dielectric layer; A source lead-out structure, a drain lead-out structure, and a gate lead-out structure are formed in the second dielectric layer, respectively; wherein the source lead-out structure is electrically connected to the source, the drain lead-out structure is electrically connected to the drain, and the gate lead-out structure is electrically connected to the gate.

9. A semiconductor structure, characterized in that, include: Semiconductor structures prepared by the preparation method according to any one of claims 1 to 8.

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