Array substrate and display panel

Abstract

The embodiment of the present application provides an array substrate and a display panel. The array substrate comprises a substrate, an active layer and a source / drain metal layer. The active layer comprises a crystalline oxide layer and an amorphous oxide layer which are arranged in a stack, and a rare earth element which is arranged in at least one of the crystalline oxide layer or the amorphous oxide layer. By arranging the crystalline oxide and the rare earth element in the active layer, the crystalline oxide layer can effectively resist plasma bombardment and acidic corrosion, thereby reducing defects of the active layer, and meanwhile, the rare earth element in the active layer can form a recombination center of photo-generated carriers, thereby inhibiting photo-generated current, improving stability of the thin film transistor, and improving comprehensive performance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display panel design and manufacturing technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the continuous development of display panel manufacturing technology, people have put forward higher requirements for the various performance characteristics of display panels and devices.

[0003] In existing technologies, the fabrication of a display panel requires the formation of a corresponding array substrate and multiple thin-film transistors (TFTs) within that substrate to ensure the normal operation of the display panel. Common TFT structures typically include functional layers such as a source, drain, gate, and active layer. When fabricating these functional layers, particularly the active layer, a high mobility and relatively low leakage current compared to low-temperature polysilicon are typically required. Currently, indium gallium zinc oxide (IGGaZn) is a commonly used active layer material. However, the single IGGaZn material is no longer sufficient to further improve the carrier mobility within the material, resulting in the TFT performance failing to meet the requirements of high-performance devices and thus reducing the overall performance of the display panel.

[0004] In summary, the carrier mobility in the active layer of the array substrate prepared by the prior art is not ideal, which does not meet the requirements of high-performance devices and is not conducive to further improving the overall performance of the display panel. Summary of the Invention

[0005] This invention provides an array substrate and a display panel. This effectively addresses the problem that the carrier mobility in the array substrate of existing display panels is not ideal and cannot meet the requirements of high-performance devices.

[0006] To address the aforementioned technical problems, the present invention provides an array substrate, the array substrate comprising:

[0007] Substrate;

[0008] An active layer disposed on the substrate; and,

[0009] A source / drain metal layer disposed on the active layer and electrically connected to the active layer;

[0010] The active layer includes a crystalline oxide layer, an amorphous oxide layer disposed on one side of the crystalline oxide layer, and rare earth elements, wherein the rare earth elements are disposed at least in the crystalline oxide layer or the amorphous oxide layer.

[0011] According to one embodiment of the present invention, the content of rare earth elements in the active layer is 0.01%-0.7%.

[0012] According to one embodiment of the present invention, the rare earth element includes any one of ytterbium, europium, praseodymium, terbium, cerium, dysprosium, and tin.

[0013] According to one embodiment of the present invention, the array substrate further includes a gate, a gate insulating layer, and a passivation layer, wherein the gate insulating layer is disposed on the active layer, and a portion of the passivation layer is disposed on the active layer and covers the gate;

[0014] The crystalline oxide layer is disposed on the side close to the source / drain metal layer, and the source / drain metal layer is disposed on the passivation layer and electrically connected to the crystalline oxide layer through a via.

[0015] According to one embodiment of the present invention, the height between the gate and the active layer is the same as the height between the source / drain metal layer and the active layer.

[0016] According to one embodiment of the present invention, the source / drain metal layer is at least partially disposed on the surface of the active layer and is electrically connected to the active layer.

[0017] According to one embodiment of the present invention, the sidewalls of the crystalline oxide layer and the amorphous oxide layer are respectively attached to the source / drain metal layer.

[0018] According to one embodiment of the present invention, the rare earth element is disposed in both the crystalline oxide layer and the amorphous oxide layer;

[0019] The content of rare earth elements in the crystalline oxide layer is greater than the content of rare earth elements in the amorphous oxide layer.

[0020] According to one embodiment of the present invention, the content of rare earth elements in the amorphous oxide layer is set to 0.01%-0.1%, and the content of rare earth elements in the crystalline oxide layer is set to 0.3%-0.7%.

[0021] According to a second aspect of the present invention, a display panel is also provided, the display panel including the array substrate of the present application.

[0022] The beneficial effects of this invention's embodiments: Compared to the prior art, this invention provides an array substrate and a display panel. The array substrate includes a substrate, an active layer, and source / drain metal layers. The active layer includes a stacked crystalline oxide layer, an amorphous oxide layer, and rare earth elements, with the rare earth elements at least disposed within either the crystalline oxide or amorphous oxide layer. In this embodiment, the active layer includes crystalline oxide and rare earth elements. During the fabrication of the array substrate, the crystalline oxide layer in the active layer can effectively resist plasma bombardment and acid corrosion, thereby reducing defects in the active layer. Simultaneously, the rare earth elements within the active layer can form recombination centers for photogenerated carriers, thereby suppressing photocurrent and improving the stability of thin-film transistors, effectively enhancing the overall performance of the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the film layer structure of an array substrate provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the film structure of the second array substrate provided in the embodiments of this application;

[0026] Figure 3 This is a schematic diagram of the film structure of the third array substrate provided in the embodiments of this application. Detailed Implementation

[0027] The following description, in conjunction with the accompanying drawings of the embodiments of the present invention, provides different implementation methods or examples to realize different structures of the present invention. To simplify the present invention, the components and arrangements of specific examples are described below. Furthermore, the various specific processes and materials provided in the present invention are examples that those skilled in the art will recognize for the application of other processes. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0029] With the continuous development of array substrate and display panel manufacturing technology, people have put forward higher requirements for the performance and display effect of display panels.

[0030] In the fabrication of an array substrate, multiple thin-film transistors (TFTs) are typically formed within the substrate. The active layer and other functional layers within the TFT significantly influence its performance. Current fabrication processes are complex for the active layer, resulting in low carrier mobility and suboptimal performance of the TFT devices, failing to meet user requirements.

[0031] In this embodiment of the application, an array substrate and a display panel are provided. The active layer in the array substrate includes a crystalline oxide layer and rare earth elements, thereby effectively improving the overall performance of the display panel.

[0032] like Figure 1 As shown, Figure 1 This is a schematic diagram of the film layer structure of an array substrate provided in an embodiment of this application. Thin-film transistor devices are disposed within this array substrate. Specifically, the array substrate includes a substrate 101, a buffer layer 102, a passivation layer 103, an insulating layer 104, a light-shielding layer 105, and various functional film layers.

[0033] Specifically, the thin-film transistor further includes an active layer 11, a gate 108, a source / drain metal layer 12, and a gate insulating layer 109. Specifically, when setting the above-mentioned film layer structure, the light-shielding layer 105 is disposed on the substrate 101, and the buffer layer 102 is disposed on the substrate 101, with the buffer layer 102 completely covering the light-shielding layer 105. In this embodiment, the light-shielding layer 105 can be configured as a metal light-shielding layer, thereby protecting the functional layers within the thin-film transistor on the light-shielding layer 105.

[0034] Furthermore, in this embodiment, the active layer 11 is disposed on the buffer layer 102, and the gate insulating layer 109 is disposed on the active layer 11, and the gate 108 is disposed on the gate insulating layer 109.

[0035] Meanwhile, the passivation layer 103 is at least partially disposed on the active layer 11, and the passivation layer 103 completely covers the gate 108.

[0036] Furthermore, the active layer 11 also includes a first contact area 311 and a second contact area 312, which are respectively disposed at the two side edges of the active layer 11. At the same time, in the corresponding areas of the first contact area 311 and the second contact area 312, the passivation layer 103 directly contacts and adheres to the upper surface of the active layer 11.

[0037] In this embodiment, a source / drain metal layer 12 is further disposed on the passivation layer 103. The source / drain metal layer 12 includes a source 107 and a drain 106 as an example. The source 107 is disposed at a corresponding position above the first contact region 311, and the drain 106 is disposed at a corresponding position above the second contact region 312. A via is also disposed on the passivation layer 103 at the corresponding positions of the source 107 and drain 106. The source 107 and drain 106 are electrically connected to the active layer 11 through the corresponding vias, forming the thin-film transistor structure of this embodiment.

[0038] In this embodiment of the application, when the gate 108 and the source / drain metal layer 12 are provided, the height between the gate 108 and the upper surface of the active layer 11 is the same as the height between the source / drain metal layer 12 and the upper surface of the active layer 11.

[0039] Meanwhile, to further improve the overall performance of the aforementioned thin-film transistor, the active layer 11 includes two different functional layers. Specifically, the active layer 11 includes a crystalline oxide layer 112 and an amorphous oxide layer 111. Specifically, the crystalline oxide layer 112 and the amorphous oxide layer 111 are stacked. Optionally, the crystalline oxide layer 112 is disposed directly above the amorphous oxide layer 111, and the amorphous oxide layer 111 is disposed on the buffer layer 102.

[0040] In this embodiment, the length of the crystalline oxide layer 112 can be the same as the length of the amorphous oxide layer 111, and the film thickness of the crystalline oxide layer 112 can be the same as the film thickness of the amorphous oxide layer 111. Optionally, the film thickness of both the crystalline oxide layer 112 and the amorphous oxide layer 111 can be set to 100-400 angstroms. For example, the thicknesses of the two different oxide layers can be set to 150 angstroms, 200 angstroms, and 300 angstroms, or different thicknesses can be set according to different products; these details will not be elaborated here.

[0041] Furthermore, the materials of the crystalline oxide layer 112 and the amorphous oxide layer 111 can be configured as metal oxide layers. Optionally, the metal oxide layer includes one or more of indium gallium zinc oxide, indium gallium oxide, indium oxide, and indium zinc oxide. When preparing the crystalline oxide layer 112 in the embodiments of this application, a metal oxide layer is first deposited, and after the deposition is completed, it is subjected to a crystallization process.

[0042] Specifically, the crystallization of the metal oxide layer can be achieved through heat treatment or laser annealing. When performing heat treatment annealing, the temperature can be between 100℃ and 600℃, with an optional range of 350℃ to 550℃, such as 400℃ or 500℃. When performing laser annealing, the entire metal oxide layer can be annealed directly, or annealed in layers. Each annealing process causes crystallization reactions in different thicknesses of the metal oxide layer, ultimately resulting in complete crystallization of the entire metal oxide layer.

[0043] In this embodiment, the crystalline oxide layer 112 is disposed above the amorphous oxide layer 111. Thus, when the active layer is doped, the crystalline oxide layer 112 can better resist the bombardment of plasma in the subsequent process and the corrosion of acidic solutions, thereby better protecting the active layer and improving the performance of the thin film transistor.

[0044] Furthermore, in this embodiment, when the active layer 11 is provided, rare earth elements are also provided within the active layer 11. Specifically, the rare earth elements are provided at least within the crystalline oxide layer 112 or the amorphous oxide layer 111. Optionally, the rare earth elements may be provided only within the crystalline oxide layer 112 or the amorphous oxide layer 111, or the rare earth elements may be provided simultaneously within both the crystalline oxide layer 112 and the amorphous oxide layer 111. In the following embodiments, the rare earth elements being provided within both the crystalline oxide layer 112 and the amorphous oxide layer 111 will be used as an example for explanation.

[0045] Specifically, the rare earth element may include lanthanides. Optionally, the rare earth element may be one or two of ytterbium, europium, praseodymium, terbium, cerium, dysprosium, and tin. When incorporating the above rare earth element, it may be doped into the crystalline oxide layer 112 and the amorphous oxide layer 111.

[0046] In this embodiment, the content of the rare earth element can be set to 0.01%-0.7%. For example, the mass percentage content of the rare earth element can be set to 0.5% or 0.6%, or it can be set according to different products.

[0047] See details Figure 1 In this embodiment, the rare earth element content in the crystalline oxide layer 112 and the amorphous oxide layer 111 can be set to different contents. The crystalline oxide layer 112 is selected from metal oxide layers with high mobility, and a certain amount of rare earth elements is provided within the metal oxide layer. Optionally, the rare earth element content in the crystalline oxide layer 112 can be greater than the rare earth element content in the amorphous oxide layer 111. Specifically, the rare earth element content in the amorphous oxide layer 111 is 0.01%-0.1%, such as 0.05% or 0.08%. Meanwhile, the rare earth element content in the crystalline oxide layer 112 is 0.3%-0.7%, such as 0.5% or 0.6%.

[0048] In this embodiment, by setting different rare earth element contents in different oxide layers, photogenerated carrier recombination centers are formed in different oxide layers, thereby suppressing photogenerated current, improving the performance of the active layer, and improving the overall performance of the display panel.

[0049] like Figure 2 As shown, Figure 2 This is a schematic diagram of the film structure of a second array substrate provided in an embodiment of this application. (Combined with...) Figure 1 In the film structure of this application embodiment, the array substrate includes a substrate 101, a buffer layer 102, a light-shielding layer 105, a passivation layer 103, a source electrode 107, a drain electrode 106, a crystalline oxide layer 112, and an amorphous oxide layer 111.

[0050] In this embodiment, the thin-film transistors disposed within the array substrate are etch-barrier type thin-film transistors. Specifically, the array substrate further includes a barrier layer 222.

[0051] Specifically, an amorphous oxide layer 111 is disposed on a buffer layer 102, a crystalline oxide layer 112 is disposed on an amorphous oxide layer 111, and a barrier layer 222 is disposed on a crystalline oxide layer 112.

[0052] Meanwhile, the source / drain metal layer is at least partially disposed on the surface of the active layer and electrically connected to the active layer. Specifically, the sidewalls of the crystalline oxide layer 112 and the amorphous oxide layer 111 are respectively attached to and electrically connected to the source electrode 107 and the drain electrode 106.

[0053] In this embodiment of the application, in setting Figure 2 In the etch-blocking thin-film transistor structure provided, at least one of the crystalline oxide layer 112 and the amorphous oxide layer 111 contains rare earth elements, and the crystalline oxide layer 112 and the amorphous oxide layer 111 can be configured according to the parameters described above, which will not be repeated here. By incorporating rare earth elements in the crystalline oxide layer 112 or the amorphous oxide layer 111, the overall performance of the active layer and the display panel is effectively improved.

[0054] like Figure 3 As shown, Figure 3 This is a schematic diagram of the film layer structure of the third array substrate provided in an embodiment of this application. (Combined with...) Figures 1-2 The thin-film transistor provided in this embodiment is a back-channel etched thin-film transistor with a film layer structure.

[0055] Specifically, the array substrate includes a substrate 101, a buffer layer 102, a passivation layer 103, a crystalline oxide layer 112, an amorphous oxide layer 111, a source 107, a drain 106, and a gate.

[0056] In this embodiment of the application, when setting the above-mentioned film layers, the buffer layer 102 is disposed on the substrate 101, the amorphous oxide layer 111 is disposed on the buffer layer 102, the crystalline oxide layer 112 is disposed on the amorphous oxide layer 111, and the source electrode 107 and the drain electrode 106 are both disposed on the crystalline oxide layer 112.

[0057] In this embodiment, the source electrode 107 and the drain electrode 106 are located at the two side edges of the crystalline oxide layer 112. Both the source electrode 107 and the drain electrode 106 are electrically connected to the crystalline oxide layer 112.

[0058] In this embodiment, rare earth elements are provided within the crystalline oxide layer 112, and the content of these rare earth elements can be referenced. Figure 1 as well as Figure 2The parameters are set as described above, which will not be elaborated further here. In this embodiment, since the active layer includes a crystalline oxide layer 112, and the crystalline oxide layer 112 is disposed on the amorphous oxide layer 111, in subsequent processes, after the crystalline oxide layer 112 crystallizes, more compact metal-oxide chemical bonds are formed within the crystalline oxide layer 112, resulting in fewer defects in the film layer, thereby better resisting plasma bombardment and acidic liquid corrosion. This ensures the performance of the active layer and improves the stability of the device.

[0059] Meanwhile, rare earth elements are also incorporated within these different oxide layers. These rare earth elements can further suppress photocurrent and enhance the photoresistance of the oxide layers. Therefore, in this embodiment, the advantages of both rare earth-doped high-mobility oxide layers and devices in crystalline oxide systems can be combined simultaneously, thereby ensuring that the thin-film transistor has higher performance.

[0060] In this embodiment, the array substrate and the corresponding display panel and display device can be any product or component with display function and thin film transistor driving function, or with touch function, such as mobile phone, computer, electronic paper, monitor, etc., and there is no specific limitation on its specific type.

[0061] In summary, the array substrate and display panel provided by the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solution and core ideas of the present invention. Although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer disposed on the substrate; as well as, A source / drain metal layer disposed on the active layer and electrically connected to the active layer; The active layer includes a crystalline oxide layer, an amorphous oxide layer, and rare earth elements. The crystalline oxide layer is disposed on the side close to the source / drain metal layer, and the rare earth elements are disposed in both the crystalline oxide layer and the amorphous oxide layer. The mass percentage content of the rare earth element in the crystalline oxide layer is set to 0.3%-0.7%, and the mass percentage content of the rare earth element in the amorphous oxide layer is set to 0.01%-0.1%.

2. The array substrate according to claim 1, characterized in that, The rare earth elements include any one of ytterbium, europium, praseodymium, terbium, cerium, dysprosium, and tin.

3. The array substrate according to claim 1, characterized in that, The array substrate further includes a gate, a gate insulating layer, and a passivation layer. The gate insulating layer is disposed on the active layer, and a portion of the passivation layer is disposed on the active layer and covers the gate. The source / drain metal layer is disposed on the passivation layer and electrically connected to the crystalline oxide layer through a via.

4. The array substrate according to claim 3, characterized in that, The height between the gate and the active layer is the same as the height between the source / drain metal layer and the active layer.

5. The array substrate according to claim 1, characterized in that, The source / drain metal layer is at least partially disposed on the surface of the active layer and is electrically connected to the active layer.

6. The array substrate according to claim 5, characterized in that, The sidewalls of both the crystalline oxide layer and the amorphous oxide layer are correspondingly attached to the source / drain metal layer.

7. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1-6.

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