Fault ride-through system and method based on dual-synchronous unified virtual oscillation controller

Abstract

The application relates to the technical field of network-constructing inverters and is a kind of fault ride-through system and method based on a double-synchronous unified virtual oscillation controller, which comprises a double-sequence current reference generator for obtaining power reference values when a fault is detected, and combining the power reference values to determine positive and negative sequence current reference values; a double-sequence vector limiter connected with the double-sequence current reference generator, which realizes overcurrent limitation under symmetrical and asymmetrical faults and outputs limited positive and negative sequence saturation current reference values; a positive sequence space vector oscillator and a negative sequence space vector oscillator, both of which are connected with the double-sequence vector limiter and realize double-sequence synchronous operation. The application can inhibit overcurrent under symmetrical or asymmetrical fault conditions, and combines enhanced synchronization capability with fast overcurrent limitation to provide voltage support and unbalanced relief fault ride-through without switching to a backup controller or a current source type control.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of grid-forming inverters, and is a fault ride-through system and method based on a double-synchronous unified virtual oscillation controller. BACKGROUND

[0002] In recent years, with the wide popularity of power electronic inverters, the proportion of distributed power sources in power distribution systems gradually increases, and grid-forming inverters become a key technology for large-scale new energy high penetration into power systems. New energy will change from additional-passive-following-network access type to main-subjective-active-grid support type, provide support capability for grid voltage and frequency, and become the main power supply. According to the "Guidelines for Safety and Stability of Power Systems", new energy stations are required to have power angle stability, frequency stability, voltage stability, transient overvoltage and multi-frequency oscillation, etc. The voltage stability involves the fault ride-through problem, which has a relatively mature method in the following-network access type, but the method for limiting overcurrent in the grid support type still needs to be solved.

[0003] The external characteristic of the grid-forming inverter is equivalent to a voltage source, which can construct the grid voltage in transient response and keep the internal potential constant, so it has outstanding grid support capability, such as voltage and frequency regulation and inertia support. However, the defect is that under fault conditions, transient overcurrent easily occurs, which causes hardware tripping to avoid damage to the converter, further threatening the safe operation of the regional power grid. So far, the ride-through of symmetric and asymmetric faults is still one of the key challenges of grid-forming inverters.

[0004] The early research on grid-forming inverters mainly focuses on virtual synchronous control technology. The work on fault ride-through under low voltage focuses on balancing power control or suppressing active power oscillation, such as switching control strategy and increasing virtual impedance. However, in the context of weak grid, the current research on grid-forming inverters mainly takes nonlinear time-domain controllers, such as virtual oscillator control (VOC) and dispatchable virtual oscillator control (dVOC) as the starting point. The design purpose is to ensure almost global synchronization in a network of N converters with zero inertia. Compared with droop control and virtual synchronous generator control, the synchronization speed of nonlinear time-domain controllers is greatly improved. For grid-forming inverters based on oscillator control, symmetric fault ride-through can be achieved without switching controller switches or adding dynamic virtual impedance. However, there is currently no compatible research on asymmetric fault ride-through methods. SUMMARY

[0005] The application provides a fault ride-through system and method based on a double-synchronous unified virtual oscillation controller, which overcomes the defects of the prior art and effectively solves the problem that the existing grid-connected inverter cannot suppress overcurrent during symmetric and asymmetric faults.

[0006] One of the technical solutions of the application is achieved by the following measures: a fault ride-through system based on a double-synchronous unified virtual oscillation controller, comprising a double-synchronous unified virtual oscillation controller, an active resistance and a virtual impedance; the double-synchronous unified virtual oscillation controller comprises a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator;

[0007] The double-sequence current reference generator is used to obtain a power reference value when a fault is detected, and to determine positive and negative sequence current reference values in combination with the power reference value;

[0008] The double-sequence vector limiter is connected with the double-sequence current reference generator, and overcurrent limitation under symmetric and asymmetric faults is realized, and the positive and negative sequence saturated current reference values after limitation are output;

[0009] The positive-sequence space vector oscillator and the negative-sequence space vector oscillator are both connected with the double-sequence vector limiter, and double-sequence synchronous operation is realized;

[0010] The active resistance and the virtual impedance are combined and used for fast overcurrent limitation.

[0011] The following is a further optimization or / and improvement of the above technical solutions of the application:

[0012] The double-sequence current reference generator calculates the positive and negative sequence current reference values by using the following formula:

[0013] The double-sequence current reference value calculation formulae are respectively:

[0014] i 0+ = i α0+ + ji β0+

[0015] i 0- = i α0- + ji β0-

[0016] Wherein, the positive and negative sequence current calculation formulae in the alpha-beta stationary coordinate system are respectively:

[0017]

[0018]

[0019]

[0020]

[0021] where D p = k p+ ||v + | 2 + k p- ||v - | 2 , D q = k q+ ||v + | 2 + k q- ||v - | 2 .

[0022] The above double-sequence vector limiter limits overcurrent under symmetrical and asymmetrical faults, that is, the current reference vector is limited below the maximum value Im allowed by the inverter hardware, where the positive and negative sequence saturated current reference values after output limiting include:

[0023] The current reference value is limited to:

[0024] i 0 = {[i a0 i b0 i c0 ] T : max{ I a0 , I b0 , I c0} ≤ I m}

[0025] where the three-phase unsaturated current reference value is represented as:

[0026] I x0 = {[||i 0+ | 2 + ||i 0- | 2 + 2(ξ1cos2γ-ξ2sin2γ)} / 2] 1 / 2

[0027] where ξ1 = (i α0+ i α0- - i β0+ i β0- ), ξ2 = (i β0+ i α0- + i α0+ i β0- ), γ = {0, -2π / 3, 2π / 3}, x takes a, b, c, and I max= max{I a0 ,I b0 ,I c0};

[0028] The positive and negative sequence saturation current reference values are obtained in combination with the limited current reference value:

[0029] [ i 0+ i 0- ] T = k sat [i 0+ i 0- ] T ;k sat = I m / I max .

[0030] The above positive sequence space vector oscillator realizes positive sequence synchronous operation by using the following dynamic equation:

[0031]

[0032] Or / and, the negative sequence space vector oscillator realizes negative sequence synchronous operation by using the following dynamic equation:

[0033]

[0034] The above also includes a power reference value setting unit, which sets the power reference value set under the pre-fault condition.

[0035] The second technical scheme of the application is realized by the following measures: a use method of a fault ride-through system based on a double-synchronous unified virtual oscillation controller, comprising:

[0036] Obtaining the power reference value after detecting the fault;

[0037] The double-sequence current reference generator determines the positive and negative sequence current reference values in combination with the power reference value after detecting the fault, and an unbalance coefficient UF reflecting the voltage unbalance degree, so as to prepare for overcurrent suppression and unbalanced voltage compensation;

[0038] The double-sequence vector limiter realizes overcurrent limitation under symmetric and asymmetric faults, and outputs the limited positive and negative sequence saturation current reference values to the positive sequence space vector oscillator and the negative sequence space vector oscillator;

[0039] The positive sequence space vector oscillator and the negative sequence space vector oscillator receive the limited positive and negative sequence saturation current reference values, and realize double-sequence synchronous operation by using the dynamic equation of internal control.

[0040] This invention utilizes a dual-sequence current reference generator, a dual-sequence vector limiter, a positive-sequence space vector oscillator, and a negative-sequence space vector oscillator to construct a fault ride-through system based on a dual-synchronous unified virtual oscillation controller. This enables overcurrent suppression under both symmetrical and asymmetrical fault conditions, and combines enhanced synchronization capability with rapid overcurrent limiting to provide voltage support and imbalance mitigation fault ride-through without needing to switch to a backup controller or current source control. Attached Figure Description

[0041] Appendix Figure 1 This is a schematic diagram of the system structure of the present invention.

[0042] Appendix Figure 2 This is an explanatory diagram illustrating the generation mode conversion signal xr from the controller fault signal xf of the present invention.

[0043] Appendix Figure 3 This is a schematic diagram of the power synchronization principle of the positive sequence space vector oscillator of the present invention.

[0044] Appendix Figure 4 This is a schematic diagram of the power synchronization principle of the negative sequence space vector oscillator of the present invention.

[0045] Appendix Figure 5 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0046] The present invention is not limited to the following embodiments, and specific implementation methods can be determined according to the technical solutions and actual conditions of the present invention.

[0047] The present invention will be further described below with reference to embodiments and accompanying drawings:

[0048] Example 1: As shown in the attached document Figure 1 As shown, this embodiment of the invention discloses a fault ride-through system based on a dual-synchronous unified virtual oscillation controller, including a dual-synchronous unified virtual oscillation controller, an active resistor, and a virtual impedance; the dual-synchronous unified virtual oscillation controller includes a dual-sequence current reference generator, a dual-sequence vector limiter, a positive-sequence space vector oscillator, and a negative-sequence space vector oscillator;

[0049] A dual-sequence current reference generator is used to obtain a power reference value when a fault is detected, and to determine the positive and negative sequence current reference values ​​in combination with the power reference value.

[0050] The dual-sequence vector limiter is connected to the dual-sequence current reference generator to realize overcurrent limiting under symmetrical and asymmetrical faults, and outputs the limited positive and negative sequence saturation current reference values.

[0051] Both the positive sequence space vector oscillator and the negative sequence space vector oscillator are connected to the dual sequence vector limiter to achieve dual sequence synchronous operation;

[0052] The active resistance and the virtual impedance are combined to quickly limit overcurrent.

[0053] The power reference value setting unit is further included to set the power reference value when the fault is detected.

[0054] The application utilizes a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator to construct a fault ride-through system based on a double-synchronous unified virtual oscillation controller, so that overcurrent can be inhibited under symmetric or asymmetric fault conditions, and the enhanced synchronization capability is combined with fast overcurrent limitation to provide fault ride-through of voltage support and unbalance mitigation without switching to a backup controller or a current source type control.

[0055] Embodiment 2: as shown in the accompanying Figures 1 to 4 The application discloses a fault ride-through system based on a double-synchronous unified virtual oscillation controller, including a double-synchronous unified virtual oscillation controller, an active resistance and a virtual impedance; the double-synchronous unified virtual oscillation controller includes a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator.

[0056] (1) The double-sequence current reference generator is used to obtain a power reference value when a fault is detected, and the positive and negative sequence current reference values are determined in combination with the power reference value.

[0057] The double-sequence current reference generator is used to calculate the current reference value in the static reference frame, and for a given set of active power reference value P0 and reactive power reference value Q0, the positive and negative sequence reference current values fed into the double-sequence vector limiter are calculated through the dynamic equation of the internal positive and negative sequence voltage of the double-sequence current reference generator, compared with symmetric fault ride-through, the power flow in the two sequences of asymmetric fault ride-through operation is coupled with each other, so that the current reference value calculation is more complex, and the double-sequence current reference value calculation formula is respectively:

[0058] i 0+ =i α0+ +ji β0+

[0059] i 0- =i α0- +ji β0-

[0060] Further, the positive and negative sequence current calculation formula in the αβ static coordinate system is respectively:

[0061]

[0062]

[0063]

[0064]

[0065] where D p = k p+ ||v + ||v 2 +k p- ||v - ||v 2 , D q = k q+ ||v + ||v 2 +k q- ||v - ||v 2 , by properly selecting k p+ , k p- , k q+ and k q- , different control objectives can be achieved, where (.)|| represents the Euclidean norm, and the operation form is

[0066] The above-mentioned power reference value (active power reference value and reactive power reference value) obtained when a fault is detected is the power reference value set before the fault, and once the fault is detected, the reactive power reference value Q0 is set to

[0067] The dynamic equation of the above-mentioned double-sequence current reference generator internal positive and negative sequence voltage can calculate the positive and negative sequence reference current values fed into the double-sequence vector limiter, and the unbalance coefficient UF reflecting the voltage unbalance degree, so as to prepare for the next overcurrent suppression and unbalanced voltage compensation.

[0068] (2) The double-sequence vector limiter is connected with the double-sequence current reference generator, and overcurrent limitation under symmetrical and asymmetrical faults is realized, and the limited positive and negative sequence saturation current reference values are outputted;

[0069] The above-mentioned double-sequence vector limiter is used to limit the current reference vector below the maximum value Im allowed by the inverter hardware, so as to prevent overcurrent outputted by the inverter during the fault, and the current reference value after the double-sequence vector limiter will be limited to:

[0070] i 0 = {[i a0 i b0 i c0 ] T :max{ I a0, I b0 , I c0}≤I m}

[0071] wherein the three-phase unsaturated current reference value is expressed as:

[0072] I x0 =[{||i 0+ || 2 +||i 0- || 2 +2(ξ1cos2γ-ξ2sin2γ)} / 2] 1 / 2

[0073] wherein ξ1=(i α0+ i α0- -i β0+ i β0- ), ξ2=(i β0+ i α0- +i α0+ i β0- ), γ={0,-2π / 3,2π / 3}, x takes a, b, c.

[0074] Next, the positive and negative sequence saturated current reference values are obtained:

[0075] [ i 0+ i 0- ] T =k sat [i 0+ i 0- ] T ; k sat =I m / I max

[0076] wherein I m =max{I a0 ,I b0 ,I c0}.

[0077] Figure 1 The double-sequence vector limiter shown is applicable under both symmetric and asymmetric fault conditions, and the imbalance degree of the grid-connected point voltage is characterized by the imbalance factor (UF), which is defined as UF=||v g- || / ||v g+ ||, and Vg is the grid-side voltage. When the grid voltage is balanced or under symmetric fault, the negative sequence current reference value i 0- =0 of the controller. Once overcurrent is detected in any phase or the voltage imbalance degree exceeds the threshold value (UF>K UF), the fault signal is locked, i.e. x f = 1, when the positive sequence voltage returns to the specified range and UF is lower than the threshold (UF < K UF ), the fault is cleared, i.e. x f = 0. In addition, by appending a falling slope after the fault signal x f , a mode switching signal x r is generated, and the slope-down time t F provides a smooth transition period when the fault is cleared.

[0078] (3) The positive sequence space vector oscillator and the negative sequence space vector oscillator are connected with the double sequence vector limiter to realize double sequence synchronous operation;

[0079] The above positive sequence space vector oscillator is used for synchronization when new energy is connected to the grid, the grid is at any low voltage, and the fast overcurrent is limited. The inverter controlled based on the oscillator can realize effective fault ride-through without switching to the backup controller during the fault. The positive sequence space vector oscillator is realized according to the standard virtual oscillator (uVOC) control law applied to the grid-connected inverter. The dynamic equation of the internal control can be described as:

[0080]

[0081] Wherein, the positive sequence current component of the inverter output current is decomposed into i + = i α+ + ji β+ in the static αβ reference frame, and iα+ and iβ+ are expressed as:

[0082] i α+ = 0.5(i α -i β⊥ ), i β+ = 0.5(i β +i α⊥ )

[0083] (.) in the formula represents the orthogonal signal obtained by delaying the original signal by T0 / 4, T0 is the basic period, and η+ and μ+ are used for the amplitude correction gain of the positive sequence SVO, and the expression is:

[0084] η + = (1+x r / τ f )η0, μ + = (1-x r )μ0

[0085] The SVO parameters η0 and μ0 are usually selected based on the rated capacity of the power system and the required steady-state response. The parameters are calculated by referring to the derivation process in the design guide. τ fControl the settling time.

[0086] The virtual oscillator is realized power synchronization with grid through power-frequency droop response, the existing research unified virtual oscillator controller adopts pure positive sequence configuration, the application increases negative sequence SVO, in order to deduce the synchronization mechanism of negative sequence SVO, first review the working principle of positive sequence space vector oscillator to realize power synchronization, let k p+ =1, k p- =0, k q+ =1, k q- =0, exclude negative sequence SVO and double sequence vector limiter on current reference generator, the dynamic equation can be rearranged as:

[0087]

[0088] Wherein,

[0089]

[0090] P + +jQ + =v + i' + , P 0+ +jQ 0+ =v + i' 0+

[0091] In the formula, (.)' represents the conjugate complex of complex vector, the graphical representation of SVO dynamics given by rearranged dynamic equation is shown in Figure Figure 3 , in which v g+ is grid voltage vector, e i+ is current error, e i+ =i 0+ -i + , the real part and imaginary part of v+ complex coefficient in rearranged dynamic equation respectively represent instantaneous frequency ω+ and the normalized change rate of instantaneous vector amplitude (1 / V + )d (V + ) / d t , wherein Obviously, on the SVO output voltage vector, along the synchronous q+ and d+ axis respectively, the analog synchronous generator active power-frequency P + -ω + , reactive power-voltage Q + -V + 2 The droop characteristic instantaneous droop response is helpful for power synchronization to positive sequence grid voltage vector vg+, and the synchronization mechanism is as follows.

[0092]

[0093] Negative-sequence space vector oscillators (SVOs) are used to provide overcurrent limiting and grid support under unbalanced faults. Positive-sequence SVOs rotate counterclockwise, with the clockwise component η of the synchronization feedback term. + e iP+ v + With counterclockwise rotation of the harmonic term η + e iP+ v + Conversely, the amplitude correction term μ + e v+ v + Radial component -η of the synchronous feedback term + e iQ+ v + Conversely (see Figure 3 These terms achieve a relative equilibrium for stable operation in the radial and tangential directions. To ensure the stable equilibrium of the clockwise rotating negative-sequence SVO, the harmonic oscillator term and the synchronization feedback term have opposite signs and are implemented as follows:

[0094]

[0095] In the formula, the synchronization and amplitude correction gain η- / μ- of the negative-sequence SVO is consistent with that of the positive-sequence SVO; it is defined as the negative-sequence current component of the inverter output current decomposed into i in the stationary αβ reference frame. - =i α- +ji β- i α- i β- Represented as:

[0096] i α- =0.5(i α +i β⊥ ), i β- =0.5(i β -i α⊥ )

[0097] Referring to the working principle of power synchronization using a positive sequence space vector oscillator, we now derive the synchronization capability of a negative sequence SVO under asymmetrical grid voltage conditions where there are no current amplitude limitations. First, we exclude positive sequence SVOs and take k... p+ =0,k p- =1,k q+ =0,k q- =1, the negative sequence SVO dynamics of the above dynamic equations can be rearranged as follows:

[0098]

[0099] in,

[0100]

[0101] P - +jQ - =v - i' - P 0- +jQ 0- =v - i' 0-

[0102] For any negative-sequence source voltage vector v g- Current error e i- The graphical representation of SVO dynamics in the negative-order synchronization framework corresponding to v- is as follows: Figure 4 As shown, the dynamics along the q- and d- axes define the instantaneous P. --ω- and Q - -V - 2 The droop response, two cascaded droop responses, contribute to the relationship with the negative-sequence grid voltage vector v. g- Synchronization can be represented as:

[0103]

[0104] During a fault event, the current limiter will enforce current-limited operation to protect the converter. Next, we will further discuss dual-sequence synchronization with current constraints. The total power references P0 and Q0 are initially decomposed into sequence reference powers, expressed as:

[0105]

[0106] Combining the positive and negative sequence current reference values ​​and considering the dual-sequence vector limiter, the positive and negative sequence droop responses during current-limited operation can be derived as follows:

[0107]

[0108]

[0109]

[0110]

[0111] As can be seen from the above equation, during current-limited operation, P-ω and QV in the two sequences 2 The droop response is unaffected. Only when the power reference value is scaled proportionally can the output current remain within the limit. The coupling between the two sequences is reflected in the power reference. Therefore, the proposed controller can perform dual synchronous operation simultaneously.

[0112] (4) The combination of active resistance and virtual impedance is used to quickly limit overcurrent.

[0113] The active resistor R0 is used for fast over-current limitation under fault conditions. The virtual impedance Zv(s) consists of a virtual resistor Rv and a virtual inductor Lv, and its expression is:

[0114]

[0115] where the virtual resistor Rv is used to enhance system damping, the virtual inductor Lv is used to quickly limit over-current at the moment of fault, and the resonant filter ΣZ h (s) is used to suppress harmonic currents.

[0116] Example 5: As shown in the appendix Figure 5 This embodiment of the present invention discloses a method for using a fault ride-through system based on a dual-synchronous unified virtual oscillation controller, including:

[0117] Step S101, obtaining the power reference value after detecting a fault;

[0118] Here, the power reference value is set before the fault. Once a fault is detected, the reactive power reference value Q0 is set to

[0119] Step S102, the dual-sequence current reference generator combines the power reference value after detecting a fault to determine the positive- and negative-sequence current reference values, and the unbalance coefficient UF reflecting the voltage unbalance degree, to prepare for over-current suppression and compensation of unbalanced voltage; as Figure 2 shown, when the voltage unbalance degree detected in any phase exceeds the threshold (UF > KUF), the fault signal is locked, that is, x f = 1. When UF is lower than the threshold (UF < KUF), the fault is cleared, that is, x f = 0. By multiplying the mode conversion signal with the active resistor and connecting it to the output signal, the two functions of fast over-current limitation and compensation of voltage unbalance degree can be achieved.

[0120] Step S103, the dual-sequence vector limiter realizes over-current limitation under symmetric and asymmetric faults, and outputs the limited positive- and negative-sequence saturated current reference values to the positive-sequence space vector oscillator and the negative-sequence space vector oscillator;

[0121] Step S104, the positive-sequence space vector oscillator and the negative-sequence space vector oscillator receive the limited positive- and negative-sequence saturated current reference values, and use the internal control dynamic equations to achieve dual-sequence synchronous operation. Thus, by combining enhanced synchronization ability with fast over-current limitation, better fault ride-through of symmetric and asymmetric short-circuit faults can be achieved.

[0122] The above technical features constitute the best embodiment of the present application, which has strong adaptability and optimal implementation effect, and unnecessary technical features can be added or reduced according to actual needs to meet the needs of different situations.

Claims

1. A dual synchronous unified virtual phasor controller based fault ride through system, characterized in that, The double synchronous unified virtual oscillation controller comprises a double sequence current reference generator, a double sequence vector limiter, a positive sequence space vector oscillator and a negative sequence space vector oscillator. The double sequence current reference generator is used to obtain a power reference value when a fault is detected, and the positive and negative sequence current reference values are determined in combination with the power reference value. The double sequence vector limiter is connected with the double sequence current reference generator, and overcurrent limitation under symmetrical and asymmetrical faults is realized, and the positive and negative sequence saturated current reference values after limitation are output. The positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double sequence vector limiter, and double sequence synchronous operation is realized. The active resistance and the virtual impedance are combined and used for fast limitation of overcurrent. The double sequence current reference generator calculates the positive and negative sequence current reference values by using the following formula: The double sequence current reference value calculation formulae are respectively: wherein, α、β The positive and negative sequence current calculation formulas in the stationary coordinate system are respectively: wherein, D p =k p+ || v + || 2 + k p- || v - || 2 , D q =k q+ || v + || 2 + k q- || v - || 2 , P 0 is an active power reference value, Q 0 is a reactive power reference value; The positive sequence space vector oscillator realizes positive sequence synchronous operation by using the following dynamic equation: wherein is the positive sequence current component of the inverter output current, η + and μ + is the synchronization and amplitude correction gain for the positive sequence SVO. The negative sequence space vector oscillator realizes negative sequence synchronous operation by using the following dynamic equation: wherein is a negative sequence current component of the inverter output current, η - and μ - is a synchronization and magnitude correction gain for the negative sequence SVO.

2. The dual synchronous unified virtual oscillator controller based fault ride through system of claim 1, wherein, The double-sequence vector limiter performs overcurrent limitation under symmetric and asymmetric faults, i.e. limits the current reference vector to the maximum value I m The following, wherein the positive and negative sequence saturated current reference values after output limitation are included: The saturated current reference value is limited to: The three-phase unsaturated current reference value is represented as: wherein , γ corresponds to the values of a, b, c, respectively ; In combination with the limited current reference value, the positive and negative sequence saturated current reference values are obtained: 。 3. The dual synchronous unified virtual oscillator controller based fault ride through system as claimed in claim 1 or 2, wherein, The power reference value setting unit is further included, and the power reference value set under the condition before the fault is set.

4. A method of using a dual synchronous unified virtual phasor controller based fault ride through system as claimed in any one of claims 1 to 3, wherein, The power reference value setting unit comprises: The power reference value after the fault is detected is obtained; The double sequence current reference generator determines the positive and negative sequence current reference values in combination with the power reference value after the fault is detected, and an unbalance coefficient UF reflecting voltage unbalance degree, so as to prepare for overcurrent suppression and unbalanced voltage compensation; The double sequence vector limiter realizes overcurrent limitation under symmetrical and asymmetrical faults, and outputs the positive and negative sequence saturated current reference values after limitation to the positive sequence space vector oscillator and the negative sequence space vector oscillator; The positive sequence space vector oscillator and the negative sequence space vector oscillator receive the positive and negative sequence saturated current reference values after limitation, and realize double sequence synchronous operation by using internal control dynamic equations.

Images