Method for controlling a switched capacitor step-down circuit of a power supply and power supply

Abstract

Embodiments of the present disclosure relate to a power supply and a method for controlling a power supply. The power supply includes a switched capacitor step-down circuit and a controller. A first end of a second switch is connected to a voltage input terminal of the power supply, and a second end of the second switch is connected to a first end of a first capacitor of the switched capacitor step-down circuit and to the first end of the first switch. The second end of the first switch is connected to a first end of a first complementary switch and to a voltage output terminal of the power supply. The second end of the first capacitor is connected to a first end of a second complementary switch of the switched capacitor step-down circuit and to the voltage output terminal, and the second end of the first complementary switch is connected to a second end of the second complementary switch and to ground. The controller is configured to: control the switching of the first switch using a first duty cycle; and control the switching of the second switch using a second duty cycle. The first duty cycle is greater than 0.5, and the second duty cycle is equal to 0.5. In this way, when the duty cycle corresponding to the desired output voltage is greater than 0.5, the duty cycle of the path having the capacitor is limited to 0.5, thereby making the output of the power supply more balanced and stable.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the electrical field, and more particularly to a method for controlling a switched capacitor buck circuit of a power supply and a power supply. Background Art

[0002] Switching-mode power supplies are used in numerous devices today, including smartphones, computers and peripherals, digital home appliances, and automobiles (ECUs: Electronic Control Units). These power supplies include a DC-to-DC (DC / DC) converter circuit that converts one DC voltage to another. DC / DC converter circuits come in a variety of topologies to achieve this voltage conversion.

[0003] The switched capacitor buck converter is a topology that has attracted much attention. A switched capacitor buck converter typically includes multiple switching elements, an output inductor, and an output capacitor. The voltage conversion function of the switched capacitor buck converter is achieved by periodically closing and opening multiple switching elements in a predetermined sequence. During the operation of the switched capacitor buck converter, energy is first stored in the output inductor through the switching coordination of the corresponding switching elements. Subsequently, the switching state of the switching elements is changed to release the previously stored energy in the output inductor to supply it to the load. The switched capacitor buck converter converts the input voltage to a specified voltage by alternating and repeating the switching cycles. Furthermore, the specified output voltage can be obtained by setting the duty cycle of the switching elements. Summary of the Invention

[0004] The embodiments of the present disclosure provide a solution for detecting the line status of an electrical device, which aims to at least overcome the problems existing in the prior art in detecting the line status of an electrical device.

[0005] A first aspect of the present disclosure relates to a power supply. The power supply includes a step-down circuit and a controller for controlling the step-down circuit, wherein the step-down circuit includes a first switch, a first complementary switch, a second switch, a second complementary switch, a first capacitor, a first output inductor, and a second output inductor, wherein a first end of the second switch is connected to a voltage input terminal of the power supply, a second end of the second switch is connected to a first end of the first capacitor and a first end of the first switch, a second end of the first switch is connected to a first end of the first complementary switch and a first end of the first output inductor, a second end of the first capacitor is connected to a first end of the second complementary switch and a first end of the second output inductor, the second end of the first complementary switch and the second end of the second complementary switch are grounded, and the second end of the first output inductor and the second end of the second output inductor are connected to a voltage output terminal of the power supply. The controller is configured to: control the switching of the first switch using a first duty cycle; and control the switching of the second switch using a second duty cycle, wherein the switching period of the first switch is equal to the switching period of the second switch. The first duty cycle is greater than 0.5, and the second duty cycle is equal to 0.5.

[0006] According to the implementation of the present disclosure, when the desired duty cycle is greater than 0.5, only the desired duty cycle is used to control the switches in the path corresponding to the first output inductor, and the duty cycle of the switches in the path corresponding to the second output inductor including the capacitor is limited to 0.5, which can make the currents in the first output inductor and the second output inductor basically equal, providing output stability.

[0007] In some embodiments, the time when the second switch S2 switches from open to closed differs from the time when the first switch switches from open to closed by half a cycle length.

[0008] In some embodiments, a controller is coupled to the first complementary switch and configured to control the first complementary switch to be open when the first switch is closed, and to control the first complementary switch to be closed when the first switch is open. The controller is also coupled to the second complementary switch and configured to control the second complementary switch to be open when the second switch is closed, and to control the second complementary switch to be closed when the second switch is open. In such an embodiment, the desired step-down function can be achieved by controlling the corresponding complementary switches in opposite switching control modes.

[0009] In some embodiments, the controller includes: a first control unit having a first terminal coupled to the control terminal of the first switch and a second terminal coupled to the control terminal of the first complementary switch, and configured to send a control signal to the control terminals of the first switch and the first complementary switch; and a second control unit having a first terminal coupled to the control terminal of the second switch and a second terminal coupled to the control terminal of the second complementary switch, and configured to send a control signal to the control terminals of the second switch and the second complementary switch, respectively. In such an embodiment, using the same control unit to control the two complementary switches can simplify the configuration of the controller.

[0010] In some embodiments, the controller further includes: a duty cycle generation unit configured to generate a first duty cycle; and a duty cycle limiter coupled between the duty cycle generation unit and the second control unit and configured to output a second duty cycle of 0.5 to the second control unit in response to determining that the first duty cycle received from the duty cycle generation unit is greater than 0.5. In such an embodiment, by providing the duty cycle limiter, the duty cycle transmitted to the second control unit can be limited to 0.5, thereby implementing the control scheme according to the present disclosure.

[0011] In some embodiments, the duty cycle generation unit includes a duty cycle generator configured to: obtain a reference output voltage and an input voltage at a voltage input terminal; and generate a first duty cycle based on the reference output voltage and the input voltage. In such embodiments, by providing the duty cycle generator, a desired duty cycle can be automatically generated based on the reference output voltage and the input voltage.

[0012] In some embodiments, the first duty cycle is determined by the following formula:

[0013]

[0014] Where V in is the input voltage, V out is the reference output voltage, and D is the first duty cycle. In such an embodiment, the formula for determining the duty cycle is the same as that in the case where the desired duty cycle is less than 0.5, thereby reducing the complexity of the duty cycle calculation.

[0015] In some embodiments, the duty cycle generation unit further includes: a duty cycle comparator coupled to the voltage output terminal and configured to determine a difference between the output voltage at the voltage output terminal and a reference output voltage; and a regulator coupled between the duty cycle comparator and the duty cycle generator and configured to generate a duty cycle adjustment value based on the difference determined by the duty cycle comparator, wherein the duty cycle generator is further configured to adjust the first duty cycle based on the received duty cycle adjustment value. In such an embodiment, by providing the comparator and the regulator, when the output voltage deviates from the reference voltage, the duty cycle can be compensated so that it can adapt to the current input voltage, thereby maintaining a stable output voltage.

[0016] In some embodiments, the buck circuit further includes a third switch, a third complementary switch, a fourth switch, a fourth complementary switch, a second capacitor, a third output inductor, and a fourth output inductor, wherein the first end of the fourth switch is connected to the voltage input terminal, the second end of the fourth switch is connected to the first end of the second capacitor and the first end of the third switch, the second end of the third switch is connected to the first end of the third complementary switch and the first end of the third output inductor, the second end of the second capacitor is connected to the first end of the fourth complementary switch and the first end of the fourth output inductor, the second end of the third complementary switch and the second end of the fourth complementary switch are grounded, and the second end of the third output inductor and the second end of the fourth output inductor are connected to the voltage output terminal. The control terminal of the third switch is connected to the control terminal of the first switch, the control terminal of the third complementary switch is connected to the control terminal of the first complementary switch, the control terminal of the fourth switch is connected to the control terminal of the second switch, and the control terminal of the fourth complementary switch is connected to the control terminal of the second complementary switch. In such an embodiment, by adding a circuit stage, the output power can be increased, and by using the same control method as the other stages, each circuit stage can implement the control scheme according to the present disclosure.

[0017] A second aspect of the present disclosure relates to a method for controlling a power supply. The power supply includes a step-down circuit, the step-down circuit including a first switch, a first complementary switch, a second switch, a second complementary switch, a first capacitor, a first output inductor, and a second output inductor, wherein the first end of the second switch is connected to a voltage input terminal of the power supply, the second end of the second switch is connected to the first end of the first capacitor and the first end of the first switch, the second end of the first switch is connected to the first end of the first complementary switch and the first end of the first output inductor, the second end of the first capacitor is connected to the first end of the second complementary switch and the first end of the second output inductor, the second end of the first complementary switch and the second end of the second complementary switch are grounded, and the second end of the first output inductor and the second end of the second output inductor are connected to the voltage output terminal of the power supply. The method includes: controlling the switching of the first switch using a first duty cycle; and controlling the switching of the second switch using a second duty cycle, the switching period of the first switch being equal to the switching period of the second switch, wherein the first duty cycle is greater than 0.5 and the second duty cycle is equal to 0.5.

[0018] In some embodiments, the method further includes: controlling the first switch to switch from open to closed at a time half the length of the cycle after controlling the second switch to switch from open to closed.

[0019] In some embodiments, the method further includes: obtaining a reference output voltage and an input voltage of the voltage input terminal; determining a first duty cycle based on the reference output voltage and the input voltage; and in response to determining that the first duty cycle is greater than 0.5, determining the second duty cycle to be 0.5.

[0020] In some embodiments, the method further includes, in response to determining that the first duty cycle is less than 0.5, determining that the second duty cycle is equal to the first duty cycle.

[0021] In some embodiments, it also includes: detecting the output voltage at the voltage output terminal; comparing the output voltage with a reference output voltage; and in response to determining that the difference between the output voltage and the reference output voltage is greater than a predetermined threshold, determining a first duty cycle based on the current input voltage and the reference output voltage.

[0022] In some embodiments, the first duty cycle is determined by the following formula:

[0023]

[0024] Wherein, V1 is the voltage at the voltage input terminal, V2 is the preset target voltage at the voltage output terminal, and D1 is the first duty cycle.

[0025] It should be understood that the power supply structure according to the first aspect of the present disclosure corresponds to the method according to the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the embodiments of the present disclosure will become more readily understood through the following detailed description with reference to the accompanying drawings, in which several embodiments of the present disclosure are illustrated by way of example and not limitation, in which:

[0027] Figure 1A A schematic diagram illustrating an example power supply in which embodiments according to the present disclosure can be implemented;

[0028] Figure 1B-1C Shows the control Figure 1A A timing diagram of the control signal of the power supply in FIG.

[0029] Figure 1D Shows the use of Figure 1C The waveform of the inductor current when the control timing control circuit is in the control sequence control circuit;

[0030] Figure 1E Shows the use of Figure 1C Bode diagram of the power level when controlling the timing control circuit in the control circuit;

[0031] Figure 2 shows a schematic diagram of an example power supply according to an embodiment of the present disclosure;

[0032] Figure 3 A timing diagram showing signals of a step-down circuit for controlling a power supply according to the present disclosure is shown;

[0033] Figures 4A-4C Schematic diagram showing the circuit of the power supply according to the present disclosure at various working stages;

[0034] Figure 5A Shows the use of Figure 3 The waveform of the inductor current when the control timing control circuit is in the control sequence control circuit;

[0035] Figure 5B Shows the use of Figure 3 Bode plot of the power stage when controlling the sequential control circuit in FIG; and

[0036] Figure 6 A schematic diagram of a cascade buck circuit according to the present disclosure is shown. DETAILED DESCRIPTION

[0037] The principles of the present disclosure will now be described with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is merely to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals may be used in the figures where possible, and similar or identical reference numerals may represent similar or identical functions. Those skilled in the art will readily recognize, from the description below, that alternative embodiments of the structures and methods described herein may be adopted without departing from the principles of the present disclosure described herein.

[0038] As used herein, the term "including" and its variations are to be interpreted as open-ended terms meaning "including but not limited to." The term "based on" is to be interpreted as "based at least in part on." The terms "one embodiment" and "an embodiment" are to be understood as "at least one embodiment." The term "another embodiment" is to be understood as "at least one other embodiment." The terms "first," "second," etc. may refer to different or identical objects. Other explicit and implicit definitions may be included below. Unless the context clearly indicates otherwise, the definitions of terms are consistent throughout the specification.

[0039] Figure 1A Schematic diagram of an example power supply 10 in which embodiments according to the present disclosure can be implemented is shown. Figure 1A As shown, the power supply 10 includes a voltage input terminal VIN and a voltage output terminal VOUT, and a switched capacitor step-down circuit 100 coupled between the voltage input terminal VIN and the voltage output terminal VOUT. The switched capacitor step-down circuit 200 includes a first switch S1, a second switch S2, a first complementary switch SR1, a second complementary switch SR2, and a first capacitor C1. The first end of the second switch S2 is connected to the voltage input terminal VIN. The second end of the second switch S2 is connected to the first end of the first capacitor C1 of the switched capacitor step-down circuit 200 and the first end of the first switch S1. The second end of the first switch S1 is connected to the first end of the first complementary switch SR1 and the first end of the first output inductor L1. The second end of the first capacitor C1 is connected to the first end of the second complementary switch SR2 and the first end of the second output inductor L2. The second end of the first output inductor L1 and the second end of the second output inductor L2 are connected to the first end of the output capacitor COUT and the voltage output terminal VOUT. The second end of the output capacitor COUT is grounded. The second end of the first complementary switch SR1 and the second end of the second complementary switch SR2 are grounded.

[0040] According to the circuit of the power supply 10, the output voltage at the voltage output terminal VOUT depends on the input voltage at the voltage input terminal VIN and the ratio of the on time to the off time of each switch in the circuit, that is, the duty cycle D. In order for the power supply 10 to output the desired voltage at the voltage output terminal VOUT, it is necessary to control the switching of the first switch S1, the second switch S2, the first complementary switch SR1 and the second complementary switch SR2 at a specific duty cycle to match the input voltage. Conventionally, the duty cycles of the first switch S1 associated with the first output inductor L1 and the second switch S2 associated with the second output inductor L2 are the same. Figure 1B and Figure 1C The control of the switches in the switched capacitor buck circuit 200 under different duty cycle ranges will be described in detail.

[0041] Figure 1B FIG shows a timing diagram of the control signal when the duty cycle D is less than 0.5. Figure 1B As shown, at time T1, the control signal SI2 for controlling the second switch S2 and the control signal SIR1 for controlling the first complementary switch SR1 are at a high level, so that the second switch S2 and the first complementary switch SR1 are closed. The control signal SI1 for controlling the first switch S1 and the control signal SIR2 for controlling the second complementary switch SR2 are at a low level, so that the first switch S1 and the second complementary switch SR2 are closed.

[0042] At time T2, which is D*T away from time T1, signal SI2 becomes low, causing the second switch S2 to be turned off. Simultaneously, signal SIR2 becomes high, causing the second complementary switch SR2 to be turned on. In the first phase [T1, T2], the first switch S1 corresponding to the first output inductor L1 is turned off, and the voltage across the first output inductor L1 is V out In contrast, the second switch S2 corresponding to the second output inductor L2 is closed, and the voltage across the second output inductor L2 is V in -V c -V out , where V c is the voltage V at the first capacitor C1 out is the voltage at the voltage output terminal VOUT, and V in is the voltage at the voltage input terminal VIN. The duration of the first phase [T1, T2] is:

[0043] t1=D*T (1).

[0044] At time T3, which is T / 2 (i.e., half a switching cycle) different from time T1, signal SI1 becomes high, closing the first switch S1. Signal SIR1 becomes low, opening the first complementary switch SR1. In the second phase [T2, T3], the first switch S1 corresponding to the first output inductor L1 is open, and the voltage across the first output inductor L1 is V out In contrast, the second switch S2 corresponding to the second output inductor L2 is disconnected, and the voltage across the second output inductor L2 is V out The duration of the second phase [T2, T3] is:

[0045] t2=(0.5-D)*T (2).

[0046] At time T4, which is D*T away from time T3, signal SI1 becomes low, causing the first switch S1 to be turned off, and signal SIR1 becomes high, causing the first complementary switch SR1 to be turned on. In the third phase [T3, T4], the first switch S1 corresponding to the first output inductor L1 is closed, and the voltage across the first output inductor L1 is V c -V out In contrast, the second switch S2 corresponding to the second output inductor L2 is disconnected, and the voltage across the second output inductor L2 is V out The duration of the third phase [T3, T4] is:

[0047] t3=D*T (3).

[0048] At time T5, which is T / 2 different from time T3, the signal SIR2 becomes high, causing the second complementary switch SR2 to be turned off, and the signal S2 becomes low, causing the second switch S2 to be turned on. In the fourth phase [T3, T4], the first switch S1 corresponding to the first output inductor L1 is turned off, and the voltage across the first output inductor L1 is V out In contrast, the second switch S2 corresponding to the second output inductor L2 is disconnected, and the voltage across the second output inductor L2 is V out The duration of the fourth phase [T3, T4] is:

[0049] t4 = (0.5 - D) * T (4).

[0050] Thus far, the entire switching sequence for each switch from time T1 to time T5 has been described. In power supply 10, according to the principle of volt-second balance of inductance, that is, for an inductor in a steady state, the volt-seconds during the switch on time (current rising period) must be numerically equal to the volt-seconds during the switch off time (current falling period), even though the two have opposite signs. The volt-second balance formula for output inductors L1 and L2 can be obtained as follows:

[0051] (V c -V out )*t3=V out *(t1+t2+t4) (5),

[0052] (V in -V c -V out )*t1=V out *(t2+t3+t4) (6). Substituting (1), (2), (3) and (4) into (5) and (6) yields the following equation:

[0053] V out =V in *D / 2 (7).

[0054] According to the ampere-second balance principle of capacitance, that is, the positive ampere-second value across the capacitor in a steady-state switching power supply is equal to the negative ampere-second value, the balance formula at the first capacitor C1 can be obtained:

[0055] I2*t1=I1*t3 (8)

[0056] Where I1 is the current in the output inductor L1, and I2 is the current in the output inductor L2. Substituting (1) and (3) into (8) again, we obtain the following relationship:

[0057] I2=I1 (9).

[0058] From this, it can be seen that Figure 1B Under the control mode, the current in the output inductor L1 is equal to the current in the output inductor L2.

[0059] Figure 1C The timing diagram of the control signals when the duty cycle D is greater than 0.5 is shown. As shown in Figure 1c, at time T1, signal SI2 and signal SI1 are high, closing the second switch S2 and the first switch S1. Signal SIR1 and signal SIR2 are low, opening the first complementary switch SR1 and the second complementary switch SR2. At time T2, which is (D-0.5)*T away from time T1, signal SI1 goes low, opening the first switch S1, and signal SIR1 goes high, closing the first complementary switch SR1.

[0060] In the first phase [T1, T2], the first switch S1 corresponding to the first output inductor L1 is closed, and the voltage across the first output inductor L1 is V in -V outIn contrast, the second switch S2 corresponding to the second output inductor L2 is closed, and the voltage across the second output inductor L2 is V in -V c -V out The duration of the first phase [T1, T2] is:

[0061] t1=(D-0.5)*T (10).

[0062] At time T3, which is T / 2 different from time T1, the signal SIR1 becomes low, causing the first complementary switch SR1 to be turned off, and the signal SI1 becomes high, causing the first switch S1 to be turned on. In the second phase [T2, T3], the first switch S1 corresponding to the first output inductor L1 is turned off, and the voltage across the first output inductor L1 is V out In contrast, the second switch S2 corresponding to the second output inductor L2 is closed, and the voltage across the second output inductor L2 is V in -V c -V out The duration of the second phase [T2, T3] is:

[0063] t2=(1-D)*T (11).

[0064] At time T4, which is (D-0.5)*T away from time T3, signal SI2 becomes low, causing the second switch S2 to be turned off, and signal SIR2 becomes high, causing the second complementary switch SR2 to be turned on. In the third phase [T3, T4], the first switch S1 corresponding to the first output inductor L1 is closed, and the voltage across the first output inductor L1 is V in -V out In contrast, the second switch S2 corresponding to the second output inductor L2 is closed, and the voltage across the second output inductor L2 is V in -V c -V out The duration of the third phase [T3, T4] is:

[0065] t3=(D-0.5)*T (12).

[0066] At time T5, which is T / 2 different from time T3, the signal SIR2 becomes high, closing the second complementary switch SR2, and the signal SI2 becomes low, opening the second switch S2. In the fourth phase [T4, T5], the first switch S1 corresponding to the first output inductor L1 is closed, and the voltage across the first output inductor L1 is V c -V outIn contrast, the second switch S2 corresponding to the second output inductor L2 is disconnected, and the voltage across the second output inductor L2 is V out The duration of the fourth phase [T3, T4] is:

[0067] t4=(1-D)*T (13).

[0068] Thus far, the entire switching sequence of each switch from time T1 to time T5 has been described. In the power supply 10, according to the volt-second balance principle of inductance, the volt-second balance formula for output inductor L1 and output inductor L2 can be obtained:

[0069] (V in -V out )*(t1+t3)+(V c -V out )*t4=V out *t2 (14),

[0070] (V in -V c -V out )*(t1+t2+t3)=V out *t4 (15). Substituting (10), (11), (12) and (13) into (14) and (15), we obtain the following relationship:

[0071] V out =V in *D 2 (16).

[0072] According to the ampere-second balance principle of capacitance, the balance formula at the first capacitor C1 can be obtained:

[0073] I2*(t1+t2+t3)=I1*t4 (17).

[0074] Substituting (10), (11), (12) and (13) into (17) again, we obtain the following relationship:

[0075] I2=I1(1-D) / D (18).

[0076] From this, it can be seen that when the duty cycle D is greater than 0.5, the currents in the output inductor L1 and the output inductor L2 are different, that is, the currents are unbalanced. Figure 1D Shows the use of Figure 1C The waveform diagram 105 of the inductor current when the power supply 10 is controlled by the control method shown. The output inductor L1 is shown in solid line, and the output inductor L2 is shown in dotted line. Figure 1D As can be seen in , the currents in the two inductors are different. In addition, Figure 1E Shows the use of Figure 1C The Bode diagram 107 of the power level when the power supply 10 is controlled by the control method shown. Figure 1E It can be seen that the phase margin drops sharply around 10000Hz and the stability decreases sharply.

[0077] Therefore, it can be seen that when using Figure 1C The control method shown, i.e., controlling the power supply 10 with the same duty cycle greater than 0.5, has two disadvantages:

[0078] 1) The voltage transfer relationship when the duty cycle is less than 0.5 is different from that when the duty cycle is greater than 0.5. This means that two sets of loop control parameters are required to achieve voltage loop control. Moreover, when the duty cycle is greater than 0.5, the phase lag will increase significantly, affecting the response speed of the control loop.

[0079] 2) When the duty cycle is greater than 0.5, it will cause an imbalance in the two inductor currents.

[0080] To address this issue, the present disclosure provides a solution for controlling a power supply when the duty cycle is greater than 0.5. In this solution, when the duty cycle is greater than 0.5, the duty cycle of a switch with a capacitor is limited to 0.5. This ensures that the relationship between the input voltage and the output voltage is consistent when the duty cycle is greater than 0.5 and less than 0.5, and also ensures that the currents in the two output inductors are the same when the duty cycle is greater than 0.5.

[0081] Figure 2 Schematic diagram of an example power supply 10 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the power supply 10 includes a switched capacitor buck circuit 100 and a controller 200 for controlling the switched capacitor buck circuit 100. The structure of the switched capacitor buck circuit 100 is generally similar to that of the Figure 1A The same as the switched capacitor step-down circuit 100 in FIG. Figure 2 In the illustrated embodiment, the controller 200 is coupled to the control terminals of all switches to transmit generated control signals to all switches. The switches in the switched capacitor buck circuit 100 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), or triodes.

[0082] When it is determined that the occupancy ratio is less than 0.5, the controller 200 may use Figure 1BThe control signal shown is used to control the switched capacitor buck circuit 100. When it is determined that the duty cycle is greater than 0.5, the Figure 3 The control signal according to the embodiment of the present disclosure is used to control the switched capacitor buck circuit 100. In this embodiment, the first switch S1 is controlled with a determined duty cycle, while the second switch S2 is controlled with a duty cycle of 0.5.

[0083] Figure 3 FIG. 1 shows a timing diagram of a control signal according to a solution of the present disclosure when the duty cycle D is greater than 0.5. Figure 3 As shown, at time T1, the signal SI2 and the signal SI1 are at high levels, so that the second switch S2 and the first switch S1 are closed, and the signal SIR2 and the signal SIR1 are at low levels, so that the second complementary switch SR2 and the first complementary switch SR1 are open.

[0084] At time T2 which differs from time T1 by (D-0.5)*T, the signal SI1 changes to a low level to open the first switch S1 , and the signal SIR1 changes to a high level to close the first complementary switch SR1 . Figure 4A A schematic diagram showing the current flow during the first phase [T1, T2]. Figure 4A As shown, in the circuit corresponding to the first output inductor L1, the first switch S1 is closed and the first complementary switch SR1 is open. At this time, the first output inductor L1 is connected between the voltage input terminal VIN and the voltage output terminal VOUT. The current flow of this circuit is shown by the dotted line marked as I1. Therefore, the voltage across the first output inductor L1 is V in -V out In contrast, in the path corresponding to the second output inductor L2, the second switch S2 is closed and the second complementary switch SR2 is open. At this time, the second output inductor L2 and the first capacitor C1 are connected in series between the voltage input terminal VIN and the voltage output terminal VOUT. The current flow of this path is shown by the dotted line marked as I2. Therefore, the voltage across the second output inductor L2 is V in -V c -V out The duration of the first phase [T1, T2] is:

[0085] t1=(D-0.5)*T (19).

[0086] return Figure 3 At time T3, which is T / 2 different from time T1, signal SIR1 becomes low, opening the first complementary switch SR1, and signal SI1 becomes high, closing the first switch S1. Simultaneously, signal SI2 becomes low, opening the switch S2, and signal SIR2 becomes high, closing the second complementary switch SR2. Figure 4BA schematic diagram showing the current flow during the second phase [T2, T3]. Figure 4B As shown, in the circuit corresponding to the first output inductor L1, the first complementary switch SR1 is closed and the first switch S1 is open. At this time, the first output inductor L1 is connected between the ground and the voltage output terminal VOUT. The current flow of this circuit is shown by the dotted line marked as I1. Therefore, the voltage across the first output inductor L1 is V out In contrast, the second output inductor L2 and the first capacitor C1 are still connected in series between the voltage input terminal VIN and the voltage output terminal VOUT. The current flow of this path is shown by the dotted line marked as I2. Therefore, the voltage across the second output inductor L2 is still V in -V c -V out The duration of the second phase [T2, T3] is:

[0087] t2=(1-D)*T (20).

[0088] Return again Figure 3 At time T4 which is T / 2 different from time T3, the signal SI2 becomes high level, so that the second switch S2 is closed, and the signal SIR2 becomes low level, so that the second complementary switch SR2 is opened. Figure 4C FIG. 1 shows a schematic diagram of the current flow during the third phase [T3, T4]. Figure 4C As shown, in the circuit corresponding to the first output inductor L1, the first complementary switch SR1 is open and the first switch S1 is closed. At this time, the first output inductor L1 and the first capacitor C1 are connected in series between the ground and the voltage output terminal VOUT. The current flow of this circuit is shown by the dotted line marked as I1. Therefore, the voltage across the first output inductor L1 is V c -V out In contrast, at this time, in the path corresponding to the second output inductor L2, the second switch S2 is open and the second complementary switch SR2 is closed. At this time, the second output inductor L2 is connected between the ground and the voltage output terminal VOUT. The current flow of this path is shown by the dotted line marked as I2. Therefore, the voltage across the second output inductor L2 is still V out The duration of the third phase [T3, T4] is:

[0089] t3=T / 2 (21).

[0090] Thus far, the entire switching sequence of each switch from time T1 to time T4 has been described. In the power supply 10, according to the volt-second balance principle of inductance, the volt-second balance formula for output inductor L1 and output inductor L2 can be obtained:

[0091] (V in -Vout )*t1+(V c -V out )*t3=V out *t2 (22),

[0092] (V in -V c -V out )*(t1+t2)=V out *t3 (23). Substituting (19), (20) and (21) into (22) and (23), we obtain the following relationship:

[0093] V out =V in *D / 2 (24).

[0094] According to the ampere-second balance principle of capacitance, the balance formula at the first capacitor C1 can be obtained:

[0095] I2*(t1+t2)=I1*t3 (25).

[0096] Substituting (19), (20) and (21) into (25) again, we obtain the following relationship:

[0097] I2=I1 (26).

[0098] In use Figure 3 When the signal sequence shown is used to control power supply 10, the relationship between the input and output voltages, as well as the relationship between the currents in the two inductors, is the same as in the control scheme with a duty cycle less than 0.5. In this way, the voltage transfer gain equation is unified, and the two inductor currents are always balanced. Figure 5A Shows the use of Figure 3 The waveform diagram 500 of the inductor current when the power supply 10 is controlled by the control method shown. The output inductor L1 is shown in solid line, and the output inductor L2 is shown in dotted line. Figure 5A As can be seen from the diagram, the currents in the two inductors are essentially equal. In addition, Figure 5B Shows the use of Figure 3 The Bode diagram 502 of the power level when the control method shown is used to control the power supply 10. Figure 5B It can be seen that the phase margin decreases less in the high frequency range, compared to Figure 1E It has been greatly improved.

[0099] Return here Figure 2 , Figure 2 It is shown that it can be achieved Figure 3 The example structure of the controller 200 of the control signal sequence is shown. Figure 2As shown, the controller 200 includes a first control unit 210. A first terminal of the first control unit 210 is coupled to the control terminal of the first switch S1, and a second terminal thereof is coupled to the control terminal of the first complementary switch SR1. The first control unit 210 can send complementary control signals, i.e., signals of opposite voltage levels, to the control terminals of the first switch S1 and the first complementary switch SR1. The controller 200 also includes a second control unit 220. A first terminal of the second control unit 220 is coupled to the control terminal of the second switch S2, and a second terminal thereof is coupled to the control terminal of the second complementary switch SR2. Similarly, the second control unit 220 can send interactive control signals to the control terminals of the second switch S2 and the second complementary switch SR2, respectively. The first control unit 210 and the second control unit 220, for example, include signal generators. The signals generated by the signal generators can be modulated using the duty cycle received by the control units to obtain signals with desired widths.

[0100] The controller 200 further includes a duty cycle generating unit 230. The duty cycle generating unit 230 can generate a first duty cycle according to the desired output voltage and the acquired input voltage, for example, based on the relationship between the input voltage and the output voltage represented by equations (7) and (24). The duty cycle generating unit 230 transmits the generated first duty cycle to the first control unit 210 and the second control unit 220. The controller 200 further includes a duty cycle limiter 240. The duty cycle limiter 240 is coupled between the duty cycle generating unit 230 and the second control unit 220 and can limit the size of the duty cycle generated by the duty cycle generating unit 230 so that the duty cycle transmitted to the second control unit 220 does not exceed 0.5. For example, when the received duty cycle is greater than 0.5, the duty cycle limiter 240 limits the received duty cycle to 0.5 and outputs a second duty cycle of 0.5 to the second control unit 220. In this way, when the determined duty cycle is greater than 0.5, the first switch S1 and the first complementary switch SR1 can be controlled at the determined duty cycle, and the second switch S2 and the second complementary switch SR2 can be controlled at the duty cycle equal to 0.5.

[0101] Specifically, the duty cycle generation unit 230 includes a duty cycle generator 231, a duty cycle comparator 232, and a regulator 233. The duty cycle generator 231 generates an initial duty cycle based on the aforementioned relationship. The comparator 232 is coupled to the voltage output terminal VOUT and compares the detected output voltage with the reference output voltage to generate a difference therebetween, and transmits the generated difference to the regulator 233. The regulator 233 is, for example, a PI regulator as shown in the figure, and is coupled between the duty cycle comparator 232 and the duty cycle generator 231. The regulator 233 generates a duty cycle adjustment value based on the difference determined by the duty cycle comparator 232, and transmits the duty cycle adjustment value to the duty cycle generator 231. The duty cycle generator 231 adjusts the initial duty cycle based on the duty cycle adjustment value to compensate for the difference. Through such a setting, when the duty cycle generation unit 230 detects that the output voltage at the voltage output terminal VOUT is different from the desired reference output voltage, the current duty cycle is compensated through adjustment of the PI regulator to change the control of the switched capacitor buck circuit 200, thereby obtaining the expected output voltage.

[0102] In some embodiments, to increase output power, the buck circuit may include multiple levels of switches and output inductors. Figure 6 FIG. 5 shows a schematic diagram of a power supply 60 according to the present disclosure, wherein the power supply 60 includes a cascade buck circuit 600 and a controller 700. Figure 6 As shown, the switched capacitor step-down circuit 600 has Figure 2 In addition to the same components as those in the switched capacitor step-down circuit 200, the switched capacitor step-down circuit 200 further includes a third switch S3, a third complementary switch SR3, a fourth switch S4, a fourth complementary switch SR4, and a second capacitor C2. A first end of the fourth switch S4 is connected to the voltage input terminal VIN. A second end of the fourth switch S4 is connected to the first end of the second capacitor C2 and the first end of the third switch S3. A second end of the third switch S3 is connected to the first end of the third complementary switch SR3 and the voltage output terminal VOUT. A second end of the second capacitor C2 is connected to the first end of the fourth complementary switch SR4 and the voltage output terminal VOUT. A second end of the third complementary switch SR3 is connected to the second end of the fourth complementary switch SR4 and to ground.

[0103] Furthermore, the control terminal of the third switch S3 is connected to the control terminal of the first switch S1. The control terminal of the third complementary switch SR3 is connected to the control terminal of the first complementary switch SR1. The control terminal of the fourth switch S4 is connected to the control terminal of the second switch S2. The control terminal of the fourth complementary switch SR4 is connected to the control terminal of the second complementary switch SR2. This connection enables the controller 700 to simultaneously control the third complementary switch SR3 and the first complementary switch SR1, the third switch S3 and the first switch S1, the fourth switch S4 and the second switch S2, and the fourth complementary switch SR4 and the second complementary switch SR2 in the same manner, thereby implementing the control scheme of the present disclosure.

[0104] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A power supply (10), comprising a step-down circuit (100) and a controller (200) for controlling the step-down circuit (100), wherein the step-down circuit (100) comprises a first switch (S1), a first complementary switch (SR1), a second switch (S2), a second complementary switch (SR2), a first capacitor (C1), a first output inductor (L1), and a second output inductor (L2), wherein a first end of the second switch (S2) is connected to a voltage input terminal (VIN) of the power supply (10), a second end of the second switch (S2) is connected to a first end of the first capacitor (C1) and the first switch (S1). a first end of the first switch (S1) connected to the first end of the first complementary switch (SR1) and the first end of the first output inductor (L1), a second end of the first capacitor (C1) connected to the first end of the second complementary switch (SR2) and the first end of the second output inductor (L2), a second end of the first complementary switch (SR1) and a second end of the second complementary switch (SR2) are grounded, a second end of the first output inductor (L1) and a second end of the second output inductor (L2) are connected to the voltage output terminal (VOUT) of the power supply (10), and The controller (200) is configured to: Controlling the switching of the first switch (S1) using a first duty cycle; and The switching of the second switch (S2) is controlled by using a second duty cycle, and the switching period of the first switch (S1) is equal to the switching period of the second switch (S2). The first duty cycle is greater than 0.5, and the second duty cycle is equal to 0.

5.

2. The power supply (10) according to claim 1, wherein the time when the second switch (S2) switches from open to closed differs from the time when the first switch switches from open to closed by half a cycle length.

3. The power supply (10) according to claim 1, wherein the controller (200) is coupled to the first complementary switch (SR1) and is configured to control the first complementary switch (SR1) to be open when the first switch (S1) is closed, and to control the first complementary switch (SR1) to be closed when the first switch (S1) is open, and The controller (200) is further coupled to the second complementary switch (SR2) and is configured to control the second complementary switch (SR2) to be opened when the second switch (S2) is closed, and to control the second complementary switch (SR2) to be closed when the second switch (S2) is opened.

4. The power supply (10) of claim 1, wherein the controller (200) comprises: a first control unit (210), a first end of which is coupled to the control end of the first switch (S1), a second end of which is coupled to the control end of the first complementary switch (SR1), and configured to send a control signal to the control end of the first switch (S1) and the control end of the first complementary switch (SR1); A second control unit (220) has a first end coupled to the control end of the second switch (S2), a second end coupled to the control end of the second complementary switch (SR2), and is configured to send control signals to the control end of the second switch (S2) and the control end of the second complementary switch (SR2), respectively.

5. The power supply (10) according to claim 4, wherein the controller (200) further comprises: A duty cycle generating unit (230) configured to generate the first duty cycle; as well as A duty cycle limiter (240) is coupled between the duty cycle generating unit (230) and the second control unit (220), and is configured to output the second duty cycle of 0.5 to the second control unit (220) in response to determining that the first duty cycle received from the duty cycle generating unit (230) is greater than 0.

5.

6. The power supply (10) according to claim 5, wherein the duty cycle generating unit (230) comprises a duty cycle generator (231), wherein the duty cycle generator (231) is configured to: obtaining a reference output voltage and an input voltage of the voltage input terminal (VIN); and The first duty cycle is generated based on the reference output voltage and the input voltage.

7. The power supply (10) according to claim 6, wherein the first duty cycle is determined by the following formula: Where V in is the input voltage, V out is the reference output voltage, and D is the first duty cycle.

8. The power supply (10) according to claim 6, wherein the duty cycle generating unit (230) further comprises: a duty cycle comparator (232) coupled to the voltage output terminal (VOUT) and configured to determine a difference between an output voltage at the voltage output terminal (VOUT) and the reference output voltage; as well as a regulator (233) coupled between the duty cycle comparator (232) and the duty cycle generator (231) and configured to generate a duty cycle adjustment value based on the difference determined by the duty cycle comparator (232), The duty cycle generator (231) is further configured to adjust the first duty cycle based on the received duty cycle adjustment value.

9. The power supply (10) according to claim 4, wherein the step-down circuit (100) further comprises a third switch (S3), a third complementary switch (SR3), a fourth switch (S4), a fourth complementary switch (SR4), a second capacitor (C2), a third output inductor (L3) and a fourth output inductor (L4), wherein a first end of the fourth switch (S4) is connected to the voltage input terminal (VIN), a second end of the fourth switch (S4) is connected to the first end of the second capacitor (C2) and the first end of the third switch (S3), and the first end of the fourth switch (S4) is connected to the first end of the second capacitor (C2) and the first end of the third switch (S3). The second end of the third switch (S3) is connected to the first end of the third complementary switch (SR3) and the first end of the third output inductor (L3), the second end of the second capacitor (C2) is connected to the first end of the fourth complementary switch (SR4) and the first end of the fourth output inductor (L4), the second end of the third complementary switch (SR3) and the second end of the fourth complementary switch (SR4) are grounded, and the second end of the third output inductor (L3) and the second end of the fourth output inductor (L4) are connected to the voltage output terminal (VOUT). The control end of the third switch (S3) is connected to the control end of the first switch (S1), the control end of the third complementary switch (SR3) is connected to the control end of the first complementary switch (SR1), the control end of the fourth switch (S4) is connected to the control end of the second switch (S2), and the control end of the fourth complementary switch (SR4) is connected to the control end of the second complementary switch (SR2).

10. The power supply (10) according to any one of claims 1 to 9, wherein the first switch (S1), the first complementary switch (SR1), the second switch (S2) and the second complementary switch (SR2) comprise one of the following: a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, or a transistor.

11. A method for controlling a power supply (10), the power supply (10) comprising a step-down circuit (100), the step-down circuit (100) comprising a first switch (S1), a first complementary switch (SR1), a second switch (S2), a second complementary switch (SR2), a first capacitor (C1), a first output inductor (L1), and a second output inductor (L2), wherein a first end of the second switch (S2) is connected to a voltage input terminal (VIN) of the power supply (10), a second end of the second switch (S2) is connected to a first end of the first capacitor (C1), and a second end of the first switch (S1). The first end of the first switch (S1) is connected to the first end of the first complementary switch (SR1) and the first end of the first output inductor (L1), the second end of the first capacitor (C1) is connected to the first end of the second complementary switch (SR2) and the first end of the second output inductor (L2), the second end of the first complementary switch (SR1) and the second end of the second complementary switch (SR2) are grounded, and the second end of the first output inductor (L1) and the second end of the second output inductor (L2) are connected to the voltage output terminal (VOUT) of the power supply (10). The method comprises: Controlling the switching of the first switch (S1) using a first duty cycle; as well as The switching of the second switch (S2) is controlled by using a second duty cycle, and the switching period of the first switch (S1) is equal to the switching period of the second switch (S2). The first duty cycle is greater than 0.5, and the second duty cycle is equal to 0.

5.

12. The method according to claim 11, further comprising: The first switch is controlled to switch from open to closed for a period of half a cycle after the second switch (S2) is controlled to switch from open to closed.

13. The method according to claim 11, further comprising: Obtaining a reference output voltage and an input voltage of the voltage input terminal (VIN); determining a first duty cycle based on the reference output voltage and the input voltage; as well as In response to determining that the first duty cycle is greater than 0.5, the second duty cycle is determined to be 0.

5.

14. The method according to claim 13, further comprising: In response to determining that the first duty cycle is less than 0.5, the second duty cycle is determined to be equal to the first duty cycle.

15. The method according to claim 13, further comprising: detecting an output voltage at the voltage output terminal (VOUT); comparing the output voltage with the reference output voltage; In response to determining that the difference between the output voltage and the reference output voltage is greater than a predetermined threshold, the first duty cycle is determined based on a current input voltage and the reference output voltage.

16. The method of claim 13, wherein the first duty cycle is determined by the following formula: Where V in is the input voltage, V out is the reference output voltage, and D is the first duty cycle.

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