A bipolar adc static parameter dnl fast test method based on ATE

Abstract

The application discloses a bipolar ADC static parameter DNL fast test method based on ATE, belongs to the technical field of electronic component detection, and solves the problems of complex hardware structure or great software programming difficulty of the existing bipolar ADC static parameter test method. The method comprises the following steps: connecting a to-be-tested bipolar ADC to an ATE, and configuring a test condition for the to-be-tested bipolar ADC by the ATE; the test condition comprises positive and negative polarity test patterns; the number of test bits in the positive and negative polarity test patterns is n-1, and n is the number of bits of the bipolar ADC; the ATE respectively samples positive and negative polarity outputs of the to-be-tested bipolar ADC based on the positive and negative polarity test patterns; the positive and negative polarity output sampling does not include a highest bit digital output pin; based on the positive and negative polarity output sampling results and the number of test bits, the static parameter DNL of the to-be-tested bipolar ADC is acquired, and whether the static parameter DNL of the to-be-tested bipolar ADC passes the test is judged.

Description

Technical Field

[0001] This invention relates to the field of electronic component testing technology, and in particular to a rapid testing method for the static parameter DNL of a bipolar ADC based on ATE. Background Technology

[0002] An ADC is an interface circuit that converts analog signals into digital signals. DNL (Differential Nonlinearity) characterizes the difference between the actual output and the ideal conversion curve of the ADC, reflecting its conversion performance and serving as a crucial static parameter. DNL primarily represents the difference between the actual code step size and the theoretical code step size. Most ADCs are unipolar ADCs, meaning their analog input range is generally from GND to positive voltage. Bipolar ADCs, on the other hand, have an analog input range covering both negative and positive voltages. Bipolar ADCs offer excellent compatibility, requiring no signal conversion to match most bipolar drive and control circuits. However, due to their positive and negative input range, the digital code conversion pattern of a bipolar ADC output is no longer monotonous, exhibiting abrupt changes. Using ATE-based static testing methods for unipolar ADCs will result in significant errors in the test results, making it difficult to accurately measure DNL. Previously, there were two methods for testing the static parameters of bipolar ADCs:

[0003] First, it requires the use of an inverter's peripheral circuit design. This method can perfectly solve the problem of non-monotonous and discontinuous conversion curves. Automatic testing equipment can directly input the parameter formulas to calculate continuous conversion curves. However, this method requires modification of the ADC peripheral test loop, which increases hardware design costs and is quite cumbersome. It also has low compatibility with general-purpose ADC test adapters of the same series or type and is rarely used.

[0004] Secondly, without changing the typical ADC test loop design, the data output by the ADC each time is sampled into the register of the automatic test machine, and the sampled data of each step is inverted by the software algorithm. This method can also obtain a complete conversion curve, but it increases the difficulty of software programming, increases the software running time, is more cumbersome, and requires customized programs for the same series of ADCs, resulting in high development costs. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a rapid testing method for the static parameters (DNL) of bipolar ADCs based on ATE, in order to solve the problems of complex hardware structure or difficult software programming in existing bipolar ADC static parameter testing methods.

[0006] This invention discloses a fast method for testing the static parameters (DNL) of a bipolar ADC based on ATE, comprising:

[0007] The bipolar ADC under test is connected to the ATE, and the ATE configures the test conditions for the bipolar ADC under test; the test conditions include positive and negative polarity test patterns; the number of test bits in the positive and negative polarity test patterns is n-1, where n is the number of bits of the bipolar ADC;

[0008] The ATE performs positive and negative polarity output sampling on the bipolar ADC under test based on positive and negative polarity test patterns, respectively; neither the positive nor negative polarity output sampling includes the most significant bit of the digital output pin;

[0009] Based on the positive and negative polarity output sampling results and the number of test bits, the static parameters DNL of the bipolar ADC under test are obtained, and it is determined whether the static parameters DNL of the bipolar ADC under test have passed the test.

[0010] Based on the above solution, the present invention also makes the following improvements:

[0011] Furthermore, the positive polarity test pattern includes a positive polarity analog input stepped wave and a positive polarity output sampling pattern; the negative polarity test pattern includes a negative polarity analog input stepped wave and a negative polarity output sampling pattern.

[0012] The positive polarity analog input stepped wave has a value range from 0V to the maximum input voltage value of the bipolar ADC; the negative polarity analog input stepped wave has a value range from the minimum input voltage value of the bipolar ADC to 0V.

[0013] The positive and negative polarity analog input stepped waves and the positive and negative polarity output sampling patterns are both matched to the number of test bits.

[0014] Furthermore, the clocks of the positive polarity analog input stepped wave and the positive polarity output sampling pattern are synchronized, and the sampling frequency of the positive polarity output sampling pattern is not lower than the output frequency of the positive polarity analog input stepped wave.

[0015] Furthermore, the positive polarity output of the bipolar ADC under test is sampled by performing the following operations:

[0016] Send the positive polarity analog input staircase wave to the analog input pin of the bipolar ADC under test;

[0017] at the same time,

[0018] Based on the positive polarity output sampling pattern, perform positive polarity output sampling on the non-highest bit digital output pin of the bipolar ADC under test.

[0019] Furthermore, the clocks of the negative polarity analog input stepped wave and the negative polarity output sampling pattern are synchronized, and the sampling frequency of the negative polarity output sampling pattern is not lower than the output frequency of the negative polarity analog input stepped wave.

[0020] Furthermore, the negative polarity output of the bipolar ADC under test is sampled by performing the following operations:

[0021] Send the negative polarity analog input staircase wave to the analog input pin of the bipolar ADC under test;

[0022] at the same time,

[0023] Based on the negative polarity output sampling pattern, negative polarity output sampling is performed on the non-highest bit digital output pin of the bipolar ADC under test.

[0024] Furthermore, one LSB code width in the positive and negative polarity analog input staircase waves corresponds to k steps in the positive and negative polarity analog input staircase waves, and the number of steps in the positive and negative polarity analog input staircase waves is k*2. n-1 ;

[0025] The number of rows used for sampling in the positive and negative polarity output sampling patterns is equal to the number of steps (k*2) of the positive and negative polarity analog input stepped waves. n-1 ;

[0026] The total number of digital output pins used for sampling in the positive and negative polarity output sampling pattern is n-1; where bit 0 is the least significant bit of the digital output pin and bit n-2 is the most significant bit of the digital output pin.

[0027] Furthermore, obtain the static parameters (DNL) of the bipolar ADC under test:

[0028] The positive and negative polarity output sampling results and the number of test bits are respectively input into the DNL algorithm to obtain the static parameters DNL corresponding to the positive and negative polarities;

[0029] The larger value among the static parameters DNL corresponding to the positive and negative polarities is taken as the static parameter DNL of the bipolar ADC under test, and it is determined whether the static parameter DNL of the bipolar ADC under test passes the test.

[0030] Furthermore, the DNL algorithm is as follows:

[0031] The output sampling results are sequentially converted into decimal data and stored in an array data_num;

[0032] Calculate the absolute value of the deviation between each element in the array data_num and lsb, and take the deviation with the largest absolute value as max_err;

[0033] DNL = max_err / lsb;

[0034] Wherein, lsb represents the ideal number of sampling points for each code in the stepped wave.

[0035] Furthermore, the determination of whether the static parameter DNL of the bipolar ADC under test has passed the test includes:

[0036] If the static parameter DNL of the bipolar ADC under test is within the DNL criterion range, the static parameter DNL test of the bipolar ADC under test passes; otherwise, the static parameter DNL test of the bipolar ADC under test fails.

[0037] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0038] The present invention provides a rapid testing method for the static parameters DNL of bipolar ADCs based on ATE, which improves the existing testing methods. While ensuring the accuracy of the test results, it simplifies the testing process of the static parameters DNL of bipolar ADCs and improves the testing efficiency. It can quickly and accurately test the static parameters DNL of bipolar ADCs.

[0039] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0040] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0041] Figure 1 This is a schematic diagram of a typical unipolar ADC conversion curve;

[0042] Figure 2 This is a schematic diagram of the conversion characteristic curve of a bipolar ADC;

[0043] Figure 3 This is a flowchart of the rapid testing method for the static parameters DNL of a bipolar ADC based on ATE in an embodiment of the present invention;

[0044] Figure 4 This diagram illustrates the pin connections between the ATE and the bipolar ADC under test. Detailed Implementation

[0045] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0046] This invention is a rapid testing method for the DNL parameters of a bipolar ADC based on an ATE (Automatic Test Equipment). First, the background involved in this embodiment is explained as follows:

[0047] ADC static parameters describe the intrinsic characteristics of the device and the errors in its internal circuitry. Among these, differential nonlinearity (DNL) error is one of the most important test parameters for an ADC. The largest difference between two adjacent scale readings of an ADC is called differential nonlinearity (DNL). DNL describes the difference between the code conversion and the ideal state. A bipolar ADC has an analog voltage input range covering both positive and negative voltages; the analog input of a bipolar ADC swings between ±VFS. A unipolar ADC's analog input voltage swings between VFS and GND.

[0048] For DNL testing of unipolar ADCs, the general electrical testing method is to send a stepped voltage signal to the analog input pin of the ADC under test through an automatic test machine. After configuring the ADC's sample-and-hold, conversion rate, power supply conditions and other operating conditions, the input stepped wave is sampled and converted at a certain frequency and output. The test system can then plot the digital code conversion curve based on the output parallel or serial digital signal data, with the horizontal axis representing the number of sampling points and the vertical axis representing the digital code value. Figure 1 This is a typical schematic diagram of a unipolar ADC conversion curve. After the conversion curve is plotted, the data on the curve is calculated using formulas. According to the definition of DNL formulas, the DNL parameter values ​​are calculated, and then it is determined whether the DNL parameters meet the requirements of the technical manual. However, because the output range of a bipolar ADC spans "0V", its conversion curve is non-monotonic. Directly applying the DNL test method for unipolar ADCs to the test system will result in distorted results at non-monotonic conversion points in the DNL formula, thus affecting the actual conversion error test.

[0049] This embodiment uses the AD7899-3, a typical bipolar ADC, as an example for illustration. The AD7899-3 is a 14-bit, successive approximation parallel output, differential input bipolar ADC with a bipolar input range of ±2.5V. During testing or application, VINA is connected to the analog signal input, and VINB is left empty. The digital code changes at the middle position of each least significant bit (LSB) (e.g., 1 / 2 LSB, 3 / 2 LSBs, 5 / 2 LSBs, etc.). For a 14-bit ADC, its LSB = FSR / 16384, i.e., 1 LSB = 5V / 16384 = 610.4μV. FSR represents the full-scale voltage. Taking the AD7899-3 as an example, its ideal input-output conversion relationship is shown in Table 1.

[0050] Table 1 Ideal Input-Output Conversion Relationship of AD7899-3

[0051]

[0052] As shown in Table 2, within the analog input range of -2.5V to 0V, there is a linear correspondence between analog input and digital output. Specifically, a -2.5V analog input corresponds to the digital output code 10 0000 0000 0000, and GND (0V) corresponds to a linear change between 11 1111 11111111. Within the analog input range of 0V to 2.5V, there is also a linear correspondence between analog input and digital output. An analog input of 0V corresponds to the digital output code 00 0000 0000 0000, and an analog input of 2.5V corresponds to the digital output code 01 1111 1111 1111. However, around 0V, there is a sudden change in the output digital code. The digital code from negative 0V to positive 0V changes directly from the maximum digital code 11 1111 1111 1111 to the minimum digital code 00 0000 0000 0000. When the analog input is around (0V-610.4uV), the digital output will change from 11 1111 1111 11111 to 00 0000 0000 0000. When the analog input is around (0V+610.4uV), the digital output will change from 00 0000 0000 0000 to 00 0000 0000001.

[0053] The specific diagram illustrating the digital output code conversion from -2.5V to 2.5V is as follows: Figure 2 As shown, Figure 2 The horizontal axis represents the analog input, and the vertical axis represents the digital output code, having already converted the binary value to a decimal value. The corresponding unipolar ADC conversion characteristics are as follows: Figure 1As shown, it is clear that the ideal conversion characteristics of a bipolar ADC differ from those of a unipolar ADC. The main reason for this is that the most significant bit of the digital output pin of a bipolar ADC is a flag bit. According to the rules of two's complement, this flag bit is 1 when the value is negative and 0 when the value is positive, resulting in a discontinuous conversion curve. Therefore, to test the static parameters of a bipolar ADC, an inverter needs to be connected to the most significant bit of the digital output pin in hardware, or the level of the most significant bit of the digital output pin needs to be inverted in the software program for each sampled value. This ensures that the digital output binary code continuously converts from 00 0000 0000 0000 to 10 0000 0000 0000, guaranteeing that the conversion curve from negative full-code input to positive full-code input is continuous and monotonic. The curve can then be substituted into the DNL formula for calculation.

[0054] The problem with these two methods is that testing peripheral circuits requires additional hardware, which increases the design difficulty of the test adapter and the testing cost; or the software algorithm requires numerical calculations, which increases the complexity of the program, especially for serial output bipolar ADCs, where the array inversion calculation needs to be completed in a loop, which greatly increases the overall test time.

[0055] To address the aforementioned issues, this embodiment provides a rapid DNL (Dual Parameter Listing) test method for the static parameters of a bipolar ADC based on ATE (Automatic Test Equipment). The flowchart is shown below. Figure 3 As shown, it includes the following steps:

[0056] Step S1: Connect the bipolar ADC under test to the ATE. The ATE configures the test conditions for the bipolar ADC under test. The test conditions include positive and negative polarity test patterns. The number of test bits in the positive and negative polarity test patterns is n-1, where n is the number of bits in the bipolar ADC.

[0057] Step S2: The ATE performs positive and negative polarity output sampling on the bipolar ADC under test based on the positive and negative polarity test patterns respectively; the positive and negative polarity output sampling does not include the most significant bit of the digital output pin;

[0058] Step S3: Based on the positive and negative polarity output sampling results and the number of test bits, obtain the static parameters DNL of the bipolar ADC under test, and determine whether the static parameters DNL of the bipolar ADC under test have passed the test.

[0059] Preferably, the above testing process assumes that the digital output pins used in the test are in normal working condition. If they are in normal working condition, the subsequent DNL test process is meaningful; if the digital output pins are in abnormal working condition, the subsequent DNL test process is meaningless, and in this case, the bipolar ADC static parameter DNL test can be considered to have failed. Specifically,

[0060] Before performing positive and negative polarity output sampling, the ATE first tests the high and low levels of the digital output pins in the bipolar ADC.

[0061] If the high and low level output tests pass, then positive and negative polarity output sampling is performed;

[0062] If the high and low level output tests fail, the bipolar ADC static parameter DNL test will also fail.

[0063] Specifically, step S1 includes:

[0064] Step S11: Connect the bipolar ADC under test to the ATE; specifically, design a test adapter for a general test loop of the bipolar ADC (no inverter hardware required); the test adapter is used to realize the adaptation and conversion between the bipolar ADC under test and the ATE; and plug the wiring from the ADC under test to the test adapter, and connect it to the corresponding hardware resources of the ATE through the test adapter.

[0065] In step S11, the test adapter design refers to the technical manual requirements of the bipolar ADC under test. Generally, the analog input pins, digital input pins, digital output pins, power supply, ground, and other pins of the bipolar ADC under test need to be led out and wired (PCB traces) as required. These wires need to be plugged into the test adapter and connected to the corresponding hardware resources of the ATE through the test adapter. The use of the test adapter facilitates engineering applications and modular development.

[0066] The analog input pins are connected to the AWG resources in the ATE via corresponding pins on the test adapter. The digital input pins serve as timing and logic control pins for the positive and negative polarity test patterns, and are connected to the ATE's digital resource DCM via corresponding pins on the test adapter. The digital output pins serve as output pins for the positive and negative polarity test patterns, and are connected to the ATE's digital channel resources via corresponding pins on the test adapter. Power and ground need to be connected to the automatic test machine's power ground loop. Furthermore, for some hardware settings requirements, such as shorting pins to ground or VCC, design them according to the manual. For the decoupling, voltage regulation, and differential circuit requirements needed for testing, design the corresponding capacitors, inductors, and other peripheral circuits (the function of the peripheral circuits is to stabilize the test waveform, stabilize the power supply, and make the test waveform more stable for easier measurement). Special attention should be paid to the connection of the digital output pins. In the usual hardware testing method for bipolar ADCs, the highest digital output pin is connected to an inverter before it can be connected to the test equipment. However, in this invention, the highest digital output pin can be directly connected to the test equipment, which is equivalent to the test connection method for unipolar ADCs.

[0067] After installing the aforementioned test adapter onto the automated test bench, determine the hardware resource connection configuration in the automated test bench according to the test adapter and device manual, and perform corresponding pin definition programming in the test software; complete the detailed definition of each pin of the ADC under test in the test bench, ensuring a one-to-one correspondence between resource channels and pins of the device under test, thus achieving a complete connection between the automated test bench and the hardware of the device under test, such as... Figure 4 As shown. Among them, AWG, DCM, and PVI are the analog, digital, and power resources of the automatic testing machine.

[0068] Step S12: The ATE configures the test conditions for the bipolar ADC under test; the test conditions include:

[0069] (1) Positive and negative polarity test pattern

[0070] The positive polarity test pattern includes a positive polarity analog input stepped waveform and a positive polarity output sampling pattern; the negative polarity test pattern includes a negative polarity analog input stepped waveform and a negative polarity output sampling pattern; the value range of the positive polarity analog input stepped waveform is from 0V to the maximum input voltage value of the bipolar ADC; the value range of the negative polarity analog input stepped waveform is from the minimum input voltage value of the bipolar ADC to 0V; the positive and negative polarity analog input stepped waveforms and the positive and negative polarity output sampling patterns are all matched to the number of test bits.

[0071] The positive polarity analog input stepped wave and the positive polarity output sampling pattern are clock-synchronized, and the sampling frequency of the positive polarity output sampling pattern is not lower than the output frequency of the positive polarity analog input stepped wave.

[0072] (2) Other general configurations, such as power-on sequence, input high and low levels, clock rate, conversion mode and other general requirements;

[0073] This is a general test procedure. Programming can be done by referring to the datasheet of the device under test (DUT). The programming language is the same as the software used by the automated test machine, typically C++ or OTPL. The implementation steps of the test program are as follows: Specifically:

[0074] a. Open the test machine software, run the test software, and enter the programming interface;

[0075] b. According to the technical manual requirements, write the test conditions such as power-on sequence, input high and low levels, clock rate, and switching mode;

[0076] C is used to compile programming files to make the program callable.

[0077] Write software programs to define DNL test parameters. Based on the device under test (DUT) datasheet, control the output frequency, number of output points, and output voltage range of the automated test machine's analog input AWG signals (i.e., positive and negative polarity analog input stepped waves). Synchronize the clocks of the positive and negative analog input stepped waves and their corresponding output sampling patterns. Write conversion sampling test programs for the two sets of DNL AWG control sampling patterns (positive and negative polarity output sampling patterns, i.e., two sets of conversion sampling programs from the minimum input voltage value of the bipolar ADC to 0V and from 0V to the maximum input voltage value of the bipolar ADC).

[0078] The specific implementation steps are as follows:

[0079] Enter the programming interface and set the analog input stepped waveform. The stepped waveform serves as the input to the conversion curve and requires two sets: one set from the minimum input voltage of the bipolar ADC to 0V (i.e., negative polarity analog input stepped waveform), and the other set from 0V to the maximum input voltage of the bipolar ADC (i.e., positive polarity analog input stepped waveform). Depending on the sampling requirements, the stepped waveform generally needs a large number of repetition points per conversion code width (to improve calculation accuracy). Here, you can set an AWG output of 40 analog voltage points for one LSB code width (generally one step corresponds to one code width, sometimes multiple steps correspond to one code width). (This can be adjusted according to the actual system memory capacity, but should not be less than 10 points). Note that the number of steps in the two AWG stepped waveforms should be increased from the 2 required for an n-bit ADC. n 2 required to change to an n-1 bit ADCn-1 That is, the sum of the two segments is still 2. n The number of steps is consistent with the total number of conversion codes of an n-bit ADC. At this point, the input signal of the ADC can be regarded as the full voltage range input of two n-1 bit ADCs, which has initially met the requirements of the static parameter calculation formula of the linear histogram.

[0080] One LSB code width in the positive and negative polarity analog input staircase waves corresponds to k steps in the positive and negative polarity analog input staircase waves, and the number of steps in the positive and negative polarity analog input staircase waves is k*2. n-1 The number of rows used for sampling in the positive and negative polarity output sampling patterns is equal to the number of steps (k*2) of the positive and negative polarity analog input stepped waves. n-1 The total number of digital output pins used for sampling in the positive and negative polarity output sampling patterns is n-1; where bit 0 is the least significant bit of the digital output pin and bit n-2 is the most significant bit. Based on the resolution of the device under test (DUT) and the resource resolution of the ATE, one LSB is divided into k steps, where k is an integer; therefore, the value of k is adaptively set according to actual test requirements, the resolution of the bipolar ADC under test, and the resource resolution of the ATE.

[0081] b. Set the output frequency for the two AWG stepped waves according to the manual requirements;

[0082] c. According to the manual, set the conversion timing of all ADC output pins and the sampling frequency of the automatic test machine for the output pins. The sampling frequency of the output pins should be no less than the output frequency of the AWG staircase wave to ensure no missed points.

[0083] In the test software, two sets of ADC static parameter test sampling patterns are used. The highest digital bit pin is set to "X" (i.e., not sampled), while the other digital bits are still sampled according to the normal conversion timing. (It should be noted that this does not mean that the highest digital output pin is not connected to hardware resources, because the state of the highest digital output pin still needs to be evaluated when testing parameters such as output level. Instead, the vector capture state in the static parameter test sampling pattern needs to be changed. Usually, the vector state of the digital output pin should be L / H, i.e., the low-high comparison edge state.)

[0084] The specific implementation steps are as follows:

[0085] Enter the pattern programming interface and set the vector models of each input and output pin (NRZ, RTZ, etc.);

[0086] b. Enter the pattern programming interface and draw two sets of AWG waveform sampling vector patterns according to the frequency and timing requirements.

[0087] Enter the pattern programming interface and set the CTV sampling edge of the two patterns. Except for setting the sampling action of the highest bit of the digital output pin to "X" (no comparison) in each step, the other digital pins are set normally, generally as low trigger edge comparison (L edge).

[0088] After the above settings are completed, step S2 can be executed. Specifically,

[0089] (1) Positive polarity output sampling:

[0090] The positive polarity output of the bipolar ADC under test is sampled by performing the following operations:

[0091] Send the positive polarity analog input staircase wave to the analog input pin of the bipolar ADC under test;

[0092] at the same time,

[0093] Based on the positive polarity output sampling pattern, perform positive polarity output sampling on the non-highest bit digital output pin of the bipolar ADC under test.

[0094] (2) Negative polarity output sampling:

[0095] The negative polarity output of the bipolar ADC under test is sampled by performing the following operations:

[0096] Send the negative polarity analog input staircase wave to the analog input pin of the bipolar ADC under test;

[0097] at the same time,

[0098] Based on the negative polarity output sampling pattern, negative polarity output sampling is performed on the non-highest bit digital output pin of the bipolar ADC under test.

[0099] It should be noted that this embodiment does not impose any restrictions on the order of sampling positive and negative polarity outputs.

[0100] In step S3, the static parameters DNL of the bipolar ADC under test are obtained by performing the following operations:

[0101] Step S31: Input the positive and negative polarity output sampling results and the number of test bits into the DNL algorithm respectively to obtain the static parameters DNL corresponding to the positive and negative polarities;

[0102] The DNL algorithm is as follows: The output sampling results are sequentially converted into decimal data and stored in an array `data_num`; the absolute value of the deviation between each element in the `data_num` array and `lsb` is calculated, and the deviation with the largest absolute value is taken as `max_err`; DNL = max_err / `lsb`; where `lsb` represents the ideal number of sampling points for each code in the stepped wave. Specifically, the execution process of the DNL algorithm can be described as follows:

[0103] Step S311: Convert the output sampling results into decimal data sequentially and store them in an array data_num;

[0104] Step S312: Let i = 1, diff_err[1] = data_num[1] - lsb, max_err = diff_err[1];

[0105] Step S313: If fabs(diff_err[i]) > fabs(max_err),

[0106] Then max_err=diff_err[i], i=i+1; otherwise, i=i+1;

[0107] Step S314: If i ≤ k*2 n-1 Calculate diff_err[i] = data_num[i] - lsb, and jump to step S313; otherwise, go to step S315.

[0108] Step S315: DNL = max_err / lsb;

[0109] Wherein, lsb represents the ideal number of sampling points for each code in the stepped wave.

[0110] Step S32: Take the larger value of the static parameters DNL corresponding to the positive and negative polarities as the static parameter DNL of the bipolar ADC under test, and determine whether the static parameter DNL of the bipolar ADC under test has passed the test.

[0111] The determination of whether the static parameter DNL of the bipolar ADC under test has passed the test includes: if the static parameter DNL of the bipolar ADC under test is within the criterion range of the static parameter DNL of the bipolar ADC under test, then the static parameter DNL test of the bipolar ADC under test has passed; otherwise, the static parameter DNL test of the bipolar ADC under test has failed.

[0112] In summary, the rapid testing method for the static parameters DNL of bipolar ADCs based on ATE provided by this invention improves upon existing testing methods. While ensuring the accuracy of test results, it simplifies the testing process for the static parameters DNL of bipolar ADCs and improves testing efficiency, enabling rapid and accurate testing of the static parameters DNL of bipolar ADCs.

[0113] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0114] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A rapid testing method for the static parameters of a bipolar ADC using differential nonlinearity (DNL) based on an automated test equipment (ATE), characterized in that, include: The bipolar ADC under test is connected to an automated test equipment (ATE). The ATE configures the test conditions for the bipolar ADC under test. The test conditions include a positive polarity test pattern and a negative polarity test pattern. The number of test bits in the positive polarity test pattern and the negative polarity test pattern is n-1, where n is the number of bits in the bipolar ADC. The automated test equipment (ATE) performs positive and negative output sampling on the bipolar ADC under test based on the positive and negative polarity test patterns, respectively; neither the positive nor negative output sampling includes the most significant bit of the digital output pin. Based on the positive polarity output sampling results and the number of test bits, the differential nonlinearity (DNL) of the static parameter of the bipolar ADC under test is obtained, and it is determined whether the differential nonlinearity (DNL) of the static parameter of the bipolar ADC under test has passed the test. The positive polarity test pattern includes a positive polarity analog input stepped wave and a positive polarity output sampling pattern; the negative polarity test pattern includes a negative polarity analog input stepped wave and a negative polarity output sampling pattern. The positive polarity analog input stepped wave has a value range from 0V to the maximum input voltage value of the bipolar ADC; the negative polarity analog input stepped wave has a value range from the minimum input voltage value of the bipolar ADC to 0V. The positive polarity analog input stepped wave, the negative polarity analog input stepped wave, the positive polarity output sampling pattern, and the negative polarity output sampling pattern are all matched with the number of test bits.

2. The rapid testing method for static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 1, characterized in that, The positive polarity analog input stepped wave and the positive polarity output sampling pattern are clock-synchronized, and the sampling frequency of the positive polarity output sampling pattern is not lower than the output frequency of the positive polarity analog input stepped wave.

3. The rapid testing method for the static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 2, characterized in that, The positive polarity output of the bipolar ADC under test is sampled by performing the following operations: Send the positive polarity analog input staircase wave to the analog input pin of the bipolar ADC under test; at the same time, Based on the positive polarity output sampling pattern, perform positive polarity output sampling on the non-highest bit digital output pin of the bipolar ADC under test.

4. The rapid testing method for the static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 3, characterized in that, The negative polarity analog input stepped wave and the negative polarity output sampling pattern are clocked synchronously, and the sampling frequency of the negative polarity output sampling pattern is not lower than the output frequency of the negative polarity analog input stepped wave.

5. The rapid testing method for the static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 4, characterized in that, The negative polarity output of the bipolar ADC under test is sampled by performing the following operations: Send the negative polarity analog input staircase wave to the analog input pin of the bipolar ADC under test; at the same time, Based on the negative polarity output sampling pattern, negative polarity output sampling is performed on the non-highest bit digital output pin of the bipolar ADC under test.

6. The rapid testing method for the static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to any one of claims 1-5, characterized in that, One LSB code width in the positive and negative analog input staircase waves corresponds to k steps in the positive and negative analog input staircase waves, respectively, and the number of steps in the positive and negative analog input staircase waves is k*2. n-1 ; The number of rows used for sampling in the positive polarity output sampling pattern and the negative polarity output sampling pattern is equal to the number of steps k*2 of the positive polarity analog input stepped wave and the negative polarity analog input stepped wave. n-1 ; The total number of digital output pins used for sampling in the positive polarity output sampling pattern and the negative polarity output sampling pattern is n-1; where bit 0 is the least significant bit of the digital output pin and bit n-2 is the most significant bit of the digital output pin.

7. The rapid testing method for static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 6, characterized in that, Obtain the differential nonlinearity (DNL) of the static parameters of the bipolar ADC under test: The positive polarity output sampling results and test bit depth, and the negative polarity output sampling results and test bit depth are respectively input into the differential nonlinear DNL algorithm to obtain the static parameter differential nonlinear DNL corresponding to the positive polarity and negative polarity. The larger value in the static parameter differential nonlinearity DNL corresponding to positive and negative polarity is taken as the static parameter differential nonlinearity DNL of the bipolar ADC under test, and it is determined whether the static parameter differential nonlinearity DNL of the bipolar ADC under test passes the test.

8. The rapid testing method for the static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 7, characterized in that, The differential nonlinear DNL algorithm is as follows: The output sampling results are sequentially converted into decimal data and stored in an array data_num; Calculate the absolute value of the deviation between each element in the array data_num and lsb, and take the deviation with the largest absolute value as max_err; Differential nonlinear DNL = max_err / lsb; Wherein, lsb represents the ideal number of sampling points for each order of code in the positive polarity analog input staircase wave or the negative polarity analog input staircase wave.

9. The rapid testing method for static parameter differential nonlinearity (DNL) of a bipolar ADC based on an automated test equipment (ATE) according to claim 8, characterized in that, Determining whether the differential nonlinearity (DNL) of the static parameters of the bipolar ADC under test passes the test includes: If the differential nonlinearity (DNL) of the static parameters of the bipolar ADC under test is within the criterion range of the differential nonlinearity (DNL) of the static parameters of the bipolar ADC under test, then the differential nonlinearity (DNL) test of the static parameters of the bipolar ADC under test passes; otherwise, the differential nonlinearity (DNL) test of the static parameters of the bipolar ADC under test fails.

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