Cloud measurement and control system and method based on real-time cloud computing architecture

Abstract

The present invention discloses a cloud measurement and control system and method based on a real-time cloud computing architecture, belonging to the field of the combination of aerospace measurement and control and cloud computing, including a real-time and non-real-time separation processing module, a transmission module, and a zero-copy module between measurement and control data threads; the real-time and non-real-time separation processing module includes an intelligent acceleration card of the FPGA type; the transmission module includes a first data structure module, a data synchronization module, and a real-time guarantee processing module; the zero-copy module between measurement and control data threads includes a large-page circular queue and a second data structure module. The present invention realizes the generalization of software and hardware, and the cloudification of measurement and control technology, which can enable the reuse of resources, reduce the development and maintenance costs, and accelerate the iteration speed.

Description

Technical Field

[0001] The present invention relates to the field of the combination of space TT&C and cloud computing. More specifically, it relates to a cloud TT&C system and method based on a real-time cloud computing architecture. Background Art

[0002] With the increasing number of space launch missions, the number of satellites in orbit has increased exponentially. At the same time, with the promotion and implementation of the civil-military integration policy, the national defense and military aerospace has gradually expanded to the civilian and commercial fields, and commercial aerospace has developed vigorously. The 5G technology has advanced rapidly, and China has also made significant progress in building a space-ground integrated network. All of these have put higher and higher requirements on the original space TT&C system. The development of the new generation of ground TT&C system not only has technical characteristics such as multi-target, multi-task, high bandwidth, low latency, high rate, and networking, but also needs to have the characteristics of information resource development and sharing, unified management, and unified scheduling, and increasingly pays attention to resource integration and efficient use. The traditional technical solutions are difficult to meet the development needs. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a cloud TT&C system and method based on a real-time cloud computing architecture, which realizes the generalization of software and hardware, realizes the cloudification of TT&C technology, and can make resources reused, reduce the development and maintenance costs, and accelerate the iteration speed, etc.

[0004] The purpose of the present invention is achieved through the following solutions:

[0005] A cloud TT&C system based on a real-time cloud computing architecture includes a real-time and non-real-time separation processing module, a transmission module, and a zero-copy module between measurement and control data threads;

[0006] The real-time and non-real-time separation processing module includes an FPGA-type intelligent acceleration card. The FPGA is used to control the accuracy of data transceiver. At the same time, the buffer size is set for the uplink transmission of the FPGA to buffer the data transmission between the acceleration card and the CPU; the capture and decoding are placed on the FPGA-type intelligent network card, and the FPGA parallel computing is used for capture and decoding to unload the pressure of the CPU;

[0007] The transmission module includes a first data structure module, a data synchronization module, and a real-time guarantee processing module;

[0008] The zero-copy module between measurement and control data threads includes a large-page circular queue and a second data structure module, and realizes the zero-copy between measurement and control data threads through the combination of the large-page circular queue and the second data structure.

[0009] Further, in the real-time and non-real-time separation processing module, the non-real-time data is modulated, demodulated, data frames are generated, and the data is reported to the CPU for processing.

[0010] Furthermore, in the design of the first data structure module, it includes an accelerator ID, a counter, a timestamp, and a data length. Among them, the accelerator ID is used to distinguish different acceleration resource information and determine the source of the data. The counter is used to continuously count the data. The downlink data count is filled in by the radio frequency front-end device and detected on the cloud platform side. The uplink data count is filled in on the cloud platform side and detected on the accelerator card and radio frequency front-end. Whether there is a packet loss phenomenon is judged according to the detection situation of the bilateral data, and an alarm is reported. The timestamp is used to determine the time information, a reception timestamp is marked when the data is received, and a transmission timestamp is marked when the data is sent. The data length is used to adapt to data transmissions of different lengths.

[0011] Furthermore, in the design of the data synchronization module, two variable detections of a low water level line and a high water level line are set up to complete data reception and transmission synchronization, which is used to ensure the data reliability and real-time performance between the CPU and the acceleration resources.

[0012] Furthermore, the real-time performance guarantee processing module includes the following processing of the modulation, demodulation, and data reception and transmission processes on the CPU side: isolate a certain CPU core, turn off the scheduling and interrupts on it, and bind the key threads to the core to ensure the minimum delay fluctuation; set the data reception and transmission network card queuing priority of the key threads to the highest to ensure data real-time performance; use the DMA method to realize the data transmission between the CPU and the intelligent accelerator card to speed up; allocate a separate memory mapping to avoid time fluctuations caused by memory preemption.

[0013] Furthermore, in the design of the large page circular queue, large pages are allocated and memory resources are allocated to the application program through a memory pool. In the initialization stage, the memory pool obtains memory resources from the large pages. In the program running stage, the application program directly obtains memory resources through the memory pool, and the memory pool is responsible for memory management, so that the data delay is reliable and there will be no data fluctuations caused by memory preemption.

[0014] Furthermore, in the design of the second data structure, it includes a data type, a data length, and a sequence number. The data type is used to describe the data type of the current step. The data length is used to describe the effective length of the data segment. The sequence number is used to describe the steps processed in the current pipeline.

[0015] Furthermore, the two variable detections of the low water level line and the high water level line set up to complete the data reception and transmission synchronization include the following detection processes: when the detection program finds that the data cached in the accelerator card is lower than the water level line, 2 packets of data are sent each time; when the data cache is between the low water level line and the high water level line, 1 packet of data is sent each time; when the data cache is higher than the high water level line, the data transmission is suspended.

[0016] Furthermore, based on the design of the second data structure, it includes: after the current processing thread receives the processing signal, it directly reads the position in the circular queue according to the current thread counter, and uses a pointer to point to the data in the queue, and directly performs calculations without copying the data; based on pointer operations, the calculated data will also directly modify the data in the memory of the circular queue without copying. After the calculation is completed, the corresponding serial number ID is modified, and then a signal is sent to the next thread for processing. The entire process will not perform repeated copying of measurement and control data.

[0017] A cloud measurement and control method based on a real-time cloud computing architecture, based on any of the cloud measurement and control systems based on a real-time cloud computing architecture as described above, further comprising the following steps:

[0018] S1, data transmission and reception are implemented in FPGA acceleration resources. FPGA is used to ensure controllable data delay, and time tags are added in FPGA acceleration resources to ensure the time accuracy requirements of subsequent processing;

[0019] S2, after the data receiving and processing is completed, the capture algorithm is directly passed to the capture module for calculation. After the capture module completes the calculation, the capture result is passed to the data synchronization module of the CPU;

[0020] S3, the data synchronization module sends the uplink data generated by the data modulation module to the acceleration resource while receiving the downlink data;

[0021] S4, after receiving the captured data, the demodulation module performs demodulation processing, the demodulation includes code synchronization, carrier synchronization, bit synchronization, and multi-thread processing is adopted, and the data transmission between the multi-thread threads is completed by the zero-copy module between the measurement and control data threads;

[0022] S5, sending the demodulated data to the FPGA acceleration resource for decoding processing;

[0023] S6, after decoding is completed, it is sent to the CPU to form a data frame and sent to the application system.

[0024] The beneficial effects of the present invention include:

[0025] (1) The measurement and control data processing architecture provided by the technical solution of the present invention can meet the requirements of traditional measurement and control technology for real-time performance and large data flow, subverting the traditional measurement and control architecture, and the architecture can also run on a private cloud computing platform.

[0026] (2) The real-time and non-real-time separation processing technical solution of the present invention solves the problems of large CPU delay and weak processing capability.

[0027] (3) Through the data structure, thread processing optimization solution, and data synchronization solution of the present invention, the reliability and real-time performance between the CPU and acceleration resources can be ensured.

[0028] (4) By using the reasonable data transfer structure and large page cache solution designed between threads in the present invention, zero-copy between threads is achieved, greatly improving throughput and real-time performance.

[0029] (5) The present invention realizes the generalization of software and hardware and the cloudification of measurement and control technology, which can enable the reuse of resources, reduce development and maintenance costs, and accelerate the iteration speed, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a partition processing architecture for real-time and non-real-time of the embodiments of the present invention;

[0032] Figure 2 It is a schematic diagram of the data structure of the embodiments of the present invention;

[0033] Figure 3 It is a schematic diagram of data synchronization of the embodiments of the present invention;

[0034] Figure 4 It is a schematic diagram of zero-copy between measurement and control data threads of the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] All the features disclosed in all the embodiments in this specification, or all the steps in the methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended, replaced in any way.

[0036] In view of the problems in the background, the technical concept of the present invention adopts a cloud computing architecture, conducts research on virtual baseband pool technology based on real-time cloud computing, forms a cloudified space ground measurement, transportation and control system, which can improve the comprehensive utilization efficiency of the ground system, reduce operating costs, conform to the trend of the times, promote the innovation and upgrading of the space industry, and create a new business model. It is an inevitable trend in the development of future military space equipment and the integration technology of civil and military in commercial space. However, after further thinking, the inventors of the present invention found that due to the large data flow, high resource occupancy, and strong real-time requirements of measurement and control algorithms, the convenience brought by simply using a cloud computing architecture cannot meet the requirements of the measurement and control system.

[0037] Therefore, after further consideration, the technical solution of the present invention proposes a new cloud measurement and control system based on a real-time cloud computing architecture, aiming to use cloud measurement and control technology based on the cloud computing architecture to solve the above technical problems under the cloud architecture and achieve comprehensive measurement and control cloudification.

[0038] The technical solution of the present invention includes a real-time and non-real-time separation processing module, a transmission module, and a zero-copy module for measurement and control data between threads.

[0039] In the real-time and non-real-time separation processing module, to meet the characteristics of high real-time requirements and large computational volume in measurement and control under the cloud computing architecture, a partition processing architecture for real-time and non-real-time measurement and control algorithms as shown in Figure 1 is designed. As can be seen from Figure 1 , for data transmission and reception with very high real-time requirements, it is placed on an FPGA-type intelligent acceleration card, and the FPGA is used to control the accuracy of data transmission and reception in terms of time. At the same time, the buffer size of the uplink transmission of the FPGA is set to buffer the data transmission between the acceleration card and the CPU. Capturing and decoding with a large computational volume are placed on an intelligent network card with an FPGA type. Utilizing the advantage of parallel computing of the FPGA, fast capturing and decoding are carried out to fully unload the pressure on the CPU. The non-real-time data modulation, demodulation, data frame generation, and data reporting module are processed by the CPU, making full use of the multi-core technology of the CPU.

[0040] In the transmission module, when transmitting data between the acceleration resource and the CPU, due to CPU scheduling problems, delay fluctuations will occur. If the data is not transmitted to the intelligent acceleration network card within a certain time range, it will cause the acceleration resource buffer to be empty, resulting in packet loss problems. To solve this technical problem, the following design is carried out:

[0041] Design a data structure as shown in Figure 2 , including accelerator ID, counter, timestamp, and data length. Among them, the accelerator ID is used to distinguish different acceleration resource information and determine the source of the data. The counter is used to continuously count the data. The downlink data count is filled in by the radio frequency front-end device and detected on the cloud platform side; the uplink data count is filled in on the cloud platform side and detected on the acceleration card and radio frequency front-end. Whether there is a packet loss phenomenon can be known based on the detection of bilateral data, and an alarm report is made. The timestamp is used to determine the time information. Since the acceleration resource time is relatively accurate and reliable, a reception timestamp will be marked when the data is received, and a transmission timestamp will be marked when the data is sent for accurate delay detection. The data length is used to adapt to data transmissions of different lengths.

[0042] In the data synchronization design, in order to ensure that the accelerated resource data cache is maintained at an appropriate position, two variables, namely the low water level line and the high water level line, are set for detection to complete data sending and receiving synchronization, ensuring data reliability and real-time performance between the CPU and the accelerated resources. The detection process is as follows: when the detection program finds that the cache data of the acceleration card is lower than the water level line, 2 packets of data are sent each time; when the data cache is between the low water level line and the high water level line, 1 packet of data is sent each time; when the data cache is higher than the high water level line, data sending is suspended. As Figure 3 shown.

[0043] In the real-time performance guarantee design, although the system separates real-time and non-real-time processing, there are still a large number of multi-threaded parallel computing requirements on the CPU side. Therefore, it is necessary to improve the computing real-time performance on the CPU side. For this reason, the following designs are carried out for the modulation, demodulation, data sending and receiving and other modules on the CPU side:

[0044] 1) Isolate a certain CPU core, turn off the scheduling and interrupts on it, and bind the critical threads to the core to ensure the minimum delay fluctuation.

[0045] 2) Set the highest queuing priority for the data sending and receiving network card of this thread to ensure data real-time performance.

[0046] 3) Use the DMA method to realize the data transmission between the CPU and the intelligent acceleration card to speed up.

[0047] 5) Allocate a separate memory mapping to avoid time fluctuations caused by memory preemption.

[0048] In the zero-copy module between measurement and control data threads, when the measurement and control data is processed by pipeline multi-threads on the CPU side, data transmission is involved between different threads. Due to the large amount of measurement and control data, if methods such as queues are used, it will involve a large amount of data transmission and copying processes, increasing the CPU load and greatly increasing the delay. To solve this problem, the zero-copy technology between measurement and control data threads is invented, which realizes this function through the combination of a large page circular queue and the corresponding data structure, as Figure 4 shown.

[0049] The following problems exist in the traditional memory allocation scheme using the malloc() function:

[0050] (1) malloc() has the problem of lazy allocation, that is, when the program runs to the malloc() function, the system does not allocate memory at this statement position, but delays it until the program first uses this memory to actually allocate memory;

[0051] (2) malloc() obtains memory resources from a 4KB memory page. For a protocol stack that requires a lot of memory resources, this will generate a large number of paging operations, reducing system performance.

[0052] (3) malloc() needs to be used in conjunction with free(). In large-scale application development, memory management is difficult and time-consuming.

[0053] In order to avoid the overhead generated by malloc(), large page allocation is used, and memory resources are allocated to the application through the memory pool. In the initialization phase, the memory pool obtains sufficient memory resources from the large page. In the program running phase, the application directly obtains memory resources through the memory pool, and the memory pool is responsible for memory management, so that data latency is reliable and data fluctuations caused by memory preemption will not occur. The composition of the large page cache applied is as follows: Figure 4 The circular queue shown is used by the system.

[0054] In terms of data structure design, the large page circular queue solves the problem of repeated application for memory release. In order to realize the zero copy technology of measurement and control data, it is necessary to design a reasonable data structure to support it, such as Figure 4 As shown, the data type is used to describe the data of the current step, such as float, int, double, etc.; the data length is used to describe the effective length of the data segment; and the serial number is used to describe the steps processed in the current pipeline.

[0055] After the current processing thread receives the processing signal, it directly reads the position in the circular queue according to the current thread counter, and uses a pointer to point to the data in the queue, without copying the data. Due to the pointer operation, the calculated data will also directly modify the data in the memory of the circular queue without copying. After the calculation is completed, the corresponding serial number ID is modified, and then a signal is sent to the next thread for processing. The whole process will not duplicate the measurement and control data.

[0056] like Figure 1 As shown, the entire architecture algorithm based on the technical solution of the present invention is divided into a real-time part and a non-real-time part, and they are deployed separately in the following manner:

[0057] Data transmission and reception are delegated to FPGA acceleration resources, which can strictly ensure that data delay is controllable, and time tags are added to the FPGA acceleration resources to ensure the time accuracy requirements of subsequent processing.

[0058] The capture algorithm has a large amount of calculation, occupies a lot of resources, and has a short time requirement. After the data is received and processed, it is directly passed to the capture module for calculation to minimize the delay. After the capture is completed, the capture result is passed to the CPU's data synchronization module.

[0059] The data synchronization module uses DMA, core binding technology, specific data structures, and synchronization technology to ensure reliable and low-latency transmission between the acceleration resources and the CPU. While receiving downlink data, it sends the uplink data generated by the data modulation module to the acceleration resources.

[0060] After the demodulation module receives the captured data, it performs demodulation processing. The demodulation includes multiple processes such as code synchronization, carrier synchronization, and bit synchronization. It uses multi-threaded processing, and the data transfer between its threads adopts zero-copy technology as shown in Figure 4 which greatly reduces the latency.

[0061] Since decoding is resource-intensive and requires a large amount of parallel computing, finally the demodulated data is sent to the FPGA acceleration resources for decoding processing.

[0062] After decoding is completed, it is sent to the CPU to form a data frame and sent to the application system.

[0063] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or extended, replaced in any logical manner from the above specific implementation manners, such as the disclosed technical principles, disclosed technical features, or implicitly disclosed technical features.

[0064] Embodiment 1

[0065] A cloud measurement and control system based on a real-time cloud computing architecture, including a real-time and non-real-time separation processing module, a transmission module, and a zero-copy module for measurement and control data between threads;

[0066] The real-time and non-real-time separation processing module includes an FPGA-type intelligent acceleration card. The FPGA is used to control the accuracy of data reception and transmission. At the same time, the buffer size is set for the uplink transmission of the FPGA to buffer the data transmission between the acceleration card and the CPU; Capturing and decoding are placed on the FPGA-type intelligent network card, and the FPGA parallel computing is used for capturing and decoding to offload the pressure on the CPU;

[0067] The transmission module includes a first data structure module, a data synchronization module, and a real-time guarantee processing module;

[0068] The zero-copy module for measurement and control data between threads includes a large-page circular queue and a second data structure module, and realizes zero-copy for measurement and control data between threads through the combination of the large-page circular queue and the second data structure.

[0069] Embodiment 2

[0070] Based on Embodiment 1, in the real-time and non-real-time separation processing module, non-real-time data modulation, demodulation, data frame generation, and data reporting to the CPU are processed.

[0071] Example 3

[0072] Based on Example 1, in the design of the first data structure module, it includes an accelerator ID, a counter, a timestamp, and a data length; among them, the accelerator ID is used to distinguish different acceleration resource information and determine the source of data; the counter is used to continuously count the data. The downlink data count is filled in by the radio frequency front-end device and detected on the cloud platform side; the uplink data count is filled in on the cloud platform side and detected on the acceleration card and radio frequency front-end side; both-sided data determines whether there is a packet loss phenomenon according to the detection situation and reports an alarm; the timestamp is used to determine the time information, a reception timestamp is marked when the data is received, and a transmission timestamp is marked when the data is sent; the data length is used to adapt to data transmissions of different lengths.

[0073] Example 4

[0074] Based on Example 1, in the design of the data synchronization module, two variable detections of a low water level line and a high water level line are set to complete data transceiver synchronization, which is used to ensure the data reliability and real-time performance between the CPU and the acceleration resources.

[0075] Example 5

[0076] Based on Example 1, the real-time performance guarantee processing module includes the following processing for the modulation, demodulation, and data transceiver processes on the CPU side: isolate a certain CPU core, turn off the scheduling and interrupts on it, and bind the key threads to the core to ensure the minimum latency fluctuation; set the highest queuing priority for the data transceiver network card of the key thread to ensure data real-time performance; use the DMA method to realize the data transmission between the CPU and the intelligent acceleration card to speed up; allocate a separate memory mapping to avoid time fluctuations caused by memory preemption.

[0077] Example 6

[0078] Based on Example 1, in the design of the large page circular queue, large pages are allocated and memory resources are allocated to the application program through a memory pool; in the initialization stage, the memory pool obtains memory resources from the large pages, and in the program running stage, the application program directly obtains memory resources through the memory pool, and the memory pool is responsible for memory management, so that the data latency is reliable and there will be no data fluctuations caused by memory preemption.

[0079] Example 7

[0080] Based on Example 1, in the design of the second data structure, it includes a data type, a data length, and a sequence number. The data type is used to describe the data type of the current step; the data length is used to describe the effective length of the data segment; the sequence number is used to describe the step being processed in the current pipeline.

[0081] Example 8

[0082] Based on Example 4, two variable detections of a low water mark and a high water mark are set to complete the synchronization of data transmission and reception, including the following detection process: when the detection program finds that the data cached by the acceleration card is lower than the water mark, 2 packets of data are sent each time; when the data cache is between the low water mark and the high water mark, one packet of data is sent each time; when the data cache is higher than the high water mark, data sending is suspended.

[0083] Example 9

[0084] On the basis of Example 7, the design based on the second data structure includes: after the current processing thread receives the processing signal, it directly reads the position in the circular queue according to the current thread counter, and uses a pointer to point to the data in the queue, and directly performs calculations without copying the data; based on pointer operations, the calculated data will also directly modify the data in the memory of the circular queue without copying. After the calculation is completed, the corresponding serial number ID is modified, and then a signal is sent to the next thread for processing. The entire process will not perform repeated copying of measurement and control data.

[0085] Example 10

[0086] A cloud measurement and control method based on a real-time cloud computing architecture, based on the cloud measurement and control system based on a real-time cloud computing architecture as described in any one of Embodiments 1 to 7, further comprising the following steps:

[0087] S1, data transmission and reception are implemented in FPGA acceleration resources. FPGA is used to ensure controllable data delay, and time tags are added in FPGA acceleration resources to ensure the time accuracy requirements of subsequent processing;

[0088] S2, after the data receiving and processing is completed, the capture algorithm is directly passed to the capture module for calculation. After the capture module completes the calculation, the capture result is passed to the data synchronization module of the CPU;

[0089] S3, the data synchronization module sends the uplink data generated by the data modulation module to the acceleration resource while receiving the downlink data;

[0090] S4, after receiving the captured data, the demodulation module performs demodulation processing, the demodulation includes code synchronization, carrier synchronization, bit synchronization, and multi-thread processing is adopted, and the data transmission between the multi-thread threads is completed by the zero-copy module between the measurement and control data threads;

[0091] S5, sending the demodulated data to the FPGA acceleration resource for decoding processing;

[0092] After S6, after decoding is completed, it is sent to the CPU to form a data frame and sent to the application system.

[0093] The units involved in the embodiments of the present invention can be implemented in software or in hardware. The described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.

[0094] According to one aspect of the embodiments of the present invention, there is provided a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various alternative implementation manners.

[0095] As another aspect, the embodiments of the present invention further provide a computer-readable medium. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist alone without being assembled into the electronic device. The above computer-readable medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.

[0096] The parts not involved in the present invention are the same as the prior art or can be implemented by the prior art.

[0097] The above technical solution is only one implementation manner of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or deformations, not limited to the methods described in the above specific implementation manners of the present invention. Therefore, the above-described manner is only preferred and does not have a restrictive meaning.

[0098] Except for the above examples, those skilled in the art obtain inspiration according to the above disclosure or make modifications using the knowledge or technology in related fields to obtain other embodiments. The features of each embodiment can be interchanged or replaced. As long as the modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, they should be within the protection scope of the appended claims of the present invention.

Claims

1. A cloud measurement and control system based on a real-time cloud computing architecture, characterized in that, it includes a real-time and non-real-time separation processing module, a transmission module, and a zero-copy module between measurement and control data threads; The real-time and non-real-time separation processing module includes an intelligent acceleration card of the FPGA type. The FPGA is used to control the accuracy of data reception and transmission. At the same time, the buffer size is set for the uplink transmission of the FPGA to buffer the data transmission between the acceleration card and the CPU; the capture and decoding are placed on an intelligent network card of the FPGA type, and the FPGA parallel calculation is used for capture and decoding to offload the pressure on the CPU; The transmission module includes a first data structure module, a data synchronization module, and a real-time guarantee processing module; in the design of the first data structure module, it includes an accelerator ID, a counter, a timestamp, and a data length; among them, the accelerator ID is used to distinguish different acceleration resource information and determine the source of the data; the counter is used to continuously count the data. The downlink data count is filled in by the radio frequency front-end device and detected on the cloud platform side; the uplink data count is filled in by the cloud platform side and detected on the acceleration card and the radio frequency front-end; both sides of the data judge whether there is a packet loss phenomenon according to the detection situation and report an alarm; the timestamp is used to determine the time information, a reception timestamp is marked when the data is received, and a transmission timestamp is marked when the data is sent; the data length is used to adapt to data transmissions of different lengths; In the design of the data synchronization module, two variable detections of a low water level line and a high water level line are set to complete data reception and transmission synchronization, which is used to ensure the reliability and real-time of the data between the CPU and the acceleration resources; The real-time guarantee processing module includes the following processing of the modulation, demodulation, and data reception and transmission processes on the CPU side: isolate a certain CPU core, turn off the scheduling and interrupts on it, and bind the key threads to the core to ensure the minimum delay fluctuation; set the highest queuing priority of the key thread data reception and transmission network card to ensure data real-time; use the DMA method to realize the data transmission between the CPU and the intelligent acceleration card to speed up; allocate a separate memory mapping to avoid time fluctuations caused by memory preemption; The zero-copy module between measurement and control data threads includes a large-page circular queue and a second data structure module, and realizes zero-copy between measurement and control data threads through the combination of the large-page circular queue and the second data structure; In the design of the large-page circular queue, large-page allocation is used and memory resources are allocated to the application program through a memory pool; in the initialization stage, the memory pool obtains memory resources from the large page. During the program operation stage, the application program directly obtains memory resources through the memory pool, and the memory pool is responsible for memory management, so that the data delay is reliable and there will be no data fluctuations caused by memory preemption; In the design of the second data structure, it includes a data type, a data length, and a sequence number. The data type is used to describe the data type of the current step; the data length is used to describe the effective length of the data segment; the sequence number is used to describe the step processed in the current pipeline; The design based on the second data structure includes: after the current processing thread receives a processing signal, it directly reads the position in the circular queue according to the current thread counter, points to the data in the queue by means of a pointer, and directly performs calculations without copying the data; based on pointer operations, the calculated data will directly modify the data in the memory of the circular queue without copying. After the calculation is completed, the corresponding serial number ID is modified, and then a signal is sent to the next thread for processing. The entire process will not perform duplicate copying of measurement and control data.

2. The cloud measurement and control system based on the real-time cloud computing architecture according to claim 1, characterized in that, in the real-time and non-real-time separation processing module, non-real-time data is modulated, demodulated, data frames are generated, and the data is reported to the CPU for processing.

3. The cloud measurement and control system based on the real-time cloud computing architecture according to claim 1, characterized in that, two variables of a low water level line and a high water level line are set to complete data sending and receiving synchronization, including the following detection processes: when the detection program finds that the data cached in the acceleration card is lower than the water level line, 2 packets of data are sent each time; when the data cache is between the low water level line and the high water level line, 1 packet of data is sent each time; when the data cache is higher than the high water level line, data sending is suspended.

4. A cloud measurement and control method based on the real-time cloud computing architecture, characterized in that, based on the cloud measurement and control system based on the real-time cloud computing architecture according to any one of claims 1 to 2, the following steps are further included: S1, data sending and receiving are implemented in the FPGA acceleration resource. It uses the FPGA to ensure that the data delay is controllable, and time tags are added in the FPGA acceleration resource to ensure the requirements for time accuracy in subsequent processing; S2, the capture algorithm is directly passed to the capture module for calculation after the data reception and processing are completed. After the capture module completes the calculation, the capture results are sent to the data synchronization module of the CPU together; S3, while receiving the downstream data, the data synchronization module sends the upstream data generated by the data modulation module to the acceleration resource; S4, after the demodulation module receives the captured data, demodulation processing is performed. The demodulation includes code synchronization, carrier synchronization, and bit synchronization, and multi-threaded processing is adopted. The data transfer between the threads of the multi-threaded processing is completed by the zero-copy module between the measurement and control data threads; S5, the demodulated data is sent to the FPGA acceleration resource for decoding processing; S6, after the decoding is completed, it is sent to the CPU to form a data frame and sent to the application system.

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