Direct network communication method from CPU MAC layer to switch MAC layer based on UBOOT architecture

Abstract

The present invention relates to the technical field of network communication, and provides a direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture. In view of the trend of miniaturization and integration of electronic devices, a network switch is integrated into a computer motherboard. A networking method from the CPU MAC layer to the switch MAC layer is proposed, and a virtual PHY device is added to the UBOOT code, that is, a virtual PHY device is set in the driver list, so that the CPU chip judges that there is a mounted PHY device in the PHY device scanning operation, and the device ID and address are forced to be returned, thereby completing the network initialization without changing the original architecture. The present invention does not change the network initialization method of UBOOT by changing the UBOOT underlying code, which can ensure the system operation stability and implementation simplicity, reduce the signal delay, and improve the signal quality.

Description

Technical Field

[0001] The present invention relates to the technical field of network communication, and in particular to a direct network communication method from a CPU MAC layer to a switch MAC layer based on a UBOOT architecture. Background Art

[0002] In the traditional computer to Ethernet switch networking method, the computer's network MAC layer (the lower layer of the data link layer) needs to be connected to the physical layer device PHY, such as Figure 1 As shown, the physical layer PHY is then connected to the physical layer of the network switch through a cable or optical fiber, and finally the physical layer of the network switch is connected to the MAC layer of the network switch to achieve networking. In the Ethernet communication architecture, an Ethernet PHY is a chip that can send and receive Ethernet data frames. PHY connects a data link layer device (MAC) to a physical medium, such as optical fiber or copper cable.

[0003] With the development of technology, electronic devices tend to be miniaturized and integrated, so there is a need to integrate network switches into computer motherboards. Figure 1 The cable or optical fiber connection in the network communication architecture shown is changed to a board-level wiring connection to achieve miniaturized integration, but the above-mentioned CPU-MAC+PHY<—>PHY+SWITCH-MAC method is still used to achieve device integration. However, the additional two PHY chips will increase the design complexity of the circuit, affect the signal quality and increase the production cost.

[0004] Directly connecting the MAC layer of the computer device's CPU to the MAC layer of the network switch will cause network connection failure during system startup due to the mechanism of UBOOT architecture loading the network. Summary of the invention

[0005] The present invention aims to provide a direct network communication method from the CPU MAC layer to the switch MAC layer, which can reduce the use of devices and PCB complexity in hardware and reduce the modification of UBOOT bottom layer code in software, so as to realize direct network communication from the CPU MAC layer to the switch MAC layer under the UBOOT architecture, reduce signal delay and improve signal quality.

[0006] According to a first aspect of the present invention, a direct network communication method from a CPU MAC layer to a switch MAC layer based on a UBOOT architecture is proposed, comprising:

[0007] Step 1: After the system is powered on, the CPU chip loads the UBOOT program from the FLASH and executes the UBOOT program startup process;

[0008] Step 2: When the UBOOT program is executed to the location where the network device is loaded, the MDIO device initialization process of the CPU chip is started, and the register information about the MDIO device recorded in the UBOOT program is written into the register of the CPU chip;

[0009] Step 3: After the CPU chip completes the MDIO device initialization, it performs a PHY device scan operation to determine whether there is a PHY device. If it is determined that there is no PHY device, it returns the result of network initialization failure. If it is determined that there is a PHY device, it returns the device address and device ID, and enters step 4; wherein, a virtual PHY device is pre-added to the PHY device driver list, and its device address and device ID are configured, so that when the PHY scan operation is executed to scan the address, the device address and device ID are forcibly returned;

[0010] Step 4: Obtain the list of PHY device models supported in the UBOOT program. The supported PHY device model refers to the PHY device of the model that has been debugged with the current model of CPU chip, and the configuration of the PHY device is written into the CPU chip;

[0011] Step 5, write the register information of the MAC device of the CPU chip recorded in the UBOOT program into the register of the CPU chip, the register information of the MAC device includes the communication rate, communication mode, and interface mode information of the MAC communication;

[0012] Step 6: According to step 3, the returned device address and device ID are obtained and matched with the PHY device model list information obtained in step 4. The parameter configuration information of the mounted PHY device is determined by querying the device ID, and the operation of writing the virtual PHY device configuration on the bus of the MDIO device is performed. Then, the register information written into the CPU chip is read out for verification, and the actual error return information is ignored. The correct information identical to the written data is forced to be returned for verification. If the verification passes, the network configuration on the CPU chip side is completed.

[0013] Step 7: The CPU chip is connected to one of the interfaces supported by the switch chip through the physical interface and communication protocol of the MDIO device, and the register information of the switch chip is configured, including: communication rate, communication mode, and interface mode information;

[0014] Step 8. Connect any of the remaining interfaces supported by the switch chip to a normally functioning computer network port, and configure the computer IP address and the CPU chip IP address to be in the same gateway. The MAC-to-MAC direct connection network initialization is now complete.

[0015] As an optional implementation, in step 3, the device address and device ID corresponding to the virtual PHY device in the PHY device driver list are pre-added and configured by the user.

[0016] As an optional implementation, when the PHY device scanning operation is performed to the device address corresponding to the pre-added virtual PHY device, the device ID corresponding to the address is forcibly returned, and it is determined that the system has mounted the PHY device.

[0017] As an optional implementation, in step 2, the register information of the MDIO device includes at least the rate of MDIO communication, the duty cycle of the clock signal, and the clock signal delay information.

[0018] As an optional implementation, the register information of the MDIO device is configured to be acquired through a data manual of a CPU chip before compiling the UBOOT program, and written into the UBOOT program.

[0019] As an optional implementation, according to different models of PHY devices supported by the CPU chip, device IDs of multiple supported PHY devices are pre-written into the CPU chip, and when step 4 is executed, all supported PHY device model list information is loaded into the cache.

[0020] As an optional implementation, in step 7, after the CPU chip completes configuring the register information of the switch chip, the register value is read back for verification to ensure that the switch chip configuration is successful.

[0021] As an optional implementation, in step 8, after configuring the computer IP address and the CPU chip IP address to be in the same gateway, the following is further included:

[0022] Run the Ping command to verify whether the network is communicating normally, and use the FTP tool to transfer files to verify the network transmission speed and bit error rate, to ensure that the network communication from the CPU chip MAC layer to the switch MAC layer is normal and effective.

[0023] It should be understood that all combinations of the aforementioned concepts and the additional concepts described in more detail below can be considered as part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of the claimed subject matter are considered as part of the inventive subject matter of the present disclosure.

[0024] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in various figures may be represented by the same reference numeral. For clarity, not every component is labeled in every figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings, in which:

[0026] Figure 1 It is a schematic diagram of a network connection method in the prior art.

[0027] Figure 2 It is a schematic diagram of a direct network communication connection mode from a CPU MAC layer to a switch MAC layer according to an embodiment of the present invention.

[0028] Figure 3 It is a flow chart of network initialization under the UBOOT architecture according to an embodiment of the present invention.

[0029] Figure 4 The present invention is a schematic diagram of a network initialization process for direct connection from CPU MAC to switch MAC under a UBOOT architecture according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0031] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0032] Combination Figure 1 , 2 As shown, the direct network communication method from the CPU MAC layer to the switch MAC layer proposed in the present invention is intended to integrate the network switch into the computer motherboard under the situation that electronic equipment tends to be miniaturized and integrated, and proposes a communication method from the CPU MAC layer directly to the MAC layer of the network switch under the UBOOT architecture, thereby reducing the use of devices, simplifying the circuit design, and reducing the delay of signal communication.

[0033] If only the hardware of the CPU chip MAC + the switch MAC is directly connected, during the system startup process, the network connection will fail due to the mechanism of loading the network in the UBOOT architecture. Therefore, a design based on a virtual PPHY device is proposed in an embodiment of the present invention. After the network initialization between the CPU chip MAC and the switch chip MAC is completed, direct network communication can be achieved.

[0034] In an embodiment of the present invention, the CPU chip will scan and load the PHY device by default when the system starts. If no PHY device is found, it is considered that there is no network device connected. In this regard, in an embodiment of the MAC to MAC networking method, a virtual PHY device is set in the driver list, so that the CPU chip determines that there is a mounted PHY device in the PHY device scanning operation, and forces the return of the device ID and address, thereby completing the network initialization and realizing direct network communication from the CPU's MAC to the switch's MAC.

[0035] Combination Figure 2-3 The direct network communication method from the CPU MAC layer to the switch MAC layer of the exemplary embodiment shown includes the following steps:

[0036] Step 1: After the system is powered on, the CPU chip loads the UBOOT program from the FLASH and executes the UBOOT program startup process;

[0037] Step 2: When the UBOOT program is executed to the position where the network device is loaded, the MDIO device initialization process of the CPU chip is started, and the register information about the MDIO device recorded in the UBOOT program is written into the register of the CPU chip; the register information of the MDIO device includes at least the rate of MDIO communication, the duty cycle of the clock signal, and the clock signal delay information;

[0038] Step 3: After the CPU chip completes the MDIO device initialization, it performs a PHY device scan operation to determine whether there is a PHY device. If it is determined that there is no PHY device, it returns the result of network initialization failure. If it is determined that there is a PHY device, it returns the device address and device ID, and enters step 4; wherein, a virtual PHY device is pre-added to the PHY device driver list, and its device address and device ID are configured, so that when the PHY scan operation is executed to scan the address, the device address and device ID are forcibly returned;

[0039] Step 4: Obtain the list of PHY device models supported in the UBOOT program. The supported PHY device model refers to the PHY device of the model that has been debugged with the current model of CPU chip, and the configuration of the PHY device is written into the CPU chip;

[0040] Step 5, write the register information of the MAC device of the CPU chip recorded in the UBOOT program into the register of the CPU chip, the register information of the MAC device includes the communication rate, communication mode, and interface mode information of the MAC communication;

[0041] Step 6: According to step 3, the returned device address and device ID are obtained and matched with the PHY device model list information obtained in step 4. The parameter configuration information of the mounted PHY device is determined by querying the device ID, and the operation of writing the virtual PHY device configuration on the bus of the MDIO device is performed. Then, the register information written into the CPU chip is read out for verification, and the actual error return information is ignored. The correct information identical to the written data is forced to be returned for verification. If the verification passes, the network configuration on the CPU chip side is completed.

[0042] Step 7: The CPU chip is connected to one of the interfaces supported by the switch chip through the physical interface and communication protocol of the MDIO device, and the register information of the switch chip is configured, including: communication rate, communication mode, and interface mode information;

[0043] Step 8. Connect any of the remaining interfaces supported by the switch chip to a normally functioning computer network port, and configure the computer IP address and the CPU chip IP address to be in the same gateway. The MAC-to-MAC direct connection network initialization is now complete.

[0044] Wherein, in the step 3, the device address and device ID corresponding to the virtual PHY device in the PHY device driver list are pre-added and configured by the user.

[0045] In an optional embodiment, when the PHY device scanning operation is performed to the device address corresponding to the pre-added virtual PHY device, the device ID corresponding to the address is forcibly returned, and it is determined that the system has mounted the PHY device.

[0046] In an optional embodiment, the register information of the MDIO device is configured to be obtained through the data manual of the CPU chip before compiling the UBOOT program, and written into the UBOOT program.

[0047] In an optional embodiment, according to different models of PHY devices supported by the CPU chip, device IDs of multiple supported PHY devices may be pre-written into the CPU chip, and when step 4 is executed, list information of all supported PHY device models is loaded into the cache.

[0048] In an optional embodiment, in step 7, after the CPU chip completes configuring the register information of the switch chip, the register value is read back for verification to ensure that the switch chip configuration is successful.

[0049] In an optional embodiment, in step 8, after configuring the computer IP address and the CPU chip IP address to be in the same gateway, the following is further included:

[0050] Run the Ping command to verify whether the network is communicating normally, and use the FTP tool to transfer files to verify the network transmission speed and bit error rate, to ensure that the network communication from the CPU chip MAC layer to the switch MAC layer is normal and effective.

[0051] Figure 3 It shows the standard network initialization process under the UBOOT architecture. Figure 3 As shown in the process, the network initialization process executed in the UBOOT program includes the following execution order of step 1 to step 7.

[0052] Step 1: The system is powered on successfully, the CPU chip starts to load the UBOOT program from the FLASH and executes the UBOOT startup process.

[0053] Step 2: When the UBOOT program executes to the location where the network device is loaded, it starts to execute the CPU's MDIO device initialization work.

[0054] The process of MDIO device initialization is: write the register information about the MDIO device in the UBOOT program into the relevant CPU register. The written information includes the MDIO communication rate, clock signal duty cycle, clock signal delay and other information.

[0055] Among them, the register information about the MDIO device recorded in the UBOOT program can be obtained through the CPU data manual before compiling the UBOOT program and written in the UBOOT program code.

[0056] Step 3: After the MDIO device of the CPU chip is initialized, a PHY scan operation will be performed.

[0057] For example, the MDIO protocol stipulates that a maximum of 32 PHY devices can be mounted on the bus interface. Therefore, when the CPU chip performs a PHY scan, it will automatically send read device ID commands from address 0 to address 31 in sequence to detect whether there is a device response, thereby determining whether a PHY device is mounted on the hardware.

[0058] For example, a frame of read device ID command is sent to the device with slave address 8, and then a response is waited. If the ID information returned by the device is received within a period of time, it is considered that there is a PHY device with slave address 8 on the bus. If no response is received after the waiting time, it is considered that there is no device with slave address 8 on the bus.

[0059] If no mounted PHY device is scanned, the program will skip the subsequent process and return the result of network initialization failure. If one or more devices are scanned, the subsequent operations will continue.

[0060] Step 4: If a PHY device is scanned, the UBOOT program continues to obtain the supported PHY device models included in the current UBOOT program and the correct configuration of each PHY device model.

[0061] The aforementioned supported PHY device models refer to a certain model of PHY device that has been debugged with the current model of CPU chip, and the correct configuration information about this PHY device has been written into the UBOOT program code.

[0062] It should be understood that a CPU can support many PHY devices of different manufacturers and models, so in the operation of registering the PHY driver, multiple supported device IDs will be loaded into the cache for subsequent operation matching.

[0063] Step 5: Write the register information about the MAC device recorded in the UBOOT program into the relevant registers of the CPU chip. The written information includes the MAC communication rate (for example, 1000M, 1000M, 10M), communication mode (for example, full-duplex, half-duplex, simplex), and interface mode (for example, MII, RMII, GMII, RGMII) information.

[0064] The register information of the MAC device recorded in the UBOOT program can be obtained through the CPU data manual before compiling the UBOOT program and written in the UBOOT program code. The processing method here is the same as the mechanism of the MDIO device.

[0065] Step 6: Based on the mounted PHY device ID obtained in step 3 and the currently supported PHY device model and configuration information obtained in step 4, the device ID is compared with the ID of the PHY device of the supported model to obtain the parameter configuration information of the PHY device.

[0066] The CPU writes the configuration information of the PHY device matched in step 6 into the relevant register of the PHY device through the physical interface and communication protocol of the MDIO device, and then reads the information written into the register for verification to ensure the correctness of the PHY configuration.

[0067] Step 7: The network initialization process ends.

[0068] Combination Figure 2 , 4 As shown, we combine the standard network initialization process under the UBOOT architecture to more specifically describe the network initialization steps of the MAC to MAC direct connection of the present invention.

[0069] Combination Figure 4 The network initialization process of the MAC-to-MAC direct connection shown includes the following steps 1 to 8 being performed in sequence.

[0070] Since there is no PHY device in the MAC-to-MAC direct network link, follow the standard initialization steps of UBOOT to Figure 3 The network initialization step will end at the "step 3" position. Considering the stability of system operation and the simplicity of implementation, the embodiment of the present invention does not change the UBOOT network initialization step by changing the UBOOT underlying code, but instead adds a virtual PHY device to the UBOOT code to implement network initialization without changing the original architecture.

[0071] Below we take Tianjin Feiteng's quad-core CPU FT-2000 and Nanfeiwei's SF2507 switch chip as examples to illustrate the specific implementation process.

[0072] Step 1: The system is powered on successfully, FT-2000 starts to load the UBOOT program from FLASH and executes the UBOOT startup steps.

[0073] Step 2: When the UBOOT program executes to the location where the network device is loaded, it starts to execute the FT-2000 MDIO device initialization work. The specific implementation method is to write the register information about the MDIO device recorded in the UBOOT program into the relevant FT-2000 register. The information includes the MDIO communication rate, clock signal duty cycle, clock signal delay and other information.

[0074] Step 3: After the MDIO device of FT-2000 is initialized, a PHY scan operation will be performed. A virtual PHY device with a device address of 0x6 and a device ID of 0x55 is added to the driver list in advance, and the program code is modified to force the return of device ID 0x55 when scanning a device with a slave device address of 6. After the scan is completed, FT-2000 believes that the PHY device is mounted on the hardware, and the network initialization step continues.

[0075] It should be understood that the device address and device ID of the virtual PHY device here can be customized. Here, the device address is 0x6 and the device ID is 0x55 for example.

[0076] Step 4: After scanning the PHY device with device address 0x6, the program obtains the supported PHY device models and corresponding configuration information contained in the current UBOOT program. The configuration information of the virtual PHY device has been pre-written in the UBOOT program code.

[0077] Step 5: Write the register information about the MAC device recorded in the UBOOT program into the relevant FT-2000 registers, including MAC communication rate (1000M, 100M, 10M), communication mode (full-duplex, half-duplex, simplex), interface mode (MII, RMII, GMII, RGMII) and other information.

[0078] Step 6: Get the virtual PHY device ID in "Step 3", get the currently supported PHY device model and configuration information in "Step 4", compare the ID with the ID of the supported model to get the parameter configuration information of this PHY device. Execute the operation of writing the virtual PHY configuration of the MDIO bus, then read the information written to the register for verification, ignore the actual error return information, modify the code to force the return of the correct information that is the same as the written data for verification. If the verification passes, the network configuration of the FT-2000 end is completed.

[0079] Step 7: FT-2000 configures the register information of the switch device SF2507 through the MDIO physical interface and communication protocol, configures register 0x1305 to 0x1 (interface mode is MAC with RGMII), register 0x1311 to 0x1006 (communication mode is Gigabit, full-duplex), and register 0x1307 to 0x986 (delay of RGMII physical interface data sending and receiving clock). After writing, read back the register value for verification to ensure that the switch configuration is successful.

[0080] Step 8: SF2507 is a 7-port switch chip. Connect any of the remaining interfaces to a computer network port that can work normally. Set the computer IP and FT-2000IP to the same gateway. Execute the Ping command to verify whether the network is connected. Use the FTP tool to transfer files to verify the network transmission speed and bit error rate. Now the MAC to MAC direct connection network initialization is completed.

[0081] Combination Figure 2 The physical connection diagram of the direct connection between the CPU MAC and the switch MAC is shown. During the execution of the above steps 1-8, signal transmission is performed through the physical connection at the board level.

[0082] For example, in Figure 2 In the MAC+MAC direct connection board-level wiring, "1" "MDC and MDIO" are two physical connection lines set by the MDIO interface. MDC transmits the clock signal and MDIO transmits the data signal when the register is read and written. Taking the IEEE 802.3 protocol as an example, the protocol stipulates that the maximum communication rate of MDC is 2.5MHz. In the example solution of the present invention, a communication rate of 1MHz can be used. Figure 4In the network initialization process of the MAC-to-MAC direct connection shown, "step 3", "step 6", and "step 7" use the MDIO interface for communication.

[0083] Figure 2 The 12 wires set at "2" and "3" are the physical connection wires of the RGMII interface. FT-2000 is the host end and SF2507 is the slave end. When the host sends data to the slave, the signal is communicated by the 6 wires at "2". TX_CLK is the clock signal line, and the clock speed varies according to the transmission speed (10M 2.5MHz / 100M 25MHz / 1000M 125 MHz). TX_CLT is the control signal line, which is used to indicate the validity of the data frame sent. This control signal gives a high level or a low level based on the judgment of the data. The speed is not fixed, and the highest speed follows the clock signal.

[0084] TXD[0:3] is a 4-bit data line used to transmit data. The speed is not fixed and the maximum speed follows the clock signal.

[0085] When the slave sends data to the master, the signal is communicated by the 6 gold wires set at "3". RX_CLK is the clock signal line, and the clock speed varies according to the transmission speed (10M 2.5MHz / 100M 25MHz / 1000M 125MHz). RX_CLT is the control signal line, which is used to indicate the validity of the sent data frame. This signal gives a high level or a low level based on the judgment of the data. The speed is not fixed, and the highest speed follows the clock signal.

[0086] RXD[0:3] is a 4-bit data line used to transmit data. The speed is not fixed and can only follow the speed of the clock signal.

[0087] In the present invention Figure 4 In the example embodiment shown, since the Gigabit, full-duplex communication mode is configured when the network is initialized, the speed of TX_CLK and RX_CLK is 125MHz, and data from the host to the slave and from the slave to the host can be sent simultaneously. In the network initialization process of MAC to MAC direct connection, "Step 8" uses this interface for communication, and the rest of the process does not use this interface.

[0088] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A direct network communication method from CPU MAC layer to switch MAC layer based on UBOOT architecture, characterized in that: include: Step 1: After the system is powered on, the CPU chip loads the UBOOT program from the FLASH and executes the UBOOT program startup process; Step 2: When the UBOOT program is executed to the location where the network device is loaded, the MDIO device initialization process of the CPU chip is started, and the register information about the MDIO device recorded in the UBOOT program is written into the register of the CPU chip; Step 3: After the CPU chip completes the MDIO device initialization, it performs a PHY device scan operation to determine whether there is a PHY device. If it is determined that there is no PHY device, it returns the result of network initialization failure. If it is determined that there is a PHY device, it returns the device address and device ID, and enters step 4; wherein, a virtual PHY device is pre-added to the PHY device driver list, and its device address and device ID are configured, so that when the PHY scan operation is executed to scan the address, the device address and device ID are forcibly returned; Step 4: Obtain the list of PHY device models supported in the UBOOT program. The supported PHY device model refers to the PHY device of the model that has been debugged with the current model of CPU chip, and the configuration of the PHY device is written into the CPU chip; Step 5, write the register information of the MAC device of the CPU chip recorded in the UBOOT program into the register of the CPU chip, the register information of the MAC device includes the communication rate, communication mode, and interface mode information of the MAC communication; Step 6: According to step 3, the returned device address and device ID are obtained and matched with the PHY device model list information obtained in step 4. The parameter configuration information of the mounted PHY device is determined by querying the device ID, and the operation of writing the virtual PHY device configuration on the bus of the MDIO device is performed. Then, the register information written into the CPU chip is read out for verification, and the actual error return information is ignored. The correct information identical to the written data is forced to be returned for verification. If the verification passes, the network configuration on the CPU chip side is completed. Step 7: The CPU chip is connected to one of the interfaces supported by the switch chip through the physical interface and communication protocol of the MDIO device, and the register information of the switch chip is configured, including: communication rate, communication mode, and interface mode information; Step 8. Connect any of the remaining interfaces supported by the switch chip to a normally functioning computer network port, and configure the computer IP address and the CPU chip IP address to be in the same gateway. The MAC-to-MAC direct connection network initialization is now complete.

2. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: In step 3, the device address and device ID corresponding to the virtual PHY device in the PHY device driver list are pre-added and configured by the user.

3. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: When the PHY device scanning operation is performed to the device address corresponding to the pre-added virtual PHY device, the device ID corresponding to the address is forcibly returned, and it is determined that the system has mounted the PHY device.

4. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: In the step 2, the register information of the MDIO device includes at least the rate of MDIO communication, the duty cycle of the clock signal and the clock signal delay information.

5. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 4, characterized in that: The register information of the MDIO device is configured to be obtained through the data manual of the CPU chip before compiling the UBOOT program, and written into the UBOOT program.

6. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: According to different types of PHY devices supported by the CPU chip, device IDs of multiple supported PHY devices are pre-written into the CPU chip, and when step 4 is executed, all supported PHY device model list information is loaded into the cache.

7. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: In step 7, after the CPU chip completes configuring the register information of the switch chip, the register value is read back for verification to ensure that the switch chip configuration is successful.

8. The direct network communication method from the CPU MAC layer to the switch MAC layer based on the UBOOT architecture according to claim 1, characterized in that: In step 8, after configuring the computer IP address and the CPU chip IP address to be in the same gateway, the following steps are also included: Run the Ping command to verify whether the network is communicating normally, and use the FTP tool to transfer files to verify the network transmission speed and bit error rate, to ensure that the network communication from the CPU chip MAC layer to the switch MAC layer is normal and effective.

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