Semiconductor package and method of manufacturing a semiconductor package

Abstract

A method for forming a package according to the present embodiment includes the steps of: molding a semiconductor chip and a light emitting element; forming a redistribution layer (RDL) that electrically connects the semiconductor chip to the light emitting element; and arranging a light receiving element on the redistribution layer to be electrically connected thereto, wherein the light receiving element is arranged such that at least a portion thereof is positioned directly above the semiconductor chip.

Description

TECHNICAL FIELD

[0001] The present technology relates to a semiconductor package and a method of manufacturing a semiconductor package. BACKGROUND

[0002] A technology of reconstructing a distance from a subject and a three-dimensional image of the subject by emitting laser light and using a time difference of light reflected from the subject is applied to various fields such as mobile devices, automobiles, medical care, etc. In order to implement this technology, a light emitting element, a light receiving element, and a chip that drives these elements and performs signal processing are required. In order to implement this in a mobile platform, it is basically required to make an optical element package light, thin, and small. SUMMARY

[0003] [PROBLEMS]

[0004] Most of the currently used packages have a large area and a complex process operation. The present embodiment aims to solve the above-described difficulties of the prior art. That is, it is one of the problems to be solved by the present technology to provide a method capable of forming a semiconductor package including an optical element having a small area and a thin thickness.

[0005] In addition, optical members such as lenses, diffusers, etc. are mainly used for manufacturing a module, and can reduce additional component and assembly costs, and by directly manufacturing optical members on a semiconductor package at a wafer level, it is possible to manufacture a package itself in a smaller size.

[0006] [TECHNICAL SOLUTION]

[0007] The method of manufacturing a package according to an embodiment includes the operations of molding a semiconductor chip and a light emitting element; forming a redistribution layer (RDL) configured to electrically connect the semiconductor chip and the light emitting element; and arranging a light receiving element on the redistribution layer to electrically connect the light receiving element and the redistribution layer, wherein the light receiving element is arranged such that at least a portion of the light receiving element is located directly above the semiconductor chip.

[0008] The package according to an embodiment includes a light emitting element; a light receiving element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to package the semiconductor chip and the light emitting element; a redistribution layer configured to electrically connect the light emitting element, the light receiving element, and the semiconductor chip; a via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the via, wherein at least a portion of the light receiving element is located directly above the semiconductor chip.

[0009] The package according to the embodiment includes a light emitting element, a semiconductor chip on which a semiconductor circuit is formed, a mold configured to package the semiconductor chip and the light emitting element, a redistribution layer configured to electrically connect the light emitting element and the semiconductor chip, a via electrically connected to the redistribution layer and passing through the mold, and an external connection terminal electrically connected to the, wherein a conductive metal pattern is located on a bottom surface of the light emitting element.

[0010] [Advantageous Effects]

[0011] According to the present embodiment, an advantage of an optical element package occupying a small area by a simple process is provided. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a flowchart showing an outline of a method of manufacturing a semiconductor package according to an embodiment.

[0013] Figure 2 is a view showing a result of performing an operation of molding a light emitting element and a semiconductor chip.

[0014] Figure 3 (a) is a view showing a light emitting surface of a light emitting element, Figure 3 (b) is a view showing a cross section of a light emitting element. Figure 3 (c) is a view schematically showing a state in which a conductive adhesive layer is formed on a second electrode and a metal pattern thicker than the second electrode is joined.

[0015] Figure 4 is a view schematically showing an operation of forming a redistribution layer electrically connecting a semiconductor chip and a light emitting element.

[0016] Figure 5 is a cross-sectional view showing a state in which a light receiving element 300 is disposed on a redistribution layer to be electrically connected to the redistribution layer.

[0017] Figure 6 is a view showing a profile of a state in which a light receiving element is disposed on a redistribution layer to be electrically connected to the redistribution layer according to another embodiment.

[0018] Figure 7 (a) to Figure 7 (c) is a plan view of the package viewed from the top.

[0019] Figure 8 is a view showing a state in which an external connection terminal is exposed.

[0020] Figure 9 is a view of a state in which at least a portion of an insulating layer located on an optical path of light provided by a light emitting element is removed.

[0021] Figure 10 FIG. 1 is a view schematically showing a state in which a lens structure is formed on a light path of light provided by a light emitting element.

[0022] Figure 11 FIG. 2 is a view schematically showing a state in which a diffusing member is formed on a light emitting surface of a light emitting element.

[0023] Figure 12 and Figure 13 FIG. 5 is a view showing a component holder of a package.

[0024] Figure 14 FIG. 6 is a view showing another embodiment of a package.

[0025] Figure 15 FIG. 7 is a view showing one embodiment of a package according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described with reference to the accompanying drawings. Figure 1 FIG. 8 is a flowchart showing an overview of a method of manufacturing a semiconductor package according to an embodiment. Referring to FIG. 8, Figure 1 The method of manufacturing a semiconductor package includes molding a semiconductor chip and a light emitting element, forming a redistribution layer (RDL) configured to electrically connect the semiconductor chip and the light emitting element, and arranging a light receiving element on the redistribution layer to electrically connect the light receiving element and the redistribution layer, wherein the light receiving element is arranged such that at least a portion of the light receiving element is positioned directly above the semiconductor chip.

[0027] Figures 2 to 12 FIG. 9 is a cross-sectional view showing a schematic process of each operation of a method of manufacturing a semiconductor package according to an embodiment. Figure 2 FIG. 10 is a view showing a result of performing an operation of molding a light emitting element 200 and a semiconductor chip 100 (S100). Referring to FIG. 10, Figure 2 A pad 102 through which an electrical signal is transmitted to a circuit formed in the semiconductor chip 100 and from which an electrical signal formed in the circuit is provided to the outside can be positioned on one surface of the semiconductor chip 100. In addition, an electrode 224 can be positioned on one surface of the light emitting element 200.

[0028] Figure 3 (a) is a view showing a light emitting surface SL of the light emitting element 200, Figure 3 (b) is a view showing a cross section of the light emitting element 200. The light emitting element 200 according to an embodiment can be a light emitting element such as a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), or the like, and can provide light in a wavelength range such as infrared light, visible light, ultraviolet light, or the like.

[0029] Please refer toFigure 3 (a), the light emitting element 200 includes a light emitting surface SL and a back surface SB. A plurality of light sources 222 can be located on the light emitting surface SL, and a first electrode 224 that provides driving power so that the light emitting element 200 emits light is located on the light emitting surface SL. A second electrode 226 is located on the back surface SB opposite the light emitting surface SL.

[0030] For example, the first electrode 224 can be connected to an anode electrode of the light source 222, and the second electrode 226 can be connected to a cathode electrode of the light source 222. As another example, the first electrode 224 can be connected to a cathode electrode of the light source 222, and the second electrode 226 can be connected to an anode electrode of the light source 222. As yet another example, since the first electrode is configured as two electrodes and thus includes both an anode electrode and a cathode electrode on the light emitting surface SL, an element having no electrode can be used on the back surface SB.

[0031] As Figure 3 (a) and Figure 3 (b) show, since the light emitting element 200 and the second electrode 226 are thin in thickness, it can be difficult to handle. In addition, even in combination with the mother substrate 1000 for providing driving power to the second electrode 226 (see Figure 13 ), there can be a case where a limitation occurs due to the thickness of the second electrode 226 and the light emitting element 200.

[0032] However, in the present embodiment, as Figure 3 (c) shows, a conductive adhesive layer 227 is formed on the second electrode 226, and a metal pattern 220 thicker than the second electrode 226 is bonded. Thus, a limitation due to the thickness of the light emitting element 200 and the second electrode 226 can be overcome.

[0033] In the illustrated embodiment, the conductive adhesive layer 227 can include silver epoxy, and the conductive metal pattern 220 is a conductive metal pattern such as a copper pattern, an aluminum pattern, a gold pattern, etc., and can be formed of a metal material having good conductivity. In addition, the thickness d2 of the metal pattern 220 can be at least twice the thickness d1 of the second electrode 226, and preferably three times or more.

[0034] In another embodiment (not shown), the conductive metal pattern can include a non-metal material formed with a conductive path. As another embodiment (not shown), the conductive adhesive layer 227 can be formed of a material such as gold-tin (AuSn), and eutectic bonding can be used to bond the second electrode 226 and the metal pattern 220.

[0035] As still another embodiment, the conductive metal pattern 220 can be formed by forming nanoparticles of a conductive metal such as copper, gold, nickel, etc. on the second electrode 226 and sintering the nanoparticles. The conductive metal nanoparticles can be dispersed in a solvent and then can be formed in the form of spray, application, etc. to the second electrode 226.

[0036] In Figure 3 (a) to Figure 3 (c), although the light emitting element is shown, the conductive metal pattern 120 can be attached to the semiconductor chip 100 in a similar manner. The conductive metal pattern 120 attached to the semiconductor chip 100 and the conductive metal pattern 220 attached to the light emitting element 200 not only can provide driving power to the light emitting element 200 and the semiconductor chip 100, but also can be used as a heat spreader.

[0037] Referring again to Figure 2 , an external connection terminal 500 is formed on the end of the via 400. The via 400 can include a conductive post 410 formed of a conductive material and a housing 420 encapsulating the conductive post.

[0038] The external connection terminal 500 can be formed at the end of the conductive post 410. For example, as shown, the external connection terminal 500 can be a solder ball. The solder ball can be formed by implementing reflow after forming a seed layer (not shown) for electroplating on the end of the conductive post 410 and then implementing electroplating to form a solder material such as tin, silver, etc. In another example (not shown), the external connection terminal can be a pad that can be connected to a solder ball or the like formed on a mother substrate. In still another example, the external connection terminal can be a conductive bump.

[0039] The conductive post 410 and the housing 420 with the external connection terminal 500 formed thereon can be molded together in an encapsulant and the external connection terminal 500 can be exposed by a later process to form the via 400 (see Figure 8 ). The external connection terminal 500 can be bonded to a connection terminal located on the mother substrate 1000 (see Figure 13 ) to electrically connect the package and the mother substrate 1000 (see Figure 13 ).

[0040] The semiconductor chip 100 and the light emitting element 200 are molded using an encapsulant (S100). In the molding process, a plurality of semiconductor chips and a plurality of light emitting elements can be molded. The semiconductor chip can be a chip that drives a light receiving element and is responsible for signal processing or drives a memory, an arithmetic element, and a light emitting element. Alternatively, the semiconductor chip can include an element capable of measuring a temperature in the package. Further, the semiconductor chip can further include a light receiving element. In this case, the light receiving element can be used as a monitor for detecting a temperature in the holder (900, see Figure 12 orFigure 13 ) damage to optical members such as lenses, diffusers, etc. fixed thereto. As another example, the light receiving element can be an auxiliary sensor for performing time-of-flight (TOF) sensing.

[0041] The encapsulant can be an epoxy molding compound (EMC), and is separated from a carrier substrate (not shown) after the encapsulant (mold) is cured. As shown, the external connection terminals 500 formed on the end portions of the vias 400 can be buried in the cured encapsulant (mold), but are exposed to the outside in a later process (see Figure 8 ).

[0042] The illustrated embodiment shows that the vias 400 are formed using the conductive stems 410 formed with the external connection terminals 500, but according to an embodiment (not shown), the vias can be formed by molding a sacrificial member (not shown) having a lower hardness than the mold together, then forming a through-hole through the sacrificial member, and forming a conductive material in the through-hole.

[0043] For example, the operation of forming the through-hole can be implemented by a method such as punching, etching, etc. The operation of forming the conductive material can be performed by forming the conductive material in the through-hole at least to the extent of forming a conductive path through the mold.

[0044] Figure 4 is a view schematically showing an operation of forming a redistribution layer (RDL) 600 electrically connecting the semiconductor chip 100 and the light emitting element 200. The redistribution layer 600 includes a lead pattern 620 electrically connecting elements such as the insulating layer 610 and the semiconductor chip 100, the light emitting element 200, and the light receiving element 300 (see Figure 5 ) arranged in a subsequent process.

[0045] The insulating layer 610 can be formed of one of a polymer such as polyimide, etc. and an oxide film, and can passivate the semiconductor chip 100 and the light emitting element 200 to prevent infiltration of foreign matter in the external environment to the inside.

[0046] The redistribution layer 600 can be formed on the light emitting surface SL of the light emitting element 200. The lead pattern 620 is arranged so as to avoid the light emitting surface SL of the light emitting element 200, such that light provided by the light emitting element 200 is not blocked, scattered, diffracted, or refracted by the redistribution layer 600. Further, the insulating layer 610 includes a material capable of transmitting light in a wavelength band emitted by the light emitting element 100. For example, the insulating layer 610 can be formed of one of a polymer such as polyimide, etc. and an oxide film, which has a transmittance of 90% or more when the light emitting element 100 provides light in a 940 nm wavelength band. The lead pattern 620 can be formed of a material having high electrical conductivity such as copper, aluminum, gold, etc.

[0047] Pads 624 can be formed on redistribution layer 600, which can be electrically connected to elements located thereon in subsequent processes. Pads 624 can be formed by opening to form pads connected to the lead pattern at desired locations and performing electroplating. Since pads 624 can be formed of, for example, copper and can be easily oxidized in air, coating can be implemented to improve the joining strength with pads 624.

[0048] For example, pads 624 can be coated with electroless nickel electroless palladium immersion gold (ENEPIG), in which an electroless nickel, electroless palladium, and gold layer are stacked on a copper pattern. As another example, pads 624 can be coated with electroless nickel immersion gold (ENIG), in which an electroless nickel and gold layer are stacked on a copper pattern. As yet another example, in pads 624, tin (Sn) can be coated on copper pads using hot air leveling (HAL). As yet another example, copper pads 624 can be coated with an organic material selectively joined to copper by an organic solderability preservative (OSP).

[0049] The light-receiving element 300 is arranged on the redistribution layer 600 to be electrically connected to the redistribution layer 600 (S400). Figure 5 is a cross-sectional view showing a state in which the light-receiving element 300 is arranged on the redistribution layer to be electrically connected to the redistribution layer. Figure 6 is a profile view showing a state in which the light-receiving element 300 according to another embodiment is arranged on the redistribution layer to be electrically connected to the redistribution layer.

[0050] Figure 5 The illustrated embodiment shows that the pads 624 and the light-receiving element 300 are electrically connected by wire bonding. The redistribution layer 600 and the light-receiving element 300 can be mechanically connected by an adhesive layer 304 located on a bonding surface of the light-receiving element 300. When the light-receiving element 300 is connected to the redistribution layer 600, the light-emitting surface SL of the light-emitting element 200 and the light-receiving surface SR of the light-receiving element 300 can face the same direction.

[0051] According to the present embodiment (not shown), electrical connection between the pads 624 and the light-receiving element 300 can be made by coupling an external connection terminal (e.g., a conductive bump, a solder ball, or the like) formed on the back surface of the light-receiving element to the pads 624.

[0052] Figure 6 The illustrated embodiment shows that the pads 624 are electrically connected to the light-receiving element 300 through a light-transmitting substrate 310 electrically connected to the light-receiving element 300. In one embodiment, the substrate 310 can be a transparent substrate formed of, for example, a material such as glass, polycarbonate (PC), or the like. The substrate 310 can not be completely transparent, and only a portion through which light passes can be partially transparent, or a cavity can be provided to pass light.

[0053] In Figure 6 In the embodiment shown, the light-receiving element 300 is arranged to receive light through the substrate 310. The substrate 310 has a pad 322 and a connection member for electrical connection with the light-receiving element 300, and is electrically connected to the light-receiving element 300. The substrate 310 can include a pad electrically connected to the pad 624 formed on the redistribution layer 600.

[0054] In Figure 6 In the embodiment shown, an example is described in which the electrical connection between the pad 322 formed on the transparent substrate 310 and the light-receiving element, the pad 324 formed on the transparent substrate 310, and the pad 624 formed on the redistribution layer 600 are all formed by solder balls, but the pads can be formed by one of a conductive bump and a pad.

[0055] Figure 7 (a) to Figure 7 (c) is a plan view of the package viewed from the top. Referring to Figures 5 to 7 (c), the light-receiving element 300 is positioned above the semiconductor chip 100, and at least a portion of the light-receiving element 300 is arranged to be positioned on the semiconductor chip 100. As Figure 7 (a) shows, the light-receiving element 300 can be positioned directly above the semiconductor chip 100. In Figure 7 (b) and Figure 7 (c), the semiconductor chip 100 and the light-receiving element 300 can have different cross-sectional areas. The light-receiving element 300 can be positioned above the semiconductor chip 100, and at least a portion of the light-receiving element 300 can be positioned directly above the semiconductor chip 100. Further, as Figure 7 (c) shows, the portion directly above the semiconductor chip 100 can be included within the cross-sectional area of the light-receiving element 300. The area of the package manufactured can be reduced by arranging the light-receiving element 300 in this way.

[0056] Figures 5 to 7 Embodiments are shown in which the light-receiving element 300 is arranged on the redistribution layer 600. However, as Figure 14 shown, the light-receiving element 300 can be connected to the package through the mother substrate 1000 (see Figure 14 ). After the semiconductor chip 100 is molded with the conductive metal pattern 120 and the light-emitting element 200 is molded with the conductive metal pattern 220, the conductive metal pattern 120 and the conductive metal pattern 220 can be exposed together with the external connection terminal 500 by a grinding process (see Figure 8 ).

[0057] Figure 8is a view showing a state in which the external connection terminal 500 is exposed. In one embodiment, the external connection terminal 500 is exposed by grinding the back surface of the package 10. For example, the grinding process can be implemented by a process such as grinding, chemical mechanical grinding (CMP), mechanical grinding, or the like. When the external connection terminal 500 is exposed, electrical connection can be performed by connection of the package according to the embodiment and a mother substrate (not shown) after the light receiving element 300 is disposed on the redistribution layer 600.

[0058] An example of a process shown in FIG. 6B is described, which is performed after the light receiving element 300 is disposed on the redistribution layer 600. However, the grinding process can be performed not only after the light receiving element 300 is disposed on the redistribution layer 600 but also before the light receiving element 300 is disposed on the redistribution layer 600. Figure 8

[0059] Although not shown in the drawings, in the package, a passive element including at least one of a resistor, an inductor, and a capacitor can be further formed on the insulating layer 610. The passive element can be formed on the redistribution layer 600. Figure 9 is a view of a state in which at least a portion of the insulating layer 610, which is on an optical path of light provided by the light emitting element 200, is removed. Figure 9 An example in which the conductive metal pattern 120 is attached to the back surface of the semiconductor chip 100 and the conductive metal pattern 220 is attached to the back surface of the light emitting element 200 is shown, and an example in which the external connection terminal 500, the conductive metal pattern 120 attached to the back surface of the semiconductor chip 100, and the conductive metal pattern 220 attached to the back surface of the light emitting element 200 are exposed during the grinding process is shown.

[0060] When the external connection terminal 500, the conductive metal pattern 120 attached to the semiconductor chip 100, and the conductive metal pattern 220 attached to the light emitting element 200 are exposed, the package according to the embodiment and a mother substrate (not shown) can be connected to form an electrical connection. For example, the mother substrate (not shown) can provide a reference voltage VSS to the light emitting element 200 through the conductive metal pattern 220. In addition, the mother substrate can provide driving power to the semiconductor chip 100 through the conductive metal pattern 120 and the external connection terminal 500.

[0061] In one embodiment, the insulating layer 610 in a path through which light provided by the light emitting element 200 passes is removed. The process of removing the insulating layer 610 can be performed by anisotropic etching, and can be performed using plasma.

[0062] An example of a process shown in FIG. 6B is described, which is performed after the light receiving element 300 is disposed on the redistribution layer 600. However, the grinding process can be performed not only after the light receiving element 300 is disposed on the redistribution layer 600 but also before the light receiving element 300 is disposed on the redistribution layer 600. Figure 9 ​The example shown is of the operation of removing a portion of the insulating layer 610, but this is only an example and the operation of removing a portion of the insulating layer 610 can be performed by patterning the insulating layer 610 in the process of forming the lead pattern 620 of the redistribution layer 300.

[0063] although Figure 9 An example of removing a portion of the insulating layer 610 is shown; however, according to an embodiment (not shown), after a protective film (not shown) is formed on the light-emitting surface SL, an anisotropic etching process using plasma can be performed by completely removing the insulating layer 610 until the protective film is exposed. However, when the insulating layer 610 is formed of a material with a high transmittance of 90% or more to the light provided by the light-emitting element 200, the process of removing the insulating layer 610 may not be performed.

[0064] Figure 10 This is a schematic view showing the formation of a lens structure in the optical path of the light provided by the light-emitting element 200. (Reference) Figure 10 The lens structure 800 includes microlenses 804 at positions corresponding to the light source 222 (see [link]). Figure 3 ).

[0065] According to another embodiment (not shown), the lens structure 804 may include one or more lenses that perform optical processing on light provided by a plurality of light sources 222 (see [link to embodiment]). Figure 3 For example, lens structure 800 may include a first lens that focuses light provided by some light sources 222 (see...). Figure 3 ) and a second lens that collimates the light provided by the remaining light source 222 (see Figure 3 ).

[0066] Although an example of forming the lens structure 800 after removing the insulating layer 610 has been described, this is merely an example, and the formation of the lens structure 800 can be performed after forming the redistribution layer 600. In another embodiment, the lens structure 800 may be disposed on a transparent substrate such as glass or polycarbonate (PC). The microlens 804 may be formed by photoresist reflow (PR reflow), inkjet printing, transfer printing, or the like.

[0067] Figure 11 This is a schematic view showing the state in which a diffuser member 700 is formed on the luminescent surface of the luminescent element 200. (Refer to...) Figure 11The diffusing member 700 can be formed by applying a photoresist (PR) on the insulating layer 610, performing patterning to form a random pattern, and then reflowing the random pattern. In an embodiment not shown, the diffusing member 700 can be formed by forming a diffusing pattern on a transparent substrate such as glass, polycarbonate (PC), or the like to diffuse light. The diffusing pattern includes an irregularly formed uneven pattern and an irregularly formed straight pattern.

[0068] In Figure 11 the example, formation of the diffusing member 700 on the insulating layer 610 is described, but this is merely an example, and formation of the diffusing member 700 can be performed after the insulating layer 610 is removed, and the diffusing member 700 can be formed after the lead pattern 620 is formed when the redistribution layer 600 is formed.

[0069] Figure 12 and Figure 13 are views showing a member holder 900 of the package 10. In Figure 12 the embodiment shown, the member holder 900 supports an optical member 920 located on an optical path of the light emitting element 200 and an optical member 930 located on an optical path of the light receiving element 300. The member holder 900 includes a leg 940 including a pin 942. The pin 942 is inserted into a hole (not shown) formed in a mother substrate 1000 (see Figure 14 ) to fix the member holder 900 to the mother substrate (not shown).

[0070] Each of the optical members 920 and 930 can be composed of a single lens or a plurality of lenses, a diffuser, a polarization filter, a band pass filter of a desired wavelength band (infrared (IR), ultraviolet (UV), visible light, or the like), and combinations thereof. For example, the optical members 920 and 930 can be fixed to an optical member housing (not shown) and coupled to the optical member holder, and the optical member housing can be, for example, a lens barrel that fixes a lens portion.

[0071] In Figure 13 the embodiment shown, the member holder 900 supports an optical member 920 located on an optical path of the light emitting element 200 and an optical member 930 located on an optical path of the light receiving element 300. The leg 940 of the member holder 900 is supported by the redistribution layer 600 and the sidewall SW of the package, and an adhesive 944 is disposed on a portion of the leg 940 facing the redistribution layer 600 and the sidewall SW of the package. The adhesive 944 adheres to the sidewall SW of the package and the upper surface of the redistribution layer 600, and fixes the holder 900 to the package.

[0072] In Figure 12 and Figure 13In the illustrated embodiment, the optical member 930 and the optical member 920 are arranged on the light paths of the light receiving element 300 and the light emitting element 200, respectively. Accordingly, the optical performance of the package can be improved by processing the light provided to the light receiving element 300 and the light provided by the light emitting element 200.

[0073] In Figure 12 and Figure 13 In the illustrated embodiment, the optical member 930 is illustrated as a convex lens. However, this is merely an example, and an optical member performing one or more functions of converging, diverging, and collimating light by including at least one of a convex lens, a concave lens, and a combination thereof can be arranged in the member holder 900. Furthermore, a lens can be formed on the light path of the light emitting element 200, and in this case, in the member holder 900, a diffusing member can be arranged on the light path of the light provided by the light emitting element 200.

[0074] Hereinafter, the package 10 according to an embodiment will be described with reference to Figures 8 to 12 However, for a brief and clear description, the description of elements identical or similar to the above-described elements can be omitted. Figures 8 to 14 is a cross-sectional view illustrating the outline of the optical element semiconductor package 10 according to an embodiment. The optical element semiconductor package 10 according to the present embodiment includes a light emitting element 200, a light receiving element 300, a semiconductor chip 100 in which a semiconductor circuit is formed, a mold covering the semiconductor chip 100 and the light emitting element 200, a redistribution layer 600 electrically connecting the light emitting element 200, the light receiving element 300, and the semiconductor chip 300, a via 400 electrically connected to the redistribution layer 600 and passing through the mold, and an external connection terminal 500 electrically connected to the via, and the light receiving element 300 is positioned on the redistribution layer 600.

[0075] The light emitting element 200 can be one of a VCSEL and an LED, and can provide light in a wavelength range such as infrared light, visible light, ultraviolet light, etc. Furthermore, the light emitting element 200 can output laser light in a desired wavelength range. In one embodiment, the light receiving element 300 can be an optical element that detects light in a desired wavelength range, and can be one of a photodiode (PD), a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), and a single-photon avalanche diode (SPAD). As Figure 7 (a) to Figure 7 (c), at least a portion of the light receiving element 300 can be positioned directly above the semiconductor chip 100, thus providing an advantage in which the total area of the semiconductor package can be reduced.

[0076] Figure 14 is a view illustrating another embodiment of the package 10. Referring to Figure 14The package 10 is electrically connected to the mother substrate 1000 through the exposed external connection terminal 500 and the conductive metal patterns 120 and 220. A driving circuit (not shown), a control circuit (not shown), a power supply circuit (not shown), etc. can be located in the mother substrate 1000. The package 10 can transmit and receive electrical signals, and receive power from the driving circuit (not shown), the control circuit (not shown), and the power supply circuit (not shown).

[0077] The light receiving element 300 can be located on the mother substrate 1000, and can be electrically connected to the package 10, the driving circuit (not shown), the control circuit (not shown), and the power supply circuit (not shown) through a conductive path (not shown) formed in the mother substrate 1000.

[0078] In one embodiment, the package 10 and the light receiving element 300 can be electrically connected to the mother substrate through anisotropic conductive film (ACF) or through surface mount technology (SMT).

[0079] Figure 15 is a view showing one embodiment of the package 10 according to an embodiment. Referring to Figure 15 The package 10 can be used to measure a distance to a target T. The light emitting element 200 receives a driving signal and / or power from the semiconductor chip 100 and provides light.

[0080] The light provided by the light emitting element 200 travels along an optical path. In one embodiment, the package 10 includes a member holder 900, and the member holder 900 includes an optical member arranged on an optical path of the light emitting element 200 and an optical path of the light receiving element 300 to perform one or more functions of converging, diverging, and collimating light.

[0081] Light is reflected from the target T and provided to the light receiving element 230 through the optical path L. The semiconductor chip 100 drives the light emitting element 200 so that the light emitting element 200 emits light, and receives an electrical signal corresponding to the reflected light detected by the light receiving element 300. The semiconductor chip 100 can calculate a time difference (TOF: Time of Flight) from a time at which the light emitting element 200 emits light to a time at which the light receiving element 300 detects light, and calculate a distance corresponding to the time difference. The calculated distance corresponds to a distance between the optical element semiconductor package 10 and the target T. The calculated time difference or distance can be provided to an external device (not shown) through the external connection terminal 500.

[0082] Although the embodiments shown in the drawings are described as references to help understanding of the present application, they are embodiments for implementation, and are merely exemplary, and various modifications and equivalents can be performed by those skilled in the art. Therefore, the true technical scope of the present application should be defined by the appended claims.

Claims

1. A method of manufacturing a package, comprising operations of: attaching a conductive metal pattern to a rear surface of a light emitting element; exposing the conductive metal pattern; molding a semiconductor chip and the light emitting element, wherein the molding is performed by molding the light emitting element and the conductive metal pattern attached to the light emitting element together; forming a redistribution layer (RDL) configured to electrically connect the semiconductor chip and the light emitting element; and arranging a light receiving element on the redistribution layer to electrically connect the light receiving element and the redistribution layer, wherein the light receiving element is arranged such that at least a portion of the light receiving element is located directly above the semiconductor chip.

2. The method of claim 1, further comprising operations of: attaching a conductive metal pattern to a rear surface of the semiconductor chip before the molding, wherein performing the molding by molding the semiconductor chip and the conductive metal pattern attached to the semiconductor chip together.

3. The method of claim 1, wherein, performing the molding by further molding a conductive bar having an external connection terminal formed thereon and the conductive metal pattern attached to the semiconductor chip and the conductive metal pattern attached to the light emitting element.

4. The method of claim 3, wherein, the external connection terminal is one of a solder ball, a conductive bump, and a pad.

5. The method of claim 1, wherein, the molding includes an operation of further molding a sacrificial member having a lower hardness than a mold, and the method of manufacturing a package further comprises operations of: punching the sacrificial member to form a through hole; and forming a conductive material in the through hole.

6. The method of claim 1, wherein, the operation of forming the redistribution layer includes operations of: forming a lead pattern configured to electrically connect the semiconductor chip and the light emitting element; and forming an insulating layer configured to passivate the lead pattern, the semiconductor chip, and the light emitting element.

7. The method of claim 6, wherein: the operation of forming the redistribution layer further includes an operation of forming a pad electrically connected to the lead pattern; and the operation of forming the pad includes operations of: removing the insulating layer to expose the lead pattern, performing electroplating to form a pad electrically connected to the exposed lead pattern, and coating the pad.

8. The method of claim 1, further comprising an operation of: forming one of an optical member and a diffuser on an optical path of light provided by the light emitting element.

9. The method of claim 8, further comprising an operation of: removing at least a portion of the redistribution layer located on the optical path before forming the one of the optical member and the diffuser.

10. The method of claim 3, further comprising an operation of: exposing the external connection terminal.

11. A package, comprising: a light emitting element; a light receiving element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to package the semiconductor chip and the light emitting element; a redistribution layer configured to electrically connect the light emitting element, the light receiving element, and the semiconductor chip; ​ a via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the via, wherein at least a portion of the light-receiving element is located directly above the semiconductor chip, wherein the light-receiving element has a conductive metal pattern attached to a rear surface of the light-emitting element, and the mold encapsulates the light-emitting element and the conductive metal pattern attached to the light-emitting element together, and wherein the via has a conductive rod electrically connecting the redistribution layer and the external connection terminal, and a housing molded together with the conductive rod and encapsulating the conductive rod.

12. The package of claim 11, wherein: the light-emitting element is one of a vertical cavity surface emitting laser (VCSEL) and a light-emitting diode (LED); and the light-receiving element is one of a photodiode (PD), a CMOS image sensor (CIS), and a single photon avalanche diode (SPAD).

13. The package of claim 11, wherein, the semiconductor circuit includes one or more of a light-emitting element driving circuit, a light-receiving element driving circuit, and a time-of-flight (TOF) arithmetic circuit.

14. The package of claim 11, wherein, the redistribution layer includes: an insulating layer configured to passivate the semiconductor chip, and a lead pattern configured to electrically connect the light-emitting element, the light-receiving element, and the semiconductor chip.

15. The package of claim 14, wherein, the insulating layer is formed as one of a polyimide layer, a polymer layer, and an oxide layer.

16. The package of claim 11, wherein, the external connection terminal is one of a solder ball, a conductive bump, and a land.

17. The package of claim 11, further comprising one of an optical member and a diffusing member formed on an optical path of the light-emitting element.

18. The package of claim 17, wherein: at least a portion of the insulating layer is removed on the optical path; and one of a light-emitting element lens unit and a diffusing unit is formed on the optical path.

19. The package of claim 17, further comprising: one of a light-emitting element lens unit and a diffusing unit; and a holder in which a light-receiving element lens unit formed on an optical path of the light-receiving element is located.

20. The package of claim 19, wherein, the holder is fixed to one or more of the package and a mother substrate on which the package is mounted.

21. The package of claim 11, wherein: the light-emitting element is stacked and located on a conductive metal pattern; and the light-receiving element is stacked and located on a conductive metal pattern.

22. The package of claim 11, wherein, the light-receiving element is located above the semiconductor chip.

23. A package, comprising: a light-emitting element; a light-receiving element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to encapsulate the semiconductor chip and the light-emitting element; a redistribution layer configured to electrically connect the light-emitting element, the light-receiving element, and the semiconductor chip; a via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the via, wherein the light-receiving element has a conductive metal pattern attached to a rear surface of the light-emitting element, and the mold encapsulates the light-emitting element and the conductive metal pattern attached to the light-emitting element together.

24. The package of claim 23, wherein: the light emitting element is one of a VCSEL and an LED; and the light receiving element is one of a photodiode (PD), a CMOS image sensor (CIS), and a single photon avalanche diode (SPAD).

25. The package of claim 23, wherein, the semiconductor circuit includes one or more of a light emitting element driving circuit, a light receiving element driving circuit, and a time of flight (TOF) arithmetic circuit.

26. The package of claim 23, wherein, the redistribution layer includes: an insulating layer configured to passivate the semiconductor chip, and a lead pattern configured to electrically connect the light emitting element, the light receiving element, and the semiconductor chip.

27. The package of claim 26, wherein, the insulating layer is formed as one of a polyimide layer, a polymer layer, and an oxide layer.

28. The package of claim 23, wherein, the external connection terminal is one of a solder ball, a conductive bump, and a land.

29. The package of claim 23, further comprising one of an optical member and a diffusing member formed on an optical path of the light emitting element.

30. The package of claim 29, wherein: at least a portion of the insulating layer is removed on the optical path; and one of a light emitting element lens unit and a diffusing unit is formed on the optical path.

31. The package of claim 29, further comprising a holder, wherein the one of the optical member and the diffusing member on the optical path is located in the holder.

32. The package of claim 31, wherein, the holder is fixed to one or more of the package and a mother substrate on which the package is mounted.

33. The package of claim 23, wherein, the semiconductor chip is stacked and located on a conductive metal pattern.

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