Novel multilayer TSV interconnection structure

Abstract

The utility model discloses a novel multilayer TSV interconnection structure, and relates to the semiconductor chip packaging technology field, the novel multilayer TSV interconnection structure comprises a middle layer chip, a top layer chip and a bottom layer chip are respectively arranged above and below the middle layer chip, the top end of the middle layer chip and the top end of the bottom layer chip are respectively provided with a second RDL rewiring layer, and the bottom layer chip is provided with a second RDL rewiring layer. TSV metal through holes are filled in the middle-layer chip through electroplating, and connecting convex balls are grown at the positions Bump, close to the TSV metal through holes, of the bottoms of the middle-layer chip and the top-layer chip; according to the utility model, the two TSVs in the chip are connected to the same output end, so that the electrical performance can be effectively improved, the connection reliability can be enhanced, the packaging process can be simplified, different packaging requirements can be met, the heat management can be optimized, and meanwhile, the area of the output end of the TSV of the chip is enlarged, so that the heat can be effectively dissipated, and the connection stability and reliability can be improved; and faults caused by poor contact or mechanical stress are reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor chip packaging, and relates to a 3D multilayer TSV interconnection packaging structure of a chip and application thereof, in particular to a novel multilayer TSV interconnection structure. BACKGROUND

[0002] Through-Silicon Via, abbreviated as TSV, is a technology that realizes interconnection between chips by making vertical conduction between chips and between wafers, and is one of the key process technologies of 2.5D / 3D packaging. Through vertical interconnection, the interconnection length, signal delay, capacitance and inductance are reduced, low-power and high-speed communication between chips is realized, bandwidth is increased, and miniaturization is achieved. The Through-Silicon Via (TSV) process technology is a key process that effectively improves the integration and performance of wafer-level multi-layer stacking technology. Wire bonding and flip chip provide electrical interconnection of chips to the outside, RDL (redistribution layer) provides electrical interconnection in the horizontal direction of the chip, and the Through-Silicon Via (TSV) process technology provides electrical interconnection in the vertical direction of the silicon wafer. The Through-Silicon Via process technology is mainly applied to high-performance computing and communication equipment, consumer electronics, image sensors and 3D memory, micro-electro-mechanical systems (MEMS), new energy vehicles and Internet of Things devices; With its unique advantages, it plays an important role in many high-tech fields and promotes the development of electronic devices to smaller and higher performance. With the progress of process technology and the driving of market demand, TSV technology is still developing, and its application fields may be more extensive in the future.

[0003] 1. The Through-Silicon Via process technology is usually a single via leading out and connected to a single solder ball. This design has specific applications and advantages in three-dimensional integrated circuit packaging, but also has some disadvantages:

[0004] 2. Electrical performance: connecting a single via to a single solder ball can simplify the signal path and reduce signal transmission delay and interference; at the same time, although single connection helps signal transmission, in high-frequency applications, it may be affected by parasitic parameters such as resistance, capacitance, etc., resulting in performance degradation.

[0005] 3. Mechanical stability: connecting a single via to a solder ball can cause mechanical stress concentration, especially in the case of temperature changes or external vibrations, which can affect the stability and reliability of the connection.

[0006] 4. Heat dissipation problem: heat transfer limitation: connecting a single via to a solder ball can limit the heat transfer path, causing local overheating problems, especially in high-power applications.

[0007] 5. Reliability: Due to the above-mentioned thermal mismatch, mechanical stress concentration and other problems, the design of a single through-silicon via connected to a solder ball may face challenges in long-term stability. If any defects or damage occur in the via, the entire connection may fail, affecting the reliability of the system;

[0008] Therefore, for the above problems, we propose a new multi-layer TSV interconnection structure, which is a design of two TSV vias connected to the same solder ball, and the via output end area is expanded, which has advantages in improving electrical performance, enhancing connection reliability, simplifying packaging process, adapting to different packaging needs, and optimizing thermal management. Practical new type

[0009] The utility model discloses a new multi-layer TSV interconnection structure to solve the problems raised in the background art.

[0010] To achieve the above object, the utility model provides the following technical scheme:

[0011] A new multi-layer TSV interconnection structure, comprising an intermediate layer chip, a top layer chip and a bottom layer chip are arranged above and below the intermediate layer chip respectively, and the top ends of the intermediate layer chip and the bottom layer chip are respectively provided with a second RDL redistribution layer, the inside of the intermediate layer chip is filled with a TSV metal via by electroplating, and the bottom of the intermediate layer chip and the top layer chip grows a connecting convex ball at the position close to the TSV metal via, the inside of the bottom layer chip is provided with a chip internal RDL redistribution structure, and the bottom of the chip internal RDL redistribution structure is provided with an output end, and the bottom end of the bottom layer chip is provided with a tin ball at the position corresponding to the output end.

[0012] As a further technical scheme of the utility model, the connecting convex ball is one of uBUMP, C ball or C ball.

[0013] As a further technical scheme of the utility model, the chip internal RDL redistribution structure is connected with two groups of TSV metal vias through the connecting convex ball.

[0014] Compared with the prior art, the utility model has the advantages that:

[0015] (1) The utility model can improve the integration: two TSV vias are led out to an output end at the same time, which can reduce the number of external connections, thereby improving the integration of packaging; at the same time, by reducing the use of output ends, the design of the packaging structure can be simplified, and the manufacturing cost and complexity can be reduced.

[0016] (2) The utility model can enhance signal integrity: two TSV vias are led out to an output end at the same time, which can reduce reflection and interference in the signal transmission path, thereby improving the integrity of the signal.

[0017] (3), the utility model discloses, can improve the reliability of signal: the same TSV of two signals is connected to the same output, can effectively avoid when one of them abnormal signal failure problem, simultaneously, increase the area of output can improve the stability and reliability of connection, reduce the failure caused by poor contact or mechanical stress,

[0018] (4), the utility model discloses, can improve the heat dissipation performance: lead two TSV via holes to an output simultaneously, help optimize the heat distribution inside package, improve the thermal management efficiency, and, the larger output area helps to dissipate heat better, avoid the performance decline or damage due to overheating. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a novel multilayer TSV interconnection structure structure schematic diagram of the utility model.

[0020] In the drawing: 1, top chip; 2, connecting convex ball; 3, first RDL rewiring layer; 4, TSV metal via hole; 5, middle layer chip; 6, second RDL rewiring layer; 7, chip internal RDL rewiring structure; 8, bottom chip; 9, output; 10, tin ball. DETAILED DESCRIPTION

[0021] The technical scheme in the embodiments of the utility model will be described clearly and completely below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the utility model.

[0022] Please refer to Figure 1 In the embodiments of the utility model, a novel multilayer TSV interconnection structure includes middle layer chip 5, top chip 1 and bottom chip 8 are arranged above and below the middle layer chip 5 respectively, and the top ends of the middle layer chip 5 and the bottom chip 8 are respectively provided with 3 and the second RDL rewiring layer 6, the inside of the middle layer chip 5 is filled with TSV metal via hole 4 by electroplating, and the middle layer chip 5 and the bottom of the top chip 1 grow bump 2 near the position of TSV metal via hole 4, the inside of the bottom chip 8 is provided with chip internal RDL rewiring structure 7, and the bottom of the chip internal RDL rewiring structure 7 is provided with output 9, and the tin ball 10 is installed on the bottom end of the bottom chip 8 corresponding to the position of output 9.

[0023] In the example, the connecting convex ball 2 is one of uBUMP, C4 ball or C2 ball.

[0024] In this example, the chip internal RDL re-wiring structure 7 is connected with two groups of TSV metal through holes 4 through the connecting convex balls 2.

[0025] The working principle of the utility model is: in use, firstly, prepare wafer, start from a chip covered with silicon dioxide layer, this layer of silicon dioxide can be formed through thermal oxidation or plasma enhanced chemical vapor deposition method;

[0026] Then, coat photoresist on the silicon wafer, pattern through exposure and development steps, design to connect every two TSV through holes to the same output end, to obtain the area to be etched in the following process;

[0027] Then, use the photoetching pattern as a mask, use dry or wet etching technology to etch the required pattern on the wafer, and deepen etching at the through hole output end, so that the subsequent metal filling area is expanded, and the output end area is increased;

[0028] After etching is completed, remove the photoresist to prepare for the following silicon through hole deposition step;

[0029] In the deposition step, a layer of silicon dioxide is deposited on the hole wall as an insulating layer through physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) technology to prevent electronic interference;Then deposit a layer of conductive barrier layer, such as titanium / copper or tantalum / copper, so that the subsequent copper plating layer can be attached on it, and also prevent electronic migration;

[0030] Then, electroplating filling is performed, and a metal layer is electroplated on the insulating layer and the barrier layer to fill the TSV hole, which is generally completed by electroplating, and after electroplating is completed, annealing process is performed to release stress;

[0031] Then, chemical mechanical polishing is performed, and CMP is used to smooth the surface, remove excess metal and barrier layer, so that the copper at the bottom of the silicon through hole is exposed, and a metal TSV flush with the wafer surface is obtained;

[0032] In order to improve the performance and reliability of the packaged device, the wafer is thinned. This step helps to reduce the thickness of the wafer and improve the packaging efficiency;

[0033] Finally, grow uBump or perform C4 / C2 ball planting at the output end at the bottom of the chip, which is convenient for connecting the lower layer chip or PCB board.

[0034] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that it can be implemented in other concrete forms without departing from the spirit or the essential characteristics of the present application. Therefore, the embodiments should be considered as exemplary and non-limiting, the scope of the present application being defined by the claims appended hereto rather than by the above description, and all the changes which fall within the meaning and the scope of the equivalent elements of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0035] Furthermore, it should be understood that although the present specification describes exemplary embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that a person skilled in the art can understand.

Claims

1. A novel multi-layer TSV interconnection structure, characterized in that: The chip includes an intermediate layer chip, a top layer chip and a bottom layer chip are arranged above and below the intermediate layer chip respectively, and the top ends of the intermediate layer chip and the bottom layer chip are respectively provided with a second RDL redistribution layer, the inside of the intermediate layer chip is filled with a TSV metal through hole by electroplating, and the bottom of the intermediate layer chip and the top layer chip grows a connecting bump near the position Bump of the TSV metal through hole, the inside of the bottom layer chip is provided with a chip internal RDL redistribution structure, and the bottom of the chip internal RDL redistribution structure is provided with an output end, and the bottom end of the bottom layer chip is installed with a tin ball at the position corresponding to the output end.

2. The novel multi-layer TSV interconnection structure according to claim 1, characterized in that: The connecting bump is one of uBUMP, C4 ball or C2 ball.

3. The novel multi-layer TSV interconnection structure according to claim 1, characterized in that: The chip internal RDL redistribution structure is connected with two groups of TSV metal through holes through the connecting bump.

Images