Semiconductor structure and method of manufacturing the same

Abstract

The semiconductor structure and the manufacturing method thereof provided by the present disclosure remove the adhesive layer in the FOSub (Fan-Out Substrate) structure and set the redistribution layer in the via defined by the substrate to reduce the overall thickness of the FOSub.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] FOSub (Fan-Out Substrate) is a method of combining Fan-Out and Substrate at present. Specifically, Fan-Out is combined with Substrate through an Adhesion film, and the electrical channel between Fan-Out and Substrate is connected through a Via.

[0003] As shown in Figure 1 The overall thickness of FOSub includes the thickness H1 of the redistribution layer, the thickness H2 of the adhesive layer, and the thickness H3 of the substrate. However, the thickness H2 of the adhesive layer used at present is about 30-60 microns, which results in that the overall thickness of FOSub cannot be thinned. SUMMARY

[0004] The present disclosure provides a semiconductor structure and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate having an opening; and a first redistribution structure disposed on the first surface of the substrate and in the opening, the first redistribution structure contacting a sidewall of the opening.

[0006] In some optional embodiments, the semiconductor structure further comprises: a second redistribution structure disposed on the second surface and in the opening, the second redistribution structure contacting the sidewall of the opening and electrically connected to the first redistribution structure.

[0007] In some optional embodiments, the first redistribution structure and / or the second redistribution structure is a multilayer redistribution structure, and at least one redistribution layer in the multilayer redistribution structure is disposed in the opening.

[0008] In some optional embodiments, the semiconductor structure further comprises: an electronic component disposed on and electrically connected to the first redistribution structure.

[0009] In some optional embodiments, the semiconductor structure further comprises: an antenna device disposed on and electrically connected to the first redistribution structure.

[0010] In some alternative embodiments, the semiconductor structure further comprises: a conductive liner disposed on the outer surface of the first redistribution structure and / or the outer surface of the second redistribution structure, and electrically connecting the first redistribution structure and / or the second redistribution structure and / or the substrate.

[0011] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate having opposite first and second surfaces, the substrate having an opening; forming a first redistribution structure on the first surface and in the opening such that the first redistribution structure contacts sidewalls of the opening, the first redistribution structure being formed in a photolithographic manner.

[0012] In some alternative embodiments, before forming the first redistribution structure on the first surface and in the opening, the method further comprises:

[0013] forming a second redistribution structure on the second surface and in the opening such that the second redistribution structure contacts the sidewalls of the opening, the second redistribution structure being formed in a photolithographic manner.

[0014] In some alternative embodiments, forming the second redistribution structure on the second surface and in the opening comprises:

[0015] providing a second carrier;

[0016] forming a second line layer on the second carrier;

[0017] disposing a second dielectric material on the second line layer;

[0018] disposing the core substrate on the second dielectric material, exposing and curing to obtain a second dielectric layer, and forming a third line layer on the second dielectric layer, the second line layer, the second dielectric layer, and the third line layer collectively forming the second redistribution structure.

[0019] In some alternative embodiments, forming the first redistribution structure on the first surface and in the opening comprises:

[0020] providing a first carrier;

[0021] forming a first line layer on the first carrier;

[0022] disposing a first dielectric material on the second redistribution structure and in the opening;

[0023] turning over the first line layer and disposing it on the first dielectric material, exposing and curing to obtain a first dielectric layer, and the first line layer and the first dielectric layer collectively forming the first redistribution structure.

[0024] In some alternative embodiments, the method further comprises: forming a conductive liner on the first redistribution structure and the second redistribution structure.

[0025] In order to solve the technical problem that the overall thickness of the FOSub cannot be reduced due to the thickness of the adhesive layer being about 30-60 microns, the semiconductor structure and the manufacturing method thereof provided by the present disclosure remove the adhesive layer and set the redistribution layer in the through hole defined by the substrate to reduce the overall thickness of the FOSub. In addition, the semiconductor structure provided by the present disclosure can be a double-sided packaging structure, which not only improves the utilization rate of the substrate and reduces the overall packaging size, but also improves the number and density of I / O. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0027] Figure 1 is a structural schematic diagram of a semiconductor structure in the prior art;

[0028] Figures 2-8 is a first structural schematic diagram to a seventh structural schematic diagram of a semiconductor structure according to the present disclosure;

[0029] Figures 9A to 9N is a structural schematic diagram in the manufacturing process of a semiconductor structure according to the present disclosure.

[0030] SYMBOL DESCRIPTION:

[0031] 1 - substrate, 11 - opening, 12 - conductive pad, 13 - external electrical connector, 2 - first redistribution structure, 21 - first wiring layer, 22 - first dielectric layer, 23 - first dielectric material, 3 - second redistribution structure, 31 - second wiring layer, 32 - second dielectric layer, 33 - second dielectric material, 4 - electronic component, 5 - antenna device, 6 - via hole, 7 - second carrier, 8 - first carrier, 9 - mask layer, 10 - third wiring layer, A - first region, B - second region, C - third region. DETAILED DESCRIPTION

[0032] The specific embodiments of the present disclosure are described below in conjunction with the drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced by the content recorded in the present description. It can be understood that the specific embodiments described herein are only used to explain the related invention, and not to limit the invention. In addition, in order to facilitate description, only the parts related to the invention are shown in the drawings.

[0033] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0034] Furthermore, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Reference will be made below. Figure 2 This disclosure will be described in detail with reference to the embodiments.

[0035] Please refer to Figures 2-8 , Figures 2-8 The first to seventh structural schematic diagrams of the semiconductor structure according to the present disclosure are shown.

[0036] Figure 2 A first structural schematic diagram of the semiconductor structure of this disclosure is shown. Figure 2 The semiconductor structure shown may include a substrate 1, a first redistribution structure 2, and a second redistribution structure 3. The substrate 1 may have a first surface and a second surface opposite to the first surface. The substrate 1 may have an opening 11. The first redistribution structure 2 may be disposed on the first surface of the substrate and in the opening 11. The first redistribution structure 2 may contact the sidewall of the opening 11. The first redistribution structure 2 may be electrically connected to the second redistribution structure 3. The second redistribution structure 3 may be disposed on the second surface and in the opening 11.

[0037] In this embodiment, the substrate 1 can comprise polyimide (PI), ABF substrate (ABF), molding compounds, pre-impregnated composite fibers (e.g., prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), and combinations thereof, or other similar materials. The substrate can also comprise gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof. The substrate 1 can include a medium- or low-density circuit layer with high performance, such as high power, high current, or high heat dissipation, etc. The substrate 1 can be a core substrate.

[0038] In this embodiment, the first redistribution structure 2 and the second redistribution structure 3 are structurally balanced with respect to the substrate 1, thereby allowing a double-sided package structure to be formed. The first redistribution structure 2 and the second redistribution structure 3 can comprise high-density circuit layers to provide more I / O counts, thereby allowing more functions to be implemented.

[0039] In this embodiment, Figure 2 The semiconductor structure shown can further include a conductive pad 12. The conductive pad 12 can be disposed on an outer surface of the first redistribution structure 2 and / or an outer surface of the second redistribution structure 3, and can be electrically connected to the first redistribution structure 2 and / or the second redistribution structure 3 and / or the substrate 1. The conductive pad 12 can be, for example, an under-ball metallurgy (UBM) pattern.

[0040] Figure 4 A third structural schematic of the semiconductor structure of the present disclosure is shown. The semiconductor structure shown is similar to the semiconductor structure shown in FIG. 1, except that Figure 2 The difference between the semiconductor structure shown and the semiconductor structure shown in FIG. 1 is that, as shown in FIG. 2, the first redistribution structure 2 and the second redistribution structure 3 are structurally balanced with respect to the substrate 1, thereby allowing a double-sided package structure to be formed. Figure 4The semiconductor structure shown may also include electronic components 4, antenna devices 5, and external electrical connectors 13. Electronic components 4 and antenna devices 5 may be disposed on the first rewiring structure 2. External electrical connectors 13 may be electrically connected to the second rewiring structure 3 and / or the substrate 1, for example, via conductive pads 12, and then electrically connected to the electronic components 4 and antenna devices 5 via the first rewiring structure 2, which is electrically connected to the second rewiring structure 3 and / or the substrate 1. External electrical connectors 13 may be, for example, solder balls, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, or microbumps.

[0041] Figure 5 A fourth structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 5 The first rewiring structure 2 and / or the second rewiring structure 3 of the semiconductor structure shown can be a multilayer rewiring structure. At least one rewiring layer in the multilayer rewiring structure can be disposed in the opening 11.

[0042] Figure 6 A fifth schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 6 The vias 6 in the first wiring structure 2 and / or the second wiring structure 3 of the semiconductor structure shown can be partially filled, which can save costs and avoid the problem that full filling can easily create gaps that affect electrical performance.

[0043] Figure 7 A sixth structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 7 The semiconductor structure shown may include multiple first rewiring structures 2 and / or multiple second rewiring structures 3.

[0044] Figure 8 A seventh structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown...) Figure 8 The vias 6 in the first rewiring structure 2 and the second rewiring structure 3 of the semiconductor structure shown can be in opposite directions. That is, the vias 6 in the first rewiring structure 2 gradually shrink in the direction toward the substrate 1, and the vias 6 in the second rewiring structure 3 gradually shrink in the direction toward the substrate 1.

[0045] Compared to existing technologies, the overall thickness of FOSub can include the thickness H1 of the redistribution layer, the thickness H2 of the adhesive layer, and the thickness H3 of the substrate (e.g., ...). Figure 2 As shown), the semiconductor structure provided in this disclosure, the overall thickness of FOSub may include a portion of the thickness H4 of the first rewiring structure 2, the thickness H5 of the substrate, and a portion of the thickness H6 of the second rewiring structure 3 (as shown).Figure 3 As can be seen, the semiconductor structure provided by the present disclosure removes the adhesive layer, i.e. the overall thickness can not include the thickness of the adhesive layer, and the first redistribution structure 2 and the second redistribution structure 3 are disposed in the opening defined by the substrate 1, i.e. the thickness of the substrate can include the partial thickness of the first redistribution structure 2 and the partial thickness of the second redistribution structure 3, thereby reducing the overall thickness of the FOSub. In addition, compared with the single-sided packaging structure of the prior art FOSub, the semiconductor structure provided by the present disclosure can be a double-sided packaging structure, which not only improves the utilization rate of the substrate and reduces the overall packaging size, but also improves the number and density of I / O.

[0046] Figures 9A to 9M The structural schematic diagrams in the manufacturing process of the semiconductor structure according to the present disclosure are shown. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0047] As shown in Figure 9A , the substrate 1 is provided.

[0048] As shown in Figure 9B , the opening 11 can be formed on the substrate 1 by laser drilling or the like.

[0049] As shown in Figures 9C to 9G , the process of forming the second redistribution structure 3 in the substrate 1 and the opening 11 is shown. Specifically, as shown in Figure 9C , the second carrier 7 is provided, and the second circuit layer 31 can be formed on the second carrier 7 by physical vapor deposition (PVD), exposure development (photolithography) or the like. As shown in Figure 9D , the second dielectric material 33 covering the second circuit layer 31 can be formed by a potting process, and the substrate 1 is disposed on the second dielectric material 33 using the bonding head of the bonding device. As shown in Figure 9E , the second dielectric layer 32 can be cured by an exposure process. As shown in Figure 9F , the patterned mask layer 9 is formed, and the via 6 and the third circuit layer 10 can be formed in the patterned mask layer 9 by an electroplating process. After removing the patterned mask layer 9, as shown in Figure 9G , the top view shown in the upper figure in , the first area A is a low-density circuit layer compared with the second area B. The second area B is a high-density circuit layer, which can provide more I / O quantity.

[0050] As shown in Figures 9H to 9L , the process of forming the first redistribution structure 2 in the substrate 1 and the opening 11 is shown. Specifically, as shown in Figure 9HAs shown, a first carrier 8 is provided, and a first line layer 21 can be formed on the first carrier 8 by a physical vapor deposition process, a photolithography process, or the like. As shown, Figure 9I As shown, a first dielectric material 23 can be formed on the second redistribution structure 3 and in the opening 11 of the substrate 1 by a potting process, and the first carrier 8 with the first line layer 21 is flipped and bonded to the first dielectric material 23. After the first carrier 8 is removed, as shown, Figure 9J As shown, a first dielectric layer 22 can be formed by an exposure process. As shown, Figure 9K As shown, a patterned mask layer 9 is formed, and a via 6 and a conductive pad 12 can be formed in the patterned mask layer 9 by an electroplating process. After the patterned mask layer 9 is removed, as shown, Figure 9L As shown in the top view of the upper part of FIG. 1, the third region C is a high-density line layer, which can provide more I / O quantity.

[0051] After the second carrier 7 is removed, as shown, Figure 9M As shown, a conductive pad 12 is formed on the second redistribution structure 3.

[0052] The method for manufacturing a semiconductor structure provided by the present disclosure can achieve similar technical effects as the aforementioned semiconductor structure, which will not be repeated here. In addition, compared with the prior art in which the redistribution structure is arranged in the opening defined by the substrate in a pick-up manner, the prior art needs accurate alignment and is prone to alignment deviation. However, the present disclosure directly forms the first redistribution structure 2 and the second redistribution structure 3 in the opening 11 of the substrate 1 by an exposure and development manner, which has higher accuracy.

[0053] Although the present disclosure has been described and illustrated with reference to specific embodiments, the descriptions and illustrations have been made by way of non-limiting examples. It will be apparent to those skilled in the art that various changes can be made without departing from the true spirit and scope of the disclosure which is defined by the appended claims. The drawings are not necessarily to scale. There can be differences between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt a specific situation, material, composition of matter, method or process to the purpose, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations can be combined, subdivided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, the order and grouping of operations are not limiting to the present disclosure unless specifically indicated herein.

Claims

1. A semiconductor structure, comprising: a substrate having opposite first and second surfaces, the substrate having an opening; a first redistribution structure disposed on the first surface of the substrate and in the opening, the first redistribution structure contacting sidewalls of the opening; a second redistribution structure disposed on the second surface and in the opening, the second redistribution structure contacting sidewalls of the opening and electrically connecting the first redistribution structure, the second redistribution structure comprising a third wiring layer, the third wiring layer disposed on an upper surface of the second redistribution structure in the opening.

2. The semiconductor structure of claim 1, wherein, The first redistribution structure and / or the second redistribution structure is a multilayer redistribution structure. At least one redistribution layer in the multilayer redistribution structure is disposed in the opening.

3. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: an electronic component disposed on the first redistribution structure and electrically connected to the first redistribution structure and / or the substrate.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a conductive liner disposed on an outer surface of the first redistribution structure and / or an outer surface of the second redistribution structure and electrically connected to the first redistribution structure and / or the second redistribution structure and / or the substrate. 5.A method of manufacturing a semiconductor structure, comprising: providing a substrate having opposite first and second surfaces, the substrate having an opening; forming a second redistribution structure on the second surface and in the opening such that the second redistribution structure contacts sidewalls of the opening, the second redistribution structure being formed by exposure and development; forming a first redistribution structure on the first surface and in the opening such that the first redistribution structure contacts sidewalls of the opening, the first redistribution structure being formed by exposure and development, the first redistribution structure comprising a third wiring layer, the third wiring layer disposed on an upper surface of the first redistribution structure in the opening; wherein the forming a second redistribution structure on the second surface and in the opening comprises: providing a second carrier; forming a second wiring layer on the second carrier; disposing a second dielectric material on the second wiring layer; disposing the substrate on the second dielectric material, exposure and curing to obtain a second dielectric layer, forming a third wiring layer on the second dielectric layer, the second wiring layer, the second dielectric layer and the third wiring layer collectively forming the second redistribution structure.

6. The method of claim 5, wherein, The forming a first redistribution structure on the first surface and in the opening comprises: providing a first carrier; forming a first wiring layer on the first carrier; disposing a first dielectric material on the second redistribution structure and in the opening; turning over the first wiring layer and disposing on the first dielectric material, exposure and curing to obtain a first dielectric layer, the first wiring layer and the first dielectric layer collectively forming the first redistribution structure.

7. The method of claim 6, wherein, The method further comprises: forming a conductive liner on the first redistribution structure and / or the second redistribution structure.

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