Integrated Circuit and Testing Method for Testing Based on I3C

Abstract

The present invention provides an integrated circuit and a test method based on I3C for testing. The integrated circuit includes: an I3C interface module configured to receive a plurality of broadcast instruction data packets sent by a master device based on the I3C protocol; a first register that is set to be valid when a command code in the broadcast instruction data packet is a first command; a second register that stores data after the first command in the broadcast instruction data packet when the first register is set to be valid; a third register that is set to be valid when a command code in the broadcast instruction data packet is a second command; a fourth register that is set to be valid or invalid to enter or exit a scan mode when the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a first predetermined condition or a second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in a reference register.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to an integrated circuit and a test method based on I3C for testing.

Background Art

[0002] The manufacturing process of chips is getting smaller and smaller, and the scale of digital chips is getting larger and larger. The test cost has further increased, even exceeding the cost of the functional part of the chip itself. How to consider the test problem in the process of chip design has become a very important part of current chip design.

[0003] Testing has become a very important factor in the process of integrated circuit design and manufacturing. It is no longer simply a means of inspection and verification of chip products, but a specialized technology closely related to integrated circuit design, and has become an organic whole with design and manufacturing. Design for testability (DFT) has opened up a practical way for the entire test field. Currently, basically all large and medium-sized IC (integrated circuit) design companies in the world have adopted the design process of design for testability. DFT has become a key link in chip design.

[0004] The scan path method is a DFT scheme for sequential circuit chips. Its basic principle is that a sequential circuit can be modeled as a combination of a combinational circuit network and a feedback of a sequential circuit network with flip-flops (FFs). Built-in self-test (BIST) design technology adds some additional self-test circuits to the design of the chip. During testing, only necessary control signals need to be applied from the outside, and the built-in self-test hardware and software are run to check for defects or faults in the circuit under test.

[0005] In the prior art, there are usually two ways to control signals such as scan_enable (scan enable) and mbist_enable (memory built-in self-test enable) of DFT: 1. Set dedicated pins to directly transmit the scan enable signal and the memory built-in self-test enable signal through these pins, and write to the register components directly through the relevant pins; 2. Use a common communication interface to write to the relevant registers. Although the first method can achieve the relevant functions, it will increase additional pins. Although the second method does not increase pins, there may be a situation where the user accidentally writes and enters the DFT mode.

[0006] Therefore, there is an urgent need to propose a new technical solution to solve the above problems.

Summary of the Invention

[0007] One of the objectives of the present invention is to provide an integrated circuit based on I3C for testing and a test method for integrated circuits based on I3C, which do not require additional pins and will not accidentally trigger the testability design mode.

[0008] According to one aspect of the present invention, the present invention provides an integrated circuit for testing based on I3C, characterized in that it includes: an I3C interface module configured to receive a plurality of broadcast instruction data packets sent by a master device based on the I3C protocol, each broadcast instruction data packet including a start identifier, a broadcast code, a command code, data, and an end identifier. When receiving each broadcast instruction data packet, first receive the start identifier and the broadcast code from the master device, then reply a response signal to the master device, and subsequently receive the command code, data, and end identifier from the master device; a processing module for parsing the received broadcast instruction data packet; a first register that is set to be valid when the command code in the broadcast instruction data packet is a first command; a second register that stores the data after the first command in the broadcast instruction data packet when the first register is set to be valid; a reference register for storing preset reference data; a third register that is set to be valid when the command code in the broadcast instruction data packet is a second command; a fourth register that is set to be valid when the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register. At this time, the scanning mode is entered. When the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, it is set to be invalid, and at this time, the scanning mode is exited.

[0009] According to another aspect of the present invention, the present invention provides a method for testing an integrated circuit based on I3C, which includes: a master device sends one or more broadcast instruction data packets to the integrated circuit as a slave device based on the I3C protocol, and each broadcast instruction data packet includes a start identifier, a broadcast code, a command code, data, and an end identifier, wherein after sending the start identifier and the broadcast code of the broadcast instruction data packet, the master device receives a response signal from the slave device, and then sends the command code, data, and end identifier of the broadcast instruction data packet; the slave device parses the received broadcast instruction data packet, after receiving the start identifier and the broadcast code of the broadcast instruction data packet, replies a response signal to the master device, and then continues to receive the command code, data, and end identifier of the broadcast instruction data packet, and performs the following operations according to the broadcast instruction data packet: when the command code in the broadcast instruction data packet is the first command, the slave device sets the first register to be valid, and when the first register is set to be valid, the slave device causes the second register to store the data after the first command in the broadcast instruction data packet; when the command code in the broadcast instruction data packet is the second command, the slave device sets the third register to be valid; when the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device sets the fourth register to be valid, and at this time, enters the scan mode; when the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device sets the fourth register to be invalid, and at this time, exits the scan mode.

[0010] Compared with the prior art, the present invention sets a scan enable signal and a memory built-in self-test enable signal according to the broadcast instruction data packet received by the I3C interface module, without the need to add pins, and there will be no mis-triggering to enter the testability design mode.

Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings. Among them:

[0012] Figure 1 is a structural block diagram of an integrated circuit for testing based on I3C in an embodiment of the present invention;

[0013] Figure 2 Schematic diagram of the format of the broadcast instruction data packet in the present invention;

[0014] Figure 3 Schematic diagram of the timing for receiving the broadcast instruction data packet to store the password;

[0015] Figure 4 Schematic diagram of the timing for receiving the broadcast instruction data packet to enter the scanning mode;

[0016] Figure 5 Schematic diagram of the timing for receiving the broadcast instruction data packet to exit the scanning mode;

[0017] Figure 6 Schematic diagram of the timing for receiving the broadcast instruction data packet to enter the built-in self-test mode of the memory;

[0018] Figure 7 Schematic diagram of the timing for receiving the broadcast instruction data packet to exit the built-in self-test mode of the memory.

Detailed implementation manners

[0019] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0020] As used herein, the term "one embodiment" or "embodiment" refers to specific features, structures, or characteristics that may be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words indicating electrical connection such as "connected", "coupled", and "joined" herein all mean direct or indirect electrical connection.

[0021] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore, should not be construed as a limitation to the present invention. In the description of the present invention, the meaning of "a plurality of" is two or more unless otherwise specifically defined. The "and / or" herein includes and as well as or, for example, A and / or B includes A, or B, or A and B three cases.

[0022] In the present invention, unless otherwise clearly specified and defined, terms such as "connected", "linked", "coupled" shall be understood in a broad sense; for example, it can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] Figure 1 FIG. 4 is a structural block diagram of an integrated circuit 200 based on I3C testing in an embodiment of the present invention. The integrated circuit 200 has a DFT mode and enters or exits the DFT mode based on the I3C protocol. I3C (Improved Inter Integrated Circuit) is a communication protocol that is compatible with the I2C protocol.

[0024] As Figure 1 shown, the integrated circuit 200 includes an I3C interface module 210, a processing module 220, and a register set 220. The register set 220 includes a plurality of registers. The integrated circuit 200 communicates with an external master device 100 as a slave device according to the I3C protocol.

[0025] The I3C interface module 210 is configured to receive a plurality of broadcast instruction data packets sent by the master device 100 based on the I3C protocol, that is, the broadcast ccc in the I3C protocol. As Figure 2 shown, each broadcast instruction data packet includes a start identifier S, a broadcast code, a command code, data, and an end identifier P. When receiving each broadcast instruction data packet, the I3C interface module 210 first receives the start identifier S and the broadcast code from the master device 100, and then sends a response signal ACK to the master device 100. After receiving the corresponding signal ACK, the master device 100 will continue to send the command code, data, and end identifier P of the broadcast instruction data packet. Correspondingly, the I3C interface module 210 receives the command code, data, and end identifier from the master device 100. The processing module 220 is used to parse the received broadcast instruction data packet.

[0026] The I3C interface module 210 receives the broadcast instruction data packet sent by the master device through the SDA (Serial Data) pin and the SCL pin (clock pin). The SDA line and the SCL line are two signal lines of the I2C protocol. The broadcast instruction data packet further includes a first check bit T after the command code and a second check bit T after the data. In one embodiment, the start identifier is that the SCL pin is high and the SDA pin is low, and the end identifier is that the SCL pin is high and the SDA pin is high.

[0027] In one embodiment, the register bank 220 includes a first register to a sixth register, and a reference register.

[0028] When the command code in the broadcast instruction data packet is the first command (such as command_1), the first register is set to be valid, and at this time the signal passwd_sel is 1. When the first register is set to be valid, that is, when the signal passwd_sel is 1, the second register passwd_reg stores the data after the first command in the broadcast instruction data packet, and the data is the password. As Figure 3 shown, it shows a timing diagram of the integrated circuit 200 receiving the broadcast instruction data packet and storing the password in the second memory. The reference register is used to store preset reference data, and the reference data is the same as or matches the password, and is used to verify whether the password is correct.

[0029] When the command code in the broadcast instruction data packet is the second command (such as command_2), the third register is set to be valid, and at this time the signal scan_enable_sel is 1. When the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets the first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the fourth register is set to be valid, and at this time the signal scan_enable is 1, and enters the scan mode scan_mode. Figure 4 It is a timing diagram for receiving the broadcast instruction data packet to enter the scan mode. Specifically, the first predetermined condition is whether it is a non-zero value. If the data after the second command in the broadcast instruction data packet is a non-zero value, it meets the first predetermined condition, otherwise, it does not meet the first predetermined condition.

[0030] When the command code in the broadcast instruction data packet is the second command (such as command_2), the third register is set to be valid, and at this time the signal scan_enable_sel is 1. When the third register is set to be valid and the data after the second command in the broadcast instruction data packet meets the second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the fourth register is set to be invalid, and at this time the signal scan_enable is 0, and at this time exits the scan mode scan_mode. Figure 5 It is a timing diagram for receiving the broadcast instruction data packet to exit the scan mode. Specifically, the second predetermined condition is whether it is a 0 value. If the data after the second command in the broadcast instruction data packet is a 0 value, it meets the second predetermined condition, otherwise, it does not meet the second predetermined condition.

[0031] In one embodiment, the integrated circuit 200 further includes a comparison module. The comparison module is configured to compare whether the data stored in the second register is the same as or matches the reference data stored in the reference register, so as to verify whether the password is correct.

[0032] When the command code in the broadcast instruction data packet is the third command (such as command_3), the fifth register is set to be valid, and at this time the signal mbist_enable_sel is 1. When the fifth register is set to be valid, the data after the third command in the broadcast instruction data packet meets the third predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the sixth register is set to be valid, and at this time the signal mbist_enable is 1, and the memory built-in self-test mode mbist_mode is entered. Figure 5 It is a timing diagram for receiving the broadcast instruction data packet to enter the memory built-in self-test mode. Specifically, the third predetermined condition is whether it is a non-zero value. If the data after the third command in the broadcast instruction data packet is a non-zero value, it meets the third predetermined condition; otherwise, it does not meet the third predetermined condition.

[0033] When the command code in the broadcast instruction data packet is the third command (such as command_3), the fifth register is set to be valid, and at this time the signal mbist_enable_sel is 1. When the fifth register is set to be valid, the data after the third command in the broadcast instruction data packet meets the fourth predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the sixth register is set to be invalid, and at this time the signal mbist_enable is 0, and the memory built-in self-test mode mbist_mode is exited. Figure 7 It is a timing diagram for receiving the broadcast instruction data packet to exit the memory built-in self-test mode. Specifically, the fourth predetermined condition is whether it is a zero value. If the data after the third command in the broadcast instruction data packet is a zero value, it meets the fourth predetermined condition; otherwise, it does not meet the fourth predetermined condition.

[0034] In one embodiment, in the scan mode scan_mode, the master device 100 sends scan test vectors to the integrated circuit through the I3C interface module 210 for scan testing. When entering the memory built-in self-test mode mbist_mode, the master device 100 sends memory built-in self-test vectors to the integrated circuit through the I3C interface module for memory built-in self-test.

[0035] The integrated circuit is a sensor integrated circuit.

[0036] The present invention is based on a user-defined broadcast instruction data packet (broadcast ccc) under the I3C protocol, and performs relevant processing inside the design after communication, so as to realize the control of signals such as scan_enable and mbist_enable. In this way, the number of additional pin feet is not increased, and the transmission rate, security and operability are taken into account. In addition, if there are relevant similar signal requirements, the idea of the present invention can also be referred to for generation.

[0037] Compared with the traditional method of writing registers using a communication interface, the user will not enter the DFT mode due to misoperation, and the present invention can improve security. The IDF mode can only be entered under the broadcast ccc in the i3c mode. The broadcast ccc does not need to allocate a dynamic address, and the present invention can be realized as long as the device supports i3c. The present invention can be carried out at a frequency of 12.5Mhz throughout the process, with a high speed.

[0038] According to another aspect of the present invention, the present invention also provides a method for testing an integrated circuit based on I3C. The testing method includes:

[0039] The master device sends one or more broadcast instruction data packets to the integrated circuit serving as the slave device based on the I3C protocol. Each broadcast instruction data packet includes a start identifier, a broadcast code, a command code, data, and an end identifier. After sending the start identifier and the broadcast code of the broadcast instruction data packet, the master device receives the response signal from the slave device, and then sends the command code, data, and end identifier of the broadcast instruction data packet;

[0040] The slave device parses the received broadcast instruction data packet, and after receiving the start identifier and the broadcast code of the broadcast instruction data packet, replies a response signal to the master device, and then continues to receive the command code, data, and end identifier of the broadcast instruction data packet, and performs the following operations according to the broadcast instruction data packet:

[0041] When the command code in the broadcast instruction data packet of the slave device is the first command, the slave device sets the first register to be valid. When the first register is set to be valid, the slave device causes the second register to store the data after the first command in the broadcast instruction data packet;

[0042] When the command code in the broadcast instruction data packet of the slave device is the second command, the third register is set to be valid;

[0043] When the third register of the slave device is set to be valid, the data after the second command in the broadcast instruction data packet meets the first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the fourth register is set to be valid, and at this time, the scan mode is entered;

[0044] When the slave device sets the third register to valid, the data after the second command in the broadcast instruction data packet meets the second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the fourth register is set to invalid, and at this time, the scanning mode is exited.

[0045] In one embodiment, when the command code in the broadcast instruction data packet of the slave device is the third command, the fifth register is set to valid;

[0046] When the slave device sets the fifth register to valid, the data after the third command in the broadcast instruction data packet meets the third predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the sixth register is set to valid, and at this time, the memory built-in self-test mode is entered.

[0047] When the slave device sets the fifth register to valid, the data after the third command in the broadcast instruction data packet meets the fourth predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the fifth register is set to invalid, and at this time, the memory built-in self-test mode is exited.

[0048] For other contents of the test method, please refer to the relevant description of the integrated circuit 200 based on I3C in the above text, which will not be elaborated here.

[0049] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0050] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. An integrated circuit for testing based on I3C, characterized in that, It includes: An I3C interface module, which is configured to receive multiple broadcast instruction data packets sent by a master device based on the I3C protocol. Each broadcast instruction data packet includes a start identifier, a broadcast code, a command code, data, and an end identifier. When receiving each broadcast instruction data packet, it first receives the start identifier and the broadcast code from the master device, then sends a response signal to the master device, and subsequently receives the command code, data, and end identifier from the master device; A processing module, which is used to parse the received broadcast instruction data packet; A first register, which is set to be valid when the command code in the broadcast instruction data packet is a first command; A second register, which stores the data after the first command in the broadcast instruction data packet when the first register is set to be valid. The data after the first command is a password; A reference register, which is used to store preset reference data. Whether the password is the same as or matches the reference data is used to verify whether the password is correct; A third register, which is set to be valid when the command code in the broadcast instruction data packet is a second command; A fourth register, which is set to be valid when the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register. At this time, it enters the scan mode. When the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets a second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, it is set to be invalid. At this time, it exits the scan mode; A fifth register, which is set to be valid when the command code in the broadcast instruction data packet is a third command; A sixth register, which is set to be valid when the fifth register is set to be valid, the data after the third command in the broadcast instruction data packet meets a third predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register. At this time, it enters the memory built-in self-test mode. When the fifth register is set to be valid, the data after the third command in the broadcast instruction data packet meets a fourth predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, it is set to be invalid. At this time, it exits the memory built-in self-test mode.

2. The integrated circuit according to claim 1, characterized in that, It further includes: A comparison module, which is used to compare whether the data stored in the second register is the same as or matches the reference data stored in the reference register.

3. The integrated circuit according to claim 1, characterized in that, The first predetermined condition is whether it is a non-zero value. If it is a non-zero value, it meets the first predetermined condition. The second predetermined condition is whether it is 0. If it is 0, it meets the second predetermined condition. The third predetermined condition is whether it is a non-zero value. If it is a non-zero value, it meets the third predetermined condition. The fourth predetermined condition is whether it is 0. If it is 0, it meets the fourth predetermined condition.

4. The integrated circuit according to claim 1, characterized in that, In the scan mode, the master device sends scan test vectors to the integrated circuit through the I3C interface module for scan testing; When entering the memory built-in self-test mode, the master device sends the memory built-in self-test vector to the integrated circuit through the I3C interface module for memory built-in self-test.

5. The integrated circuit according to claim 1, characterized in that, The I3C interface module receives the broadcast instruction data packet sent by the master device through the SDA pin and the SCL pin.

6. The integrated circuit according to claim 5, characterized in that, The start identifier is that the SCL pin is high and the SDA pin is low. The end identifier is that the SCL pin is high and the SDA pin is high.

7. The integrated circuit according to claim 1, characterized in that, The broadcast instruction data packet further includes a first check bit after the command code and a second check bit after the data. The integrated circuit is a sensor integrated circuit.

8. A method for testing an integrated circuit based on I3C, characterized in that, It includes: The master device sends one or more broadcast instruction data packets to the integrated circuit as a slave device based on the I3C protocol. Each broadcast instruction data packet includes a start identifier, a broadcast code, a command code, data, and an end identifier. After sending the start identifier and the broadcast code of the broadcast instruction data packet, the master device receives the response signal from the slave device, and then sends the command code, data, and end identifier of the broadcast instruction data packet. The slave device parses the received broadcast instruction data packet. After receiving the start identifier and the broadcast code of the broadcast instruction data packet, it replies a response signal to the master device, and then continues to receive the command code, data, and end identifier of the broadcast instruction data packet, and performs the following operations according to the broadcast instruction data packet: When the command code in the broadcast instruction data packet is the first command, the slave device sets the first register to be valid. When the first register is set to be valid, the slave device makes the second register store the data after the first command in the broadcast instruction data packet, and the data after the first command is the password. When the command code in the broadcast instruction data packet is the second command, the slave device sets the third register to be valid. When the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets the first predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device sets the fourth register to be valid. At this time, it enters the scan mode. Whether the password is the same as or matches the reference data is used to verify whether the password is correct. When the third register is set to be valid, the data after the second command in the broadcast instruction data packet meets the second predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device sets the fourth register to be invalid. At this time, it exits the scan mode. When the command code in the broadcast instruction data packet is the third command, the slave device sets the fifth register to be valid. When the fifth register is set to be valid, the data after the third command in the broadcast instruction data packet meets the third predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device sets the sixth register to be valid. At this time, it enters the memory built-in self-test mode. When the slave device sets the fifth register to invalid after the fifth register is set to valid, the data after the third command in the broadcast instruction data packet meets the fourth predetermined condition, and the data stored in the second register is the same as or matches the reference data stored in the reference register, the slave device exits the memory built-in self-test mode at this time.

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