FPGA and lightweight CNN embedded fast nuclide identification method

Abstract

The application discloses a kind of based on FPGA and light-weight CNN embedded fast nuclear recognition method of chip resource can be fully utilized, more quickly calculate the recognition result.The based on FPGA and light-weight CNN embedded fast nuclear recognition method includes the following steps: S1, model establishment;S2, model deployment;That is, build light-weight convolutional neural network MobileNet model, deployment is carried out in FPGA chip, including nuclear pulse signal feature extraction, the establishment of light-weight convolutional neural network, deployment is carried out in FPGA and ARM heterogeneous chip.The above-mentioned based on FPGA and light-weight CNN embedded fast nuclear recognition method reduces the parameter quantity and calculation amount of model, facilitates the practical popularization and application of model;Different acceleration calculation strategies can be proposed, and nuclear recognition time is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of nuclear radiation detection, in particular to an embedded fast nuclide identification method based on FPGA and lightweight CNN. BACKGROUND

[0002] It is well known that nuclide identification is an important research content in the field of nuclear safety. With the development of nuclear energy and the wide application of nuclear technology, loss and theft of radioactive nuclear materials occur frequently. According to the statistics of the International Atomic Energy Agency (IAEA) Incident and Trafficking Database (ITDB), since the database was established in 1995, more than 3500 accidents have been reported by 2020, of which about 10% have been confirmed to be related to trafficking or malicious use of nuclear materials. Therefore, in the customs, port and other entry and exit inspection, it is extremely important to quickly and accurately detect radioactive nuclides.

[0003] The traditional radioactive nuclide identification instrument is mainly composed of a detector, a multi-channel pulse amplitude analyzer (MCA) and a spectrum analysis software. The detector converts the ray particle into a nuclear pulse signal; the MCA performs a series of processing such as filtering shaping, amplitude extraction, etc. on the nuclear pulse, and forms a spectrum data through each channel counting statistics; the spectrum analysis software performs smoothing, peak searching, energy calibration, etc. on the data, and then matches with the nuclide library characteristic energy to determine the type of radioactive nuclide. For a long time, the qualitative detection of radioactive nuclides adopts the spectrum method, but in the environment with low counting rate and large background noise, the spectrum analysis is difficult, especially in the specific scene of entry and exit, the time of the detected object is short, the effective pulse data is less, and the spectrum peak shape is not obvious, the recognition effect is poor. On the other hand, embedded and intelligent has become the development trend of radioactive detection instrument, therefore, it is necessary to study the deployment of radioactive nuclide identification algorithm on embedded chip and develop related devices. SUMMARY

[0004] The technical problem to be solved by the present application is to provide an embedded fast nuclide identification method based on FPGA and lightweight CNN which can make full use of chip resources and calculate the identification result faster.

[0005] The technical solution adopted by the present application to solve the technical problem is: an embedded fast nuclide identification method based on FPGA and lightweight CNN, comprising the following steps:

[0006] S1, model establishment;

[0007] S11, first use a nuclear pulse generator to generate a large amount of nuclear pulse data;

[0008] S12, the time-frequency characteristics of the pulse signal are extracted by HHT, a data set for a deep learning algorithm is established, and the data set is divided into a training set and a test set according to a 7:3 ratio;

[0009] S13, a light-weight convolutional neural network MobileNet model is built through a Pytorch deep learning framework, the MobileNet light-weight convolutional neural network includes a convolutional layer, a pooling layer and a fully connected layer;

[0010] The model is continuously trained, hyperparameter optimized and evaluated until the identification performance of the model for the nuclide reaches an optimal state, the model weight parameters are derived, and the model weight parameters are quantized to 16 bits;

[0011] S2, model deployment;

[0012] An XC7Z020 chip is used for deployment, the XC7Z020 chip has an FPGA logic module, two Cortex-A9 ARM processors;

[0013] The two Cortex-A9 ARM processors are processor system modules, and the FPGA logic module is a programmable logic module;

[0014] The execution logic of the entire model is controlled by the processor system module, and the specific calculation of the nuclide identification neural network is implemented in the programmable logic module;

[0015] The data interaction between the processor system module and the programmable logic module uses an AXI data bus connection;

[0016] The weight parameters of the network are formed into a Bin file and stored in an SD card, and when the chip is powered on, the data in the SD card is read into a RAM data cache area; after the nuclide pulse feature is input, the convolution module, the pooling module and the fully connected module of the MobileNet are executed in turn;

[0017] After the fully connected module calculates the predicted nuclide probability, the calculation result is transmitted to the processor system unit again through the AXI bus, the processor system unit selects the nuclide corresponding to the maximum probability, and outputs the predicted class.

[0018] Further, in step S12, the time-frequency characteristics of the nuclear pulse signal are extracted by HHT;

[0019] The HHT includes two processes of EMD decomposition and Hilbert transformation;

[0020] Let the original signal be x(n), and the EMD decomposition steps are as follows:

[0021] a1: find the extreme points of x(n), find all the maximum and minimum values, and extract the upper and lower envelope sequences of x(n) by interpolation;

[0022] a2: find the local mean curve by the upper and lower envelope lines, set as m(n);

[0023] a3: calculate h(n), h(n) = x(n) - m(n);

[0024] a4: judge whether h(n) satisfies the condition, if it satisfies the IMF condition, go to a5, if not, let x(n) = h(n), return to a1 and continue to loop;

[0025] a5: set the i-th IMF as C i (n), C i (n) = x(n) - h(n);

[0026] a6: judge whether C i satisfies the EMD decomposition end condition, if it satisfies, end the EMD process, if not, save C i , let x(n) = C i (n), return to a1 and continue to loop;

[0027] The decomposition adjustment is as follows:

[0028] For the nuclear pulse signal sequence x(t), it can be decomposed into a plurality of intrinsic mode functions IMF by EMD, that is, the original signal is the superposition of these intrinsic mode functions:

[0029]

[0030] Wherein, n is the order of IMF component, c i (t) is the i-th order IMF component, r n (t) is the residual after signal decomposition;

[0031] Wherein, the signal subjected to EMD decomposition satisfies the following three basic conditions:

[0032] 1) The signal sequence contains at least one maximum value and one minimum value;

[0033] 2) The local time domain characteristics of the signal are determined only by the time scale between the extreme points;

[0034] 3) When the signal sequence only contains inflection points, the extreme value can be obtained by differentiation;

[0035] The IMF function obtained by EMD decomposition satisfies the following two conditions:

[0036] 1) The number of extreme points and the number of zero points differ by at most one;

[0037] 2) The maximum and minimum of each IMF form the upper envelope and lower envelope of the function respectively, and the average of the two is 0;

[0038] The signal C after EMD decomposition i And then the Hilbert transform is performed for feature extraction:

[0039]

[0040] Wherein P represents the Cauchy principal value;

[0041] The instantaneous frequency and amplitude of each IMF are obtained, and the evaluation expression is:

[0042]

[0043] The time series, instantaneous frequency and amplitude jointly form the time-frequency diagram of the nuclear pulse, and the time-frequency diagram is grayed and sent to the neural network for recognition.

[0044] Further, in step S13, a light-weight convolutional neural network MobileNet model is built, including a convolutional layer, a pooling layer and a fully connected layer;

[0045] The convolutional layer changes the ordinary convolution operation to a depth separable convolution;

[0046] The depth separable convolution decomposes the ordinary convolution operation into a channel-by-channel convolution and a point-by-point convolution;

[0047] In the channel-by-channel convolution, one convolution kernel is responsible for one channel, and one channel is only convolved by one convolution kernel;

[0048] The point-by-point convolution has a convolution kernel size of 1x1xM, and M is the number of channels of the previous layer;

[0049] The data obtained in step S12 are used to train the model, and after the model is trained, the weight parameters of each layer are exported;

[0050] The pooling layer adopts maximum pooling, and the pooling size is set to 2;

[0051] The fully connected layer is used to establish the relationship between the data features and the output categories, and to perform classification.

[0052] Further, a rectified linear unit is added after each layer of the convolutional layer and the fully connected layer, and the definition formula is as follows:

[0053] ReLU(x)=max(x,0).

[0054] Further, after the convolutional layer further extracts features from the input data, a fully connected network is used to establish the relationship between the features and the output categories, and a softmax function is used to estimate the probability of each prediction result, and the specific formula of the function is as follows:

[0055]

[0056] where w is the weight of the neuron, k is the number of categories to be classified, x is the output result of the previous layer, and the probability of predicting the category j is P, and the maximum value of the output probability is the prediction result.

[0057] Further, in step S2, the HLS high-level synthesis tool is used to deploy the FPGA logic module for the deep learning model;

[0058] b1, determine the input and output of the module and the function to be implemented inside the module, use C / C++ high-level language and library functions provided by HLS to write the specific implementation form of the algorithm inside the module;

[0059] b2, optimize the algorithm when running in FPGA through optimization instructions;

[0060] b3, establish C simulation, write Testbench to verify the function of the module;

[0061] b4, after verification, synthesize the project written in high-level language into an RTL hardware description language IP core through C synthesis; obtain the performance indicators such as clock period, running time, and resource consumption of the module in use;

[0062] b5, if the hardware resources are not fully utilized or the resource utilization rate exceeds the existing resources in b4, the algorithm needs to be optimized again using optimization instructions until the calculation efficiency and resource consumption meet the requirements;

[0063] b6, use C / RTL co-simulation to determine again that the C / C++ high-level language and the hardware description language running results are correct, and then export the IP core, which can be used when deploying in FPGA.

[0064] Further, in step S13, the weight parameters of the lightweight neural network are completed; 32-bit floating-point numbers are used for representation;

[0065] Convert 32-bit floating-point number operation to 16-bit fixed-point number operation;

[0066] Use 16-bit dynamic fixed-point numbers to quantize the weight parameters and input and output feature maps of the network, and the quantization formula is as follows:

[0067]

[0068] x fixed For the quantized 16-bit fixed-point number, s represents the sign bit, f represents the exponent, B represents the bit width length of quantization, x i represents the mantissa part;

[0069] The HLS provides an arbitrary precision type library ap_fixed to represent a floating-point number, and manually sets the floating-point number integer width, decimal width, quantization mode and minimum value constraint mode.

[0070] Further, the loop operation in the light-weight convolutional neural network MobileNet model includes convolution operation and full connection operation;

[0071] The FPGA has a plurality of multipliers and adders constructed by digital circuits inside; the multiplexer of the multiplier and the adder is used during operation; that is, one, loop unrolling and pipeline execution; two, in addition to parallel multiplication in a large number of operations of full connection operation, the form of addition tree is used to convert the sequential accumulation calculation into layered parallel addition.

[0072] Further, the loop unrolling and pipeline execution include the following steps:

[0073] The calculation formula of the convolution operation in the convolution layer is Y=CONV(W,X)+B, W and B are divided into weight and bias parameters; X is the input data of the current layer, and Y is the output data;

[0074] The input data and the weight data are convolved, the convolution loop is unrolled using the UNROLL instruction, and the FPGA internal DSP, LUT is used for parallel calculation;

[0075] When reading parameters, the ARRAY_PARTITION instruction is used to store the data in the RAM in BRAM in blocks, and the number of blocks is divided according to the number of parameters required for each calculation of loop unrolling;

[0076] After loop unrolling, data is read, calculated and output at the same time between different loops; the pipeline technology is adopted to increase the throughput and parallelism of calculation; the pipeline is set through the PIPELINE command;

[0077] In the pooling layer, the maximum pooling is used for the pooling calculation unit, and the pooling size is set to 2;

[0078] In the full connection layer, when full connection calculation is carried out, the data dimension is reduced layer by layer, and each layer of feature data needs to map all data to neurons in the next layer, just like the convolution layer, there are a large number of multiplication and addition operations inside, and the same strategy as the convolution layer is used, that is, pipeline and loop unrolling calculation are used; first, the product of the output result x of the last layer and the weight w is stored in the register, and then an addition tree is constructed, and parallel accumulation is carried out using the form of the addition tree;

[0079] The addition tree adds the product values in the register two by two in one clock cycle, and the last layer addition result is used as the next layer addition input, and recursion is realized in turn to realize the pipeline.

[0080] Further, the lightweight convolutional neural network MobileNet model is called in the FPGA chip in the form of an IP core.

[0081] The IP core includes six interfaces, namely, an s_axi_CONTROL interface, an ap_clk interface, an ap_rst_n interface, a m_axi_DATA interface, a m_axi_OUT_r interface and an interrupt interface.

[0082] The IP core adopts an AXI_Lite protocol, and data interaction is carried out with the outside through an AXI bus.

[0083] The ap_clk provides a clock signal for the operation of the IP core.

[0084] The ap_rst_n provides a reset signal for the IP core, and a low-level reset mode is adopted.

[0085] The interrupt interface can output an interrupt signal.

[0086] The method has the following advantages:

[0087] 1) The method directly analyzes the nuclear pulse signal characteristics, proposes a lightweight convolutional neural network nuclear identification model, reduces the parameter quantity and calculation quantity of the model, and is convenient for the practical popularization and application of the model.

[0088] 2) In the practical application scenario of the fast nuclide identification method based on FPGA and lightweight CNN embedded in this invention, the algorithm is deployed using FPGA chip, making full use of the internal resources of FPGA. Different acceleration computing strategies are proposed for the computing characteristics of each layer of lightweight neural network, which effectively reduces the nuclide identification time. Attached Figure Description

[0089] Figure 1 This is a flowchart illustrating the fast nuclide identification method based on FPGA and lightweight CNN embedded according to the present invention.

[0090] Figure 2 This is a schematic diagram of the nuclear pulse signal feature extraction process based on HHT in an embodiment of the present invention;

[0091] Figure 3 This is a flowchart of the deep learning nuclide identification process in an embodiment of the present invention;

[0092] Figure 4 This is a flowchart of depth-separable convolution in an embodiment of the present invention;

[0093] Figure 5 This is a schematic diagram of the production line process in an embodiment of the present invention;

[0094] Figure 6 This is a schematic diagram of the addition tree structure in an embodiment of the present invention;

[0095] Figure 7 This is a schematic diagram of the nuclide identification IP core structure in an embodiment of the present invention. Detailed Implementation

[0096] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0097] As attached Figure 1 As shown, the fast nuclide identification method based on FPGA and lightweight CNN embedded according to the present invention includes the following steps:

[0098] S1. Model Establishment;

[0099] S11. First, a large amount of nuclear pulse data is generated using a nuclear pulse generator;

[0100] S12. Use HHT to extract the time-frequency features of pulse signals, establish a dataset for deep learning algorithms, and divide it into training and test sets in a 7:3 ratio.

[0101] S13. Using the PyTorch deep learning framework, build a lightweight convolutional neural network model, MobileNet, which includes convolutional layers, pooling layers, and fully connected layers.

[0102] The model is continuously trained, hyperparameters are optimized and evaluated until the model reaches the best state for the recognition performance of the nuclide, the model weight parameters are derived, and are quantized to 16 bits;

[0103] S2, model deployment;

[0104] An XC7Z020 chip is used for deployment, the XC7Z020 chip has an FPGA logic module, two Cortex-

[0105] A9 ARM processor;

[0106] Two Cortex-A9 ARM processors are processor system modules; the FPGA logic module is a programmable logic module;

[0107] The execution logic of the entire model is controlled by the processor system module, and the specific calculation of the nuclide recognition neural network is implemented in the programmable logic module;

[0108] The data interaction between the processor system module and the programmable logic module uses an AXI data bus connection;

[0109] The weight parameters of the network are formed into a Bin file and stored in an SD card, and when the chip is powered on, the data in the SD card is read into the RAM data cache area; after the nuclide pulse feature is input, the convolution module, the pooling module and the full connection module of MobileNet are executed in turn;

[0110] After the full connection module calculates the predicted nuclide probability, the calculation result is transmitted to the processor system unit again through the AXI bus, the processor system unit selects the nuclide corresponding to the maximum probability, and outputs the predicted class.

[0111] Specifically, in step S12, the time-frequency features of the nuclear pulse signal are extracted by HHT;

[0112] The HHT includes two processes of EMD decomposition and Hilbert transformation;

[0113] Let the original signal be x(n), and the EMD decomposition step is as follows:

[0114] a1: Find all extreme values of x(n), find all extreme values and extreme values, and extract the upper envelope and lower envelope sequences of x(n) through interpolation;

[0115] a2: Obtain the local mean curve by the upper and lower envelope lines, and set it as m(n);

[0116] a3: Calculate h(n), h(n) = x(n) - m(n);

[0117] a4: judge whether h(n) satisfies the condition, if yes, go to a5, if not, let x(n)=h(n), and return to a1 to continue the loop;

[0118] a5: let the i-th IMF be C i (n), C i (n)=x(n)-h(n);

[0119] a6: judge whether C i satisfies the EMD end condition, if yes, end the EMD process, if not, save C i , let x(n)=C i (n), and return to a1 to continue the loop;

[0120] The decomposition adjustment is as follows:

[0121] For a nuclear pulse signal sequence x(t), it can be decomposed into several finite intrinsic mode functions (IMF) by EMD, i.e. the original signal is the superposition of these intrinsic mode functions:

[0122]

[0123] Where n is the order of IMF component, c i (t) is the i-th order IMF component, r n (t) is the residual after signal decomposition;

[0124] Where the signal subjected to EMD decomposition satisfies the following three basic conditions:

[0125] 4) The signal sequence contains at least one maximum value and one minimum value;

[0126] 5) The local time domain characteristics of the signal are determined only by the time scale between extreme points;

[0127] 6) When the signal sequence only contains inflection points, the extreme values can be obtained by differentiation;

[0128] The IMF functions obtained by EMD decomposition satisfy the following two conditions:

[0129] 1) The number of extreme points and the number of zero points differ by at most one;

[0130] 2) The local maximum and minimum values of the IMF form the upper envelope line and the lower envelope line of the function respectively, and the average of the two is 0;

[0131] After EMD decomposition, the signal C i is subjected to Hilbert transform for feature extraction:

[0132]

[0133] where P represents the Cauchy principal value;

[0134] The instantaneous frequency and amplitude of each IMF are obtained, and the evaluation expression is:

[0135]

[0136] The time series, the instantaneous frequency and the amplitude jointly constitute a nuclear pulse time-frequency graph, and the time-frequency graph is grayed and sent to a neural network for recognition.

[0137] The HHT algorithm can effectively extract the time-frequency characteristics of the nuclear pulse signal, reduce the sequence dimension, and provide training data for the deep learning model.

[0138] Further, in a feasible embodiment, the lightweight convolutional neural network MobileNet model built in step S13 includes a convolutional layer, a pooling layer and a fully connected layer;

[0139] The convolutional layer changes the ordinary convolution operation to a depth separable convolution;

[0140] The depth separable convolution decomposes the ordinary convolution operation into a channel-wise convolution and a point-wise convolution;

[0141] In the channel-wise convolution, one convolution kernel is responsible for one channel, and one channel is only convolved by one convolution kernel;

[0142] The point-wise convolution has a convolution kernel size of 1x1xM, where M is the number of channels of the previous layer;

[0143] The data obtained in step S12 is used to train the model, and after the model is trained, the weight parameters of each layer are exported;

[0144] The pooling layer uses maximum pooling with a pooling size of 2;

[0145] The fully connected layer is used to establish the relationship between data features and output categories for classification.

[0146] The lightweight MobileNet convolutional neural network is established, which facilitates the deployment of the model in the chip, so as to achieve the purpose of portable, fast and accurate nuclear identification, and improve the recognition accuracy and speed.

[0147] In order to increase the nonlinearity of the model and represent the sparsity of the data, further, a rectified linear unit defined by the following formula is added after each layer of the convolutional layer and the fully connected layer:

[0148] ReLU(x)=max(x,0).

[0149] After the further feature extraction of the input data by the convolutional layer, a full connection network is used to establish the relationship between the features and the output categories, and a softmax function is used to estimate the probability of each prediction result, and the specific formula of the function is as follows:

[0150]

[0151] where w is the weight of the neuron, k is the number of categories to be classified, x is the output result of the previous layer, and the probability of predicting the category j is P, and the maximum value of the output probability is the prediction result.

[0152] The HLS development method is to use C / C++ high-level language to describe the function, and after optimization such as interface constraint and loop unrolling, it can be directly synthesized into IP core for use, which improves the development efficiency and shortens the development cycle. Therefore, in step S2, the HLS high-level synthesis tool is used to deploy the deep learning model of the FPGA logic module; including the following steps:

[0153] b1, determine the input and output of the module and the function to be implemented inside the module, use C / C++ high-level language and HLS

[0154] self-contained library function to write the specific implementation form of the internal algorithm;

[0155] b2, optimize the algorithm running in FPGA through optimization instructions;

[0156] b3, establish Csimulation, write Testbench to verify the function of the module;

[0157] b4, after verification, synthesize the high-level language project into RTL hardware description language IP core through Csynthesis; get the clock period, running time, resource consumption and other performance indicators of the module in use;

[0158] b5, if the hardware resources are not fully utilized or the resource utilization rate exceeds the existing resources in b4, the algorithm needs to be optimized by using optimization instructions until the calculation efficiency and resource consumption meet the requirements;

[0159] b6, use C / RTL co-simulation, and after confirming that the C / C++ high-level language and the hardware description language running results are correct, export the IP core, which can be used when deploying in FPGA.

[0160] Because there is no special floating-point operation unit in the FPGA, running floating-point operation will consume more internal resources of the FPGA, therefore, the input data and weight parameters of the network are subjected to fixed-point quantization processing; specifically, the weight parameters of the lightweight neural network are completed in step S13; 32-bit floating-point numbers are used for representation;

[0161] 32-bit floating-point operation is converted into 16-bit fixed-point operation;

[0162] The weight parameters and input and output feature maps of the network are quantized by using 16-bit dynamic fixed-point numbers, and the quantization formula is as follows:

[0163]

[0164] x fixed is a quantized 16-bit fixed-point number, s represents a sign bit, f represents a mantissa, B represents a quantized bit width length, x i represents a mantissa part;

[0165] The HLS provides an arbitrary precision type library ap_fixed to represent a fixed-point number, and manually sets the fixed-point number integer width, decimal width, quantization mode and minimum value constraint mode.

[0166] The convolutional neural network structure mainly includes recurrent convolution operation and full connection operation, the operations of the channels are independent of each other and have no direct connection, the FPGA has multiple multipliers (DSP) and adders constructed by digital circuits, and the multiplication and addition of the multipliers and adders are multiplexed by using the strategy of using resources to exchange time during operation.

[0167] Specifically, the recurrent operation in the lightweight convolutional neural network MobileNet model includes convolution operation and full connection operation.

[0168] The FPGA has multiple multipliers and adders constructed by digital circuits; the multiplication and addition of the multipliers and adders are multiplexed during operation; that is, one is the expansion and pipeline execution of the loop, and two is that, in addition to the parallel multiplication calculation in the large amount of full connection operation, the addition adopts the form of addition tree to convert the sequential addition calculation into layered parallel addition.

[0169] The expansion and pipeline execution of the loop include the following steps:

[0170] The calculation formula of the convolution operation in the convolution layer is Y=CONV(W,X)+B, W and B are weight and bias parameters; X is the input data of the current layer, and Y is the output data.

[0171] The input data and weight data are subjected to convolution calculation, the convolution loop is expanded by using the UNROLL instruction, and the FPGA internal DSP and LUT are used for parallel calculation;

[0172] When reading parameters, the ARRAY_PARTITION instruction is used to store the data in the RAM in BRAM in blocks, and the number of blocks is divided according to the number of parameters required by each calculation after loop unrolling;

[0173] After loop unrolling, data is read, calculated and output simultaneously between different loops; the pipeline technology is adopted to improve the throughput and parallelism; the PIPELINE command is used to set the pipeline;

[0174] In the pooling layer, the maximum pooling is adopted for the pooling calculation unit, and the pooling size is set to 2;

[0175] In the full connection layer, the data dimension is reduced layer by layer during full connection calculation, and all data of each layer of feature data needs to be mapped to the neurons of the next layer; similarly to the convolution layer, there are a large number of multiplication and addition operations inside, and the same strategy as the convolution layer is adopted, that is, the pipeline and loop unrolling are used for calculation; first, the product of the output result x of the last layer and the weight w is stored in the register, and then an addition tree is constructed to perform parallel accumulation in the form of the addition tree;

[0176] The addition tree adds the product values in the register two by two in one clock cycle, and the addition result of the last layer is used as the input of the next layer, and the recursion is performed in sequence to realize the pipeline.

[0177] The MobileNet model of the lightweight convolutional neural network is called in the FPGA chip in the form of an IP core;

[0178] The IP core includes six interfaces, namely, the s_axi_CONTROL interface, the ap_clk interface, the ap_rst_n interface, the m_axi_DATA interface, the m_axi_OUT_r interface, and the interrupt interface;

[0179] The IP core adopts the AXI_Lite protocol to interact with the outside world through the AXI bus, and the s_axi_CONTROL interface is the AXI_Lite data transmission protocol control interface;

[0180] The ap_clk provides a clock signal for the operation of the IP core;

[0181] The ap_rst_n provides a reset signal for the IP core, which adopts a low-level reset mode; the m_axi_DATA interface receives the characteristic data of the kernel pulse, and the probability predicted by each kernel element is calculated internally and output through the m_axi_OUT_r interface;

[0182] The interrupt interface can output an interrupt signal.

[0183] Embodiment

[0184] (1) Nuclear pulse data acquisition based on nuclear pulse signal generator

[0185] Geant4 can establish the physical process of gamma-ray interaction with matter, and simulate the energy deposition of particles in the detector in each process. In an ideal case, the particle energy is fully deposited in the detector, and the generated charge has no statistical fluctuation and noise, so the simulated gamma energy spectrum will not be broadened. In actual measurement, due to a series of complex physical processes and statistical fluctuations experienced by gamma rays during detection, the gamma energy spectrum is broadened. Therefore, the energy spectrum data simulated by Geant4 needs to be broadened. The broadened energy spectrum generates nuclear pulse data through the DT5800 nuclear pulse signal generator of CANE company.

[0186] (2) Nuclear pulse signal feature extraction based on Hilbert-Huang transform

[0187] If the entire nuclear pulse signal sampling data is directly used as the input of the deep network, it will cause a large number of parameters and calculations of the model, so dimensionality reduction of the nuclear pulse sequence is the key to establishing a lightweight model. The present application uses HHT (Hilbert-Huang Transform) to extract the time-frequency features of the nuclear pulse signal.

[0188] HHT includes EMD decomposition and Hilbert transformation two processes.

[0189] EMD decomposition algorithm is an algorithm that can adaptively decompose non-linear and non-stationary signals. According to the principle of EMD algorithm, any complex signal can be decomposed into a limited number of intrinsic mode functions. The IMF function obtained by EMD decomposition of the original signal function can clearly reflect the local characteristics of the original signal function in the time domain.

[0190] For a nuclear pulse signal sequence x(t), it can be decomposed into a limited number of intrinsic mode functions IMF through EMD, that is, the original signal is the superposition of these intrinsic mode functions:

[0191]

[0192] Where n is the order of the IMF component, c i (t) is the i-th order IMF component, r n (t) is the residual after signal decomposition, representing the overall trend of the signal. EMD decomposition has adaptivity and does not need to set specific parameters during signal decomposition. The decomposition process is based on the local characteristics of the data, so it is suitable for non-linear and non-stationary processes. During decomposition, the signal needs to meet three

[0193] basic conditions:

[0194] 1) The signal sequence contains at least one maximum value and one minimum value (i.e. at least two extreme points);

[0195] 2) The local time domain characteristics of the signal are determined only by the time scale between the extreme points;

[0196] 3) When the signal sequence contains only inflection points, the extreme points can be obtained by differentiation.

[0197] The decomposed IMF function should satisfy the following two conditions:

[0198] 1) The number of extreme points and the number of zero points differ by at most one;

[0199] 2) The local maximum and minimum values of the IMF form the upper envelope and lower envelope of the function, respectively, and the average of the two is 0.

[0200] Based on the above conditions, let the original signal be x(n), the EMD decomposition steps are as follows:

[0201] Step 1: Find the extreme points of x(n), find all the maximum and minimum values, and extract the upper envelope and lower envelope sequences of x(n) through interpolation;

[0202] Step 2: Calculate the local mean curve through the upper and lower envelope lines, denoted as m(n);

[0203] Step 3: Calculate h(n), h(n) = x(n) - m(n);

[0204] Step 4: Determine whether h(n) satisfies the condition. If it satisfies the IMF condition, go to Step 5; if not, let x(n) = h(n) and return to Step 1 for continuous loop;

[0205] Step 5: Let the i-th IMF be C i (n), C i (n) = x(n) - h(n);

[0206] Step 6: Determine whether Ci satisfies the EMD decomposition end condition. If it satisfies, end the EMD process; if not, save Ci, let x(n) = Ci(n), and return to Step 1 for continuous loop.

[0207] After EMD decomposition, the signal C i is further processed for feature extraction through Hilbert transform:

[0208]

[0209] Where P represents the Cauchy principal value, which is used to avoid points that are not integrable in integration.

[0210] Then, the instantaneous frequency and amplitude of each IMF are obtained, and the evaluation expression is as follows:

[0211]

[0212] The time-frequency diagram of the nuclear pulse is constructed by combining the time series, instantaneous frequency, and amplitude. The time-frequency diagram is then grayscaled and fed into a neural network for recognition.

[0213] The HHT algorithm can effectively extract the time-frequency features of nuclear pulse signals, reduce sequence dimensionality, and provide training data for deep learning models.

[0214] In summary, the technical approach for feature extraction and dimensionality reduction of nuclear pulse sequences is as follows: Figure 2 As shown:

[0215] 2. Establishment and Training of a Lightweight Deep Learning Model for Radionuclide Identification

[0216] Building a lightweight neural network model requires reducing the dimensionality of the input data and minimizing the computational load and number of parameters. This invention establishes a lightweight MobileNet convolutional neural network based on the time-frequency diagram of nuclear pulse signals, facilitating model deployment on chips. This achieves portable, fast, and accurate nuclide identification, improving both accuracy and speed. The entire identification process is as follows: Figure 3 As shown.

[0217] The MobileNet lightweight convolutional neural network consists of convolutional layers, pooling layers, and fully connected layers. The convolutional layers replace ordinary convolution operations with depthwise separable convolutions. Depthwise separable convolutions can reduce the computational cost of convolution operations and the number of parameters in the overall network, improve the model inference speed, and facilitate the subsequent deployment of the network on hardware.

[0218] In regular convolutional neural network training, one channel generates multiple convolutional kernels, and a single convolutional operation fuses all channels of the previous layer's output into a single feature map. For example... Figure 4 As shown, depthwise separable convolution decomposes ordinary convolution operations into channel-wise convolution and pointwise convolution. In channel-wise convolution, each kernel is responsible for only one channel, and each channel is convolved by only one kernel. Pointwise convolution is similar to ordinary convolution operations, with a kernel size of 1×1×M, where M is the number of channels in the previous layer. Therefore, channel-wise convolution combines features from different channels to generate the feature map of the next layer.

[0219] Compared to ordinary convolution, depthwise separable convolution reduces both the number of parameters and computational cost, with a reduction ratio of:

[0220]

[0221] Wherein M, N are respectively the input, output channel number of convolution kernel; Dk is the convolution kernel size, DF is the feature map size. In the actual training of the network, N is greater than 1, and the convolution kernel size is 3*3.

[0222] In order to increase the nonlinearity of the model, the sparsity of the data, the rectified linear unit is added after each layer of the convolution layer and the fully connected layer, and the definition formula is as follows:

[0223] ReLU(x)=max(x,0) (6)

[0224] After the input data is further extracted in the convolution layer, the relationship between the features and the output categories is established using the fully connected network, in order to express the confidence of the recognition result, the probability of each prediction result is estimated using the softmax function, and the specific formula of the function is as follows:

[0225]

[0226] Wherein w is the weight of the neuron, k is the number of categories to be classified, x is the output result of the previous layer, the probability of predicting the category j is P, and the maximum value of the output probability is the prediction result.

[0227] After the model is trained, the weight parameters of each layer need to be exported to facilitate the use of hardware implementation.

[0228] 3, lightweight deep learning model deployment based on FPGA

[0229] When deploying the network, the FPGA development has two ways of HDL (Hardware Description Language) hardware description language development and HLS (High-Level Synthesis) high-level synthesis development.

[0230] HDL development can fully utilize hardware resources, but developers need to have a lot of circuit-related knowledge and hardware development foundation. For neural networks with a large number of floating-point multiplication and addition calculations, the development cycle is long and the development difficulty is great. The HLS development method is to use C / C++ high-level language to describe the function, and after optimization such as interface constraint and loop unrolling, it can be directly synthesized into IP core for use, which improves the development efficiency and shortens the development cycle. Therefore, the present application uses HLS high-level synthesis tool to deploy the deep learning model on FPGA.

[0231] HLS development needs to determine the input and output of the module and the function to be implemented in the module first, use C / C++ high-level language and library functions provided by HLS to write the specific implementation of the algorithm in the module, optimize the algorithm running in FPGA through optimization instructions, and fully use the internal resources of FPGA. Csimulation is established, and Testbench is written to verify the function of the module. After verification, the project written in high-level language is synthesized into RTL hardware description language IP core through Csynthesis. The performance indicators such as clock cycle, running time and resource consumption of the module can be obtained. If the hardware resources are not fully utilized or the resource utilization rate exceeds the existing resources, the algorithm needs to be optimized by using optimization instructions until the calculation efficiency and resource consumption are satisfactory. Then, C / RTL co-simulation is used, and after the running results of C / C++ high-level language and hardware description language are determined to be correct, the IP core is exported, which can be used in FPGA development.

[0232] The model training is performed on the computer, and the weight parameters of the light neural network are completed; 32-bit floating-point numbers are used for representation, and there is no special floating-point operation unit in FPGA, and running floating-point operation will consume more internal resources of FPGA, therefore, fixed-point quantization processing is performed on the input data and weight parameters of the network.

[0233] When 32-bit floating-point numbers are used for multiplication operation, 3 DSPs are needed, and 1 DSP is needed for addition operation, while 16-bit fixed-point number multiplication only consumes 1 DSP, and addition operation does not consume DSP. Converting 32-bit floating-point operation into 16-bit fixed-point operation can more effectively save the internal resources of FPGA and improve the resource utilization rate. The weight parameters and input and output feature maps of the network are quantized by using 16-bit dynamic fixed-point numbers, and the quantization formula is shown in formula 11.

[0234]

[0235] x fixed is a quantized 16-bit fixed-point number, s represents a sign bit, f represents a mantissa, B represents a quantized bit width length, and xi represents a mantissa part.

[0236] HLS provides an arbitrary precision type library ap_fixed to represent floating-point numbers, manually sets the integer width, decimal width, quantization mode and minimum value constraint mode of the floating-point number. The arbitrary precision data type can perfectly match the hardware requirements, and also inherits the operations allowed by the original data type, and can complete the forward inference operation of the network with very small precision loss.

[0237] The convolutional neural network structure mainly includes cyclic convolution operation and full connection operation. The operations are independent of each other and have no direct connection between channels. The FPGA has multiple multiplication (DSP) and adders constructed by digital circuits. The strategy of using resources to exchange time is used to multiplex the multiplier and the adder. One is the expansion and pipeline execution of the cycle, and the other is the large number of addition operations in the full connection layer. In addition to parallel multiplication, the addition is in the form of an addition tree, which converts the sequential accumulation calculation into layered parallel addition.

[0238] For the convolution calculation unit, the purpose of convolution operation is to extract the features of input data, and the more representative data is used to represent the input data. The calculation amount of the entire network is mainly concentrated in the convolution operation.

[0239] The convolution calculation formula is Y=CONV(W,X)+B, and W and B are weight and bias parameters. X is the input data of the current layer, and Y is the output data.

[0240] The essence of convolution calculation is matrix operation, which includes a large number of cyclic multiplication and addition operations.

[0241] When the program starts, the input data and the weight data are convolved. The convolution loop is expanded using the UNROLL instruction, and the FPGA internal DSP, LUT and other resources are used for parallel calculation. When reading parameters, since the parameters are stored in RAM, RAM only allows reading two data at a time, which does not meet the throughput of parallel operation. The PARTITION instruction is used to store the data in BRAM in blocks. The number of blocks is divided according to the number of parameters required for each calculation after loop expansion. After data blocking, the bottleneck of data calculation caused by data reading is eliminated.

[0242] After loop expansion, data is read, calculated and output at the same time in different loops. Pipeline technology is used to further improve the throughput and parallelism of the calculation. The basic idea of pipeline is to perform multiple different operations at the same time to prevent a single operation from limiting the calculation speed. In the case of a clock cycle for an operation, the pipeline idea is as shown in Figure 4 , when executing in sequence, 7 clock cycles can perform two complete data operations, and when using a three-stage pipeline, 7 clock cycles can perform five complete data operations. In HLS, the loop is first expanded for parallel execution, and then the PIPELINE command is used to set the pipeline after the data is cached in blocks.

[0243] For the pooling calculation unit, maximum pooling is adopted, and the pooling size is set to 2. Pooling can down-sample data, reduce dimensionality, remove redundant data, and reduce computation. Maximum pooling can avoid data calculation, and is the pooling mode with the least resource consumption, which can be realized by relying on a data selector and a comparator. In the pooling operation, the various pooling units do not interfere with each other, so the strategy of loop unrolling and pipelining can also be adopted for acceleration.

[0244] For the fully connected calculation unit, the role of full connection is to establish the relationship between data features and output categories, and to perform classification. The parameter quantity of the entire network is mainly concentrated in the full connection layer. During full connection calculation, the data dimension is reduced layer by layer, and each layer of feature data needs to be mapped to the neurons of the next layer. Like the convolution layer, there are a large number of multiplication and addition operations inside, and the calculation amount of addition and multiplication in the loop of a single neuron operation is larger. The same strategy as the convolution layer is adopted, and the pipeline and loop unrolling calculation are used. First, the product of the output result x of the previous layer and the weight w is stored in the register, and then an addition tree is constructed to perform parallel accumulation in the form of the addition tree to avoid consuming too many clock cycles in the loop addition. The entire structure of the addition tree is similar to a binary tree, and in one clock cycle, the product values in the register are added two by two, and the previous layer addition result is used as the next layer addition input, and the recursion is performed in turn to realize the pipeline, as shown in Figure 6 As shown in the figure, the product of 16 neurons and weight parameters is added in sequence, and it takes 15 clock cycles to complete the calculation, and using the addition tree parallel addition can obtain the calculation result in 4 clock cycles, which greatly improves the operation efficiency.

[0245] The lightweight isotope recognition neural network device designed by the application is called in the chip in the form of an IP core, as shown in Figure 6 As shown in the figure, the IP core provides 6 interfaces, which are s_axi_CONTROL interface, ap_clk interface, ap_rst_n interface, m_axi_DATA interface, m_axi_OUT_r interface and interrupt interface. The IP core adopts AXI_Lite protocol, and interacts with the outside world through AXI bus. The s_axi_CONTROL interface is the AXI_Lite data transmission protocol control interface. The ap_clk provides a clock signal for the operation of the IP core. The ap_rst_n provides a reset signal for the IP core, which is a low-level reset mode. The m_axi_DATA interface receives nuclear pulse feature data, and the probability of each isotope prediction calculated internally is output through the m_axi_OUT_r interface. The interrupt interface can output an interrupt signal.

Claims

1. An FPGA-based and lightweight CNN embedded fast nuclide identification method, characterized in that, The method comprises the following steps: S1, model establishment; S11, first generate a large amount of nuclear pulse data using a nuclear pulse generator; S12, extract the time-frequency characteristics of the pulse signal using HHT, establish a data set for the deep learning algorithm, and divide it into a training set and a test set according to a 7:3 ratio; S13, build a lightweight convolutional neural network MobileNet model through a Pytorch deep learning framework, wherein the MobileNet lightweight convolutional neural network comprises a convolutional layer, a pooling layer and a fully connected layer; continuously train, optimize and evaluate the model until the recognition performance of the model for the nuclide reaches an optimal state, derive the model weight parameters, and quantize them to 16 bits; S2, model deployment; deploy using an XC7Z020 chip, wherein the XC7Z020 chip has an FPGA logic module and two Cortex-A9 ARM processors; The two Cortex-A9 ARM processors are processor system modules, and the FPGA logic module is a programmable logic module; The processor system modules control the execution logic of the entire model, and the programmable logic module implements specific calculations of the nuclide recognition neural network; The data interaction between the processor system modules and the programmable logic module uses an AXI data bus connection; Store the weight parameters of the network in a Bin file in an SD card, and when the chip is powered on, read the data in the SD card into a RAM data buffer area; After inputting the nuclide pulse characteristics, sequentially execute the convolution module, the pooling module and the fully connected module of the MobileNet; After the fully connected module calculates the predicted nuclide probability, transmit the calculation result to the processor system unit again through the AXI bus, and the processor system unit selects the nuclide corresponding to the maximum probability to output the predicted category.

2. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 1, characterized in that: In step S12, the time-frequency characteristics of the nuclear pulse signal are extracted using HHT; The HHT comprises two processes of EMD decomposition and Hilbert transformation; Let the original signal be x(n), and the EMD decomposition steps are as follows: a1: find all extreme values of x(n) and extract the upper and lower envelope sequences of x(n) through interpolation; a2: calculate the local mean curve of the upper and lower envelope lines, and set it as m(n); a3: calculate h(n), h(n) = x(n) - m(n); a4: determine whether h(n) meets the condition, if it meets the IMF condition, go to a5, otherwise, let x(n) = h(n) and return to a1 for continuous loop; a5: let the ith IMF be C i (n), C i (n) = x(n) - h(n); a6: judge C i whether the EMD decomposition end condition is met, if met, end the EMD process, if not met, save C i , let x(n)=C i (n), return to a1 and continue the loop; The decomposition adjustment is as follows: For the nuclear pulse signal sequence x(t), it can be decomposed into a plurality of intrinsic mode functions IMF through EMD, i.e. the original signal is the superposition of these intrinsic mode functions: wherein n is the order of the IMF component, c i (t) is the i-th order IMF component, r n (t) is the residual after signal decomposition; The signals subjected to EMD decomposition meet the following three basic conditions: 1) The signal sequence contains at least one maximum value and one minimum value; 2) The local time domain characteristics of the signal are determined only by the time scale between extreme points; 3) When the signal sequence only contains inflection points, the extreme values can be obtained by differentiation; The IMF functions obtained by EMD decomposition satisfy the following two conditions: 1) The number of extreme points and zero points differ by at most one; 2) The local maximum and minimum of the IMF form the upper envelope line and the lower envelope line of the function respectively, and the average of the two is 0; After EMD decomposition, the signal Ci is subjected to Hilbert transform for feature extraction: Where P represents the Cauchy principal value; The instantaneous frequency and amplitude of each IMF are obtained, and the evaluation expression is: The time series, instantaneous frequency and amplitude jointly form the time-frequency diagram of the nuclear pulse, and the time-frequency diagram is subjected to gray-scale processing and sent to the neural network for recognition.

3. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 2, characterized in that: In step S13, the lightweight convolutional neural network MobileNet model is built, including a convolutional layer, a pooling layer and a fully connected layer; The convolutional layer changes the ordinary convolution operation into a depth separable convolution; The depth separable convolution decomposes the ordinary convolution operation into a channel-wise convolution and a point-wise convolution; In the channel-wise convolution, one convolution kernel is responsible for one channel, and one channel is only convolved by one convolution kernel; The point-wise convolution has a convolution kernel size of 1x1xM, where M is the number of channels of the previous layer; The data obtained in step S12 are used to train the model, and after the model is trained, the weight parameters of each layer are exported; The pooling layer adopts maximum pooling, and the pooling size is set to 2; The fully connected layer is used to establish the relationship between the data features and the output categories, and perform classification.

4. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 3, characterized in that: The rectified linear unit is added after each convolutional layer and fully connected layer, and the definition formula is as follows: ReLU(x)=max(x,0).

5. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 4, characterized in that: After the convolutional layer further extracts the features of the input data, the fully connected network is used to establish the relationship between the features and the output categories, and the softmax function is used to estimate the probability of each prediction result, and the specific formula is as follows: Where w is the weight of the neuron, k is the number of categories to be classified, x is the output result of the previous layer, the probability of predicting the category j is P, and the maximum probability of the output is the prediction result.

6. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 1, characterized in that: In step S2, the HLS high-level synthesis tool is used to deploy the deep learning model of the FPGA logic module; b1, determine the input and output of the module and the function to be realized in the module, use C / C++ high-level language and library functions provided by HLS to write the specific implementation form of the algorithm in the module; b2, optimize the algorithm running in the FPGA through optimization instructions; b3, establish C simulation, write Testbench to verify the function of the module; b4, after verification, the high-level language project is synthesized into an RTL hardware description language IP core through C synthesis; The clock period, running time and resource consumption performance indicators of the module are obtained; b5, if the hardware resources are not fully utilized or the resource utilization rate exceeds the existing resources in b4, the algorithm needs to be optimized by using optimization instructions until the calculation efficiency and resource consumption meet the requirements. b6. After confirming that the C / C++ high-level language and hardware description language results are complete and error-free through C / RTL co-simulation, export the IP core, which can then be used during FPGA deployment.

7. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 6, characterized in that: The lightweight neural network weight parameters completed in step S13 are represented using 32-bit floating-point numbers. Convert 32-bit floating-point arithmetic to 16-bit fixed-point arithmetic; The network's weight parameters and input / output feature maps are quantized using a 16-bit dynamic fixed-point quantization method. The quantization formula is as follows: x fixed For the quantized 16-bit fixed-point number, s represents a sign bit, f represents a mantissa, B represents a quantized bit width length, x i represents a mantissa part; The HLS provides an arbitrary precision type library ap_fixed to represent floating-point numbers, allowing manual setting of the integer width, decimal width, quantization mode, and minimum value constraint method for floating-point numbers.

8. The FPGA-based and lightweight CNN embedded fast nuclide identification method according to claim 7, characterized in that: The loop operations in the lightweight convolutional neural network MobileNet model include convolution operations and fully connected operations. The FPGA internally has multiple multipliers and adders constructed from digital circuits; during operation, the multipliers and adders are reused; that is:

1. Loop unrolling and pipelined execution; 2. Fully connected operation. In addition to parallel multiplication calculations, addition is performed in the form of an addition tree, which transforms sequential cumulative calculations into hierarchical parallel addition.

9. The fast nuclide identification method based on FPGA and lightweight CNN embedded as described in claim 8, characterized in that: The unrolling and pipeline execution of the loop includes the following steps: The formula for calculating the convolution operation in the convolutional layer is Y = CONV(W,X) + B, where W and B are weights and bias parameters, respectively; X is the input data of the current layer, and Y is the output data. The input data and weight data are convolved, and the convolution loop is unwound using the UNROLL instruction. Parallel computation is then performed using the FPGA's internal DSP and LUT. When reading parameters, the ARRAY_PARTITION instruction is used to divide the data in RAM into blocks and store them in BRAM. The number of blocks is divided according to the number of parameters required for each calculation in the loop expansion. After loop unrolling, data is read, calculated, and output simultaneously across different loops; pipelining techniques are employed to increase computational throughput and parallelism; the pipelining is configured using the PIPELINE command. In the pooling layer, max pooling is used for pooling calculation units, and the pooling size is set to 2. In the fully connected layer, the data dimensionality is reduced layer by layer during fully connected computation. The feature data of each layer needs to be mapped to the neurons of the next layer. Similar to the convolutional layer, there are a large number of multiplication and addition operations inside. The same strategy as the convolutional layer is used, using pipeline and loop unrolling for computation. First, the product of the output result x of the previous layer and the weight w is stored in a register. Then, an addition tree is built and parallel accumulation is performed in the form of the addition tree. The addition tree adds the product values ​​in the registers pairwise within one clock cycle, and uses the sum of the previous layer as the input for the next layer, recursively implementing a pipelined process.

10. The fast nuclide identification method based on FPGA and lightweight CNN embedded as described in claim 1, characterized in that: The lightweight convolutional neural network MobileNet model is called in the FPGA chip in the form of an IP core; The IP core includes six interfaces, namely, an s_axi_CONTROL interface, an ap_clk interface, an ap_rst_n interface, a m_axi_DATA interface, a m_axi_OUT_r interface and an interrupt interface; The IP core adopts an AXI_Lite protocol and interacts with the outside world through an AXI bus, and the s_axi_CONTROL interface is an AXI_Lite data transmission protocol control interface; The ap_clk provides a clock signal for the operation of the IP core; The ap_rst_n provides a reset signal for the IP core, and is a low-level reset mode; the m_axi_DATA interface receives nuclear pulse characteristic data, and the probability of each nuclear prediction calculated internally is output through the m_axi_OUT_r interface; The interrupt interface can output an interrupt signal.

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