Shift register and gate drive circuit

Abstract

The application discloses a shift register and a gate driving circuit, and the second output control module of the shift register comprises a first output control unit and a second output control unit, and the second output control unit is used for controlling the transmission of a first potential signal to a second node according to a second clock signal and an output signal of an output end of the shift register. When the shift register outputs a valid potential signal and the second clock signal is a valid potential signal, the second output control unit transmits the first potential signal to the second node, the second node is connected with a control end of a second output module, the control end of the second output module is the first potential signal (an invalid potential signal), and then the second output module is kept in good off state, so that when the shift register outputs the valid potential signal, the invalid potential signal (the first potential signal) cannot be transmitted to the output end of the shift register. The technical scheme has the advantages of improving the stability of the output signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular to a shift register and a gate driving circuit. BACKGROUND

[0002] With the development of display technology, people have higher and higher requirements for display quality.

[0003] In the existing display panel, a gate driving circuit is usually included, the gate driving circuit includes a plurality of shift registers, and the display panel is controlled to display through the output signals of the shift registers. However, the signal output of the shift register in the existing display panel is unstable, which leads to poor display quality. SUMMARY

[0004] The present application provides a shift register and a gate driving circuit to improve the stability of the output signal of the shift register and thus improve the display quality of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a shift register, comprising: a first output control module, a second output control module, a first output module, and a second output module.

[0006] The first output control module is configured to control transmission of a start signal and a first potential signal to a first node according to a first clock signal, a second clock signal, and a potential of a second node, wherein the first node is electrically connected to a control end of the first output module, and the second node is electrically connected to a control end of the second output module.

[0007] The second output control module includes a first output control unit and a second output control unit. The first output control unit is configured to control transmission of the first clock signal and a second potential signal to the second node according to the first clock signal and the potential of the first node. The second output control unit is configured to control transmission of the first potential signal to the second node according to the second clock signal and an output signal of an output end of the shift register.

[0008] The first output module is configured to control transmission of the second clock signal to the output end of the shift register according to a potential of a control end of the first output module.

[0009] The second output module is configured to control transmission of the first potential signal to the output end of the shift register according to a potential of a control end of the second output module.

[0010] Optionally, the first output control module includes a third output control unit and a fourth output control unit.

[0011] The third output control unit is configured to control transmission of the start signal to the first node according to the first clock signal. When the first clock signal is an active potential signal, the first clock signal transmits the start signal to the first node.

[0012] The fourth output control unit is configured to control transmission of the first potential signal to the first node according to the second clock signal and the potential of the second node; when the second clock signal is the active potential signal and the potential of the second node is the active potential signal, the fourth output control unit transmits the first potential signal to the first node.

[0013] Optionally, the third output control unit comprises a first transistor, a gate of the first transistor is connected to the first clock signal, a first pole of the first transistor is connected to the start signal, and a second pole of the first transistor is connected to the first node.

[0014] The fourth output control unit comprises a second transistor and a third transistor, a gate of the second transistor is electrically connected to the second node, a first pole of the second transistor is connected to the first potential signal, and a second pole of the second transistor is electrically connected to a first pole of the third transistor.

[0015] A gate of the third transistor is connected to the second clock signal, and a second pole of the third transistor is electrically connected to the first node.

[0016] Optionally, the first output control unit comprises a first output control subunit, a second output control subunit and a third output control subunit; the first output control subunit is configured to control transmission of the first clock signal to the second node according to the potential of the first node; the second output control subunit is configured to control transmission of the second potential signal to the second node according to the first clock signal and the potential of the first node; and the third output control subunit is configured to control transmission of the second potential signal to the second node according to the first clock signal. By configuring the first output control unit to comprise the first output control subunit, the second output control subunit and the third output control subunit, when the first clock signal is the active potential signal (and the second clock signal is the inactive potential signal) and the potential of the first node is the active potential signal, the second node can also be maintained as the active potential signal, thereby ensuring that when the first clock signal is the active potential signal, the second clock signal is the inactive potential signal and the potential of the first node is the active potential signal, the inactive potential signal of the second clock signal can be output through the first output module, and at the same time, the first potential signal (inactive potential signal) can be output through the second output module, thereby ensuring the stability of the output signal.

[0017] Optionally, the first output control subunit comprises a fourth transistor, a gate of the fourth transistor is electrically connected to the first node, a first pole of the fourth transistor is connected to the first clock signal, and a second pole of the fourth transistor is electrically connected to the second node.

[0018] The second output control subunit comprises a fifth transistor and a sixth transistor, a gate of the fifth transistor is electrically connected to the first node, a first pole of the fifth transistor is connected to the second potential signal, and a second pole of the fifth transistor is electrically connected to a first pole of the sixth transistor.

[0019] The gate of the sixth transistor is connected to the first clock signal, and the second electrode of the sixth transistor is electrically connected to the second node.

[0020] The third output control subunit comprises a seventh transistor, the gate of the seventh transistor is connected to the first clock signal, the first electrode of the seventh transistor is connected to the second potential signal, and the second electrode of the seventh transistor is electrically connected to the second node.

[0021] Optionally, the second output control unit comprises an eighth transistor and a ninth transistor, the gate of the eighth transistor is connected to the second clock signal, the first electrode of the eighth transistor is connected to the first potential signal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the ninth transistor; the gate of the ninth transistor is electrically connected to the output end of the shift register, and the second electrode of the ninth transistor is electrically connected to the second node. By setting that the second output control unit comprises the eighth transistor and the ninth transistor, when the shift register outputs the effective potential signal and the second clock signal is the effective potential signal, the first potential signal is transmitted to the second node, the second node is connected to the control end of the second output module, so that the control end of the second output module is the first potential signal (the ineffective potential signal), thereby ensuring that the second output module is kept good off, so that when the shift register outputs the effective potential signal, the ineffective potential signal (the first potential signal) will not be transmitted to the output end of the shift register.

[0022] Optionally, the second output control unit is further configured to control transmission of the second potential signal to the second node according to the first clock signal and the output signal.

[0023] Optionally, the second output control unit further comprises a tenth transistor, the gate of the tenth transistor is connected to the first clock signal, the first electrode of the tenth transistor is connected to the second potential signal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the ninth transistor. The tenth transistor is provided, so that when the first clock signal jumps from the ineffective potential signal to the low potential (the effective potential signal), and the output end of the shift register cannot jump from the low potential (the effective potential signal) to the high potential (the ineffective potential signal) in time, the ninth transistor and the tenth transistor are turned on at the same time, the output end of the shift register is quickly pulled to the ineffective potential signal, thereby facilitating improvement of stability of the output signal.

[0024] Optionally, the first output module comprises an eleventh transistor and a first capacitor; a gate of the eleventh transistor is used as a control terminal of the first output module, a first pole of the eleventh transistor is connected to the second clock signal, and a second pole of the eleventh transistor is electrically connected to the output terminal of the shift register; a first terminal of the first capacitor is electrically connected to the gate of the eleventh transistor, and a second terminal of the first capacitor is electrically connected to the second pole of the eleventh transistor. The first capacitor can make the potential at the control terminal of the first output module change with the potential jump of the output terminal of the shift register, for example, when the low potential signal is the effective potential signal of the first output module, the potential of the output terminal of the shift register jumps from the high potential signal to the low potential signal, and the potential at the control terminal of the first output module can be further lowered, thereby ensuring that the opening degree of the eleventh transistor included in the first output module is relatively complete, thereby facilitating the improvement of the stability of the output signal, and the influence of the threshold voltage change of the eleventh transistor on the voltage size of the output signal can be avoided.

[0025] Optionally, the second output module further comprises a twelfth transistor and a second capacitor; a gate of the twelfth transistor is electrically connected to the second node, a first pole of the twelfth transistor is connected to the first potential signal, and a second pole of the twelfth transistor is electrically connected to the output terminal of the shift register.

[0026] Optionally, the first output module further comprises a thirteenth transistor; a gate of the thirteenth transistor is electrically connected to the output terminal of the shift register, a first pole of the thirteenth transistor is connected to the second clock signal, and a second pole of the thirteenth transistor is electrically connected to the output terminal of the shift register. When the signal output by the output terminal of the shift register is the effective potential signal, the thirteenth transistor is turned on, thereby making the output of the effective level signal by the output terminal of the shift register be output through the thirteenth transistor and the eleventh transistor, which is beneficial to the improvement of the stability of the output signal.

[0027] In a second aspect, the embodiments of the present application further provide a gate drive circuit comprising a plurality of stages of the shift register of the first aspect, and the shift registers are connected in cascade.

[0028] The embodiment of the present application provides a shift register and a gate drive circuit, the shift register comprises a first output control module, a second output control module, a first output module and a second output module, the second output control module comprises a first output control unit and a second output control unit, the first output control unit is used for controlling the transmission of a first clock signal and a second potential signal to a second node according to the first clock signal and the potential of a first node, and the second output control unit is used for controlling the transmission of a first potential signal to the second node according to a second clock signal and the output signal of an output end of the shift register. For the first output module, the first potential signal is an invalid potential signal, so when the second output control unit outputs a valid potential signal and the second clock signal is a valid potential signal, the first potential signal is transmitted to the second node, the second node is connected with a control end of the second output module, so that the control end of the second output module is the first potential signal (invalid potential signal), and then the second output module is kept well off, so that when the shift register outputs the valid potential signal, the invalid potential signal (first potential signal) cannot be transmitted to the output end of the shift register. Therefore, through the setting of the second output control unit, the potential of the control end of the second output module can be kept as the first potential signal when the shift register outputs the valid potential signal, so that the problem that the potential cannot be kept due to the change of the drain current and the drift of the threshold voltage of the transistor of the shift register in the prior art cannot occur, and then the second output module can be well off when the first output module outputs the valid potential signal, and then the stability of the output signal is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a structural schematic diagram of a shift register in the prior art;

[0030] Figure 2 is a structural schematic diagram of a shift register provided by the embodiment of the present application;

[0031] Figure 3 is a structural schematic diagram of another shift register provided by the embodiment of the present application;

[0032] Figure 4 is a structural schematic diagram of another shift register provided by the embodiment of the present application;

[0033] Figure 5 is a structural schematic diagram of another shift register provided by the embodiment of the present application;

[0034] Figure 6 is a structural schematic diagram of another shift register provided by the embodiment of the present application;

[0035] Figure 7is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0036] Figure 8 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0037] Figure 9 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0038] Figure 10 is a working timing diagram of a shift register provided by an embodiment of the present application;

[0039] Figure 11 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0041] As described in the background, the signal output of the shift register in the existing display panel is unstable, resulting in poor display quality. The inventors have found that the reason for the above problem is that the existing shift register usually includes a pull-up output module, a pull-down output module, a pull-up output control module for controlling the pull-up output module, and a pull-down output control module for controlling the pull-down output module, Figure 1 is a structural schematic diagram of a shift register in the prior art, wherein Figure 1 only part of the structure of the shift register is shown schematically, and reference is made to Figure 1 The pull-up output module 01 includes a pull-up transistor T01, and the pull-down output module 02 includes a pull-down transistor T02. When the pull-up transistor T01 is turned on, the pull-up output module 01 outputs a high-level signal V1; when the pull-down transistor T02 is turned on, the pull-down output module 02 outputs a low-level signal V2. The transistor included in the pull-up output control module 03 (wherein the pull-up output control module 03 can include multiple transistors, Figure 1 one of which is shown schematically in the pull-up output control module 03 in FIG. 1) is used to control the gate potential of the pull-up transistor T01, and the transistor included in the pull-down output control module 04 (wherein the pull-down output control module 04 can include multiple transistors, Figure 1The pull-down output control module 04 includes a transistor for controlling the gate potential of the pull-down transistor T02. As the operation time of the shift register is prolonged, the threshold voltage of the transistor in each module of the shift register can drift, and the leakage current can increase, causing the gate potential of the transistor included in the pull-up output module 01 and / or the pull-down output module 02 to be unstable, resulting in unstable output signals of the shift register.

[0042] Based on the above reasons, the embodiment of the present application provides a shift register. Before introducing the specific implementation of the embodiment of the present application, the signals used by the shift register of each embodiment of the present application are briefly introduced.

[0043] In one frame, the first clock signal is a signal including a plurality of high potential pulses and a plurality of low potential pulses, and the high potential pulses and the low potential pulses alternate; in one frame, the second clock signal is also a signal including a plurality of high potential pulses and a plurality of low potential pulses, and the high potential pulses and the low potential pulses alternate; the high potential pulse of the first clock signal overlaps with the low potential pulse of the second clock signal, and the low potential pulse of the first clock signal overlaps with the high potential pulse signal of the second clock signal. Optionally, the width of the high potential pulse of the first clock signal is equal to the width of the high potential pulse of the second clock signal; the width of the low potential pulse of the first clock signal is equal to the width of the low potential pulse of the second clock signal.

[0044] In one frame, the start signal is a signal including a high potential pulse and a low potential pulse, and the high potential pulse and the low potential pulse alternate.

[0045] The above first clock signal, second clock signal and start signal are collectively referred to as control signals. For any control signal, the effective potential signal in the control signal is determined by the type of the device in the module of the shift register controlled by the control signal. Specifically, the effective potential signal of the control signal is a signal that can control the conduction of the corresponding device. For example, when the control signal is used to control a P-type transistor, the effective potential signal is a low potential signal, and when the control signal is used to control an N-type transistor, the effective potential signal is a high potential signal.

[0046] The first potential signal and the second potential signal can both be fixed signals, and the potentials of the first potential signal and the second potential signal are opposite. Optionally, the first potential signal is a high potential signal, and the second potential signal is a low potential signal; or the first potential signal is a low potential signal, and the second potential signal is a high potential signal.

[0047] Optionally, the voltage of the high potential signal of each control signal can be equal, for example, +7V, and the voltage of the low potential signal can also be equal, for example, -7V. The voltage of the high potential signal of the first potential signal and the second potential signal can also be +7V, and the voltage of the low potential signal can also be -7V.

[0048] Figure 2 is a structural diagram of a shift register provided by an embodiment of the present application, referring to Figure 2 The shift register comprises a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140. The first output control module 110 is configured to control the transmission of a start signal SIN and a first potential signal VGH to a first node N1 according to a first clock signal CK1, a second clock signal CK2, and the potential of a second node N2, wherein the first node N1 is electrically connected to the control end of the first output module 130, and the second node N2 is electrically connected to the control end of the second output module 140. The second output control module 120 comprises a first output control unit 121 and a second output control unit 122. The first output control unit 121 is configured to control the transmission of the first clock signal CK1 and a second potential signal VGL to the second node N2 according to the first clock signal CK1 and the potential of the first node N1. The second output control unit 122 is configured to control the transmission of the first potential signal VGH to the second node N2 according to the second clock signal CK2 and the output signal of the output end OUT of the shift register. The first output module 130 is configured to control the transmission of the second clock signal CK2 to the output end OUT of the shift register according to the potential of the control end thereof. The second output module 140 is configured to control the transmission of the first potential signal VGH to the output end OUT of the shift register according to the potential of the control end thereof.

[0049] The first output control module 110 is configured to control the transmission of the start signal SIN to the first node N1 according to the first clock signal CK1, and specifically, when the first clock signal CK1 is an effective potential signal, the first output control module 110 transmits the start signal SIN to the first node N1. The first output control module 110 is also configured to control the transmission of the first potential signal VGH to the first node N1 according to the potential of the second node N2 and the second clock signal CK2, and specifically, when the potential of the second node N2 is an effective potential signal and the second clock signal CK2 is an effective potential signal, the first output control module 110 transmits the first potential signal VGH to the first node N1.

[0050] The second output control module 120 comprises a first output control unit 121 and a second output control unit 122. The first output control unit 121 is configured to control transmission of the first clock signal CK1 and the second potential signal VGL to the second node N2 according to the first clock signal CK1 and the potential of the first node N1. Specifically, the first output control unit 121 transmits the first clock signal CK1 to the second node N2 when the potential of the first node N1 is the active potential signal. In addition, the first output control unit 121 transmits the second potential signal VGL to the second node N2 when the potential of the first node N1 is the active potential signal and the first clock signal CK1 is the active potential signal. Furthermore, the first output control unit 121 transmits the second potential signal VGL to the second node N2 when the first clock signal CK1 is the active potential signal.

[0051] The second output control unit 122 is configured to control transmission of the first potential signal VGH to the second node N2 according to the second clock signal CK2 and the output signal of the output terminal OUT of the shift register. Specifically, the second output control unit 122 transmits the first potential signal VGH to the second node N2 when the second clock signal CK2 is the active potential signal and the output signal of the output terminal OUT of the shift register is the active potential signal. In the embodiment, for the second output module 140, the first potential signal VGH is the inactive potential signal. Therefore, the second output control unit 122 transmits the first potential signal VGH to the second node N2 when the shift register outputs the active potential signal and the second clock signal CK2 is the active potential signal. The second node N2 is connected to the control terminal of the second output module 140, so that the control terminal of the second output module 140 is the first potential signal VGH, thereby ensuring that the second output module 140 is well turned off. When the shift register outputs the active potential signal, the inactive potential signal (the first potential signal VGH) will not be transmitted to the output terminal OUT of the shift register. Therefore, the second output control unit 122 is provided in the embodiment, so that the potential of the control terminal of the second output module 140 can be maintained as the first potential signal VGH (the inactive potential signal) when the shift register outputs the active potential signal. In addition, the problem that the potential cannot be maintained due to the change of the leakage current of the transistor of the shift register and the drift of the threshold voltage in the prior art is avoided, thereby ensuring that the second output module 140 can be well turned off, and thereby the stability of the output signal is improved.

[0052] The first output module 130 is configured to control transmission of the second clock signal CK2 to the output terminal OUT of the shift register according to a potential of a control terminal of the first output module 130. When the potential of the control terminal of the first output module 130 is an effective potential signal, the first output module 130 transmits the second clock signal CK2 to the output terminal OUT of the shift register. In this embodiment, the control terminal of the first output module 130 is electrically connected to the first node N1. The electrical connection between the control terminal of the first output module 130 and the first node N1 can be direct electrical connection or indirect electrical connection (i.e. a switch element such as a transistor can be connected between the control terminal of the first output module 130 and the first node N1, and the switch element can be normally open). Therefore, when the potential of the first node N1 is an effective potential signal, the potential of the control terminal of the first output module 130 is an effective potential signal.

[0053] The second output module 140 is configured to control transmission of the first potential signal VGH to the output terminal OUT of the shift register according to a potential of a control terminal of the second output module 140. When the potential of the control terminal of the second output module 140 is an effective potential signal, the second output module 140 transmits the first potential signal VGH to the output terminal OUT of the shift register. In this embodiment, the control terminal of the second output module 140 is electrically connected to the second node N2. The electrical connection between the control terminal of the second output module 140 and the second node N2 can be direct electrical connection or indirect electrical connection (i.e. a switch element such as a transistor can be connected between the control terminal of the second output module 140 and the second node N2, and the switch element can be normally open). Therefore, when the potential of the second node N2 is an effective potential signal, the potential of the control terminal of the second output module 140 is an effective potential signal.

[0054] The shift register of the embodiment comprises a first output control module, a second output control module, a first output module and a second output module. The second output control module comprises a first output control unit and a second output control unit. The first output control unit is configured to control transmission of the first clock signal and the second potential signal to the second node according to the first clock signal and the potential of the first node. The second output control unit is configured to control transmission of the first potential signal to the second node according to the second clock signal and the output signal of the output end of the shift register. For the second output module, the first potential signal is an invalid potential signal. Therefore, when the shift register outputs a valid potential signal and the second clock signal is a valid potential signal, the second output control unit transmits the first potential signal to the second node. The second node is connected to the control end of the second output module, so that the control end of the second output module is the first potential signal (invalid potential signal), thereby ensuring that the second output module is well turned off, so that when the shift register outputs a valid potential signal, the invalid potential signal (first potential signal) will not be transmitted to the output end of the shift register. Therefore, by means of the second output control unit, the potential of the control end of the second output module can be maintained as the first potential signal when the shift register outputs a valid potential signal, so that the problem of being unable to maintain the potential due to the change of the leakage current of the transistor and the drift of the threshold voltage in the prior art is avoided, thereby ensuring that the second output module can be well turned off when the first output module outputs a valid potential signal, thereby facilitating improvement of the stability of the output signal.

[0055] Figure 3 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 3 Optionally, the first output control module 110 comprises a third output control unit 111 and a fourth output control unit 112. The third output control unit 111 is configured to control transmission of the start signal SIN to the first node N1 according to the first clock signal CK1. The fourth output control unit 112 is configured to control transmission of the first potential signal VGH to the first node N1 according to the second clock signal CK2 and the potential of the second node N2.

[0056] The third output control unit 111 is configured to control transmission of the start signal SIN to the first node N1 according to the first clock signal CK1, which means that when the first clock signal CK1 is a valid potential signal, the first clock signal CK1 transmits the start signal SIN to the first node N1. The fourth output control unit 112 is configured to control transmission of the first potential signal VGH to the first node N1 according to the second clock signal CK2 and the potential of the second node N2, which means that when the second clock signal CK2 is a valid potential signal and the potential of the second node N2 is a valid potential signal, the fourth output control unit 112 transmits the first potential signal VGH to the first node N1.

[0057] With reference to the foregoing Figure 3 Optionally, the third output control unit 111 comprises a first transistor T1, a gate of the first transistor T1 is connected to the first clock signal CK1, a first pole of the first transistor T1 is connected to the start signal SIN, and a second pole of the first transistor T1 is connected to the first node N1; the fourth output control unit 112 comprises a second transistor T2 and a third transistor T3, a gate of the second transistor T2 is electrically connected to the second node N2, a first pole of the second transistor T2 is connected to the first potential signal VGH, and a second pole of the second transistor T2 is electrically connected to a first pole of the third transistor T3; a gate of the third transistor T3 is connected to the second clock signal CK2, and a second pole of the third transistor T3 is electrically connected to the first node N1.

[0058] The first transistor T1 is turned on or turned off according to the first clock signal CK1, when the first clock signal CK1 is a valid potential signal, the first transistor T1 is turned on and transmits the start signal SIN to the first node N1. The second transistor T2 is turned on or turned off according to the potential of the second node N2, when the potential of the second node N2 is a valid potential signal, the second transistor T2 is turned on and transmits the first potential signal VGH to the first pole of the third transistor T3; the third transistor T3 is turned on or turned off according to the second clock signal CK2, when the second clock signal CK2 is a valid potential signal, the third transistor T3 is turned on and transmits the potential signal of the first pole to the first node N1. Therefore, when the potential of the second node N2 is a valid potential signal and the second clock signal CK2 is a valid potential signal, the first potential signal VGH is transmitted to the first node N1 through the second transistor T2 and the third transistor T3.

[0059] Figure 4 is another structure diagram of a shift register provided by the embodiment of the present application, with reference to Figure 4 Optionally, the first output control unit 121 comprises a first output control subunit 1211, a second output control subunit 1212 and a third output control subunit 1213; the first output control subunit 1211 is configured to control transmission of the first clock signal CK1 to the second node N2 according to the potential of the first node N1; the second output control subunit 1212 is configured to control transmission of the second potential signal VGL to the second node N2 according to the first clock signal CK1 and the potential of the first node N1; and the third output control subunit 1213 is configured to control transmission of the second potential signal VGL to the second node N2 according to the first clock signal CK1.

[0060] The first output control subunit 1211 is configured to control transmission of the first clock signal CK1 to the second node N2 according to the potential of the first node N1. When the potential of the first node N1 is the active potential signal, the first output control subunit 1211 transmits the first clock signal CK1 to the second node N2. The second output control subunit 1212 is configured to control transmission of the second potential signal VGL to the second node N2 according to the first clock signal CK1 and the potential of the first node N1. When the first clock signal CK1 is the active potential signal and the potential of the first node N1 is the active potential signal, the second output control subunit 1212 transmits the second potential signal VGL to the second node N2. The third output control subunit 1213 is configured to control transmission of the second potential signal VGL to the second node N2 according to the first clock signal CK1. When the first clock signal CK1 is the active potential signal, the third output control subunit 1213 transmits the second potential signal VGL to the second node N2. The shift register in this embodiment includes the first output control subunit 121, which includes the first output control subunit 1211, the second output control subunit 1212, and the third output control subunit 1213. When the first clock signal CK1 is the active potential signal (and the second clock signal CK2 is the inactive potential signal) and the potential of the first node N1 is the active potential signal, the second node N2 can also be maintained as the active potential signal, thereby ensuring that, when the first clock signal CK1 is the active potential signal, the second clock signal CK2 is the inactive potential signal, and the potential of the first node N1 is the active potential signal, the inactive potential signal of the second clock signal CK2 can be output by the first output module 130, and the first potential signal VGH (inactive potential signal) can be output by the second output module 140, thereby ensuring the stability of the output signal.

[0061] With reference to Figure 4 Optionally, the first output control subunit 1211 includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the first node N1. The first pole of the fourth transistor T4 is connected to the first clock signal CK1. The second pole of the fourth transistor T4 is electrically connected to the second node N2.

[0062] Specifically, the fourth transistor T4 is turned on or turned off according to the potential of the first node N1. When the potential of the first node N1 is the active potential signal, the fourth transistor T4 is turned on and transmits the first clock signal CK1 to the second node N2.

[0063] Optionally, the second output control subunit 1212 comprises a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is electrically connected with the first node N1, the first electrode of the fifth transistor T5 is connected with the second potential signal VGL, and the second electrode of the fifth transistor T5 is electrically connected with the first electrode of the sixth transistor T6; the gate of the sixth transistor T6 is connected with the first clock signal CK1, and the second electrode of the sixth transistor T6 is electrically connected with the second node N2.

[0064] Specifically, the fifth transistor T5 is turned on or turned off according to the potential of the first node N1, when the potential of the first node N1 is the effective potential signal, the fifth transistor T5 is turned on and transmits the second potential signal VGL to the first electrode of the sixth transistor T6; the sixth transistor T6 is turned on or turned off according to the first clock signal CK1, when the first clock signal CK1 is the effective potential signal, the sixth transistor T6 is turned on and transmits the potential signal of the first electrode to the second node N2. Therefore, when the potential of the first node N1 is the effective potential signal and the first clock signal CK1 is the effective potential signal, the second potential signal is transmitted to the second node N2.

[0065] Optionally, the third output control subunit 1213 comprises a seventh transistor T7, the gate of the seventh transistor T7 is connected with the first clock signal CK1, the first electrode of the seventh transistor T7 is connected with the second potential signal VGL, and the second electrode of the seventh transistor T7 is electrically connected with the second node N2.

[0066] Specifically, the seventh transistor T7 is turned on or turned off according to the first clock signal CK1, when the first clock signal CK1 is the effective potential signal, the seventh transistor T7 is turned on and transmits the second potential signal VGL to the second node N2.

[0067] Figure 5 is another structure diagram of a shift register provided by the embodiment of the application, referring to Figure 5 Optionally, the second output control unit 122 comprises an eighth transistor T8 and a ninth transistor T9, the gate of the eighth transistor T8 is connected with the second clock signal CK2, the first electrode of the eighth transistor T8 is connected with the first potential signal VGH, the second electrode of the eighth transistor T8 is electrically connected with the first electrode of the ninth transistor T9; the gate of the ninth transistor T9 is electrically connected with the output end OUT of the shift register, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2.

[0068] Specifically, the eighth transistor T8 is turned on or turned off according to the second clock signal CK2, when the second clock signal CK2 is an effective potential signal, the eighth transistor T8 is turned on and transmits the first potential signal VGH to the first electrode of the ninth transistor T9; the ninth transistor T9 is turned on or turned off according to the output signal of the output terminal OUT of the shift register, when the output signal is an effective potential signal, the ninth transistor T9 is turned on and transmits the potential signal of the first electrode to the second node N2. Therefore, when the potential signal of the second clock signal CK2 and the output signal of the output terminal OUT of the shift register is an effective potential signal, the first potential signal VGH is transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9. By setting the second output control unit 122 to include the eighth transistor T8 and the ninth transistor T9, the second output control unit transmits the first potential signal VGH to the second node N2 when the shift register outputs an effective potential signal and the second clock signal CK2 is an effective potential signal, the second node N2 is connected with the control end of the second output module 140, so that the control end of the second output module 140 is the first potential signal VGH (ineffective potential signal), thereby ensuring that the second output module 140 remains good off, so that when the shift register outputs an effective potential signal, the ineffective potential signal (first potential signal) will not be transmitted to the output terminal OUT of the shift register.

[0069] Figure 6 is another structure diagram of a shift register provided by the embodiment of the application, referring to Figure 6 Optionally, the second output control unit 122 is further configured to transmit the second potential signal VGL to the second node N2 according to the first clock signal CK1 and the output signal.

[0070] Specifically, when the first clock signal CK1 is an effective potential signal and the output signal is an effective potential signal, the second output control unit 122 transmits the second potential signal to the second node N2.

[0071] Optionally, the second output control unit 122 further includes a tenth transistor T10, the gate electrode of the tenth transistor T10 is connected with the first clock signal CK1, the first electrode of the tenth transistor T10 is connected with the second potential signal VGL, and the second electrode of the tenth transistor T10 is electrically connected with the first electrode of the ninth transistor T9.

[0072] Specifically, the tenth transistor T10 is turned on or turned off according to the first clock signal CK1, when the first clock signal CK1 is the active potential signal, the tenth transistor T10 is turned on, and the second potential signal VGL is transmitted to the second electrode of the tenth transistor T10. Moreover, when the first clock signal CK1 is the active potential signal and the output signal of the output terminal OUT of the shift register is the active potential signal, the tenth transistor T10 and the ninth transistor T9 are both turned on, and the second potential signal is transmitted to the second node N2 through the tenth transistor T10 and the ninth transistor T9. Taking the active potential signal as the second potential signal and the low potential signal as an example, the tenth transistor T10 is arranged to make the first clock signal CK1 jump from the high potential (inactive potential signal) to the low potential (active potential signal), and when the output terminal OUT of the shift register cannot jump from the low potential (active potential signal) to the high potential (inactive potential signal) in time, the tenth transistor T10 is turned on in response to the low potential first clock signal CK1, and the ninth transistor T9 is turned on in response to the low potential output signal, so that the second potential signal VGL is transmitted to the second node N2 through the tenth transistor T10 and the ninth transistor T9, and the potential of the second node N2 is pulled to be very low, so that the second output module 140 is turned on, the first potential signal VGH is output through the second output module 140, and the output terminal OUT of the shift register can be quickly pulled to the inactive potential signal, thereby improving the stability of the output signal.

[0073] Figure 7 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 7 Optionally, the first output module 130 comprises an eleventh transistor T11 and a first capacitor C1.

[0074] The gate of the eleventh transistor T11 is used as the control terminal of the first output module 130, the first electrode of the eleventh transistor T11 is connected to the second clock signal CK2, and the second electrode of the eleventh transistor T11 is electrically connected to the output terminal OUT of the shift register.

[0075] The first end of the first capacitor C1 is electrically connected to the gate of the eleventh transistor T11, and the second end of the first capacitor C1 is electrically connected to the second electrode of the eleventh transistor T11.

[0076] Specifically, the eleventh transistor T11 is turned on or turned off according to the potential of the gate of the eleventh transistor T11, when the potential of the gate of the eleventh transistor T11 is the effective potential signal, the eleventh transistor T11 is turned on and the second clock signal CK2 is transmitted to the output terminal OUT of the shift register. The first capacitor C1 can store the gate potential of the eleventh transistor T11, and the first capacitor C1 also has a bootstrap function, when the potential of the output terminal OUT of the shift register jumps, the first capacitor C1 can couple the potential jump of the output terminal OUT of the shift register to the gate of the eleventh transistor T11. The setting of the first capacitor C1 can make the potential of the control terminal of the first output module 130 change with the potential jump of the output terminal OUT of the shift register, for example, when the low potential signal is the effective potential signal of the first output module 130, the potential of the output terminal OUT of the shift register jumps from the high potential signal to the low potential signal, the potential of the control terminal of the first output module 130 can be further lowered, thereby ensuring that the opening degree of the eleventh transistor T11 included in the first output module 130 is relatively complete, thereby facilitating to improve the stability of the output signal, and the influence of the threshold voltage change of the eleventh transistor T11 on the voltage size of the output signal can be avoided.

[0077] With reference to Figure 7 Optionally, the second output module 140 further includes a twelfth transistor T12 and a second capacitor C2; the gate of the twelfth transistor T12 is electrically connected with the second node N2, the first pole of the twelfth transistor T12 is connected with the first potential signal VGH, and the second pole of the twelfth transistor T12 is electrically connected with the output terminal OUT of the shift register.

[0078] Specifically, the twelfth transistor T12 is turned on or turned off according to the potential of the gate of the twelfth transistor T12, when the potential of the gate of the twelfth transistor T12 is the effective potential signal, the twelfth transistor T12 is turned on and the first potential signal VGH is transmitted to the output terminal OUT of the shift register. The second capacitor C2 can store the gate potential of the twelfth transistor T12.

[0079] Figure 8 is another structure diagram of a shift register provided by the embodiment of the application, with reference to Figure 8 Optionally, the first output module 130 further includes a thirteenth transistor T13, the gate of the thirteenth transistor T13 is electrically connected with the output terminal OUT of the shift register, the first pole of the thirteenth transistor T13 is connected with the second clock signal CK2, and the second pole of the thirteenth transistor T13 is electrically connected with the output terminal OUT of the shift register.

[0080] Specifically, the first output module 130 further comprises a thirteenth transistor T13. When the signal output by the output end OUT of the shift register is a valid potential signal, the thirteenth transistor T13 is turned on, and then when the output end OUT of the shift register outputs a valid level signal, the output can be performed through the thirteenth transistor T13 and the eleventh transistor T11, which is beneficial to improve the stability of the output signal. Figure 8 As shown in the shift register structure, the thirteenth transistor T13 and the eleventh transistor T11 form a parallel structure, and then the resistance after parallel connection is reduced, so that the voltage of the output signal decreases relatively small with respect to the second clock signal CK2, and the voltage amplitude of the output signal is ensured to decrease relatively small.

[0081] Figure 9 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 9The shift register comprises a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140. The second output control module 120 comprises a first output control unit 121 and a second output control unit 122. The first output control module 110 comprises a third output control unit 111 and a fourth output control unit 112. The third output control unit 111 comprises a first transistor T1, and the fourth output control unit 112 comprises a second transistor T2 and a third transistor T3. The first output control unit 121 comprises a first output control subunit 1211, a second output control subunit 1212, and a third output control subunit 1213. The first output control subunit 1211 comprises a fourth transistor T4. The second output control subunit 1212 comprises a fifth transistor T5 and a sixth transistor T6. The third output control subunit 1213 comprises a seventh transistor T7. The second output control unit 122 comprises an eighth transistor T8 and a ninth transistor T9. The second output control unit 122 can further comprise a tenth transistor T10. The first output module 130 comprises an eleventh transistor T11 and a first capacitor C1. The first output module 130 can further comprise a thirteenth transistor T13. The second output module 140 further comprises a twelfth transistor T12 and a second capacitor C2. The shift register further comprises a fourteenth transistor T14 and a fifteenth transistor T15. The gate of the fourteenth transistor T14 is connected to a second potential signal VGL. The first pole of the fourteenth transistor T14 is connected to a first node N1. The second pole of the fourteenth transistor T14 is electrically connected to the control end (the gate of the eleventh transistor T11) of the first output module 130. The gate of the fifteenth transistor T15 is connected to the second potential signal VGL. The first pole of the fifteenth transistor T15 is connected to a second node N2. The second pole of the fifteenth transistor T15 is electrically connected to the control end (the gate of the twelfth transistor T12) of the second output module 140. The second potential signal VGL can be an effective potential signal for the fourteenth transistor T14 and the fifteenth transistor T15, so the fourteenth transistor T14 and the fifteenth transistor T15 can be always-on transistors. The transistors comprised in the shift register can be P-type transistors or N-type transistors. Figure 9 The first potential signal VGH is a high potential signal, and the second potential signal VGL is a low potential signal. The effective potential signal is a low potential signal for each transistor.

[0082] Figure 10 is a working timing diagram of a shift register provided by an embodiment of the present application. The working timing diagram can be applied to the shift register shown in Figure 9 . Referring to Figure 9 and Figure 10,The working process of the shift register includes multiple stages.

[0083] In the first phase t1, the start signal SIN is at a low potential, the first clock signal CK1 is at a low potential, and the second clock signal CK2 is at a high potential. The first transistor T1 is turned on in response to the low potential of the first clock signal CK1, transmitting the low potential start signal SIN to the first node N1. The low potential of the first node N1 is transmitted to the gate of the eleventh transistor T11 via the fourteenth transistor T14, causing the eleventh transistor T11 to be turned on in response to the low potential of its own electrode and transmit the high potential second clock signal CK2 to the output terminal OUT of the shift register. The fourth transistor T4 is turned on in response to the low potential of the first node N1, and transmits the low potential first clock signal CK1 to the second node N2; the seventh transistor T7 is turned on in response to the low potential of the first clock signal CK1, and transmits the second potential signal VGL (low potential signal) to the second node N2; at the same time, the fifth transistor T5 is turned on in response to the low potential of the first node N1, and the sixth transistor T6 is turned on in response to the low potential of the first clock signal CK1, and the second potential signal VGL (low potential signal) is transmitted to the second node N2 through the fifth transistor T5 and the sixth transistor T6; the low potential of the second node N2 is transmitted to the gate of the twelfth transistor T12 through the normally-on fifteenth transistor T15, so that the twelfth transistor T12 is turned on and transmits the first potential signal VGH (high potential signal) to the output terminal OUT of the shift register. That is, in the first stage, the potential signals of the first node N1 and the second node N2 are both low-potential signals, and accordingly, the eleventh transistor T11 and the twelfth transistor T12 are both turned on, the eleventh transistor T11 transmits the high-potential second clock signal CK2 to the output terminal OUT of the shift register, and the twelfth transistor T12 transmits the first potential signal VGH (high-potential signal) to the output terminal OUT of the shift register.

[0084] In the second stage t2, the start signal SIN is high, the first clock signal CK1 is high, and the second clock signal CK2 is low. The first transistor T1, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off in response to the high first clock signal CK1. Due to the storage and retention of the first capacitor C1, the gate potential of the eleventh transistor T11 remains low in the first stage, and accordingly, the first node N1 is low. The fourth transistor T4 is turned on in response to the low first node N1, and the high first clock signal CK1 is transmitted to the second node N2 through the fourth transistor T4 and to the gate of the twelfth transistor T12 through the always-on fifteenth transistor T15, so that the twelfth transistor T12 is turned off. Since the gate of the eleventh transistor T11 remains low in the second stage, the eleventh transistor T11 is turned on in the second stage, and the low second clock signal CK2 is transmitted to the output end OUT of the shift register through the turned-on eleventh transistor T11. Therefore, at the junction time of the first stage t1 and the second stage t2, the output signal of the shift register output end OUT jumps from a high signal to a low signal, and due to the bootstrap effect of the first capacitor C1, the gate of the eleventh transistor T11 is pulled to a lower potential (for example, taking +7v as the high signal and -7v as the low signal, considering the threshold voltage of the transistor itself, the gate potential of the eleventh transistor T11 is -5.3V after the first stage, and due to the jump of the output signal of the shift register and the bootstrap effect of the first capacitor C1, the gate potential of the eleventh transistor T11 is pulled to about -19V after entering the second stage), so that the eleventh transistor T11 quickly opens into the deep linear region, so that the eleventh transistor T11 can quickly output a low signal after entering the second stage t2 and make the low signal well maintained.

[0085] And, after the eleventh transistor T11 transmits the low potential second clock signal CK2 to the output end OUT of the shift register, the thirteenth transistor T13 is turned on in response to the low potential output signal, the low potential second clock signal CK2 is transmitted to the output end OUT of the shift register through the two transistors of the eleventh transistor T11 and the thirteenth transistor T13, thereby facilitating the stability of the output signal. And, in the second stage, the second clock signal CK2 is a low potential signal, the eighth transistor T8 is turned on in response to the low potential second clock signal CK2, and the ninth transistor T9 is turned on in response to the low potential output signal, so that the first potential signal VGH (high potential signal) is transmitted to the second node N2 of the shift register through the turned-on eighth transistor T8 and the ninth transistor T9, and the high potential signal of the second node N2 is transmitted to the gate of the twelfth transistor T12 through the always-on fifteenth transistor T15, thereby making the eleventh transistor T11 turned on, and when the low potential second clock signal is output, the second node N2 can maintain the high potential signal, thereby ensuring that the twelfth transistor T12 is in a good off state, thereby improving the stability of the output signal.

[0086] From the above analysis of the working process of the first stage t1 and the second stage t2 of the shift register, it can be seen that by pre-lowering the first node N1 to a low potential in the first stage t1, the potential of the first node N1 is further lowered due to the transition of the output signal of the shift register and the bootstrap of the first capacitor C1 after entering the second stage t2, thereby ensuring that the eleventh transistor T11 can be completely opened, ensuring that the output low potential signal can be well maintained, and improving the stability of the output signal.

[0087] In the third stage t3, the start signal SIN is high potential, the first clock signal CK1 is low potential, and the second clock signal CK2 is high potential. The first transistor T1 is turned on in response to the low potential first clock signal CK1, the high potential start signal SIN is transmitted to the first node N1 through the first transistor T1, and is transmitted to the gate of the eleventh transistor T11 through the always-on fourteenth transistor T14, so that the eleventh transistor T11 is turned off. At the same time, the fourth transistor T4 and the fifth transistor T5 are turned off in response to the high potential of the first node N1. The seventh transistor T7 is turned on in response to the low potential first clock signal CK1, transmits the second potential signal VGL (low potential signal) to the second node N2, and transmits the second potential signal VGL (low potential signal) to the gate of the twelfth transistor T12 through the always-on fifteenth transistor T15, so that the twelfth transistor T12 is turned on in response to the low potential of its own gate and transmits the first potential signal VGH (high potential signal) to the output end OUT of the shift register.

[0088] It should be noted that, at the transition from the second stage t2 to the third stage t3, the first clock signal CK1 jumps from high to low, and the output OUT of the shift register can not jump from low to high in time, so that the first clock signal CK1 and the output OUT of the shift register can be low at the same time, at this time, the tenth transistor T10 is turned on in response to the low first clock signal CK1, and the ninth transistor T9 is turned on in response to the output low signal, so that the second potential signal VGL is transmitted to the second node N2 through the tenth transistor T10 and the ninth transistor T9, and then the potential of the second node N2 is pulled to be very low, so that the twelfth transistor T12 is turned on, and the first potential signal VGH is output through the twelfth transistor T12, so as to ensure that the output OUT of the shift register can be pulled to high in time, thereby facilitating to improve the stability of the output signal.

[0089] In the fourth stage t4, the start signal SIN is high, the first clock signal CK1 is high, and the second clock signal CK2 is low. The first transistor T1, the sixth transistor T6, the seventh transistor T7 and the tenth transistor T10 are turned off in response to the high first clock signal CK1. Due to the holding effect of the second capacitor C2, the gate of the twelfth transistor T12 keeps the low potential in the third stage t3, and the twelfth transistor T12 keeps the conductive state, and the first potential signal VGH (high potential signal) is transmitted to the output OUT of the shift register. The ninth transistor T9 is turned off in response to the high potential signal output by the shift register. The second transistor T2 is turned on in response to the low potential of the second node N2, and the third transistor T3 is turned on in response to the low second clock signal CK2. The first potential signal VGH (high potential signal) is transmitted to the first node N1 through the turned-on second transistor T2 and the turned-on third transistor T3, and is transmitted to the gate of the eleventh transistor T11 through the always-on fourteenth transistor T14, so that the eleventh transistor T11 keeps the off state.

[0090] The embodiment of the present application also provides a gate drive circuit, Figure 11 is a structural schematic diagram of a gate drive circuit provided by the embodiment of the present application, referring to Figure 11 The gate drive circuit comprises a plurality of shift registers 100 in any of the above embodiments.

[0091] The gate drive circuit of the embodiment has the beneficial effects of the shift register in any of the above embodiments of the present application, which will not be repeated here.

[0092] Note that the above merely describes preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, modifications and substitutions can be made without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A shift register, characterized by, The application relates to a shift register, which comprises: a first output control module, a second output control module, a first output module and a second output module; the first output control module is used for controlling the transmission of a start signal and a first potential signal to a first node according to a first clock signal, a second clock signal and the potential of a second node, wherein the first node is electrically connected with the control end of the first output module, and the second node is electrically connected with the control end of the second output module; the second output control module comprises a first output control unit and a second output control unit, the first output control unit is used for controlling the transmission of the first clock signal and a second potential signal to the second node according to the first clock signal and the potential of the first node, and the second output control unit is used for controlling the transmission of the first potential signal to the second node according to the second clock signal and the output signal of the output end of the shift register; the first output module is used for controlling the transmission of the second clock signal to the output end of the shift register according to the potential of the control end of the first output module; the second output module is used for controlling the transmission of the first potential signal to the output end of the shift register according to the potential of the control end of the second output module; the first output control module comprises a third output control unit and a fourth output control unit; the third output control unit is used for controlling the transmission of the start signal to the first node according to the first clock signal; the fourth output control unit is used for controlling the transmission of the first potential signal to the first node according to the second clock signal and the potential of the second node.

2. The shift register of claim 1, wherein, the third output control unit comprises a first transistor, the gate of the first transistor is connected with the first clock signal, the first pole of the first transistor is connected with the start signal, and the second pole of the first transistor is connected with the first node; the fourth output control unit comprises a second transistor and a third transistor, the gate of the second transistor is electrically connected with the second node, the first pole of the second transistor is connected with the first potential signal, and the second pole of the second transistor is electrically connected with the first pole of the third transistor; the gate of the third transistor is connected with the second clock signal, and the second pole of the third transistor is electrically connected with the first node.

3. The shift register of claim 1, wherein, the first output control unit comprises a first output control subunit, a second output control subunit and a third output control subunit; the first output control subunit is used for controlling the transmission of the first clock signal to the second node according to the potential of the first node; the second output control subunit is used for controlling the transmission of the second potential signal to the second node according to the first clock signal and the potential of the first node; the third output control subunit is used for controlling the transmission of the second potential signal to the second node according to the first clock signal.

4. The shift register of claim 3, wherein, the first output control subunit comprises a fourth transistor, the gate of the fourth transistor is electrically connected with the first node, the first pole of the fourth transistor is connected with the first clock signal, and the second pole of the fourth transistor is electrically connected with the second node. The second output control subunit comprises a fifth transistor and a sixth transistor, a gate of the fifth transistor is electrically connected with the first node, a first pole of the fifth transistor is connected with the second potential signal, and a second pole of the fifth transistor is electrically connected with a first pole of the sixth transistor; a gate of the sixth transistor is connected with the first clock signal, and a second pole of the sixth transistor is electrically connected with the second node; The third output control subunit comprises a seventh transistor, a gate of the seventh transistor is connected with the first clock signal, a first pole of the seventh transistor is connected with the second potential signal, and a second pole of the seventh transistor is electrically connected with the second node.

5. The shift register of claim 1, wherein, The second output control unit comprises an eighth transistor and a ninth transistor, a gate of the eighth transistor is connected with the second clock signal, a first pole of the eighth transistor is connected with the first potential signal, and a second pole of the eighth transistor is electrically connected with a first pole of the ninth transistor; a gate of the ninth transistor is electrically connected with an output end of the shift register, and a second pole of the ninth transistor is electrically connected with the second node.

6. The shift register of claim 5, wherein, The second output control unit is further configured to control transmission of the second potential signal to the second node according to the first clock signal and the output signal.

7. The shift register of claim 5, wherein, The second output control unit further comprises a tenth transistor, a gate of the tenth transistor is connected with the first clock signal, a first pole of the tenth transistor is connected with the second potential signal, and a second pole of the tenth transistor is electrically connected with a first pole of the ninth transistor.

8. The shift register of claim 1, wherein, The first output module comprises an eleventh transistor and a first capacitor; a gate of the eleventh transistor is used as a control end of the first output module, a first pole of the eleventh transistor is connected with the second clock signal, and a second pole of the eleventh transistor is electrically connected with the output end of the shift register; a first end of the first capacitor is electrically connected with the gate of the eleventh transistor, and a second end of the first capacitor is electrically connected with the second pole of the eleventh transistor.

9. The shift register of claim 1, wherein, The second output module further comprises a twelfth transistor and a second capacitor, a gate of the twelfth transistor is electrically connected with the second node, a first pole of the twelfth transistor is connected with the first potential signal, and a second pole of the twelfth transistor is electrically connected with the output end of the shift register.

10. The shift register of claim 8, wherein, The first output module further comprises a thirteenth transistor, a gate of the thirteenth transistor is electrically connected with the output end of the shift register, a first pole of the thirteenth transistor is connected with the second clock signal, and a second pole of the thirteenth transistor is electrically connected with the output end of the shift register.

11. A gate drive circuit, characterized by comprising: The application further provides a shift register comprising a plurality of stages of the shift register according to any one of claims 1-10, and the shift registers are connected in cascade.

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