A data sampling circuit and a semiconductor memory

Abstract

An embodiment of the present application provides a data sampling circuit and a semiconductor memory. The data sampling circuit includes: a frequency division circuit for receiving a first data sampling signal and performing frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with a phase; a sampling circuit for receiving the plurality of second data sampling signals and a first data signal, and performing sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with a phase; and a selection circuit for receiving preamble information and mode register setting information, and respectively performing selection processing on the plurality of second data sampling signals and the plurality of second data signals according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal. In this way, not only can the phase information be accurately identified, but also the bit error rate of the DRAM product can be quickly detected.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and particularly to a data sampling circuit and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technologies, when manufacturing and using devices such as computers, people have put forward higher and higher requirements for data transmission speeds. To obtain faster data transmission speeds, a series of devices such as memories that can transmit data at double data rate (DDR) have emerged.

[0003] In a dynamic random access memory (DRAM), for the DRAM, a loopback function has been proposed at present to quickly detect the bit error rate of DRAM products. Summary of the Invention

[0004] This application provides a data sampling circuit and a semiconductor memory, which can not only accurately identify phase information, but also quickly detect the bit error rate of DRAM products.

[0005] In a first aspect, an embodiment of this application provides a data sampling circuit, which includes a frequency division circuit, a sampling circuit, and a selection circuit; wherein,

[0006] The frequency division circuit is configured to receive a first data sampling signal, and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases;

[0007] The sampling circuit is configured to receive a plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases;

[0008] The selection circuit is configured to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal.

[0009] In some embodiments, the plurality of second data sampling signals include: a second data sampling signal associated with a first phase, a second data sampling signal associated with a second phase, a second data sampling signal associated with a third phase, and a second data sampling signal associated with a fourth phase;

[0010] The plurality of second data signals include: a second data signal associated with a first phase, a second data signal associated with a second phase, a second data signal associated with a third phase, and a second data signal associated with a fourth phase.

[0011] In some embodiments, the first phase is 0 degrees, the second phase is 90 degrees, the third phase is 180 degrees, and the fourth phase is 270 degrees.

[0012] In some embodiments, the data sampling circuit further includes an enable control circuit, and the enable control circuit is connected to the frequency division circuit; wherein,

[0013] The enable control circuit is configured to receive an initial data sampling signal and a write enable signal, and perform a logical operation on the initial data sampling signal and the write enable signal to obtain a first data sampling signal.

[0014] In some embodiments, the first data sampling signal includes a first positive data sampling signal and a first complementary data sampling signal; wherein,

[0015] The enable control circuit is specifically configured to generate a first positive data sampling signal and a first complementary data sampling signal when the write enable signal is in a first level state; wherein, the phase difference between the first positive data sampling signal and the first complementary data sampling signal is 180 degrees.

[0016] In some embodiments, the initial data sampling signal includes a positive data sampling signal and a complementary data sampling signal, and the phase difference between the positive data sampling signal and the complementary data sampling signal is 180 degrees. The enable control circuit includes a first AND gate and a second AND gate; wherein,

[0017] The first AND gate is configured to receive the positive data sampling signal and the write enable signal, and perform an AND operation on the positive data sampling signal and the write enable signal to obtain a first positive data sampling signal;

[0018] The second AND gate is configured to receive the complementary data sampling signal and the write enable signal, and perform an AND operation on the complementary data sampling signal and the write enable signal to obtain a first complementary data sampling signal.

[0019] In some embodiments, the selection circuit includes a first selection module and a second selection module; wherein,

[0020] The first selection module is configured to receive preamble information and mode register setting information, and perform a selection process on a plurality of second data sampling signals according to the preamble information and the mode register setting information to obtain a target data sampling signal;

[0021] A second selection module, configured to receive preamble information and mode register setting information, and respectively perform selection processing on a plurality of second data signals according to the preamble information and the mode register setting information to obtain a target data signal.

[0022] In some embodiments, the first selection module includes a first selection sub-module and a second selection sub-module; wherein,

[0023] The first selection sub-module is configured to receive preamble information and select, according to the preamble information, a plurality of second data sampling signals to obtain second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence;

[0024] The second selection sub-module is configured to receive mode register setting information and select, according to the mode register setting information, the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence, and use the second data sampling signal corresponding to the selected target phase as the target data sampling signal.

[0025] In some embodiments, the first selection sub-module is specifically configured to, when the preamble information is used to indicate a first preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; or,

[0026] The first selection sub-module is specifically configured to, when the preamble information is used to indicate a second preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; or,

[0027] The first selection sub-module is specifically configured to, when the preamble information is used to indicate a third preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the first phase, the second data sampling signal associated with the second phase, the second data sampling signal associated with the third phase, and the second data sampling signal associated with the fourth phase.

[0028] In some embodiments, the second selection sub-module is specifically configured to, when the value of the mode register setting information is a first value, determine that the target phase is phase A, and use the second data sampling signal corresponding to phase A as the target data sampling signal; or,

[0029] The second selection sub-module is specifically configured to, when the value of the mode register setting information is the second value, determine that the target phase is phase B, and use the second data sampling signal corresponding to phase B as the target data sampling signal; or,

[0030] The second selection sub-module is specifically configured to, when the value of the mode register setting information is the third value, determine that the target phase is phase C, and use the second data sampling signal corresponding to phase C as the target data sampling signal; or,

[0031] The second selection sub-module is specifically configured to, when the value of the mode register setting information is the fourth value, determine that the target phase is phase D, and use the second data sampling signal corresponding to phase D as the target data sampling signal.

[0032] In some embodiments, the second selection module includes a third selection sub-module and a fourth selection sub-module; wherein,

[0033] The third selection sub-module is configured to receive the preamble information and select several second data signals according to the preamble information to obtain the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence;

[0034] The fourth selection sub-module is configured to receive the mode register setting information and select the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence according to the mode register setting information, and use the second data signal corresponding to the selected target phase as the target data signal.

[0035] In some embodiments, the third selection sub-module is specifically configured to, when the preamble information is used to indicate the first preamble mode, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, the second data signal associated with the second phase; or,

[0036] The third selection sub-module is specifically configured to, when the preamble information is used to indicate the second preamble mode, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, the second data signal associated with the second phase; or,

[0037] The third selection sub-module is specifically configured to, when the preamble information is used to indicate the third preamble mode, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the first phase, the second data signal associated with the second phase, the second data signal associated with the third phase, the second data signal associated with the fourth phase.

[0038] In some embodiments, the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the first value, determine the target phase as phase A and use the second data signal corresponding to phase A as the target data signal; or,

[0039] the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the second value, determine the target phase as phase B and use the second data signal corresponding to phase B as the target data signal; or,

[0040] the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the third value, determine the target phase as phase C and use the second data signal corresponding to phase C as the target data signal; or,

[0041] the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the fourth value, determine the target phase as phase D and use the second data signal corresponding to phase D as the target data signal.

[0042] In some embodiments, the first preamble mode is a preamble mode of 2 clock cycles;

[0043] the second preamble mode is a preamble mode of 3 clock cycles;

[0044] the third preamble mode is a preamble mode of 4 clock cycles.

[0045] In some embodiments, the first value is 00, the second value is 01, the third value is 10, and the fourth value is 11.

[0046] In a second aspect, an embodiment of the present application provides a semiconductor memory, including the data sampling circuit according to any one of the first aspect.

[0047] In some embodiments, the semiconductor memory is a DRAM chip.

[0048] In some embodiments, the DRAM chip complies with the DDR5 memory specification.

[0049] The embodiment of the present application provides a data sampling circuit and a semiconductor memory. The data sampling circuit includes a frequency division circuit, a sampling circuit, and a selection circuit. Among them, the frequency division circuit is configured to receive a first data sampling signal and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases. The sampling circuit is configured to receive the plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases. The selection circuit is configured to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal. In this way, after obtaining the plurality of second data sampling signals and the plurality of second data signals, signal selection corresponding to the target phase can be performed according to the preamble information and the mode register setting information, which can not only accurately identify the phase information, but also quickly detect the bit error rate of the DRAM product. Brief Description of the Drawings

[0050] Figure 1 is a schematic structural diagram of the composition of a data sampling circuit;

[0051] Figure 2 is a schematic signal timing diagram of a data sampling circuit;

[0052] Figure 3 is a schematic structural diagram of the composition of a data sampling circuit provided by an embodiment of the present application;

[0053] Figure 4 is a schematic structural diagram of the composition of another data sampling circuit provided by an embodiment of the present application;

[0054] Figure 5 is a schematic structural diagram of the composition of a first selection module provided by an embodiment of the present application;

[0055] Figure 6 is a schematic structural diagram of the composition of a second selection module provided by an embodiment of the present application;

[0056] Figure 7 is a schematic signal timing diagram of a write enable signal and an initial data sampling signal under different preamble modes provided by an embodiment of the present application;

[0057] Figure 8 is a schematic signal timing diagram of a data sampling circuit provided by an embodiment of the present application;

[0058] Figure 9 is a schematic structural diagram of the composition of yet another data sampling circuit provided by an embodiment of the present application;

[0059] Figure 10 It is a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present application. Specific implementation manners

[0060] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that for the convenience of description, only the parts related to the related application are shown in the drawings.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0062] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0063] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0064] Before further elaborating on the embodiments of the present application, the nouns and terms involved in the embodiments of the present application will be described. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations:

[0065] Dynamic Random Access Memory (DRAM)

[0066] Synchronous Dynamic Random Access Memory (SDRAM)

[0067] Double Data Rate (DDR)

[0068] Fourth Generation DDR (4th DDR, DDR4)

[0069] Fifth Generation DDR (5th DDR, DDR5)

[0070] Central Processing Unit (CPU)

[0071] Clock Dividers (CLK DIV)

[0072] Column Address Strobe Write Latency (CWL)

[0073] Mode Register Set (MRS)

[0074] With the rapid development of semiconductor processes, the transmission rate of signals is getting faster and faster; moreover, with the continuous improvement of the CPU processing power, the requirements for the speed and capacity of DDR are also constantly increasing, and currently DDR5 has emerged. Among them, the highest rate of DDR5 is expected to reach 8.4 GT / s, which is twice the highest rate of DDR4; at the same time, the operating voltage has been reduced from 1.2 V to 1.1 V, which means that while the performance of DDR5 is improved, the power consumption is further reduced.

[0075] In addition, compared with DDR4, DDR5 also newly adds a Loopback function. Specifically, in DDR5 products, there is an RCD interface that can output data after equalization processing; during testing, this RCD interface can be used to compare the input signal with the signal output by the last RCD interface, so as to obtain the bit error rate of the entire system. That is to say, in DDR5 products, through the Loopback function, the bit error rate of DDR5 products can be quickly detected.

[0076] See Figure 1 , which shows a schematic diagram of the composition structure of a data sampling circuit. As Figure 1As shown, the data sampling circuit may include a clock divider 11, a first data sampler 12, a first selector (MUX1) 13, a second selector (MUX2) 14, and a second data sampler 15. Among them, the two input signals of the clock divider 11 are a forward data sampling signal (represented by DQS_T) and a reverse data sampling signal (represented by DQS_B), and the phase difference between the DQS_T signal and the DQS_B signal is 180 degrees. After the DQS_T signal and the DQS_B signal are frequency-divided by the clock divider 11, four data sampling signals with different phases (DQS_I signal, DQS_Q signal, DQS_IB signal, and DQS_QB signal) can be output, specifically including: a data sampling signal at 0 degrees, a data sampling signal at 90 degrees, a data sampling signal at 180 degrees, and a data sampling signal at 270 degrees; then these four data sampling signals with different phases and the initial data signal (represented by DQ) are input to the first data sampler 12, and four data signals with different phases (DTAT_I signal, DATA_Q signal, DATA_IB signal, and DATA_QB signal) can be output through the first data sampler 12, specifically including: a data signal at 0 degrees, a data signal at 90 degrees, a data signal at 180 degrees, and a data signal at 270 degrees; then according to the mode register setting information (i.e., MRS information), the first selector 13 selects the phase of the DQS_I signal, DQS_Q signal, DQS_IB signal, and DQS_QB signal to output a target data sampling signal (represented by DQS_Loopback); and the first selector 14 selects the phase of the DATA_I signal, DATA_Q signal, DATA_IB signal, and DATA_QB signal to output a target data signal (represented by D_Loopback). Further, the DQS_Loopback signal and the D_Loopback signal can also be input to the second data sampler 15, and the D_Loopback signal is sampled by the DQS_Loopback signal to obtain a final data signal (represented by LBDQ) and a final clock signal (represented by LBDQS), and by comparing them with the input signals, the bit error rate can be determined.

[0077] According to Figure 1 the data sampling circuit shown, refer to Figure 2 , which shows a signal timing diagram of a data sampling circuit. As Figure 2As shown, the signal timing relationship between the positive data sampling signal (DQS_T signal) input to the clock divider 11 and the four data sampling signals (DQS_I signal, DQS_Q signal, DQS_IB signal, and DQS_QB signal) with different phases output after passing through the clock divider is provided here. Since the positive data sampling signal can also be regarded as a clock signal, for the clock divider, the period of the four data sampling signals with different phases output after passing through the clock divider is twice the period of the original positive data sampling signal. From Figure 2 it can be seen that there is a phase-opposite relationship between the DQS_I signal and the DQS_IB signal, and there is a phase-opposite relationship between the DQS_Q signal and the DQS_QB signal; moreover, for the positive data sampling signal, at the rising edge of the signal in the first clock cycle, the DQS_I signal is output; at the falling edge of the signal in the first clock cycle, the DQS_Q signal is output; at the rising edge of the signal in the second clock cycle, the DQS_IB signal is output; at the falling edge of the signal in the second clock cycle, the DQS_QB signal is output. In this way, according to the different selections of the first clock cycle of the positive data sampling signal, the phases of the DQS_I signal, DQS_Q signal, DQS_IB signal, and DQS_QB signal are also different. For example, the phases of the DQS_I signal and the DQS_IB signal can be interchanged, and the phases of the DQS_Q signal and the DQS_QB signal can also be interchanged.

[0078] That is to say, due to the existence of the clock divider, although four data sampling signals with different phases can be generated, the existing scheme cannot select the corresponding phase relationship through the MRS information; that is, due to the uncertainty of the phases of the DQS_I signal, DQS_Q signal, DQS_IB signal, and DQS_QB signal, the DQS_I signal and the DQS_IB signal actually output by the clock divider can be interchanged, and the phases of the DQS_Q signal and the DQS_QB signal can also be interchanged.

[0079] Based on this, an embodiment of the present application provides a data sampling circuit, which includes a frequency division circuit, a sampling circuit, and a selection circuit. Among them, the frequency division circuit is used to receive a first data sampling signal and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases; the sampling circuit is used to receive the plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases; the selection circuit is used to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal. In this way, after obtaining the plurality of second data sampling signals and the plurality of second data signals, signal selection corresponding to the target phase can be performed according to the preamble information and the mode register setting information, which not only solves the problem of uncertain phase caused by the clock divider, can accurately identify phase information, but also can quickly detect the bit error rate of DRAM products.

[0080] The following will describe each embodiment of the present application in detail with reference to the accompanying drawings.

[0081] In an embodiment of the present application, refer to Figure 3 , which shows a schematic structural diagram of the composition of a data sampling circuit 30 provided by an embodiment of the present application. As Figure 3 shown, the data sampling circuit 30 may include a frequency division circuit 31, a sampling circuit 32, and a selection circuit 33. Among them,

[0082] The frequency division circuit 31 is used to receive a first data sampling signal and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases;

[0083] The sampling circuit 32 is used to receive the plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases;

[0084] The selection circuit 33 is used to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal.

[0085] It should be noted that in the embodiments of the present application, the data sampling circuit 30 can be used to implement the Loopback function, that is, the data sampling circuit 30 can be regarded as a part of a Loopback function implementation circuit. Here, in order to accurately identify the phase information, in addition to using the mode register setting information for phase selection in the embodiments of the present application, leading information is added to assist in phase selection, so that the final required target data sampling signal and target data signal can be selected.

[0086] It should also be noted that for the frequency division circuit 31, several second data sampling signals output by it, usually four second data sampling signals here, specifically may include: a second data sampling signal associated with the first phase, a second data sampling signal associated with the second phase, a second data sampling signal associated with the third phase, and a second data sampling signal associated with the fourth phase.

[0087] It should also be noted that for the sampling circuit 32, several second data signals output by it, usually four second data signals here, specifically may include: a second data signal associated with the first phase, a second data signal associated with the second phase, a second data signal associated with the third phase, and a second data signal associated with the fourth phase.

[0088] In the embodiments of the present application, the second data sampling signal associated with the first phase can be represented by DQS_I, the second data sampling signal associated with the second phase can be represented by DQS_Q, the second data sampling signal associated with the third phase can be represented by DQS_IB, and the second data sampling signal associated with the fourth phase can be represented by DQS_QB; the second data signal associated with the first phase can be represented by DATA_I, the second data signal associated with the second phase can be represented by DATA_Q, the second data signal associated with the third phase can be represented by DATA_IB, and the second data signal associated with the fourth phase can be represented by DATA_QB.

[0089] In a specific embodiment, the first phase is 0 degrees, the second phase is 90 degrees, the third phase is 180 degrees, and the fourth phase is 270 degrees.

[0090] That is to say, after the first data sampling signal and the first data signal pass through the frequency division circuit 31 and the sampling circuit 32, four second data sampling signals with different phases and four second data signals with different phases can be obtained. Among them, the four second data sampling signals are specifically the DQS_I signal, the DQS_Q signal, the DQS_IB signal, and the DQS_QB signal, and the phases of these four second data sampling signals are in turn: 0 degrees, 90 degrees, 180 degrees, and 270 degrees; the four second data signals are specifically the DATA_I signal, the DATA_Q signal, the DATA_IB signal, and the DATA_QB signal, and the phases of these four second data signals are in turn: 0 degrees, 90 degrees, 180 degrees, and 270 degrees. In other words, the embodiment of the present application can achieve signal frequency division of the first data sampling signal and the first data signal, and the four phases corresponding to the divided signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees.

[0091] In some embodiments, based on Figure 3 the data sampling circuit 30 shown, referring to Figure 4 , the data sampling circuit 30 may further include an enable control circuit 34, and the enable control circuit 34 is connected to the frequency division circuit 31; where

[0092] the enable control circuit 34 is configured to receive an initial data sampling signal and a write enable signal, and perform a logical operation on the initial data sampling signal and the write enable signal to obtain the first data sampling signal.

[0093] In the embodiment of the present application, the first data sampling signal may include a first positive data sampling signal and a first complementary data sampling signal. That is to say, in some embodiments, the enable control circuit 34 is specifically configured to generate a first positive data sampling signal and a first complementary data sampling signal when the write enable signal is in a first level state.

[0094] It should be noted that in the embodiment of the present application, the first level state is a high level state, and the second level state is a low level state. For the write enable signal, the write enable signal can be represented by IWES, which is the internal write enable signal required after the Write Leveling (WL) operation. Here, the Write Leveling operation can adjust the relative position of the first data sampling signal and the clock signal, so that the first data sampling signal is edge-aligned with the clock signal. That is, when the IWES signal is in a high level state, an initial phase state is provided for the frequency division circuit 31, which is convenient for subsequent accurate identification of phase information.

[0095] It should also be noted that in the embodiments of the present application, for the first positive data sampling signal and the first complementary data sampling signal, the phase difference between the first positive data sampling signal and the first complementary data sampling signal is 180 degrees. Correspondingly, for the initial data sampling signal, the initial data sampling signal may include a positive data sampling signal and a complementary data sampling signal, and the phase difference between the positive data sampling signal and the complementary data sampling signal is also 180 degrees.

[0096] Further, in some embodiments, referring to Figure 4 , the enable control circuit 34 may include a first AND gate 341 and a second AND gate 342; wherein,

[0097] The first AND gate 341 is configured to receive the positive data sampling signal and the write enable signal, and perform an AND operation on the positive data sampling signal and the write enable signal to obtain a first positive data sampling signal;

[0098] The second AND gate 342 is configured to receive the complementary data sampling signal and the write enable signal, and perform an AND operation on the complementary data sampling signal and the write enable signal to obtain a first complementary data sampling signal.

[0099] It should be noted that the positive data sampling signal may be represented by DQS_T, and the complementary data sampling signal may be represented by DQS_B.

[0100] That is to say, for the initial data sampling signal, an AND operation may be performed on it and the IWES signal through the first AND gate 341 and the second AND gate 342. When the IWES signal is in the high level state, the obtained first data sampling signal (including the first positive data sampling signal and the first reverse data sampling signal) is provided to the frequency division circuit 31, thereby providing an initial state for the frequency division circuit 31 so that the phase information can be accurately identified according to the preamble information and the mode register setting information subsequently.

[0101] Further, in some embodiments, based on the data sampling circuit 30 shown in Figure 3 , referring to Figure 4 , the selection circuit 33 may further include a first selection module 331 and a second selection module 332; wherein,

[0102] The first selection module 331 is configured to receive the preamble information and the mode register setting information, and perform selection processing on a plurality of second data sampling signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal;

[0103] The second selection module 332 is configured to receive the preamble information and the mode register setting information, and perform selection processing on a plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data signal.

[0104] It should be noted that the first selection module 331 can be represented by MUX1, and the second selection module 332 can be represented by MUX2. In addition, the preamble information can be represented by Preamble Information; the mode register setting information can be represented by MRS information, specifically MR53:OP[6:5]. In the embodiments of the present application, both the target data sampling signal and the target data signal are obtained by making two selections using the preamble information and the mode register setting information.

[0105] Further, for the target data sampling signal, in some embodiments, referring to Figure 5 , the first selection module 331 may include a first selection sub-module 3311 and a second selection sub-module 3312; wherein,

[0106] The first selection sub-module 3311 is configured to receive the preamble information and select several second data sampling signals according to the preamble information to obtain the second data sampling signals corresponding to Phase A, Phase B, Phase C, and Phase D in sequence;

[0107] The second selection sub-module 3312 is configured to receive the mode register setting information and select the second data sampling signals corresponding to Phase A, Phase B, Phase C, and Phase D in sequence according to the mode register setting information, and use the second data sampling signal corresponding to the selected target phase as the target data sampling signal.

[0108] It should be noted that in Figure 5 , the second data sampling signal corresponding to Phase A can be represented by DQS_PhaseA, the second data sampling signal corresponding to Phase B can be represented by DQS_PhaseB, the second data sampling signal corresponding to Phase C can be represented by DQS_PhaseC, and the second data sampling signal corresponding to Phase D can be represented by DQS_PhaseD. Specifically, as Figure 5As shown in the figure, the first selection sub-module 3311 can further include four selectors, namely the first selector, the second selector, the third selector, and the fourth selector. Among them, the inputs of the first selector are the DQS_I signal and the DQS_IB signal, and the output is the DQS_PhaseA signal; the inputs of the second selector are the DQS_Q signal and the DQS_QB signal, and the output is the DQS_PhaseB signal; the inputs of the third selector are the DQS_IB signal and the DQS_I signal, and the output is the DQS_PhaseC signal; the inputs of the fourth selector are the DQS_QB signal and the DQS_Q signal, and the output is the DQS_PhaseD signal. Then, after inputting the DQS_PhaseA signal, the DQS_PhaseB signal, the DQS_PhaseC signal, and the DQS_PhaseD signal into the second selection sub-module 3312, the target data sampling signal finally output in combination with the mode register setting information can be represented by DQS_Loopback.

[0109] That is to say, in the embodiment of the present application, first, selection is performed according to the preamble information to determine the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence; then, selection is performed according to the mode register setting information to determine the target phase, and further the target data sampling signal (i.e., the second data sampling signal corresponding to the target phase) is obtained. It can be seen that the embodiment of the present application can solve the problem of phase uncertainty caused by the clock divider, so as to accurately identify the target phase and the corresponding target data sampling signal.

[0110] Furthermore, in the first selection sub-module 3311, according to different preamble patterns indicated by the preamble information, the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are also different. In the embodiment of the present application, the preamble patterns indicated by the preamble information can include the first preamble pattern, the second preamble pattern, and the third preamble pattern. The second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence under these three preamble patterns will be described respectively below.

[0111] In a possible embodiment, the first selection sub-module 3311 is specifically configured to, when the preamble information is used to indicate the first preamble pattern, determine the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence as: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; or,

[0112] In another possible embodiment, the first selection sub-module 3311 is specifically configured to, when the preamble information is used to indicate the second preamble mode, determine that the second data sampling signals corresponding to phases A, B, C, and D in sequence are: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; or,

[0113] In yet another possible embodiment, the first selection sub-module 3311 is specifically configured to, when the preamble information is used to indicate the third preamble mode, determine that the second data sampling signals corresponding to phases A, B, C, and D in sequence are: the second data sampling signal associated with the first phase, the second data sampling signal associated with the second phase, the second data sampling signal associated with the third phase, and the second data sampling signal associated with the fourth phase.

[0114] It should be noted that the second data sampling signal associated with the first phase can be represented by DQS_I, the second data sampling signal associated with the second phase can be represented by DQS_Q, the second data sampling signal associated with the third phase can be represented by DQS_IB, and the second data sampling signal associated with the fourth phase can be represented by DQS_QB. In this way, under different preamble modes, the phase relationship between phases A, B, C, and D and the second data sampling signals is shown in Table 1.

[0115] Table 1

[0116]

[0117] That is to say, according to the phase relationship shown in Table 1, after determining the preamble mode indicated by the preamble information, the initial state, that is, the second data sampling signal corresponding to phase A, can be determined according to the determined preamble mode. Furthermore, the second data sampling signals corresponding to phases A, B, C, and D in sequence can be determined, so that the target phase and the corresponding target data sampling signal can be accurately identified in combination with the mode register setting information subsequently.

[0118] It should also be noted that in the second selection sub-module 3312, the target phase is different according to different values of the mode register setting information. In the embodiments of the present application, the values of the mode register setting information can include a first value, a second value, a third value, and a fourth value. The target phases and the corresponding target data sampling signals obtained under these four values will be described separately below.

[0119] In a possible embodiment, the second selection sub-module 3312 is specifically configured to, when the value of the mode register setting information is the first value, determine that the target phase is phase A, and use the second data sampling signal corresponding to phase A as the target data sampling signal; or,

[0120] In another possible embodiment, the second selection sub-module 3312 is specifically configured to, when the value of the mode register setting information is the second value, determine that the target phase is phase B, and use the second data sampling signal corresponding to phase B as the target data sampling signal; or,

[0121] In yet another possible embodiment, the second selection sub-module 3312 is specifically configured to, when the value of the mode register setting information is the third value, determine that the target phase is phase C, and use the second data sampling signal corresponding to phase C as the target data sampling signal; or,

[0122] In yet another possible embodiment, the second selection sub-module 3312 is specifically configured to, when the value of the mode register setting information is the fourth value, determine that the target phase is phase D, and use the second data sampling signal corresponding to phase D as the target data sampling signal.

[0123] It should be noted that, in the embodiments of the present application, the first value may be 00, the second value may be 01, the third value may be 10, and the fourth value may be 11. In this way, when the value of the mode register setting information is different, the corresponding relationship between the value and the target phase is shown in Table 2.

[0124] Table 2

[0125]

[0126] Exemplarily, when the value of the mode register setting information is 00, the target phase at this time is phase A, then the second data sampling signal corresponding to phase A is the target data sampling signal; among them, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data sampling signal is the second data sampling signal associated with the third phase, that is, the DQS_IB signal; when the preamble information is used to indicate the third preamble mode, the target data sampling signal is the second data sampling signal associated with the first phase, that is, the DQS_I signal.

[0127] Exemplarily, when the value of the mode register setting information is 01, the target phase at this time is phase B, and then the second data sampling signal corresponding to phase B is the target data sampling signal; wherein, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data sampling signal is the second data sampling signal associated with the fourth phase, that is, the DQS_QB signal; when the preamble information is used to indicate the third preamble mode, the target data sampling signal is the second data sampling signal associated with the second phase, that is, the DQS_Q signal.

[0128] Exemplarily, when the value of the mode register setting information is 10, the target phase at this time is phase C, and then the second data sampling signal corresponding to phase C is the target data sampling signal; wherein, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data sampling signal is the second data sampling signal associated with the first phase, that is, the DQS_I signal; when the preamble information is used to indicate the third preamble mode, the target data sampling signal is the second data sampling signal associated with the third phase, that is, the DQS_IB signal.

[0129] Exemplarily, when the value of the mode register setting information is 11, the target phase at this time is phase D, and then the second data sampling signal corresponding to phase D is the target data sampling signal; wherein, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data sampling signal is the second data sampling signal associated with the second phase, that is, the DQS_Q signal; when the preamble information is used to indicate the third preamble mode, the target data sampling signal is the second data sampling signal associated with the fourth phase, that is, the DQS_QB signal.

[0130] In this way, for a plurality of second data sampling signals, after determining the preamble mode indicated by the preamble information, the initial state, that is, the second data sampling signal corresponding to phase A, can be determined according to the determined preamble mode. Furthermore, the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence can be determined, and then the target phase can be determined according to the value of the mode register setting information, so as to obtain the target data sampling signal; thus, by selecting the target data sampling signal according to the preamble information and the mode register setting information, not only the problem of phase uncertainty caused by the clock divider is solved, the phase information can be accurately identified, but also the error rate of the DRAM product can be quickly detected.

[0131] Furthermore, for the target data signal, in some embodiments, refer to Figure 6 , the second selection module 332 may include a third selection sub-module 3321 and a fourth selection sub-module 3322; wherein,

[0132] The third selection sub-module 3321 is configured to receive preamble information and select a plurality of second data signals according to the preamble information, so as to obtain the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence;

[0133] The fourth selection sub-module 3322 is configured to receive mode register setting information and select the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence according to the mode register setting information, and use the second data signal corresponding to the selected target phase as the target data signal.

[0134] It should be noted that in Figure 6 the second data signal corresponding to phase A can be represented by D_PhaseA, the second data signal corresponding to phase B can be represented by D_PhaseB, the second data signal corresponding to phase C can be represented by D_PhaseC, and the second data signal corresponding to phase D can be represented by D_PhaseD. Specifically, as Figure 6 shown, the third selection sub-module 3321 can further include four selectors, namely the fifth selector, the sixth selector, the seventh selector, and the eighth selector. Among them, the input of the fifth selector is the DATA_I signal and the DATA_IB signal, and the output is the D_PhaseA signal; the input of the sixth selector is the DATA_Q signal and the DATA_QB signal, and the output is the D_PhaseB signal; the input of the seventh selector is the DATA_IB signal and the DATA_I signal, and the output is the D_PhaseC signal; the input of the eighth selector is the DATA_QB signal and the DATA_Q signal, and the output is the D_PhaseD signal. Then, after inputting the D_PhaseA signal, the D_PhaseB signal, the D_PhaseC signal, and the D_PhaseD signal into the fourth selection sub-module 3322, the target data signal finally output in combination with the mode register setting information can be represented by D_Loopback.

[0135] That is to say, in the embodiment of the present application, first, selection is performed according to the preamble information to determine the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence; then, selection is performed according to the mode register setting information to determine the target phase, and further obtain the target data signal (that is, the second data signal corresponding to the target phase). It can be seen that the embodiment of the present application can solve the problem of phase uncertainty caused by the clock divider, so as to accurately identify the target phase and the corresponding target data signal.

[0136] Further, in the third selection sub-module 3321, according to different preamble patterns indicated by the preamble information, the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are also different. In the embodiments of the present application, the preamble patterns indicated by the preamble information may include a first preamble pattern, a second preamble pattern, and a third preamble pattern. The second data signals corresponding to phase A, phase B, phase C, and phase D in sequence under these three preamble patterns will be described separately below.

[0137] In a possible embodiment, the third selection sub-module 3321 is specifically configured to, when the preamble information is used to indicate the first preamble pattern, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, and the second data signal associated with the second phase; or,

[0138] In another possible embodiment, the third selection sub-module 3321 is specifically configured to, when the preamble information is used to indicate the second preamble pattern, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, and the second data signal associated with the second phase; or,

[0139] In still another possible embodiment, the third selection sub-module 3321 is specifically configured to, when the preamble information is used to indicate the third preamble pattern, determine that the second data signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data signal associated with the first phase, the second data signal associated with the second phase, the second data signal associated with the third phase, and the second data signal associated with the fourth phase.

[0140] It should be noted that the second data signal associated with the first phase may be represented by DATA_I, the second data signal associated with the second phase may be represented by DATA_Q, the second data signal associated with the third phase may be represented by DATA_IB, and the second data signal associated with the fourth phase may be represented by DATA_QB. In this way, the phase relationships between phase A, phase B, phase C, and phase D and the second data signals under different preamble patterns are shown in Table 3.

[0141] Table 3

[0142]

[0143] That is to say, according to the phase relationship shown in Table 3, after determining the preamble mode indicated by the preamble information, the initial state can be determined according to the determined preamble mode, that is, the second data signal corresponding to Phase A. Furthermore, the second data signals corresponding to Phase A, Phase B, Phase C, and Phase D can be determined in sequence, so that the target phase and the corresponding target data signal can be accurately identified in combination with the mode register setting information subsequently.

[0144] It should also be noted that in the fourth selection sub-module 3322, the target phase is different according to different values of the mode register setting information. In the embodiment of the present application, the values of the mode register setting information can include a first value, a second value, a third value, and a fourth value. The target phase and the corresponding target data signal obtained under these four values will be described separately below.

[0145] In a possible embodiment, the fourth selection sub-module 3322 is specifically configured to, when the value of the mode register setting information is the first value, determine the target phase as Phase A and use the second data signal corresponding to Phase A as the target data signal; or

[0146] In another possible embodiment, the fourth selection sub-module 3322 is specifically configured to, when the value of the mode register setting information is the second value, determine the target phase as Phase B and use the second data signal corresponding to Phase B as the target data signal; or

[0147] In still another possible embodiment, the fourth selection sub-module 3322 is specifically configured to, when the value of the mode register setting information is the third value, determine the target phase as Phase C and use the second data signal corresponding to Phase C as the target data signal; or

[0148] In still another possible embodiment, the fourth selection sub-module 3322 is specifically configured to, when the value of the mode register setting information is the fourth value, determine the target phase as Phase D and use the second data signal corresponding to Phase D as the target data signal.

[0149] It should be noted that in the embodiment of the present application, the first value can be 00, the second value can be 01, the third value can be 10, and the fourth value can be 11. In this way, when the value of the mode register setting information is different, the corresponding relationship between its value and the target phase is the same as that shown in Table 2 above.

[0150] Exemplarily, when the value of the mode register setting information is 00, the target phase at this time is phase A, and then the second data signal corresponding to phase A is the target data signal; among them, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data signal is the second data signal associated with the third phase, that is, the DATA_IB signal; when the preamble information is used to indicate the third preamble mode, the target data signal is the second data signal associated with the first phase, that is, the DATA_I signal.

[0151] Exemplarily, when the value of the mode register setting information is 01, the target phase at this time is phase B, and then the second data signal corresponding to phase B is the target data signal; among them, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data signal is the second data signal associated with the fourth phase, that is, the DATA_QB signal; when the preamble information is used to indicate the third preamble mode, the target data signal is the second data signal associated with the second phase, that is, the DATA_Q signal.

[0152] Exemplarily, when the value of the mode register setting information is 10, the target phase at this time is phase C, and then the second data signal corresponding to phase C is the target data signal; among them, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data signal is the second data signal associated with the first phase, that is, the DATA_I signal; when the preamble information is used to indicate the third preamble mode, the target data signal is the second data signal associated with the third phase, that is, the DATA_IB signal.

[0153] Exemplarily, when the value of the mode register setting information is 11, the target phase at this time is phase D, and then the second data signal corresponding to phase D is the target data signal; among them, when the preamble information is used to indicate the first preamble mode or the second preamble mode, the target data signal is the second data signal associated with the second phase, that is, the DATA_Q signal; when the preamble information is used to indicate the third preamble mode, the target data signal is the second data signal associated with the fourth phase, that is, the DATA_QB signal.

[0154] In this way, for a plurality of second data signals, after determining the preamble pattern indicated by the preamble information, the initial state can be determined according to the determined preamble pattern, that is, the second data signal corresponding to phase A. Furthermore, the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence can be determined. Then, the target phase can be determined according to the value of the mode register setting information, thereby obtaining the target data signal. Thus, the selection of the target data signal based on the preamble information and the mode register setting information not only solves the problem of phase uncertainty caused by the clock divider, can accurately identify the phase information, but also can quickly detect the bit error rate of the DRAM product.

[0155] Furthermore, in some embodiments, for the three preamble patterns, specifically as follows:

[0156] The first preamble pattern is a preamble pattern of 2 clock cycles;

[0157] The second preamble pattern is a preamble pattern of 3 clock cycles;

[0158] The third preamble pattern is a preamble pattern of 4 clock cycles.

[0159] In the embodiments of the present application, in the first preamble pattern, the preamble pattern of 2 clock cycles may include a static signal of 1 clock cycle and an oscillating signal of 1 clock cycle; in the second preamble pattern, the preamble pattern of 3 clock cycles may include a static signal of 2 clock cycles and an oscillating signal of 1 clock cycle; in the third preamble pattern, the preamble pattern of 4 clock cycles may include a static signal of 2 clock cycles and an oscillating signal of 2 clock cycles.

[0160] For details, see Figure 7 , which shows a signal timing diagram of the write enable signal and the initial data sampling signal in different preamble patterns provided by the embodiments of the present application. As Figure 7 shown, CWL represents the delay time length between the write column address and the data; that is, after the write command operation is sent, it is necessary to wait for the CWL time before the first data arrives. In other words, CWL represents the arrival time of the first data after the write command operation is sent. From Figure 7It can be seen that for the first leading pattern, since it includes a static signal of 1 clock cycle and a oscillating signal of 1 clock cycle, i.e., twpre = 2; when the write enable signal is in the high level state, the initial data sampling signal is provided to the frequency division circuit only, which means that the rising edge of the signal in the first clock cycle is fixed for the frequency division circuit, i.e., the position of the DQS_I signal; then when the first data arrives, at this time it is the DQS_IB signal or the DATA_IB signal; that is, the second data sampling signal corresponding to phase A is the DQS_IB signal, and the second data signal corresponding to phase A is the DATA_IB signal. For the second leading pattern, since it includes a static signal of 2 clock cycles and a oscillating signal of 1 clock cycle, i.e., twpre = 3; when the write enable signal is in the high level state, the initial data sampling signal is also provided to the frequency division circuit only, then when the first data arrives, at this time it is still the DQS_IB signal or the DATA_IB signal; that is, the second data sampling signal corresponding to phase A is the DQS_IB signal, and the second data signal corresponding to phase A is the DATA_IB signal. For the third leading pattern, since it includes a static signal of 2 clock cycles and a oscillating signal of 2 clock cycles, i.e., twpre = 4; when the write enable signal is in the high level state, the initial data sampling signal is also provided to the frequency division circuit only, then when the first data arrives, at this time it is the DQS_I signal or the DATA_I signal; that is, the second data sampling signal corresponding to phase A is the DQS_I signal, and the second data signal corresponding to phase A is the DATA_I signal.

[0161] In this way, according to Figure 7 , not only can a phase relationship table between phase A, phase B, phase C, and phase D and the second data sampling signal as shown in Table 1 be established, but also a phase relationship table between phase A, phase B, phase C, and phase D and the second data signal as shown in Table 3 can be established, so that the target phase and the corresponding target data signal can be accurately identified in combination with the mode register setting information subsequently.

[0162] Exemplarily, referring to Figure 8 , it shows a signal timing diagram of a data sampling circuit 30 provided by an embodiment of the present application. As Figure 8As shown, the DQS signal represents the first data sampling signal, the DQ signal represents the first data signal, and the DQ signal may include D0, D1, D2, D3, D4, D5, D6, D7. Additionally, the four second data sampling signals associated with the phase obtained after the DQS signal passes through the frequency division circuit 31 are the DQS_I signal, the DQS_Q signal, the DQS_IB signal, and the DQS_QB signal respectively; the four second data signals associated with the phase obtained after the DQ signal passes through the sampling circuit 32 are: the DATA_I signal, the DATA_Q signal, the DATA_IB signal, and the DATA_QB signal.

[0163] Here, the clock cycle of the DQS_I signal, the DQS_Q signal, the DQS_IB signal, and the DQS_QB signal becomes twice the clock cycle of the original DQS signal. Then, for the DATA_I signal, its output is D2 and D6; for the DATA_Q signal, its output is D3 and D7; for the DATA_IB signal, its output is D0 and D4; for the DATA_QB signal, its output is D1 and D5.

[0164] Specifically, taking the preamble mode indicated by the preamble information with 3 clock cycles as an example, the initial state can be determined according to this preamble mode, that is, the second data sampling signal corresponding to phase A, which is represented by the DQS_PhaseA signal in Figure 8 At this time, the DQS_PhaseA signal is the DQS_IB signal; then successively, the second data sampling signal corresponding to phase B (represented by the DQS_PhaseB signal) is the DQS_QB signal, the second data sampling signal corresponding to phase C (represented by the DQS_PhaseC signal) is the DQS_I signal, and the second data sampling signal corresponding to phase D (represented by the DQS_PhaseD signal) is the DQS_Q signal. Similarly, for the second data signal corresponding to phase A, it is represented by the D_PhaseA signal in Figure 8 At this time, the D_PhaseA signal is the DATA_IB signal; then successively, the second data signal corresponding to phase B (represented by the D_PhaseB signal) is the DATA_QB signal, the second data signal corresponding to phase C (represented by the D_PhaseC signal) is the DATA_I signal, and the second data signal corresponding to phase D (represented by the D_PhaseD signal) is the DATA_Q signal. That is to say, for the DQS signal / DQ signal output by the DQS / DQ input buffer, after passing through Figure 8After the signal timing of , the DQS phase signal / DQ phase signal can be determined. Here, the DQS phase signal includes the DQS_PhaseA signal, the DQS_PhaseB signal, the DQS_PhaseC signal, and the DQS_PhaseD signal, and the DQ phase signal includes the D_PhaseA signal, the D_PhaseB signal, the D_PhaseC signal, and the D_PhaseD signal.

[0165] Furthermore, according to the mode register setting information, the target data sampling signal can be determined from the DQS_PhaseA signal, the DQS_PhaseB signal, the DQS_PhaseC signal, and the DQS_PhaseD signal, and the target data signal can be determined from the D_PhaseA signal, the D_PhaseB signal, the D_PhaseC signal, and the D_PhaseD signal.

[0166] In addition, after obtaining the target data sampling signal and the target data signal, the target data signal can be resampled using the target data sampling signal to achieve further data alignment. Therefore, in some embodiments, based on the Figure 4 data sampling circuit 30 shown, referring to Figure 9 , the data sampling circuit 30 may further include a target sampler 35; wherein,

[0167] The target sampler 35 is configured to receive the target data sampling signal and the target data signal, and sample the target data signal according to the target data sampling signal to obtain the final data signal and the final clock signal.

[0168] It should be noted that in the embodiments of the present application, the target sampler 35 may be a type of D flip-flop. Here, the D flip-flop may include an input terminal (D), a clock terminal (CK), a first output terminal, and a second output terminal.

[0169] Specifically, for the D flip-flop, the input terminal (D) is used to receive the target data signal, the clock terminal (CK) is used to receive the target data sampling signal, and after internal sampling processing by the D flip-flop, the first output terminal is used to output the final data signal (denoted as LBDQ), and the second output terminal is used to output the final clock signal (denoted as LBDQS). In this way, for DRAM products, comparing the LBDQ signal and the LBDQS signal with the input DQ signal and DQS_T / DQS_B signal can quickly detect the bit error rate of DRAM products.

[0170] In summary, the embodiment of the present application provides a data sampling circuit, which includes a frequency division circuit, a sampling circuit, and a selection circuit. Among them, the frequency division circuit is configured to receive a first data sampling signal and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases. The sampling circuit is configured to receive the plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases. The selection circuit is configured to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal. In this way, after obtaining the plurality of second data sampling signals and the plurality of second data signals, signal selection corresponding to the target phase can be performed according to the preamble information and the mode register setting information, which not only solves the problem of phase uncertainty caused by the clock divider, can accurately identify phase information, but also can quickly detect the bit error rate of DRAM products.

[0171] In another embodiment of the present application, refer to Figure 10 , which shows a schematic structural diagram of a semiconductor memory 100 provided by the embodiment of the present application. As Figure 10 shown, the semiconductor memory 100 may include the data sampling circuit 30 described in any one of the foregoing embodiments.

[0172] In the embodiment of the present application, the semiconductor memory 100 may be a DRAM chip.

[0173] Further, in some embodiments, the DRAM chip complies with the DDR5 memory specification.

[0174] It should be noted that the embodiment of the present application relates to a data sampling circuit 30 in a DDR5 DRAM chip, and this data sampling circuit 30 can implement a loopback function for quickly detecting the bit error rate of DDR5 products.

[0175] Specifically, in the embodiment of the present application, since the semiconductor memory 100 includes the data sampling circuit 30, in this way, after obtaining the plurality of second data sampling signals and the plurality of second data signals, signal selection corresponding to the target phase can be performed according to the preamble information and the mode register setting information, which not only solves the problem of phase uncertainty caused by the clock divider, can accurately identify phase information, but also can quickly detect the bit error rate of DRAM products.

[0176] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

[0177] It should be noted that in this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0178] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0179] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0181] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0182] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A data sampling circuit, characterized in that, The data sampling circuit includes a frequency division circuit, a sampling circuit, and a selection circuit; wherein, the frequency division circuit is configured to receive a first data sampling signal and perform frequency division processing on the first data sampling signal to obtain a plurality of second data sampling signals associated with phases; the sampling circuit is configured to receive the plurality of second data sampling signals and a first data signal, and perform sampling processing on the first data signal according to the plurality of second data sampling signals to obtain a plurality of second data signals associated with phases; the selection circuit is configured to receive preamble information and mode register setting information, and perform selection processing on the plurality of second data sampling signals and the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain a target data sampling signal and a target data signal.

2. The data sampling circuit according to claim 1, wherein the plurality of second data sampling signals include: a second data sampling signal associated with a first phase, a second data sampling signal associated with a second phase, a second data sampling signal associated with a third phase, and a second data sampling signal associated with a fourth phase; the plurality of second data signals include: a second data signal associated with a first phase, a second data signal associated with a second phase, a second data signal associated with a third phase, and a second data signal associated with a fourth phase.

3. The data sampling circuit according to claim 2, wherein the first phase is 0 degrees, the second phase is 90 degrees, the third phase is 180 degrees, and the fourth phase is 270 degrees.

4. The data sampling circuit according to claim 1, wherein The data sampling circuit further includes an enable control circuit, and the enable control circuit is connected to the frequency division circuit; wherein, the enable control circuit is configured to receive an initial data sampling signal and a write enable signal, and perform a logical operation on the initial data sampling signal and the write enable signal to obtain the first data sampling signal.

5. The data sampling circuit according to claim 4, wherein The first data sampling signal includes a first positive data sampling signal and a first complementary data sampling signal; wherein, the enable control circuit is specifically configured to generate the first positive data sampling signal and the first complementary data sampling signal when the write enable signal is in a first level state; wherein, the phase difference between the first positive data sampling signal and the first complementary data sampling signal is 180 degrees.

6. The data sampling circuit according to claim 5, wherein The initial data sampling signal includes a positive data sampling signal and a complementary data sampling signal, and the phase difference between the positive data sampling signal and the complementary data sampling signal is 180 degrees. The enable control circuit includes a first AND gate and a second AND gate; wherein, the first AND gate is configured to receive the positive data sampling signal and the write enable signal, and perform an AND operation on the positive data sampling signal and the write enable signal to obtain the first positive data sampling signal; the second AND gate is configured to receive the complementary data sampling signal and the write enable signal, and perform an AND operation on the complementary data sampling signal and the write enable signal to obtain the first complementary data sampling signal.

7. The data sampling circuit according to claim 3, wherein The selection circuit includes a first selection module and a second selection module; wherein, The first selection module is configured to receive the preamble information and the mode register setting information, and perform selection processing on the plurality of second data sampling signals respectively according to the preamble information and the mode register setting information to obtain the target data sampling signal; The second selection module is configured to receive the preamble information and the mode register setting information, and perform selection processing on the plurality of second data signals respectively according to the preamble information and the mode register setting information to obtain the target data signal.

8. The data sampling circuit according to claim 7, wherein The first selection module includes a first selection sub-module and a second selection sub-module; wherein, The first selection sub-module is configured to receive the preamble information, and perform selection on the plurality of second data sampling signals according to the preamble information to obtain the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence; The second selection sub-module is configured to receive the mode register setting information, and perform selection on the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence according to the mode register setting information, and use the second data sampling signal corresponding to the selected target phase as the target data sampling signal.

9. The data sampling circuit according to claim 8, wherein The first selection sub-module is specifically configured to, when the preamble information is used to indicate a first preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; Or, The first selection sub-module is specifically configured to, when the preamble information is used to indicate a second preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the third phase, the second data sampling signal associated with the fourth phase, the second data sampling signal associated with the first phase, and the second data sampling signal associated with the second phase; Or, The first selection sub-module is specifically configured to, when the preamble information is used to indicate a third preamble mode, determine that the second data sampling signals corresponding to phase A, phase B, phase C, and phase D in sequence are: the second data sampling signal associated with the first phase, the second data sampling signal associated with the second phase, the second data sampling signal associated with the third phase, and the second data sampling signal associated with the fourth phase.

10. The data sampling circuit according to claim 9, wherein The second selection sub-module is specifically configured to, when the value of the mode register setting information is the first value, determine that the target phase is the phase A, and use the second data sampling signal corresponding to the phase A as the target data sampling signal; Or, The second selection sub-module is specifically configured to, when the value of the mode register setting information is the second value, determine that the target phase is the phase B, and use the second data sampling signal corresponding to the phase B as the target data sampling signal; Or, The second selection sub-module is specifically configured to, when the value of the mode register setting information is the third value, determine that the target phase is the phase C, and use the second data sampling signal corresponding to the phase C as the target data sampling signal; Or, The second selection sub-module is specifically configured to, when the value of the mode register setting information is the fourth value, determine that the target phase is the phase D, and use the second data sampling signal corresponding to the phase D as the target data sampling signal.

11. The data sampling circuit according to claim 7, wherein The second selection module includes a third selection sub-module and a fourth selection sub-module; wherein, The third selection sub-module is configured to receive the preamble information, and select the plurality of second data signals according to the preamble information to obtain the second data signals corresponding to the phase A, the phase B, the phase C, and the phase D in sequence; The fourth selection sub-module is configured to receive the mode register setting information, and select the second data signals corresponding to the phase A, the phase B, the phase C, and the phase D in sequence according to the mode register setting information, and use the second data signal corresponding to the selected target phase as the target data signal.

12. The data sampling circuit according to claim 11, wherein The third selection sub-module is specifically configured to, when the preamble information is used to indicate the first preamble mode, determine that the second data signals corresponding to the phase A, the phase B, the phase C, and the phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, the second data signal associated with the second phase; Or, The third selection sub-module is specifically configured to, when the preamble information is used to indicate the second preamble mode, determine that the second data signals corresponding to the phase A, the phase B, the phase C, and the phase D in sequence are: the second data signal associated with the third phase, the second data signal associated with the fourth phase, the second data signal associated with the first phase, the second data signal associated with the second phase; Or, The third selection sub-module is specifically configured to, when the preamble information is used to indicate the third preamble mode, determine that the second data signals corresponding to the phase A, the phase B, the phase C, and the phase D in sequence are: the second data signal associated with the first phase, the second data signal associated with the second phase, the second data signal associated with the third phase, the second data signal associated with the fourth phase.

13. The data sampling circuit according to claim 12, wherein the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the first value, determine that the target phase is the phase A, and use the second data signal corresponding to the phase A as the target data signal; or the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the second value, determine that the target phase is the phase B, and use the second data signal corresponding to the phase B as the target data signal; or the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the third value, determine that the target phase is the phase C, and use the second data signal corresponding to the phase C as the target data signal; or the fourth selection sub-module is specifically configured to, when the value of the mode register setting information is the fourth value, determine that the target phase is the phase D, and use the second data signal corresponding to the phase D as the target data signal.

14. The data sampling circuit according to claim 9, 10, 12 or 13, wherein the first preamble mode is a preamble mode of 2 clock cycles; the second preamble mode is a preamble mode of 3 clock cycles; the third preamble mode is a preamble mode of 4 clock cycles.

15. The data sampling circuit according to claim 10 or 13, wherein the first value is 00, the second value is 01, the third value is 10, and the fourth value is 11.

16. A semiconductor memory, characterized in that, including the data sampling circuit according to any one of claims 1 to 15.

17. The semiconductor memory according to claim 16, wherein, The semiconductor memory is a dynamic random access memory DRAM chip.

18. The semiconductor memory according to claim 17, wherein, The dynamic random access memory DRAM chip complies with the DDR5 memory specification.

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