Active refresh of edge data wordlines for half-circle drain side select gates

Abstract

The invention is entitled "Active refresh of edge data word lines for half-round drain side select gates." The invention provides a memory device and method of operation. The device includes a memory cell connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cell is arranged in a string and configured to hold a threshold voltage corresponding to one of a plurality of data states. The memory device further includes a control device coupled to the plurality of word lines and the string. The control device is configured to identify the at least one edge word line. The control device is further configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line.

Description

TECHNICAL FIELD

[0001] The present application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information related to the technical field of the disclosure and as such is not necessarily prior art.

[0003] Semicircular drain side gate (“SC-SGD”) memory technology provides several advantages, including reduced die size. To produce SC-SGDs, etching techniques are used to cut memory holes, thereby imparting them with a semicircular shape and dividing a block or row into several strings. Depending on the process used to form SC-SGDs, certain inefficiencies can arise. For example, cutting memory holes will remove at least some portions of the SC-SGD, such as a metal layer, that would otherwise shield from electric fields from the channel and / or charge trapping layer. As a result, SC-SGDs can be affected by “adjacent” electric fields, resulting in parasitic transistors leaking along the SC-SGD transistor. In some cases, this results in a sense amplifier incorrectly determining that the SC-SGD is turning on, which can impact certain sensing operations. Furthermore, due to etching variations, some dies can be cut into SGD layers while others can be cut into layers that form dummy word lines. As a result, data retention can be adversely affected due to charge loss in the memory holes comprising SC-SGDs. Accordingly, there is a need for improved non-volatile memory devices and methods of operation. SUMMARY

[0004] This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0005] It is an object of the present disclosure to provide memory devices and methods of operating the memory devices that address and overcome the above-mentioned disadvantages.

[0006] Accordingly, one aspect of the present disclosure is to provide a device comprising a memory cell connected to one of a plurality of word lines, the plurality of word lines comprising at least one edge word line and a plurality of other data word lines. The memory cell is arranged in a string and is configured to hold a threshold voltage corresponding to one of a plurality of data states. The memory device further comprises a control device coupled to the plurality of word lines and the string. The control device is configured to identify the at least one edge word line. The control device is further configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line.

[0007] According to another aspect of the disclosure, a controller in communication with a memory device is also provided, the controller including the memory device having memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and are configured to hold a threshold voltage corresponding to one of a plurality of data states. The controller is configured to identify the at least one edge word line. The controller is further configured to instruct the memory device to periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0008] According to an additional aspect of the disclosure, a method of operating a memory device is provided. The memory device includes memory cells connected to one of a plurality of word lines, the plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and are configured to hold a threshold voltage corresponding to one of a plurality of data states. The method includes the step of identifying the at least one edge word line. The method further includes the steps of periodically applying a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0009] Additional areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The drawings described herein are for illustrative purposes only of selected embodiments and are not intended to limit the scope of the present disclosure.

[0011] Figure 1A Block diagram of an exemplary memory device according to aspects of the disclosure;

[0012] Figure 1B Block diagram of an exemplary control circuit including a program circuit, a count circuit, and a determination circuit according to aspects of the disclosure;

[0013] Figure 2 Illustration of three types of memory architectures utilizing interleaved memory strings according to aspects of the disclosure;

[0014] Figure 3A Cross-sectional view of an exemplary floating gate memory cell in a NAND string according to aspects of the disclosure;

[0015] Figure 3Bshows a cross-sectional view along the contact line shown in Figure 3A

[0016] Figure 4A Figure 4B shows a non-volatile memory in which charge-trapping memory cells use a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner, in accordance with aspects of the present disclosure;

[0017] Figure 5 shows an exemplary block diagram of the sensing block of FIG. 1, in accordance with aspects of the present disclosure;

[0018] Figure 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1, in accordance with aspects of the present disclosure;

[0019] Figure 6B shows an exemplary cross-sectional view of a portion of one of the blocks of Figure 6A

[0020] Figure 6C shows a graph of memory hole diameters in a stack of Figure 6B

[0021] Figure 6D shows a close-up view of a region of a stack of Figure 6B

[0022] Figure 7A shows a schematic plan view of a memory array having a plurality of memory holes, in accordance with aspects of the present disclosure;

[0023] Figure 7B shows a cross-sectional view of a memory array, in accordance with aspects of the present disclosure;

[0024] Figure 8A Figure 8B shows an alternative memory structure without dummy holes, in accordance with aspects of the present disclosure;

[0025] Figure 9 depicts a set of exemplary threshold voltage distributions, in accordance with aspects of the present disclosure;

[0026] Figure 10 shows a cross-sectional top view of a memory hole taken at a drain-side select gate layer and an edge word line layer, in accordance with aspects of the present disclosure;

[0027] Figure 11 shows threshold voltage distributions and corresponding data or memory states for an exemplary memory device before and after a high-temperature data retention test, in accordance with aspects of the present disclosure;​​​​​​

[0028] Figure 12 Another cross-sectional top view showing memory holes taken at a drain side select gate layer, a layer corresponding to one of a plurality of other data word lines, and an edge word line layer, in accordance with aspects of the present disclosure;

[0029] Figure 13 A threshold voltage distribution of memory cells in strings or memory holes connected to memory holes or strings having full circle and half circle drain side select gates and associated with half circle rows and full circle rows after a high temperature data retention test determines that the edge higher data state is substantially less than the edge highest data state threshold after programming, and after reprogramming memory cells associated with at least one edge word line without erasing memory cells associated with at least one edge word line, in accordance with aspects of the present disclosure; and

[0030] Figure 14 Steps of a method of operating a memory device are shown, in accordance with aspects of the present disclosure.

[0031] To facilitate an understanding of this description, like reference characters are used to identify like elements throughout the description and its drawings. It is contemplated that elements disclosed in one embodiment can be advantageous ly employed with other embodiments without specific recitation. DETAILED DESCRIPTION

[0032] In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. In some instances, certain circuitry, structures and techniques have not been described in detail or have been shown only in block diagram form in order not to obscure the present disclosure.

[0033] In general, the present disclosure relates to non-volatile memory devices of the type that are well suited for many applications. The non-volatile memory devices and associated methods of operation of the present disclosure will be described in connection with one or more example embodiments. However, the specific example embodiments disclosed are merely for the purposes of clarity of description and to allow those of ordinary skill in the art to understand and practice the present disclosure. Specifically, example embodiments are provided so that the present disclosure will be thorough and will fully convey the scope of the disclosure to those skilled in the art. Numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. Those skilled in the art will recognize, however, that the embodiments of the present disclosure can be practiced without the specific details, and that example embodiments can be practiced in a variety of different forms and that the scope of the disclosure is not limited to the specific details as described.

[0034] In some memory devices or apparatuses, memory cells are joined to one another, such as in NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) on a drain side of the NAND string connected to a bit line and one or more source-side SG transistors (SGS transistors) on a source side of the NAND string connected to a source line. Further, the memory cells can be arranged with a common control gate line (e.g., word line) that serves as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings, and can also be connected in other ways.

[0035] In 3D memory structures, memory cells can be arranged in stacked vertical strings, where the stack includes alternating conductive layers and dielectric layers. The conductive layers serve as word lines connected to the memory cells. The memory cells can include data memory cells that are eligible to store user data, and dummy memory cells or non-data memory cells that are not eligible to store user data.

[0036] Prior to programming certain non-volatile memory devices, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gates of the erased memory cells. Alternatively, the erase operation removes electrons from the charge-trapping layers.

[0037] Each memory cell can be associated with a data state according to write data in a program command. Based on the data state of that memory cell, the memory cell will remain in an erased state or be programmed to a programmed data state. For example, in a three-bit-per-cell memory device, there are eight data states, including an erased state and programmed states (see, e.g., Figure 9 ).

[0038] During a program operation, the memory cells are programmed according to a word line programming order. For example, the programming can start from the word lines on the source side of the block and progress to the word lines on the drain side of the block. In one approach, the programming of each word line is completed before programming of the next word line. For example, a first word line WL0 is programmed using one or more program pulses until programming is complete. Next, a second word line WL1 is programmed using one or more program pulses until programming is complete, etc. The program pulses can include a set of increasing program voltages that are applied to the word line in a corresponding program cycle or program-verify iteration. A verify operation or phase can be performed after each program voltage to determine whether the memory cells have completed programming. When programming of a memory cell is complete, that memory cell can be inhibited from further programming while programming of other memory cells continues in subsequent program cycles.

[0039] When creating various rows and strings for a memory structure, a cut operation (e.g., a shallow hole etch (SHE)) can be used. This SHE cut can divide a block (in memory) into multiple strings within the block. While the SHE can form / define the strings, the SHE cut can further separate the strings, i.e., cut the edge memory holes in the strings in half (or approximately two equal halves). In this regard, both the SGD and the channel are separated. However, this operation will cut out portions of the memory holes of some rows, resulting in a half-circle drain side select gate (“SC-SGD”). Using the SHE cut operation, the degree / amount / percentage of the cut can vary. Thus, some top-level SGD (“SGDT”) on the SC-SGD are cut to a greater degree than other SGDT. In other words, the amount of material removed from some SC-SGD memory holes can be greater than the amount removed from other SC-SGD memory holes, and can cause the SHE cut to extend down to one or more dummy word line layers. As the SHE cut is closer to the data word lines (i.e., deeper), data retention issues can arise. Thus, described herein are memory systems or devices and corresponding methods of operation that involve refreshing data associated with one or more word lines to improve data retention.

[0040] Aspects of the disclosure can be embodied in the form of apparatuses, systems, methods, or computer program processes. Thus, aspects of the disclosure can be entirely in a hardware embodiment or a software embodiment (including but not limited to firmware, resident software, microcode, etc.), or can be a combination of hardware and software components, generally as can be referred to as a “circuit,” “module,” “device,” or “system.” In addition, aspects of the disclosure can be in the form of computer program processes embodied in one or more non-transitory computer-readable storage media, for example.

[0041] Additionally, various terminology is used herein to refer to particular system components. Different companies may refer to the same or similar components differently, and this document does not intend to distinguish between the different names used by different companies. Such terminology includes the descriptive terms that begin with "module," which refers to a software or hardware component that is implemented to perform a particular function. The implementation of a "module" can be tangible or intangible, separate or integrated, and can be realized using an independently applied software program or code, firmware, operating system, computer program product, or other device. As used herein, the term "code" can include any type of computer instructions, whether software or firmware instructions, one or more procedures, a single activity, or some other type of code. The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other mediums capable of storing, containing, or carrying computer instructions and / or data. Thus, the term "computer program product" as used herein is intended to encompass a computer program that exists permanently or temporarily in machine- readable storage medium, such as on storage media associated with the computer program product or on a memory of a machine that reads the computer program product. Additionally, various terminology is used herein to refer to particular system components. Different companies may refer to the same or similar components differently, and this document does not intend to distinguish between the different names used by different companies. Such terminology includes the descriptive terms that begin with "module," which refers to a software or hardware component that is implemented to perform a particular function. The implementation of a "module" can be tangible or intangible, separate or integrated, and can be realized using an independently applied software program or code, firmware, operating system, computer program product, or other device. As used herein, the term "code" can include any type of computer instructions, whether software or firmware instructions, one or more procedures, a single activity, or some other type of code. The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other mediums capable of storing, containing, or carrying computer instructions and / or data. Thus, the term "computer program product" as used herein is intended to encompass a computer program that exists permanently or temporarily in machine- readable storage medium, such as on storage media associated with the computer program product or on a memory of a machine that reads the computer program product.

[0042] Similarly, for purposes of the present disclosure, the term "component" can refer to any tangible, physical, and non-transitory device that is constructed to perform a function(s) (e.g., a device that is constructed to perform one or more of the techniques described herein). For example, a component can be in the form of a hardware logic circuit that is constructed using custom VLSI circuits, gate arrays, or other integrated circuits, or from a combination of pre-existing semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic devices. Further, a component can also be implemented in programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic components, programmable logic devices, and the like. Additionally, components can be constructed from one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrical communication configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs) and the like. Thus, modules as defined above can in certain embodiments be embodied as or implemented as components, and in some cases the terms module and component can be used interchangeably.

[0043] Where the term "circuit" is used in the present disclosure, it includes one or more electrical and / or electronic components that constitute an electrical current flow path or paths. A circuit can be in the form of a closed loop configuration or an open loop configuration. In a closed loop configuration, the circuit components can provide a return path for electrical current. In contrast, in an open loop configuration, the circuit components therein can be considered to form a circuit, although a return path for electrical current is not included. For example, an integrated circuit is referred to as a circuit whether or not it is grounded as a return path for electrical current. In certain example embodiments, a circuit can include a group of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit can include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and can include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit can include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrical communication configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs) and the like. A circuit can also be implemented as a synthesized circuit with respect to programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic components, and / or programmable logic devices and the like. In other example embodiments, a circuit can include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Thus, modules as defined above can in certain embodiments be embodied as or implemented as circuits.

[0044] It should be appreciated that the exemplary embodiments disclosed herein can include one or more microprocessors and specially- stored computer program instructions that control the one or more microprocessors to implement some, most, or all of the functionality disclosed herein in combination with certain non-processor circuits and other elements. Alternatively, some or all of the functionality can be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), or in field programmable gate arrays (FPGAs), where each function or some combination of functions can be implemented as custom logic. Combinations of these approaches can also be used. In addition, reference below to "a controller" should be construed to include individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field programmable gate array (FPGA), and / or a processor with control software, or combinations thereof.

[0045] Further, as can be used herein, the terms "program" "software", "software application", and the like, refer to a sequence of instructions designed for execution on a computer implemented system. Thus, a "program", "software", "application", "computer program", or "software application" can include a subroutine, a function, a procedure, an object method, an object implementation, a

[0046] Additionally, as can be used herein, the terms "coupled", "coupling", or "coupling" are intended to mean either a direct connection or an indirect connection via another device (or component) and a connection. Thus, if a first device is coupled or coupled to a second device, the connection can be through a direct connection or through an indirect connection via other devices (or components) and connections.

[0047] With respect to the use of terms such as "embodiment", "one embodiment", "exemplary embodiment", "certain embodiments" or other similar terminology, such terminology is intended to indicate that the described feature is present in at least one embodiment of the present disclosure. Thus, the appearance of such phrases in various places throughout this specification is not necessarily intended to refer to the same embodiment of the present disclosure, unless otherwise indicated. Further, the terms "comprising", "having", "including", and their variations are used herein to mean "including but not limited to", and are thus to be construed as open-ended terminology not limiting the scope of the subject process, method, system, article, or apparatus. Additionally, recitation of "means" or "step" plus function recitations are intended to refer to the corresponding structure, material, or acts intended to accomplish the recited function.

[0048] The terms "a," "an," and "the" also refer to "one or more" unless explicitly indicated to the contrary. Moreover, the phrase "at least one of A and B" (where A and B are variables indicating a particular object or attribute) as used herein and / or in the appended claims, means A or B, or both A and B, similar to the phrase "and / or," is used in the same manner in this context. In the case where more than two variables are present, the phrase "at least one of A, B, and C" (where A, B, and C are variables indicating a particular object or attribute) is defined to include A, B, C individually, any combination of A, B, and C in any order (or sub-combinations), and the entirety of A, B, and C.

[0049] Furthermore, as used herein, the term "about" or "approximately" applies to all numeric values, unless otherwise clearly indicated. These terms generally refer to a range of values that one of skill in the art would consider equivalent to the referenced value (e.g., having the same function or result). In certain instances, these terms can include values rounded to the nearest significant figure.

[0050] Furthermore, no implication arises that any or all of the recited items are mutually exclusive and / or mutually inclusive, unless explicitly indicated otherwise. Additionally, as used herein, the term "set" shall be construed to mean "one or more" in accordance with the doctrine of expressio unius, and in the case of "multiple sets," shall be construed to mean "one or more" and / or "a plurality or more" of the plural (multiple), unless otherwise explicitly indicated.

[0051] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. It is recognized that the preceding description has been presented only as an example and is not intended to limit the application in any way. Additional aspects, example embodiments, and features will become apparent to those skilled in the art upon examination of the following detailed description, which is provided herein for illustrative purposes only. Descriptions of elements in each figure can refer to the descriptions of the same or similar elements in one or more of the other figures. Like reference numerals can refer to like elements throughout the figures, including alternative example embodiments of the same.

[0052] Figure 1Ais a block diagram of an example memory device. The memory device 100 can include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuits 128 include a plurality of sense blocks SB1, SB2,..., SBp (sense circuitry) and allow a page of memory cells to be read or programmed in parallel. A controller 122 is typically included in the same memory device 100 (e.g., removable memory card) as one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0053] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 can include one or more arrays of memory cells including a three-dimensional array. The memory structure 126 can include a monolithic three-dimensional memory structure in which multiple levels of memory cells are formed above (rather than in) a single substrate, such as a wafer, without intervening substrates. The memory structure 126 can include any type of non-volatile memory that is integrally formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure 126 can be in a non-volatile memory device having circuitry associated with operation of the memory cells whether the associated circuitry is above the substrate or within the substrate.

[0054] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip level control over internal cache operations, data flow, and timing.

[0055] A storage region 113 can be provided, for example, for programming parameters. The programming parameters can include program voltages, program voltage biases, location parameters indicative of locations of memory cells, contact line connector thickness parameters, verify voltages, etc. The location parameters can indicate locations of memory cells within an entire array of NAND strings, locations of memory cells within a particular group of NAND strings, locations of memory cells on a particular plane, etc. The contact line connector thickness parameters can indicate thicknesses of contact line connectors, substrates or materials making up the contact line connectors, etc.

[0056] On-chip address decoders 114 provide an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module can include drivers for the word lines, SGS transistors, and SGD transistors and source lines. In one approach, the sense blocks can include bit line drivers. SGS transistors are select gate transistors at the source end of the NAND string, and SGD transistors are select gate transistors at the drain end of the NAND string.

[0057] In some embodiments, some of the components can be combined. In various designs, one or more of the components other than memory structure 126 (alone or in combination) can be considered at least one control circuit that is configured to perform the actions described herein. For example, the control circuit can include any one or a combination of control circuit 110, state machine 112, decoders 114 / 132, power control module 116, sense blocks SBb, SB2,... SBp, read / write circuits 128, controller 122, etc.

[0058] The control circuit can include a program circuit configured to perform program and verify operations on a set of memory cells, where the set of memory cells includes memory cells allocated for representing one of a plurality of data states and memory cells allocated for representing another of the plurality of data states, the program and verify operations include a plurality of program and verify iterations, and at each program and verify iteration, the program circuit performs a program on one word line, after which the program circuit applies a verify signal to the one word line. The control circuit can also include a count circuit configured to obtain a count of memory cells that pass a verify test for the one data state. The control circuit can also include a determination circuit configured to determine, based on the count exceeding an amount of a threshold, a particular program and verify iteration of the plurality of program and verify iterations in which to perform a verify test on the another of the plurality of data states for the memory cells allocated for representing the another of the plurality of data states.

[0059] For example, Figure 1B is a block diagram of an example control circuit 150 that includes program circuit 151, count circuit 152, and determination circuit 153.

[0060] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as a ROM 122a and a RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct a number of read errors that occur when the upper tail of the Vth distribution becomes too high. However, in some cases there can be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors occurring.

[0061] The memory devices 122a, 122b include code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions to provide the functionality described herein. Alternatively, or in addition, the processor 122c can access code from the storage devices 126a of the memory structure 126, such as a reserved area of memory cells in one or more word lines. For example, the controller 122 can use the code to access the memory structure 126, such as for program, read, and erase operations. The code can include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller 122 during a boot or startup process and enables the controller 122 to access the memory structure 126. The controller 122 can use the code to control one or more memory structures 126. Upon power up, the processor 122c fetches the boot code from the ROM 122a or the storage devices 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM 122b, it is executed by the processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0062] Generally, the control code can include instructions to perform the functionality described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms, including those discussed further below.

[0063] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0064] In addition to NAND flash memory, other types of non-volatile memory can be used.

[0065] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, nonvolatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetic random access memory ("MRAM") devices, and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in either a NAND or a NOR configuration.

[0066] The memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as resistive-switching or phase-change materials, and optional steering elements, such as diodes or transistors. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0067] Multiple memory elements can be configured such that they are connected in series or such that each element can be individually accessed. By way of non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and SG transistors.

[0068] A NAND memory array can be configured such that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0069] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an x-y directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer on or in which layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. As non-limiting examples, the substrate can comprise a semiconductor, such as silicon.

[0070] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in irregular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0071] A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to a major surface of the substrate).

[0072] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to a major surface of the substrate, i.e., along the y direction), each column having a plurality of memory cells. The columns can be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements, with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0073] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR configurations, as well as ReRAM configurations.

[0074] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array can also have one or more memory levels at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor, such as silicon. In a monolithic three-dimensional array, each memory device level that makes up the array is typically formed on a layer of a lower memory device level of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array can be shared or have intervening layers between the memory device levels.

[0075] A two-dimensional array can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory levels. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0076] Figure 2 Schematics of three types of memory architectures utilizing interleaved memory strings are shown. For example, reference number 201 shows a schematic of a first example memory architecture, reference number 203 shows a schematic of a second example memory architecture, and reference number 205 shows a schematic of a third example memory architecture. In some embodiments, as shown, the memory architectures can include an array of interleaved NAND strings.

[0077] Figure 2 Blocks 200, 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array 126 can include many such blocks 200, 210 of memory. Each example block 200, 210 includes a plurality of NAND strings and corresponding bit lines, e.g., BL0, BL1,... shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD) and a control gate of that drain select gate is connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS) which in turn is connected to a common source line 220. Sixteen word lines, e.g., WL0-WL15, extend between the SGD and the SGS. In some cases, dummy word lines that do not contain user data can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0078] One type of non-volatile memory that can be provided in a memory array is a floating gate memory, such as Figure 3A and Figure 3B floating gate memory of the type shown. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in Figure 4A and Figure 4B charge trapping memory cell stores charge in a non-volatile manner using a non-conductive dielectric material instead of a conductive floating gate. A three layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a finite region. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A split gate configuration can provide a similar cell, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0079] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending over the channel between the source and drain diffusions. Charges for one data bit are located in the dielectric layer adjacent to the drain, and charges for the other data bit are located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0080] Figure 3A Cross-sectional views of exemplary floating gate memory cells 300, 310, 320 in a NAND string are shown. In this figure, the bit line or NAND string direction goes into the page, and the word line direction is from left to right. For example, a word line 324 extends across a NAND string that includes respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each of the memory cells 300, 310, and 320 is in a different respective NAND string. A polysilicon interpoly dielectric (IPD) layer 328 is also shown. The control gates 302, 312, 322 are part of a word line. Figure 3B A cross-sectional view along a contact line connector 329 is provided in

[0081] The control gates 302, 312, 322 wrap around the floating gates 304, 314, 321, increasing the surface contact area between the control gates 302, 312, 322 and the floating gates 304, 314, 321. This results in higher IPD capacitance, resulting in higher coupling ratios, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is little room for the control gates 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 304, 314, 321.

[0082] As an alternative, as shown in FIGS. 4, 5, and 6, planar or flat memory cells 400, 410, 420 have been developed in which the control gates 402, 412, 422 are flat or planar; that is, the control gates do not wrap around the floating gates, and the only contact of the control gates to the charge storage layer 428 is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the ballistic electron transport problem, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming. Figure 4A Figure 4B

[0083] Figure 4A Cross-sectional views of exemplary charge-trapping memory cells 400, 410, 420 in a NAND string are shown. The view is in the word line direction of the memory cells 400, 410, 420 including planar control gates and charge-trapping regions, as a two-dimensional example of the memory cells 400, 410, 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses insulators such as SiN films to store electrons, as compared to floating gate MOSFET technology, which uses conductors such as doped polysilicon to store electrons. For example, a word line 424 extends across a NAND string, which includes respective channel regions 406, 416, 426. Portions of the word line provide control gates 402, 412, 422. IPD layers 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408 are below the word line. Each charge-trapping layer 404, 414, 421 extends continuously in the respective NAND string. The planar configuration of the control gates can be made thinner than the floating gate. In addition, the memory cells can be placed closer together.

[0084] Figure 4B Cross-sectional views of exemplary charge-trapping memory cells 400, 410, 420 in a NAND string are shown. The view is in the word line direction of the memory cells 400, 410, 420 including planar control gates and charge-trapping regions, as a two-dimensional example of the memory cells 400, 410, 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses insulators such as SiN films to store electrons, as compared to floating gate MOSFET technology, which uses conductors such as doped polysilicon to store electrons. For example, a word line 424 extends across a NAND string, which includes respective channel regions 406, 416, 426. Portions of the word line provide control gates 402, 412, 422. IPD layers 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408 are below the word line. Each charge-trapping layer 404, 414, 421 extends continuously in the respective NAND string. The planar configuration of the control gates can be made thinner than the floating gate. In addition, the memory cells can be placed closer together. Figure 4A ​​A cross-sectional view of the structure along the contact line connector 429. The NAND string 430 includes SGS transistor 431, exemplary memory cell 400, 433,... 435, and SGD transistor 436. The vias in the IPD layer 428 in the SGS transistor 431 and the SGD transistor 436 allow the control gate layer 402 and the floating gate layer to be in communication. For example, the control gate layer 402 and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in an N-O-N-O-N configuration.

[0085] The NAND string can be formed on a substrate that includes a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, N-type source / drain diffusion regions sd2, N-type source / drain diffusion regions sd3, N-type source / drain diffusion regions sd4, N-type source / drain diffusion regions sd5, N-type source / drain diffusion regions sd6, and N-type source / drain diffusion regions sd7 are formed in the p-type well. A channel voltage Vch can be applied directly to the channel region of the substrate.

[0086] Figure 5An exemplary block diagram of sensing block SB1 of Figure 1 is shown. In one approach, the sensing block includes a plurality of sensing circuits. Each sensing circuit is associated with a data latch. For example, exemplary sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different respective sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be divided and processed by respective processors in each sensing block. For example, sensing circuit controller 560 in SB1 can communicate with the set of sensing circuits and latches. Sensing circuit controller 560 can include a pre-charge circuit 561 that provides a voltage to each sensing circuit for setting a pre-charge voltage. In one possible approach, the voltage can be provided to each sensing circuit independently, e.g., via a data bus and a local bus. In another possible approach, a common voltage can be provided to each sensing circuit simultaneously. Sensing circuit controller 560 can also include a pre-charge circuit 561, a memory 562, and a processor 563. Memory 562 can store code that can be executed by the processor to perform the functions described herein. These functions can include reading the latches 550b, 551b, 552b, 553b associated with sensing circuits 550a, 551a, 552a, 553a, setting bit values in the latches, and providing a voltage for setting a pre-charge level in a sensing node of sensing circuits 550a, 551a, 552a, 553a. Further exemplary details of sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, 553a are provided below.

[0087] In some embodiments, a memory cell can include a flag register that includes a set of latches storing flag bits. In some embodiments, the number of flag registers can correspond to the number of data states. In some embodiments, one or more flag registers can be used to control the type of verification technique used in verifying a memory cell. In some embodiments, the output of the flag bits can modify the associated logic of a device, such as an address decode circuit, so that a specified block of cells is selected. Bulk operations (e.g., erase operations, etc.) can be performed using the flags set in the flag registers, or a combination of flag registers and address registers, as in implicit addressing, or alternatively by directly addressing with only the address registers.

[0088] Figure 6AA perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. 1. On a substrate are exemplary blocks BLKO, BLKl, BLK2, BLK3 of memory cells (storage elements), and a peripheral region 604 with circuitry for use by the blocks BLKO, BLKl, BLK2, BLK3. For example, the circuitry can include voltage drivers 605 that can be connected to control gate layers of the blocks BLKO, BLKl, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLKO, BLKl, BLK2, BLK3 are commonly driven. The substrate 601 can also carry circuitry below the blocks BLKO, BLKl, BLK2, BLK3, along with one or more lower metal layers that are patterned in conductive paths to carry signals of the circuitry. The blocks BLKO, BLKl, BLK2, BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLKO, BLKl, BLK2, BLK3 includes a stacked region of memory cells, with the stacked, alternating levels representing word lines. In one possible approach, each block BLKO, BLKl, BLK2, BLK3 has an opposite, layered side from which vertical contacts extend upward to the upper metal layers to form connections with the conductive paths. Although four blocks BLKO, BLKl, BLK2, BLK3 are shown as an example, two or more blocks extending in the x-direction and / or the y-direction can be used.

[0089] In one possible approach, a length of a plane in the x-direction represents a direction in which a signal path to a word line extends in the one or more upper metal layers (word line or SGD line direction), and a width of a plane in the y-direction represents a direction in which a signal path to a bit line extends in the one or more upper metal layers (bit line direction). The z-direction represents a height of the memory device.

[0090] Figure 6B A perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. 1. On a substrate are exemplary blocks BLKO, BLKl, BLK2, BLK3 of memory cells (storage elements), and a peripheral region 604 with circuitry for use by the blocks BLKO, BLKl, BLK2, BLK3. For example, the circuitry can include voltage drivers 605 that can be connected to control gate layers of the blocks BLKO, BLKl, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLKO, BLKl, BLK2, BLK3 are commonly driven. The substrate 601 can also carry circuitry below the blocks BLKO, BLKl, BLK2, BLK3, along with one or more lower metal layers that are patterned in conductive paths to carry signals of the circuitry. The blocks BLKO, BLKl, BLK2, BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLKO, BLKl, BLK2, BLK3 includes a stacked region of memory cells, with the stacked, alternating levels representing word lines. In one possible approach, each block BLKO, BLKl, BLK2, BLK3 has an opposite, layered side from which vertical contacts extend upward to the upper metal layers to form connections with the conductive paths. Although four blocks BLKO, BLKl, BLK2, BLK3 are shown as an example, two or more blocks extending in the x-direction and / or the y-direction can be used. Figure 6AAn exemplary cross-sectional view of a portion of one of the blocks BLKO, BLKI, BLK2, BLK3 of the memory device 100. The block includes a stack 610 of alternating conductive layers and dielectric layers. In this example, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1 in addition to the data word line layers (word lines) WLL0 through WLL10. The dielectric layers are labeled DL0 through DL19. In addition, a region of the stack 610 is shown that includes a NAND string NS1 and a NAND string NS2. Each NAND string contains memory holes 618, 619 filled with material that forms memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in more detail in Figure 6D and is discussed in further detail below.

[0091] The stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled slits) 617, 620 can be provided periodically across the stack 610 as interconnects that extend through the stack 610, such as to connect the source line to a particular contact line above the stack 610. The contact line connectors 617, 620 can be used during formation of the word lines and subsequently filled with metal. A portion of a bit line BLO is also shown. A conductive via 621 connects the drain end 615 to BLO.

[0092] Figure 6C A graph of memory hole diameters in a stack of the memory device 100 is shown. The vertical axis is aligned with the stack 610 and shows the width (wMH), e.g., diameter, of the memory hole 618 and the memory hole 619. Figure 6B Figure 6B A graph of memory hole diameters in a stack of the memory device 100 is shown. The vertical axis is aligned with the stack 610 and shows the width (wMH), e.g., diameter, of the memory hole 618 and the memory hole 619. Figure 6A The word line layers WLL0-WLL10 of the memory device 100 are repeated as examples and are at respective heights z0-z10 in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory holes can have a circular cross-section. Due to the etching process, the width of the memory hole can vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, such that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0093] ​Due to the non-uniformity of memory via width, the programming speed, including the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via (e.g., based on the height of the memory cell in the stack). For smaller diameter memory vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define a group of adjacent word lines with a diameter similar to the memory via (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0094] Figure 6D It shows Figure 6B A close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cell MC. Multiple layers may be deposited, for example, along the sidewalls (SW) of memory via 630 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. Word line layers may include a blocking oxide / bulk high-k material 660, a metal blocking layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided within memory via 630. In other methods, some layers within the layer can be in the control gate layer. Additional pillars are similarly formed in different memory vias. These pillars can form pillared active regions (AA) of the NAND string.

[0095] When a data memory cell MC is programmed, electrons are stored in a portion of the charge trapping layer 663 associated with the memory cell MC. These electrons are attracted from the channel 665 into the charge trapping layer 663 and pass through the tunnel layer 664. The Vth of the memory cell MC increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel 665.

[0096] Each memory via 630 may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer 665. The core region of each memory via 630 is filled with the host material, and the multiple annular layers are located between the core region and the word line in each memory via 630.

[0097] The NAND string can be considered to have a floating body channel 665 because the length of the channel 665 is not formed on the substrate. Further, the NAND string is provided by multiple word line layers stacked on top of one another and separated from one another by dielectric layers.

[0098] Figure 7A A schematic plan view of a memory array 700 is shown with a plurality of memory holes 722, which can be chains of vertical memory cells as described herein, and a plurality of dummy holes 705 that do not require a full memory structure. A shallow trench etch or shallow etch feature (SHE) 710 extends through multiple word lines (e.g., five) but not all the way through the chip to electrically isolate adjacent strings from one another. The SHE extends directly through a set of aligned dummy holes 705, thereby preventing those dummy holes 705 from storing data or otherwise being functional memory cells.

[0099] Reference is now made to Figure 8A and 8B There are no dummy holes. Unlike the memory structure 700 of Figure 7A and 7B The SHE 810 is located in the gap between two adjacent rows of memory cells 825 and overlaps with the memory holes 825, thereby forming a working chain with a trench etched into one side of at least the SGD switch at the top of the working memory chain, here shown as a memory hole 825. This configuration greatly improves yield and memory density because all of the memory holes 822, 825 are functional, i.e., fewer memory holes are wasted.

[0100] Unlike the full circular memory holes 822, the memory holes 825 and SGD switches that are partially cut by the SHE 810 have a semi-circular shape, which can be a semicircle or can be larger or smaller than a semicircle. In some cases, the memory holes 825 and SGD switches can be smaller than a semicircle on one side of the SHE 810 and larger than a semicircle on the other side of the SHE 810.

[0101] The memory holes 822, 825 are connected with multiple bit lines 830, labeled as Figure 8A bit lines 0-7 in . For ease of illustration, only eight bit lines 830 are shown. The bit lines 830 extend over the memory holes and are connected to select the memory holes via connection points. The memory holes in each string region are also connected at one end to a SGD switch and at the other end to a SGS switch.

[0102] At the end of a successful program process (with verify), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 9Exemplary threshold voltage Vt distributions corresponding to data states for an array of memory cells are shown when each memory cell stores three bits of data. However, other embodiments can use more or less than three bits of data per memory cell. Figure 9 Eight threshold voltage Vt distributions corresponding to the erase state and the programmed states A-G are shown. In one embodiment, the threshold voltage in the erase state is negative and the threshold voltages in the programmed states A-G are positive.

[0103] However, the threshold voltage in one or more of the programmed states A-G can be negative. Thus, in one embodiment, at least VrA is negative. Other voltages such as VvA, VrB, VvB, etc. can also be negative.

[0104] Between each of the data states is a read reference voltage for reading data from a memory cell. For example, Figure 9 A read reference voltage VrA between the erase state and the A state is shown, as well as VrB between the A state and the B state. By testing whether the threshold voltage of a given memory cell is above or below the respective read reference voltage, the system can determine the state in which the memory cell resides.

[0105] At or near the lower edge of each programmed state is a verify reference voltage. For example, Figure 9 VvA for the A state and VvB for the B state are shown. When programming memory cells to a given state, the system will test whether these memory cells have a threshold voltage greater than or equal to the verify reference voltage.

[0106] As discussed above and returning reference to Figure 8A and Figure 8B The SHE trench 810 can be etched into a portion of the drain side select gate SGD switch. Ideally, the SHE cut or trench 810 only needs to go down to the drain side select gate SGD layer (i.e., SGD1 in Figure 6D ). However, due to process (etching) variations, it can be extremely difficult to consistently and precisely cut to the drain side select gate SGD layer, some dies will be cut to the first dummy word line or layer DD0 (i.e., DWLD0 in Figure 6D ), and some dies are even cut to the second dummy word line or layer DD1 (i.e., DWLD1 in Figure 6D ). When the SHE cut or trench 810 is closer to the data word line (i.e., deeper), the data retention becomes significantly worse. This is due to physical damage to the memory cells near the physical SHE bottom caused by the SHE etch / clean. Figure 10 The left-most portion of the drain side select gate SGD layer ( Figure 10 ) and the edge word line layer ( Figure 10Memory hole (MH) taken at the right-most portion of the cross-sectional top view of the memory hole (MH) in Figure 10 Memory holes with semi-circle drain side select gates SC-SGD are represented with dashed boxes, while other memory holes do not include semi-circle drain side select gates SC-SGD. Figure 11 Threshold voltage distributions and corresponding data or memory states are shown for an exemplary memory device before (plot denoted as 850) and after (plot denoted as 852) a high temperature data retention (HTDR) test. As shown, memory cells of memory holes without semi-circle drain side select gates SC-SGD (i.e., full-circle drain side select gates FC-SGD) and associated with edge word lines exhibit relatively better data retention, while memory cells of memory holes with semi-circle drain side select gates SC-SGD and associated with edge word lines exhibit relatively worse data retention. In other words, memory cells of memory holes with semi-circle drain side select gates SC-SGD lose more charge due to additional SHERIE damage than memory cells of memory holes without semi-circle drain side select gates SC-SGD, but only for edge word lines.

[0107] One solution to the data retention problem resulting from the depth of the SHE trench 810 is to have one or more additional dummy word line layers to avoid this edge word line data retention loss. However, such additional dummy word lines add process cost. Another solution is to introduce a plasma-induced oxidation (PIO) process to recover the RIE damage. This has been proven to be effective in mitigating the edge word line data retention problem, however, it is not a complete fix as some states (e.g., F / G states) can still be contaminated at best. Accordingly, described herein is a memory device (e.g., memory apparatus 100 of

[0108] Accordingly, described herein is a memory device (e.g., memory apparatus 100 of Figure 6D including memory cells (e.g., data memory cells MC and dummy memory cells 682, 683 of Figure 1A the memory device 100 of Figure 6B the data word line layers (word lines) WLL0-WLL10 or Figure 6D WLL10) of Figure 6B the NAND strings NS1 and NS2 of Figure 9). The apparatus also includes a control circuit or apparatus (e.g., one or any combination of a control circuit 110, decoders 114 / 132, power control module 116, sense blocks SBb, SB2,..., SBp, read / write circuits 128, Figure 1A controller 122 of Figure 1B control circuit 150, and / or Figure 5 sensing circuit controller 560 of and / or any combination thereof) coupled to the plurality of word lines and strings. The control apparatus is configured to identify at least one edge word line. The control apparatus is further configured to periodically apply a program voltage to the at least one edge word line to reprogram memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0109] Referring back to Figure 6B , for example, a plurality of word lines (e.g., Figure 6B word line layers (word lines) WLL0-WLL10 of ) and a plurality of dielectric layers (e.g., Figure 6B DL0-DL19 of ) extend horizontally and are stacked on top of each other in an alternating fashion in a stack (e.g., stack 610), and strings (e.g., Figure 6B NAND strings NS1 and NS2 of ) extend vertically through the stack. Memory cells are connected in series between at least one drain side select gate SGD transistor on a drain side of each of the strings and at least one source side select gate transistor on a source side of each of the strings. The at least one drain side select gate SGD transistor is connected to one of a plurality of bit lines (e.g., Figure 6B BL0 of ), and the at least one source side select gate transistor is connected to a source line. Damage to memory cells near the bottom of the SHE trench 810 Figure 8B , Figure 10 and Figure 11 and resulting data retention issues typically penetrate about one or two word lines deeper than the bottom of the SHE trench 810. Fortunately, this data retention issue primarily occurs only on at least one edge word line. Accordingly, in accordance with an aspect, at least one edge word line (e.g., Figure 6B WLL10 of ) is disposed vertically above a plurality of other data word lines (e.g., Figure 6B data word line layers (word lines) WLL0-WLL9 of ) and immediately adjacent to at least one drain side select gate SGD transistor (e.g., Figure 6D 681 of ).

[0110] According to an aspect, the control device is further configured to store data storage information identifying which of the plurality of word lines are at least one edge word line and a plurality of other data word lines. The control device can also store edge information identifying which of the memory cells connected to the plurality of word lines contain data. Thus, the control device can then utilize the data storage information and the edge information to determine whether each of the plurality of word lines of one of the plurality of blocks is at least one edge word line and whether the memory cells connected to the at least one edge word line contain data.

[0111] Figure 12 Another cross-sectional top view of memory holes (MH) (shaded circles in Figure 12 ) taken at the left-most portion of the drain side select gate SGD layer (SGD layer in Figure 12 ), the middle portion of the layer corresponding to one of the plurality of other data word lines (other data word line in Figure 12 ), and the right-most portion of the edge word line layer (edge word line layer in Figure 12 ). As shown, the memory holes or strings are arranged in rows including full circle rows and half circle rows. The half circle rows include memory holes forming strings that are partially cut by the vertically extending SHE trenches in the stack. Thus, the half circle rows of strings have half circle drain side select gates SC-SGD and are shown aligned with the SHE trenches 810 and indicated with a dashed box, while the full circle rows of other memory holes do not include half circle drain side select gates SC-SGD and are indicated with a separate dashed box. If it is desired to reduce system power or current consumption, then only the half circle rows can be refreshed. Thus, according to an aspect, the control device is further configured to apply a suppress bit line voltage to a plurality of the plurality of bit lines coupled to the strings of the full circle rows (indicated as no refresh or refresh in Figure 12 ) while reprogramming the memory cells associated with the at least one edge word line to prevent reprogramming of the memory cells in the strings associated with the full circle rows. The control device is also configured to apply a select bit line voltage (e.g., about 0 volts) to a plurality of the plurality of bit lines coupled to the strings of the half circle rows while reprogramming the memory cells associated with the at least one edge word line to facilitate reprogramming of the memory cells in the strings associated with the half circle rows (indicated as refresh in Figure 12 ). However, the full circle and half circle memory hole rows can be refreshed together, and thus it should be understood that the memory cells in the strings associated with the full circle rows can alternatively be refreshed simultaneously with the memory cells in the strings associated with the half circle rows (i.e., all of the memory cells connected to the at least one edge word line).

[0112] As discussed above, the memory device can also include an error correction code engine 245 ( Figure 1A ) configured to determine and correct errors when reading memory cells. Further, referring back toFigure 9 The possible threshold voltages Vt for each of the memory cells span a threshold window 900. Each of the memory cells is configured to store a plurality of bits. The plurality of data states includes an erase state (e.g., state 0 in Figure 9 ) at a first end 902 of the threshold window 900 and a plurality of programmed data states (e.g., states A, B, C, D, E, F, and G in Figure 9 ) each corresponding to a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state. The plurality of programmed data states includes a highest data state (e.g., state G in Figure 9 ) at a second end 904 of the threshold window opposite the first end 902 and associated with a threshold voltage Vt higher than the threshold voltages Vt associated with the erase state and at least another one of the plurality of programmed data states. Accordingly, according to additional aspects, the control device is further configured to count an edge higher data state quantity of the memory cells associated with the at least one edge word line having a threshold voltage Vt higher than a verify voltage (e.g., VvG in Figure 9 ) corresponding to the highest data state (e.g., state G in Figure 9 ). The control device is also configured to determine whether the edge higher data state quantity is less than an edge highest data state threshold. The control device is additionally configured to, in response to determining that the edge higher data state quantity is less than the edge highest data state threshold, read data of the memory cells associated with the at least one edge word line and generate correction data from the data using the error correction code engine 245. Moreover, the control device uses the correction data while reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0113] According to an aspect, the memory cells include a plurality of blocks. Accordingly, the control device is further configured to determine whether all of the plurality of blocks have been checked for the at least one edge word line in response to triggering the proactive refresh operation. For example, the control device can determine when approximately several months to about 1 year has passed to trigger the proactive refresh or reprogramming. The control device is also configured to end the reprogramming of the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line in response to determining that all of the plurality of blocks have been checked for the at least one edge word line. The control device continues to check one of the plurality of blocks for the at least one edge word line in response to determining that not all of the plurality of blocks have been checked for the at least one edge word line. The control device is also configured to determine whether each of the plurality of word lines of the one of the plurality of blocks is the at least one edge word line and whether the memory cells connected to the at least one edge word line contain data. The control device returns to determining whether all of the plurality of blocks have been checked for the at least one edge word line in response to determining at least one of that each of the plurality of word lines of the one of the plurality of blocks is not the at least one edge word line and that the memory cells connected to the at least one edge word line do not contain data. Further, the control device returns to determining whether all of the plurality of blocks have been checked for the at least one edge word line in response to determining that the edge higher data state amount is not less than the edge higher data state threshold. The control device is additionally configured to return to determining whether all of the plurality of blocks have been checked for the at least one edge word line after reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0114] According to an aspect, the plurality of data states includes a total state amount of the plurality of data states, and the edge highest data state threshold is equal to one divided by the total state amount of the plurality of data states multiplied by a total cell amount of all of the memory cells. For example, referring back to Figure 9 , the plurality of bits includes three bits (i.e., triple level cell (TLC)), which means that the total state amount of the plurality of data states is eight. Accordingly, the plurality of programmed data states can include, in order of increasing magnitude of threshold voltage Vt, a first data state A, a second data state B, a third data state C, a fourth data state D, a fifth data state E, a sixth data state F, and a seventh data state G. Accordingly, the highest data state is the seventh data state G, and the edge highest data state threshold is equal to one divided by eight multiplied by a total cell amount of all of the memory cells.

[0115] Figure 13Threshold voltage Vt distributions 950, 952, 954, 956 of memory cells in strings or memory holes associated with the half circle and full circle rows are shown in the top representation 946 and perspective representation 948. The threshold voltage Vt distributions 950, 952, 954, 956 are shown after programming, after a high temperature data retention test determines that the amount of edge higher data states is significantly less than the edge highest data state threshold (e.g., the state G memory cells are shifted down too much), and after reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line (i.e., reprogramming without erase). As shown, immediately after the programming operation Figure 13 all data or memory states are correctly formed. Then, after the high temperature data retention test Figure 13 (i.e., after baking or a long period of time), the memory cells associated with the memory holes in the half circle SGD rows exhibit more aggressive shifting down than the memory cells associated with the memory holes in the full circle SGD rows. Now, it can be detected whether there is significant shifting down (e.g., by determining whether the amount of edge higher data states is less than the edge highest data state threshold) Figure 13 The threshold voltage Vt distributions 950, 952, 954, 956 can leave enough margin before a true ECC failure, so data can be correctly read out using the ECC engine 245 (data reconstruction). After data reconstruction, the memory cells associated with the at least one edge word line (e.g., the top edge word line, labeled edge data WL in the perspective representation 948) can be reprogrammed without erasing the memory cells associated with the at least one edge word line Figure 13 Thus, the data is fully recovered.

[0116] Referring now to Figure 14 A method of operating a memory device is also provided. As discussed above, a memory device (e.g., the memory device 100 of Figure 1A includes memory cells (e.g., the data memory cells MC and dummy memory cells 682, 683 of Figure 6D connected to one of a plurality of word lines, including at least one edge word line (e.g., the WLL10 of Figure 6B and a plurality of other data word lines (e.g., the data word line tiers (word lines) WLL0-WLL9 of Figure 6B The memory cells are in strings (e.g., the strings 680 of Figure 6Bof the NAND strings NS1 and NS2) and is configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of data states (see, e.g., Figure 9 ). The method includes the step 1000 of triggering an active refresh. The method also includes the step 1002 of identifying at least one edge word line. The method also includes the step 1004 of periodically applying a program voltage to the at least one edge word line to reprogram memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line. Thus, again, the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked on top of one another in an alternating fashion in a stack, the strings extend vertically through the stack, a memory cell is connected in series between at least one drain side select gate SGD transistor located on a drain side of each of the strings and connected to one of the plurality of bit lines and at least one source side select gate transistor located on a source side of each of the strings and connected to a source line, the at least one edge word line is disposed vertically above the plurality of other data word lines and proximate to the at least one drain side select gate SGD transistor.

[0117] As discussed, the memory cells include a plurality of blocks, thus in more detail, the method continues to 1006 of determining whether all of the plurality of blocks have been checked for the at least one edge word line in response to triggering the active refresh operation. The method then includes the step 1008 of ending the reprogramming of the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line in response to determining that all of the plurality of blocks have been checked for the at least one edge word line. The method continues to 1010 of continuing to check one of the plurality of blocks for the at least one edge word line in response to determining that not all of the plurality of blocks have been checked for the at least one edge word line.

[0118] The method additionally includes a step 1012 of determining whether each word line of the plurality of word lines of one of the plurality of blocks is at least one edge word line and whether the memory cells connected to the at least one edge word line contain data. According to an aspect, and as discussed above, information related to whether each word line of the plurality of word lines is at least one edge word line and whether the corresponding memory cells contain data can be stored and / or tracked, for example, by the control device. Thus, the method further includes a step of storing data storage information identifying which of the plurality of word lines are at least one edge word line and a plurality of other data word lines. The method can further include a step of storing edge information identifying which of the memory cells connected to the plurality of word lines contain data. Such steps can be performed, for example, during erase, program, and / or read operations of the memory device. The method continues with a step 1014 of utilizing the data storage information and the edge information when determining whether each word line of the plurality of word lines of one of the plurality of blocks is at least one edge word line and whether the memory cells connected to the at least one edge word line contain data. The method further includes a step 1016 of returning 1006 to determining whether all of the plurality of blocks have been checked for at least one edge word line in response to determining at least one of that each word line of the plurality of word lines of one of the plurality of blocks is not at least one edge word line and that the memory cells connected to the at least one edge word line do not contain data.

[0119] As discussed above, the memory device further includes an error correction code engine 245 configured to determine and correct errors when reading memory cells. Further, referring back to Figure 9 For each of the memory cells, a possible threshold voltage Vt spans a threshold window 900. Each of the memory cells is configured to store a plurality of bits. The plurality of data states includes an erase state (e.g., the erase state in Figure 9 ) at a first end 902 of the threshold window 900 and a plurality of programmed data states (e.g., the states A, B, C, D, E, F, and G in Figure 9 ) each corresponding to a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state. The plurality of programmed data states includes a highest data state (e.g., the state G in Figure 9 ) at a second end 904 of the threshold window opposite the first end 902 and associated with a threshold voltage Vt higher than the threshold voltage Vt associated with the erase state and at least another one of the plurality of programmed data states. Thus, the method further includes a step 1018 of applying a verify voltage (e.g., the verify voltage Vv in Figure 9 ) higher than a verify voltage corresponding to the highest data state (e.g., the state G in Figure 9the edge higher data state quantity is less than the edge highest data state threshold.

[0120] Again, according to an aspect, the plurality of data states includes a total quantity of data states of the plurality of data states, and the edge highest data state threshold is equal to one divided by the total quantity of data states of the plurality of data states multiplied by a total quantity of all memory cells. For example, referring back to Figure 9 , the plurality of bits includes three bits (i.e., triple level cells (TLC)), which means that the total quantity of data states of the plurality of data states is eight. Thus, the plurality of programmed data states can include, in order of increasing magnitude of threshold voltage Vt, a first data state A, a second data state B, a third data state C, a fourth data state D, a fifth data state E, a sixth data state F, and a seventh data state G. Thus, the highest data state is the seventh data state G, and the edge highest data state threshold is equal to one divided by eight multiplied by a total quantity of all memory cells. The method further includes the step 1022 of, in response to determining that the edge higher data state quantity is not less than the edge higher data state threshold, returning 1006 to determining whether all blocks in the plurality of blocks have been checked for the at least one edge word line.

[0121] The next step of the method is 1024: responsive to determining that the edge higher data state amount is less than the edge highest data state threshold, reading data from the memory cells associated with the at least one edge word line (e.g., lower page (LP), middle page (MP), and upper page (UP)) and generating correction data from the data using the error correction code engine 245. In more detail, the method includes the step 1026 of reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line using the correction data. As discussed, the strings are arranged in rows including full circle rows and half circle rows, the half circle rows including memory holes forming the strings that are partially cut by a shallow hole etch extending vertically into the stack. Thus, according to an aspect, the method can further include the step 1028 of applying a suppress bit line voltage to a plurality of the plurality of bit lines coupled to the strings of the full circle rows while reprogramming the memory cells associated with the at least one edge word line to prevent reprogramming of the memory cells in the strings associated with the full circle rows. Further, the method can include the step 1030 of applying a select bit line voltage (e.g., about 0 volts) to a plurality of the plurality of bit lines coupled to the strings of the half circle rows while reprogramming the memory cells associated with the at least one edge word line to facilitate reprogramming of the memory cells in the strings associated with the half circle rows. The method then includes the step 1030 of returning 1006 to determining whether all blocks in the plurality of blocks have been checked for the at least one edge word line after reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

[0122] Advantages of the memory devices and methods disclosed herein include no reliability issues as the refresh or reprogramming does not require any erase operation and only reprograms the memory cells associated with the at least one edge word line. The downshifted memory cells (in the at least one edge word line) swing back to normal with a small threshold voltage Vt reprogramming. Further, as there is only the at least one edge word line (e.g., top edge WL), the reprogramming does not have any “pre-charge” issues, thus the memory cells are easily programmed back without pre-charge / boosting issues. While other solutions such as PIO processes greatly improve the high temperature data retention for the at least one edge word line, further improvement is possible, however, in combination with the PIO processes, there is no need for very frequent refresh or programming (e.g., about several months to about 1 year per refresh). Thus, OPS (on-pitch SGD) techniques become more feasible and do not require additional dummy word lines (thus, process / die cost can be reduced).

[0123] Obviously, modifications and alterations will occur to others upon reading and understanding the preceding specification and are intended to be within the scope of the appended claims. The foregoing description of the implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Various elements or features of a particular implementation are generally not limited to that particular implementation, but are interchangeable with each other, or with other implementations, where applicable, unless otherwise specifically noted. The same can hold true for the description of features or elements within each implementation. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. The disclosure is to be accorded the broadest possible interpretation within the scope of the appended claims, and equivalents thereof.

Claims

1. A memory device, comprising: A memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, wherein the string is arranged in rows including full-circle rows and semi-circle rows. and A control device, coupled to the plurality of word lines and the string, and configured to: Identify the at least one edge character line, and A programming voltage is periodically applied to the at least one edge word line to reprogram the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, wherein periodically applying the programming voltage includes applying a suppressor bit line voltage to a plurality of bit lines among a plurality of bit lines of the string coupled to the full circle row, while reprogramming the memory cell associated with the at least one edge word line to suppress reprogramming of the memory cell in the string associated with the full circle row.

2. The memory device of claim 1, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cell is connected in series between at least one drain-side select gate transistor located on the drain side of each string and connected to one of the plurality of bit lines and at least one source-side select gate transistor located on the source side of each string and connected to the source line, and the at least one edge word line is vertically disposed above the plurality of other data word lines, wherein, Of the plurality of word lines, the at least one edge word line is closest to the at least one drain-side selected gate transistor.

3. The memory device of claim 2, wherein the semicircular row includes memory holes forming the string, the memory holes being partially cut by shallow holes etched vertically into the stack, and wherein, In order to periodically apply the programming voltage, the control device is further configured to: Select bit line voltages are simultaneously applied to multiple bit lines of the string coupled to the semicircular row, while reprogramming the memory cells associated with the at least one edge word line to facilitate the reprogramming of the memory cells in the string associated with the semicircular row.

4. The memory device of claim 1, further comprising an error correction code engine configured to identify and correct errors in reading the memory cells, wherein the possible threshold voltage for each memory cell spans a threshold window, each memory cell is configured to store a plurality of bits, the plurality of data states including an erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least one of the plurality of programming data states, and the control means being further configured to: The amount of higher edge data states associated with the at least one edge word line that have a threshold voltage higher than the verification voltage corresponding to the highest data state is counted; Determine whether the higher edge data state quantity is less than the highest edge data state threshold; In response to determining that the higher data state quantity of the edge is less than the highest data state threshold of the edge, data from the memory cell associated with the at least one edge word line is read and correction data is generated from the data using the error correction code engine; and The correction data is used to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

5. The memory device of claim 4, wherein the memory cell comprises a plurality of blocks, and the control device is further configured to: In response to triggering an active refresh operation, determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; In response to determining that all blocks of the plurality of blocks have been checked for the at least one edge word line, the reprogramming of the memory cell associated with the at least one edge word line is terminated without erasing the memory cell associated with the at least one edge word line; In response to determining that not all blocks in the plurality of blocks have been checked for the at least one edge word line, the check of one of the plurality of blocks continues for the at least one edge word line; Determine whether each word line of the plurality of word lines in one of the plurality of blocks is the at least one edge word line and whether the memory cell connected to the at least one edge word line contains the data; In response to determining that each word line of the plurality of word lines of one of the plurality of blocks is not the at least one edge word line and that the memory cell connected to the at least one edge word line does not contain at least one of the data, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; In response to determining that the edge higher data state quantity is not less than the edge higher data state threshold, a determination is returned as to whether all blocks of the plurality of blocks have been checked for the at least one edge word line; and After reprogramming the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line.

6. The memory device of claim 5, wherein the control device is further configured to: Store data storage information that identifies which of the plurality of word lines are the at least one edge word line and the plurality of other data word lines; The storage identifies edge information of which memory cells among the memory cells connected to the plurality of word lines contain the data; and The data storage information and the edge information are used to determine whether each word line of the plurality of word lines of the one of the plurality of blocks is the at least one edge word line and whether the memory cell connected to the at least one edge word line contains the data.

7. The memory device of claim 4, wherein the plurality of data states includes a total number of states of the plurality of data states.

8. The memory device of claim 7, wherein the plurality of bits comprises three bits, the total number of states of the plurality of data states is eight, the plurality of programming data states include a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state in ascending order of the threshold voltage value, and the highest data state is the seventh data state.

9. A controller for communicating with a memory device, the memory device including memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, wherein the string is arranged in rows including full-circle rows and semi-circle rows, the controller being configured to: Identify the at least one edge word line; and The memory device is instructed to periodically apply a programming voltage to the at least one edge word line to reprogram the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, wherein periodically applying the programming voltage includes applying a suppressor bit line voltage to a plurality of bit lines among a plurality of bit lines coupled to the string of the full-circle row, while reprogramming the memory cell associated with the at least one edge word line to suppress reprogramming of the memory cell in the string associated with the full-circle row.

10. The controller of claim 9, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cells are connected in series between at least one drain-side select-gate transistor located on the drain side of each of the strings and connected to one of the plurality of bit lines and at least one source-side select-gate transistor located on the source side of each of the strings and connected to the source line, and the at least one edge word line is vertically disposed above the plurality of other data word lines, wherein, Of the plurality of word lines, the at least one edge word line is closest to the at least one drain-side selected gate transistor.

11. The controller of claim 10, wherein the semicircular row includes memory holes forming the string, the memory holes being partially cut by shallow holes etched vertically into the stack, wherein, In order to periodically apply the programmed voltage, the controller is further configured to: The memory device is instructed to simultaneously apply a selection bit line voltage to multiple bit lines of the string coupled to the semicircular row, while reprogramming the memory cells associated with the at least one edge word line to facilitate the reprogramming of the memory cells in the string associated with the semicircular row.

12. The controller of claim 9, wherein at least one of the memory device and the controller further comprises an error correction code engine configured to determine and correct errors in reading the memory cells, and wherein the possible threshold voltage for each memory cell spans a threshold window, each memory cell is configured to store a plurality of bits, the plurality of data states including an erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least another programming data state, the controller being further configured to: The memory device is instructed to count the amount of higher edge data states associated with the at least one edge word line that have a threshold voltage higher than the verification voltage corresponding to the highest data state; Determine whether the higher edge data state quantity is less than the highest edge data state threshold; The memory device is instructed to read data from the memory cell associated with the at least one edge word line in response to determining that the higher edge data state quantity is less than the highest edge data state threshold, and to generate correction data from the data using the error correction code engine; and The memory device is instructed to use the correction data while reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

13. The controller of claim 12, wherein the memory unit comprises a plurality of blocks, and the controller is further configured to: In response to triggering an active refresh operation, determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; The memory device is instructed to terminate the reprogramming of the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line in response to determining that all blocks of the plurality of blocks have been checked for the at least one edge word line. The memory device is instructed to continue checking one of the plurality of blocks for the at least one edge word line in response to determining that not all blocks of the plurality of blocks have been checked for the at least one edge word line; Determine whether each word line of the plurality of word lines in one of the plurality of blocks is the at least one edge word line and whether the memory cell connected to the at least one edge word line contains the data; In response to determining that each word line of the plurality of word lines of one of the plurality of blocks is not the at least one edge word line and that the memory cell connected to the at least one edge word line does not contain at least one of the data, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; In response to determining that the edge higher data state quantity is not less than the edge higher data state threshold, a determination is returned as to whether all blocks of the plurality of blocks have been checked for the at least one edge word line; and After reprogramming the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line.

14. A method of operating a memory device, the memory device comprising a memory cell connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines, and arranged in a string and configured to maintain a threshold voltage corresponding to one of a plurality of data states, wherein the string is arranged in rows including full-circle rows and semi-circle rows, the method comprising the steps of: Identify at least one edge word line; as well as A programming voltage is periodically applied to the at least one edge word line to reprogram the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, wherein periodically applying the programming voltage includes applying a suppressor bit line voltage to a plurality of bit lines among a plurality of bit lines of the string coupled to the full circle row, while reprogramming the memory cell associated with the at least one edge word line to suppress reprogramming of the memory cell in the string associated with the full circle row.

15. The method of claim 14, wherein the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked alternately on top of each other in a stack, the strings extend vertically through the stack, the memory cell is connected in series between at least one drain-side select gate transistor located on the drain side of each string and connected to one of the plurality of bit lines and at least one source-side select gate transistor located on the source side of each string and connected to the source line, and the at least one edge word line is vertically disposed above the plurality of other data word lines, wherein, Of the plurality of word lines, the at least one edge word line is closest to the at least one drain-side selected gate transistor.

16. The method of claim 15, wherein the semicircular row includes memory holes forming the string, the memory holes being partially cut by shallow holes etched vertically into the stack, and the method further comprises: Select bit line voltages are simultaneously applied to multiple bit lines of the string coupled to the semicircular row, while reprogramming the memory cells associated with the at least one edge word line to facilitate the reprogramming of the memory cells in the string associated with the semicircular row.

17. The method of claim 14, wherein the memory device further comprises an error correction code engine configured to determine and correct errors in reading the memory cells, and wherein the possible threshold voltage for each memory cell spans a threshold window, each memory cell is configured to store a plurality of bits, the plurality of data states including an erase state at a first end of the threshold window and a plurality of programming data states each corresponding to a threshold voltage higher than the threshold voltage associated with the erase state, the plurality of programming data states including a highest data state at a second end of the threshold window opposite to the first end and associated with a threshold voltage higher than the threshold voltage associated with the erase state and at least one of the plurality of programming data states, the method further comprising the step of: The amount of higher edge data states associated with the at least one edge word line that have a threshold voltage higher than the verification voltage corresponding to the highest data state is counted; Determine whether the higher edge data state quantity is less than the highest edge data state threshold; In response to determining that the higher data state quantity of the edge is less than the highest data state threshold of the edge, data of the memory cell associated with the at least one edge word line is read and correction data is generated from the data using the error correction code engine; as well as The correction data is used to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

18. The method of claim 17, wherein the memory cell comprises a plurality of blocks, and the method further comprises the following steps: In response to triggering an active refresh operation, determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; In response to determining that all blocks of the plurality of blocks have been checked for the at least one edge word line, the reprogramming of the memory cell associated with the at least one edge word line is terminated without erasing the memory cell associated with the at least one edge word line; In response to determining that not all blocks in the plurality of blocks have been checked for the at least one edge word line, the check of one of the plurality of blocks continues for the at least one edge word line; Determine whether each word line of the plurality of word lines in one of the plurality of blocks is the at least one edge word line and whether the memory cell connected to the at least one edge word line contains the data; In response to determining that each word line of the plurality of word lines of one of the plurality of blocks is not the at least one edge word line and that the memory cell connected to the at least one edge word line does not contain at least one of the data, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; In response to determining that the edge higher data state quantity is not less than the edge higher data state threshold, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line; as well as After reprogramming the memory cell associated with the at least one edge word line without erasing the memory cell associated with the at least one edge word line, return to determine whether all blocks of the plurality of blocks have been checked for the at least one edge word line.

19. The method of claim 18, further comprising the step of: Store data storage information that identifies which of the plurality of word lines are the at least one edge word line and the plurality of other data word lines; The storage identifies edge information of which memory cells among the memory cells connected to the plurality of word lines contain the data; as well as When determining whether each word line of the plurality of word lines of one of the plurality of blocks is the at least one edge word line and whether the memory cell connected to the at least one edge word line contains the data, the data storage information and the edge information are used.

20. The method of claim 17, wherein the plurality of data states includes a total number of states of the plurality of data states.

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