Method for manufacturing shallow trench isolation structure and method for manufacturing semiconductor structure
By forming a sacrificial layer on the upper surface and sidewalls of the shallow trench isolation structure, the problem of electrical performance degradation caused by pits in traditional methods is solved, and higher quality semiconductor device fabrication is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-11
- Publication Date
- 2026-03-31
AI Technical Summary
In the semiconductor device manufacturing process, the traditional sacrificial layer is formed only on the surface of the substrate, which causes pits in the edge region of the shallow trench isolation structure, affecting the electrical performance of the device.
A sacrificial layer is formed on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate. An atomic layer deposition process is used to form a silicon oxide layer as a sacrificial layer to cover the sidewalls and upper surface of the initial shallow trench isolation structure and protect it from pit formation when the sacrificial layer is removed.
By covering the sidewalls and top surface of the initial shallow trench isolation structure, pit formation is avoided, gate leakage is prevented, and the electrical performance of the semiconductor device is improved.
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Figure CN115881619B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a shallow trench isolation structure and a method for fabricating a semiconductor structure. Background Technology
[0002] With the continuous improvement of semiconductor process technology, the size of devices is constantly shrinking. After entering the deep submicron scale, the traditional LOCOS (Local Oxidation of Silicon) isolation structure can no longer meet the requirements, and STI (Shallow Trench Isolation) technology has received widespread attention and application.
[0003] In the semiconductor device manufacturing process, after the initial shallow trench isolation structure is formed, a sacrificial layer is formed on the upper surface of the substrate to protect the substrate during subsequent ion implantation. The sacrificial layer needs to be removed after ion implantation. However, the sacrificial layer is only located on the upper surface of the substrate between adjacent shallow trench isolation structures. During the removal of the sacrificial layer on the upper surface of the substrate, a dimpling (Divot) will be generated in the edge region of the upper surface of the shallow trench isolation structure. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for fabricating a shallow trench isolation structure and a method for fabricating a semiconductor structure to address the problem of pits appearing on the edge region of the upper surface of the shallow trench isolation structure.
[0005] To achieve the above objectives, this application provides a method for preparing a shallow trench isolation structure, comprising:
[0006] Provide a base;
[0007] An initial shallow trench isolation structure is formed within the substrate, wherein the initial shallow trench isolation structure isolates multiple spaced active regions within the substrate;
[0008] A sacrificial layer is formed on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate;
[0009] Remove the sacrificial layer to obtain a shallow trench isolation structure.
[0010] The method for fabricating a shallow trench isolation structure disclosed in this application involves forming an initial shallow trench isolation structure within a substrate, and then forming a sacrificial layer on the upper surface and sidewalls of the initial shallow trench isolation structure, as well as on the upper surface of the substrate, to protect the initial shallow trench isolation structure. Compared to the conventional method where the sacrificial layer is only formed on the upper surface of the substrate, the sacrificial layer in this application covers the upper surface and sidewalls of the initial shallow trench isolation structure, as well as the upper surface of the substrate. When the sacrificial layer is removed, no pits are formed at the edges of the sidewalls and upper surface of the initial shallow trench isolation structure, thus obtaining a complete shallow trench isolation structure and avoiding the adverse effects of pit formation on the device.
[0011] In one embodiment, forming a sacrificial layer on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate includes:
[0012] A silicon oxide layer is formed on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate using an atomic layer deposition process as the sacrificial layer.
[0013] In one embodiment, forming the initial shallow trench isolation structure within the substrate includes:
[0014] An isolation stack is formed on the upper surface of the substrate, the isolation stack having an opening;
[0015] Based on the opening, the substrate is etched to form shallow trenches within the substrate;
[0016] A filling medium layer is formed in the shallow trench, the opening, and on the upper surface of the isolation stack;
[0017] The filling medium layer located on the upper surface of the isolation stack, the filling medium layer partially located in the opening, and the isolation stack are removed to obtain the initial shallow trench isolation structure.
[0018] In one embodiment, the isolation stack includes a padding layer and a patterned mask layer; the isolation stack is formed on the upper surface of the substrate, the isolation stack having an opening, including:
[0019] A padding material layer is formed on the upper surface of the substrate;
[0020] A mask layer is formed on the upper surface of the padding material layer;
[0021] A photoresist layer is formed on the upper surface of the mask layer;
[0022] The photoresist layer is exposed and developed to obtain a patterned photoresist layer, the patterned photoresist layer having a first opening;
[0023] The mask layer is etched based on the patterned photoresist layer to obtain the patterned mask layer, the patterned mask layer having a second opening;
[0024] The padding material layer is etched based on the patterned mask layer to obtain the padding layer, the padding layer having a third opening.
[0025] In one embodiment, forming a padding material layer on the upper surface of the substrate includes:
[0026] A silicon oxide layer is formed on the upper surface of the substrate as the padding material layer.
[0027] In one embodiment, forming a mask layer on the upper surface of the padding material layer includes:
[0028] A silicon nitride layer is formed on the upper surface of the padding material layer as the mask layer.
[0029] In one embodiment, forming a filling medium layer within the shallow trench, the opening, and the upper surface of the isolation stack includes:
[0030] An oxide layer is formed in the shallow trench, the opening, and the upper surface of the isolation stack using a high-energy plasma process, serving as the filling medium layer.
[0031] In one embodiment, the filling medium layer has a groove; the removal of the filling medium layer located on the upper surface of the isolation stack, the filling medium layer partially located within the opening, and the isolation stack to obtain the initial shallow trench isolation structure includes:
[0032] Remove the portion of the filling medium layer located outside the groove;
[0033] Remove the filling medium layer located on the upper surface of the isolation stack and part of the filling medium layer located in the opening;
[0034] Remove the isolation stack.
[0035] In one embodiment, before removing the sacrificial layer to obtain the shallow trench isolation structure, the method further includes:
[0036] A barrier layer is formed on the upper surface of the sacrificial layer, the barrier layer having a fourth opening;
[0037] Based on the fourth opening, ion implantation is performed on the substrate to form a lightly doped region within the active region.
[0038] This application also provides a method for fabricating a semiconductor structure, including:
[0039] The shallow trench isolation structure is prepared using the preparation method of the shallow trench isolation structure described in any of the above schemes.
[0040] The semiconductor structure fabrication method of this application uses the shallow trench isolation structure fabrication method of this application to fabricate the shallow trench isolation structure. In this method, an initial shallow trench isolation structure is formed in the substrate, and a sacrificial layer is formed on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate to protect the initial shallow trench isolation structure. Compared with the conventional method where the sacrificial layer is only formed on the upper surface of the substrate, the sacrificial layer of this application covers the upper surface and sidewalls of the initial shallow trench isolation structure and the upper surface of the substrate. When the sacrificial layer is removed, no pits are formed at the edge positions of the sidewalls and upper surface of the initial shallow trench isolation structure, and no pits are formed in the resulting shallow trench isolation structure. This can avoid gate leakage problems caused by pits in related technologies. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 A schematic diagram of the cross-sectional structure when a pit is generated in a conventional semiconductor device;
[0043] Figure 2 This is a flowchart of a method for preparing a shallow trench isolation structure provided in one embodiment;
[0044] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S11 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0045] Figure 4 This is a flowchart of step S12 in the method for preparing a shallow trench isolation structure provided in one embodiment;
[0046] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S1211 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0047] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S1212 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0048] Figure 7This is a schematic cross-sectional view of the structure obtained in step S1213 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0049] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S1214 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0050] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S1215 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0051] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S1216 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0052] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S122 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0053] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S123 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0054] Figure 13 This is a schematic cross-sectional view of the structure obtained in step S1241 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0055] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S1242 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0056] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S1243 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0057] Figure 16 This is a schematic cross-sectional view of the structure obtained in step S13 of the method for preparing a shallow trench isolation structure provided in one embodiment.
[0058] Figure 17 This is a schematic cross-sectional view of the structure obtained by forming a barrier layer on the upper surface of the sacrificial layer in the preparation method of the shallow trench isolation structure provided in one embodiment;
[0059] Figure 18 This is a schematic diagram of the cross-sectional structure of the shallow trench isolation structure fabrication method provided in one embodiment, in which ion implantation is performed on the substrate based on the fourth opening to form a lightly doped region in the active region.
[0060] Figure 19This is a schematic cross-sectional view of the structure obtained in step S14 of the preparation method of the shallow trench isolation structure provided in one embodiment.
[0061] Explanation of reference numerals in the attached figures:
[0062] 1-Substrate; 11-Active region; 12-Lightly doped region; 2-Isolation stack; 20-Opening; 21-Pad layer; 211-Pad material layer; 212-Third opening; 22-Patterned mask layer; 221-Mask layer; 222-Second opening; 3-Patterned photoresist layer; 31-Photoresist layer; 32-First opening; 4-Shallow trench isolation structure; 41-Shallow trench; 42-Initial shallow trench isolation structure; 43-Filling dielectric layer; 431-Groove; 44-Pit; 5-Sacrificial layer; 6-Blocking layer; 61-Fourth opening. Detailed Implementation
[0063] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion.
[0066] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0067] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0068] With continuous improvements in semiconductor process technology, device dimensions are constantly shrinking. Entering the deep submicron scale, traditional LOCOS (Local Oxidation of Silicon) isolation structures can no longer meet the requirements. STI (Shallow Trench Isolation) technology has gained widespread attention and application.
[0069] In conventional semiconductor device manufacturing processes, after forming the initial shallow trench isolation structure, a sacrificial layer is formed on the upper surface of the substrate to protect the substrate during subsequent ion implantation. This sacrificial layer needs to be removed after ion implantation. However, the sacrificial layer is only located on the upper surface of the substrate between adjacent shallow trench isolation structures. Figure 1 As shown, during the removal of the sacrificial layer on the upper surface of the substrate, a pit 44 (Divot) is generated in the edge region of the upper surface of the shallow trench isolation structure. The pit 44 will have an adverse effect on the gate electric field of the semiconductor device, such as causing gate leakage current problems, resulting in a deterioration of the electrical performance of the semiconductor device.
[0070] Therefore, it is necessary to provide a method for fabricating a shallow trench isolation structure, and a method for fabricating a shallow trench isolation structure and a semiconductor structure, to address the problem of pits appearing on the edge region of the upper surface of the aforementioned shallow trench isolation structure.
[0071] like Figure 2 As shown, this application provides a method for fabricating a shallow trench isolation structure, comprising:
[0072] S11: Provides a substrate;
[0073] S12: An initial shallow trench isolation structure is formed in the substrate, which isolates multiple spaced active regions in the substrate.
[0074] S13: A sacrificial layer 5 is formed on the upper surface and sidewalls of the initial shallow trench isolation structure and on the upper surface of the substrate;
[0075] S14: Remove the sacrificial layer to obtain a shallow trench isolation structure.
[0076] The method for fabricating the shallow trench isolation structure in the above embodiments involves forming an initial shallow trench isolation structure within a substrate, and then forming a sacrificial layer on the upper surface and sidewalls of the initial shallow trench isolation structure, as well as on the upper surface of the substrate, to protect the initial shallow trench isolation structure. Compared to the conventional method where the sacrificial layer is only formed on the upper surface of the substrate, the sacrificial layer in this application covers the upper surface and sidewalls of the initial shallow trench isolation structure, as well as the upper surface of the substrate. When the sacrificial layer is removed, pits will not form at the edges of the sidewalls and upper surface of the initial shallow trench isolation structure, thus obtaining a complete shallow trench isolation structure and avoiding pit formation that could adversely affect the device.
[0077] In step S11, please refer to Figure 3 Provides base 1.
[0078] The material of the substrate 1 may include, but is not limited to, silicon carbide or silicon, or other materials, not limited to the examples above.
[0079] In step S12, please refer to Figures 4 to 15 An initial shallow trench isolation structure 42 is formed within the substrate 1, and the initial shallow trench isolation structure 42 isolates multiple spaced active regions 11 within the substrate 1.
[0080] In one embodiment, such as Figure 4 As shown, the initial shallow trench isolation structure 42 formed within the substrate 1 may include:
[0081] S121: An isolation stack 2 is formed on the upper surface of the substrate 1, the isolation stack 2 having an opening 20;
[0082] S122: Etch substrate 1 based on opening 20 to form shallow trench 41 in substrate 1;
[0083] S123: A filling medium layer 43 is formed in the shallow trench 41, the opening 20 and the upper surface of the isolation stack 2;
[0084] S124: Remove the filling medium layer 43 located on the upper surface of the isolation stack 2, the filling medium layer 43 partially located in the opening 20, and the isolation stack 2 to obtain the initial shallow trench isolation structure 42.
[0085] In step S121, please refer to Figures 5 to 10 An isolation stack 2 is formed on the upper surface of the substrate 1, and the isolation stack 2 has an opening 20.
[0086] In one embodiment, the isolation stack 2 includes a padding layer 21 and a patterned mask layer 22; the isolation stack 2 is formed on the upper surface of the substrate 1, and the isolation stack 2 has an opening 20, which may include:
[0087] S1211: A padding material layer 211 is formed on the upper surface of the substrate 1, resulting in the following structure: Figure 5 As shown; wherein, a padding material layer 211 can be formed on the upper surface of the substrate 1 by chemical vapor deposition or atomic layer deposition.
[0088] S1212: A mask layer 221 is formed on the upper surface of the padding material layer 211, resulting in the structure shown below. Figure 6 As shown; wherein, a mask layer 221 can be formed on the upper surface of the pad material layer 211 by chemical vapor deposition or atomic layer deposition.
[0089] S1213: A photoresist layer 31 is formed on the upper surface of the mask layer 221, resulting in the following structure: Figure 7 As shown; wherein, a photoresist layer 31 can be formed on the upper surface of the mask layer 221 by coating method. The photoresist layer 31 may include a positive photoresist layer 31 or a negative photoresist layer 31.
[0090] S1214: Expose and develop the photoresist layer 31 to obtain a patterned photoresist layer 3, the patterned photoresist layer 3 having a first opening 32, the resulting structure as shown. Figure 8 As shown.
[0091] S1215: Based on the patterned photoresist layer 3, the mask layer 221 is etched to obtain the patterned mask layer 22, which has a second opening 222, and the resulting structure is as follows. Figure 9 As shown; wherein, the mask layer 221 can be etched based on the patterned photoresist layer 3 using dry etching or wet etching methods to obtain the patterned mask layer 22, the patterned mask layer 22 can be, but is not limited to, a silicon nitride layer; after etching the mask layer 221 based on the patterned photoresist layer 3, the patterned photoresist layer 3 can be removed using a wet stripping process.
[0092] S1216: Based on the patterned mask layer 22, the pad material layer 211 is etched to obtain the pad layer 21, which has a third opening 212, and the resulting structure is as follows. Figure 10 As shown; wherein, the pad material layer 211 can be etched based on the patterned mask layer 22 using dry etching or wet etching methods to obtain the pad layer 21, which can be, but is not limited to, a silicon dioxide layer.
[0093] Among them, the photoresist layer 31 can be formed on the upper surface of the mask layer 221 by spin coating in the coating method.
[0094] In the above embodiments, a patterned mask layer 22 is obtained based on the patterned photoresist layer 3. The first opening 32 in the patterned photoresist layer 3 has a precise shape and size, so the second opening 222 in the obtained patterned mask layer 22 also has a precise shape and size. The pad material layer 211 is etched based on the patterned mask layer 22 to obtain the pad layer 21, so the third opening 212 also has a precise shape and size.
[0095] In one embodiment, forming a padding material layer 211 on the upper surface of the substrate 1 may include forming a silicon oxide layer on the upper surface of the substrate 1 as the padding material layer 211; that is, the padding material layer 211 may be, but is not limited to, a silicon dioxide layer.
[0096] In one embodiment, forming a mask layer 221 on the upper surface of the padding material layer 211 may include forming a silicon nitride layer as a mask layer 221 on the upper surface of the padding material layer 211; that is, the mask layer 221 may be, but is not limited to, a silicon nitride layer.
[0097] In the above embodiments, if a silicon nitride mask layer is formed directly on the upper surface of the substrate 1, the stress of silicon nitride is very high, and direct deposition on the upper surface of the substrate 1 will cause dislocations on the surface of the substrate 1. Therefore, a pad material layer 211 is needed as a buffer layer. In addition, the pad layer 21 obtained based on the pad material layer 211 also serves as an etching barrier layer when the patterned mask layer 22 is subsequently removed.
[0098] In step S122, please refer to Figure 10 and Figure 11 The substrate 1 is etched based on the opening 20 to form a shallow trench 41 within the substrate 1.
[0099] The isolation stack 2 includes a pad layer 21 and a patterned mask layer 22. The second opening 222 in the patterned mask layer 22 and the third opening 212 in the pad layer 21 together form the opening 20 of the isolation stack 2. The second opening 222 in the patterned mask layer 22 and the third opening 212 in the pad layer 21 have precise shapes and sizes. The substrate 1 is etched based on the opening 20 of the isolation stack 2 to form a shallow trench 41 in the substrate 1. Therefore, the shallow trench 41 also has precise shapes and sizes.
[0100] In step S123, please refer to Figure 12 A filling medium layer 43 is formed in the shallow trench 41, the opening 20 and the upper surface of the isolation stack 2.
[0101] In one embodiment, forming a filling medium layer 43 in the shallow trench 41, the opening 20, and the upper surface of the isolation stack 2 may include forming an oxide layer as the filling medium layer 43 in the shallow trench 41, the opening 20, and the upper surface of the isolation stack 2 using a high-energy plasma process.
[0102] The filling dielectric layer 43 can be, but is not limited to, a silicon oxide layer.
[0103] In step S124, please refer to Figures 13 to 15 Remove the filling medium layer 43 located on the upper surface of the isolation stack 2, the filling medium layer 43 partially located in the opening 20, and the isolation stack 2 to obtain the initial shallow trench isolation structure 42.
[0104] In one embodiment, see Figure 12 The filling medium layer 43 has a groove 431; see reference Figures 13 to 15 The filling medium layer 43 located on the upper surface of the isolation stack 2, the filling medium layer 43 partially located within the opening 20, and the isolation stack 2 are removed to obtain an initial shallow trench isolation structure 42, including:
[0105] S1241: Remove the portion of the filling medium layer 43 located outside the groove 431, and the resulting structure is as follows: Figure 13 As shown; whereby dry etching can be used to remove part of the filling dielectric layer 43 located outside the groove 431.
[0106] S1242: Remove the filling medium layer 43 located on the upper surface of the isolation stack 2 and part of the filling medium layer 43 located in the opening 20, and the resulting structure is as follows. Figure 14 As shown; wherein, chemical mechanical polishing process can be used to remove the filling medium layer 43 located on the upper surface of the isolation stack 2 and part of the filling medium layer 43 located in the opening 20.
[0107] S1243: Remove isolation layer 2, the resulting structure is as follows Figure 15As shown; the isolation stack 2 can be removed using a wet etching process.
[0108] In step S13, please refer to Figure 16 A sacrificial layer 5 is formed on the upper surface and sidewalls of the initial shallow trench isolation structure 42 and on the upper surface of the substrate 1.
[0109] The sacrificial layer 5 can be, but is not limited to, a silicon dioxide layer.
[0110] In one embodiment, forming a sacrificial layer 5 on the upper surface and sidewalls of the initial shallow trench isolation structure 42 and the upper surface of the substrate 1 may include forming a silicon oxide layer as a sacrificial layer 5 on the upper surface and sidewalls of the initial shallow trench isolation structure 42 and the upper surface of the substrate 1 using an atomic layer deposition process.
[0111] Among them, atomic layer deposition (ALD) technology has good film uniformity, and the sacrificial layer 5 formed by ALD is uniform and of good quality. During the preparation process, the required preset film thickness of sacrificial layer 5 can be calculated according to the etching solution and the set etching rate. Then, the sacrificial layer 5 with the preset film thickness can be accurately formed by ALD technology, which facilitates the subsequent precise etching and removal of sacrificial layer 5 without etching the shallow trench isolation structure 4.
[0112] In one embodiment, before removing the sacrificial layer 5 to obtain the shallow trench isolation structure 4, the method further includes:
[0113] A barrier layer 6 is formed on the upper surface of the sacrificial layer 5. The barrier layer 6 has a fourth opening 61, resulting in the following structure: Figure 17 As shown;
[0114] Based on the fourth opening 61, ion implantation is performed on the substrate 1 to form a lightly doped region 12 within the active region 11, resulting in the structure shown below. Figure 18 As shown.
[0115] After ion implantation is completed, the barrier layer 6 can be removed. The barrier layer 6 can be, but is not limited to, a photoresist layer. If the photoresist layer is in direct contact with the substrate 1, it will cause contamination to the substrate 1. Ion implantation is performed before the sacrificial layer 5 is removed. Therefore, the sacrificial layer 5 can isolate the barrier layer 6 from the substrate 1 to protect the substrate 1.
[0116] In some examples, a photoresist layer can be formed on the upper surface of the sacrificial layer 5 using spin coating in the coating process, and then a barrier layer 6 can be formed based on photolithography. Therefore, the fourth opening 61 of the barrier layer 6 has a precise pattern, that is, the fourth opening 61 has a precise shape and size. When ion implantation is performed on the substrate 1 based on the fourth opening 61, the implanted ions can accurately enter the position in the substrate 1 where ion implantation is required.
[0117] In the above embodiments, ion implantation is performed after the barrier layer 6 is formed. The fourth opening 61 of the barrier layer 6 can have a precise size and shape so as to accurately implant the substrate 1 without affecting other areas that do not need to be implanted with ions.
[0118] In other embodiments, the blocking layer 6 may also be an oxide layer, not limited to the photoresist layer described above.
[0119] In step S14, please refer to Figure 19 Remove the sacrificial layer 5 to obtain the shallow trench isolation structure 4.
[0120] Since the sacrificial layer 5 covers the sidewalls and top surface of the shallow trench isolation structure 4, the sacrificial layer on the sidewalls and top surface of the shallow trench isolation structure 4 protects the shallow trench isolation structure 4 during the etching process. Moreover, the thickness of the sacrificial layer 5 is a pre-calculated thickness corresponding to the etching solution and etching rate used. Therefore, the sacrificial layer 5 can be removed precisely without affecting the morphology at the junction of the shallow trench isolation structure 4 and the top surface of the substrate 1, that is, no pits will be generated at the junction of the shallow trench isolation structure 4 and the top surface of the substrate 1.
[0121] See Figure 19 This application also provides a shallow trench isolation structure 4, which is prepared using the preparation method of the shallow trench isolation structure 4 of this application.
[0122] The shallow trench isolation structure 4 in the above embodiments is prepared using the shallow trench isolation structure preparation method of this application. In this method, an initial shallow trench isolation structure 42 is formed in the substrate 1, and a sacrificial layer 5 is formed on the upper surface and sidewalls of the initial shallow trench isolation structure 42 and on the upper surface of the substrate 1 to protect the initial shallow trench isolation structure 42. Compared with the conventional method where the sacrificial layer 5 is only formed on the upper surface of the substrate 1, the sacrificial layer 5 of this application covers the upper surface and sidewalls of the initial shallow trench isolation structure 42 and the upper surface of the substrate 1. When the sacrificial layer 5 is removed, no pits are formed at the edge positions of the sidewalls and upper surface of the initial shallow trench isolation structure 42, and the resulting shallow trench isolation structure 4 is also free of pits.
[0123] This application also provides a method for fabricating a semiconductor structure, comprising: fabricating the shallow trench isolation structure using the method for fabricating a shallow trench isolation structure of this application.
[0124] The semiconductor structure fabrication method in the above embodiments uses the shallow trench isolation structure fabrication method of this application to fabricate the shallow trench isolation structure. In this method, an initial shallow trench isolation structure 42 is formed in the substrate 1, and a sacrificial layer 5 is formed on the upper surface and sidewalls of the initial shallow trench isolation structure 42 and on the upper surface of the substrate 1 to protect the initial shallow trench isolation structure 42. Compared with the conventional method where the sacrificial layer 5 is only formed on the upper surface of the substrate 1, the sacrificial layer 5 of this application covers the upper surface and sidewalls of the initial shallow trench isolation structure 42 and the upper surface of the substrate 1. When the sacrificial layer 5 is removed, no pits are formed on the sidewalls and the edge of the upper surface of the initial shallow trench isolation structure 42, and no pits are formed in the resulting shallow trench isolation structure 4. The semiconductor structure fabricated in this way can also avoid gate leakage problems caused by pits.
[0125] It should be understood that although the steps in the flowcharts of various embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of various embodiments may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of forming a shallow trench isolation structure, comprising: The application relates to a method for forming a shallow trench isolation structure. The method comprises the following steps: providing a substrate; forming an initial shallow trench isolation structure in the substrate, the initial shallow trench isolation structure separates a plurality of spaced active regions in the substrate; forming a sacrificial layer on the upper surface and sidewall of the initial shallow trench isolation structure and the upper surface of the substrate; wherein the upper surface of the initial shallow trench isolation structure is protruded from the upper surface of the substrate, the sidewall of the initial shallow trench isolation structure is exposed to the substrate, and the upper surface and sidewall of the initial shallow trench isolation structure and the upper surface of the substrate are in contact with the sacrificial layer; 2. The method of claim 1, wherein removing the sacrificial layer to obtain a shallow trench isolation structure. The method for forming the sacrificial layer on the upper surface and sidewall of the initial shallow trench isolation structure and the upper surface of the substrate comprises:
3. The method of claim 1, wherein forming a silicon oxide layer as the sacrificial layer on the upper surface and sidewall of the initial shallow trench isolation structure and the upper surface of the substrate by using an atomic layer deposition process. The method for forming the initial shallow trench isolation structure in the substrate comprises: forming an isolation stack on the upper surface of the substrate, the isolation stack has an opening; etching the substrate based on the opening to form a shallow trench in the substrate; forming a filling medium layer in the shallow trench, the opening and the upper surface of the isolation stack; 4. The method of claim 3, wherein removing the filling medium layer on the upper surface of the isolation stack, the filling medium layer partially in the opening and the isolation stack to obtain the initial shallow trench isolation structure. The isolation stack comprises a liner layer and a patterned mask layer. The method for forming the isolation stack on the upper surface of the substrate, the isolation stack having an opening, comprises: forming a liner material layer on the upper surface of the substrate; forming a mask layer on the upper surface of the liner material layer; forming a photoresist layer on the upper surface of the mask layer; exposing and developing the photoresist layer to obtain a patterned photoresist layer, the patterned photoresist layer having a first opening; etching the mask layer based on the patterned photoresist layer to obtain the patterned mask layer, the patterned mask layer having a second opening; 5. The method of claim 4, wherein etching the liner material layer based on the patterned mask layer to obtain the liner layer, the liner layer having a third opening. The method for forming the liner material layer on the upper surface of the substrate comprises:
6. The method of claim 4, wherein forming a silicon oxide layer as the liner material layer on the upper surface of the substrate. The method for forming the mask layer on the upper surface of the liner material layer comprises:
7. The method of claim 3, wherein forming a silicon nitride layer as the mask layer on the upper surface of the liner material layer. The method for forming the filling medium layer in the shallow trench, the opening and the upper surface of the isolation stack comprises:
8. The method of claim 3, wherein: forming an oxide layer as the filling medium layer in the shallow trench, the opening and the upper surface of the isolation stack by using a high-energy plasma process. The filling medium layer has a groove; the method for removing the filling medium layer on the upper surface of the isolation stack, the filling medium layer partially in the opening and the isolation stack to obtain the initial shallow trench isolation structure comprises: removing the part of the filling medium layer outside the groove; removing the filling medium layer on the upper surface of the isolation stack and the part of the filling medium layer in the opening; and removing the isolation stack. removing the isolation stack.
9. The method of claim 1 to 8, wherein before the removing the sacrificial layer to obtain the shallow trench isolation structure, the method further comprises: forming a blocking layer on an upper surface of the sacrificial layer, the blocking layer having a fourth opening; based on the fourth opening, performing ion implantation on the substrate to form a lightly doped region in the active region.
10. A method of fabricating a semiconductor structure, characterized by, comprising: manufacturing the shallow trench isolation structure by using the manufacturing method of the shallow trench isolation structure according to any one of claims 1 to 9.
Citation Information
Patent Citations
Manufacturing method of embedded word line transistor, transistor and memory
CN114267641A