A method for fabricating a silicon-based strained semiconductor structure

Abstract

The application provides a method for manufacturing a silicon-based strained semiconductor structure, comprising the following steps: providing a semiconductor layer, the semiconductor layer comprising a substrate layer and a plurality of gate structures arranged in a horizontal direction on the substrate layer; etching the substrate layer with the gate structures as a mask to obtain a trench in the substrate layer, the trench crossing between two adjacent gate structures in the horizontal direction, the trench comprising a plurality of inclined inner walls connected in sequence, and a concave angle being formed between two adjacent inclined inner walls, wherein at least one of the concave angles remains a by-product generated when the trench is formed; performing isochronal etching based on the trench to remove the by-product; and epitaxially growing an epitaxial layer in the trench. The method for manufacturing the silicon-based strained semiconductor structure adds an isochronal etching step between the etching to form the trench and the epitaxial growth in the trench, avoids defects caused by the by-product remaining in the trench during the epitaxial growth and adversely affects the device performance, and improves the product yield and performance stability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing and relates to a method for fabricating a silicon-based strained semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the feature size of silicon substrate semiconductor devices has been continuously reduced, severely restricting their integration and manufacturing capabilities, with dimensions almost reaching their limits. Silicon integrated circuit technology, driven by the proportional reduction of CMOS devices, has entered the nanoscale and will continue to pursue Moore's Law, further miniaturizing device dimensions to meet the requirements of chip miniaturization, high density, high speed, and system integration. However, as technology nodes decrease, the size of transistors on the chip becomes smaller and smaller, and the size of internal components becomes increasingly smaller. Improving transistor performance solely through gate dielectric layer shrinkage is gradually approaching its physical and technological limits. Physical limits such as off-state leakage current, increased power density, and mobility degradation degrade device performance, posing increasingly stringent challenges to proportional reduction technology. Currently, various CMOS technologies are seeking methods to increase the on-state conduction current and improve device speed without significantly increasing semiconductor device leakage current. Strained silicon technology is currently widely used. Strained silicon technology refers to the process of generating stress by straining materials and directing the stress to the channel of a device. This alters the energy band structure of the conduction or valence band of the silicon material in the channel. By designing the device appropriately, a suitable stress direction can be obtained, thereby reducing the probability of scattering within and between energy band valleys and the effective mass of carriers in the channel direction. This enhances carrier mobility and increases device speed. The process of manufacturing integrated circuits using strained silicon technology is called strained silicon process technology.

[0003] Conventionally, CMOS device manufacturing technology processes P-type metal-oxide-semiconductor field-effect transistors (PMOS) and N-type metal-oxide-semiconductor field-effect transistors (NMOS) separately. For example, compressive stress materials are used in the manufacturing process of PMOS devices, while tensile stress materials are used in NMOS devices to apply appropriate stress to the channel region, thereby improving carrier mobility. Embedded germanium-silicon (SiGe) technology has become one of the main techniques for PMOS stress engineering because it can apply appropriate compressive stress to the channel region to improve hole mobility. The conventional steps for generating SiGe are to first form a trench in the substrate, and then epitaxially grow a SiGe epitaxial layer based on the trench. Please refer to... Figure 1 and Figure 2 ,in, Figure 1 The diagram shown is a cross-sectional view of a substrate 1 with grooves 2 formed thereon. Figure 2 for Figure 1A partial enlarged view of the groove 2 shows that, when forming the groove, the morphology of the groove sometimes needs to be diamond-shaped based on the requirements of device performance, so as to improve the performance of PMOS device and the consistency of parameters between devices. Due to the narrow space generated by the two contact surfaces of the (100) and (110) surfaces of the groove, the etched product cannot be completely removed by wet method, and the subsequent epitaxial layer will have growth defects, resulting in insufficient stress and the device performance cannot meet the requirements.

[0004] Therefore, how to provide a method for fabricating silicon-based strained semiconductor structures, so as to process the trenches after etching to react away the byproducts accumulated in the narrow space during etching, so as to avoid the impact of growth defects generated during epitaxial growth on device performance, has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a silicon-based strained semiconductor structure, which solves the problem in the prior art where etching byproducts generated during the etching process accumulate at the concave corners between adjacent sidewalls in the trench and remain there, resulting in defects in the epitaxial layer obtained during subsequent epitaxial growth and adversely affecting device performance.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon-based strained semiconductor structure, comprising the following steps:

[0008] A semiconductor layer is provided, the semiconductor layer including a substrate layer and a plurality of gate structures located on the substrate layer and spaced apart in a horizontal direction;

[0009] The substrate layer is etched using the gate structure as a mask to obtain a trench in the substrate layer. The trench spans horizontally between two adjacent gate structures. The trench includes a plurality of inclined inner walls that are connected in sequence. A concave angle is formed between two connected inclined inner walls. At least one concave angle has residual byproducts generated during the formation of the trench.

[0010] In-situ etching is performed based on the trench to remove the byproducts;

[0011] An epitaxial layer is obtained by epitaxial growth inside and outside the trench.

[0012] Alternatively, the method for forming the trench includes wet etching.

[0013] Optionally, the chamber pressure range of the reaction chamber during the isotopic etching is 5 Torr-50 Torr.

[0014] Optionally, the temperature range of the reaction chamber during the in-situ etching is 600℃-800℃.

[0015] Optionally, the etching gas used for the in-situ etching includes GeH4 and HCl.

[0016] Optionally, the flow rate ratio of GeH4 to HCl is 0.1:1 to 0.5:1.

[0017] Optionally, the carrier gas used in the in-situ etching includes H2.

[0018] Optionally, the epitaxial layer may be made of SiGe.

[0019] Optionally, the method for forming the epitaxial layer includes at least one of chemical vapor deposition and molecular beam epitaxy.

[0020] Optionally, the gate structure includes a gate dielectric layer, a gate conductive layer, and a hard mask layer stacked sequentially from bottom to top, and includes gate sidewalls located on both sides of the gate conductive layer.

[0021] As described above, the method for fabricating a silicon-based strained semiconductor structure of the present invention improves the product yield and performance stability of the device by adding a co-etching step before etching to form trenches and before epitaxial growth inside and outside the trenches. Attached Figure Description

[0022] Figure 1 The diagram shows a cross-sectional view of a substrate with grooves formed.

[0023] Figure 2 Displayed as Figure 1 Enlarged cross-sectional view of the central groove.

[0024] Figure 3 The diagram shows the steps of the method for fabricating the silicon-based strained semiconductor structure of the present invention.

[0025] Figure 4 The diagram shows a cross-sectional view of the semiconductor layer structure obtained after performing step S1 in the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0026] Figure 5The diagram shows a cross-sectional view of the semiconductor layer structure obtained after performing step S2 in the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0027] Figure 6 The diagram shows a cross-sectional view of the semiconductor layer structure obtained after performing step S3 in the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0028] Figure 7 The diagram shows the chemical structure of the etching gas after it is introduced in the in-situ etching step of the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0029] Figure 8 The diagram shows the principle of chemical reaction (1) in the in-situ etching step of the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0030] Figure 9 The diagram shows the principle of chemical reaction (2) in the in-situ etching step of the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0031] Figure 10 The diagram shows the principle of chemical reaction (3) in the in-situ etching step of the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0032] Figure 11 The diagram shows a cross-sectional view of the semiconductor layer structure obtained after performing step S4 in the method for fabricating a silicon-based strained semiconductor structure according to the present invention.

[0033] Component designation explanation

[0034] 1 Substrate

[0035] 2 grooves

[0036] 3 Semiconductor layer

[0037] 31 Substrate layer

[0038] 32 gate structure

[0039] 321 Gate dielectric layer

[0040] 322 Gate conductive layer

[0041] 323 Hard mask layer

[0042] 3231 Silicon nitride hard mask layer

[0043] 3232 oxide hard mask layer

[0044] 324 gate sidewall

[0045] 3241 Oxide Sidewall Layer

[0046] 3242 Silicon nitride sidewall layer

[0047] 33. Trench

[0048] 34 Byproducts

[0049] 35 Epitaxial Layer

[0050] Steps S1 to S4 Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please refer to 3 to Figure 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] This embodiment provides a method for fabricating a silicon-based strained semiconductor structure. Please refer to [link to relevant documentation]. Figure 3 The flowchart of this method is shown, including the following steps:

[0054] S1: A semiconductor layer is provided, the semiconductor layer including a substrate layer and a plurality of gate structures located on the substrate layer and spaced apart in the horizontal direction;

[0055] S2: Using the gate structure as a mask, the substrate layer is etched to obtain a trench in the substrate layer. The trench spans horizontally between two adjacent gate structures. The trench includes a plurality of inclined inner walls connected in sequence. A concave angle is formed between two connected inclined inner walls. At least one concave angle has residual byproducts generated during the formation of the trench.

[0056] S3: Perform in-situ etching based on the trench to remove the byproducts;

[0057] S4: An epitaxial layer is obtained by epitaxial growth inside and outside the trench.

[0058] First, please refer to Figure 4Step S1 is executed to provide a semiconductor layer 3, the semiconductor layer 3 including a substrate layer 31 and a plurality of gate structures 32 located on the substrate and spaced apart in the horizontal direction.

[0059] As an example, the gate structure 32 includes a gate dielectric layer 321, a gate conductive layer 322, and a hard mask layer 323 stacked sequentially from bottom to top, and includes a gate sidewall 324 located on both sides of the gate conductive layer 322. The gate sidewall 324 can be a single-layer or multi-layer structure. In this embodiment, the gate dielectric layer 321 is made of silicon dioxide, the gate conductive layer 322 is made of polysilicon, the hard mask layer 323 includes a silicon nitride hard mask layer 3231 and an oxide hard mask layer 3232 stacked from bottom to top, and the gate sidewall 324 is a two-layer structure composed of an oxide sidewall layer 3241 and a silicon nitride sidewall layer 3242 covering the oxide sidewall layer 3241. The materials and structural features of the above-mentioned structural layers are not limited to this and can be reasonably set according to the actual application scenario.

[0060] Please see Figure 5 Step S2 is executed, using the gate structure 32 as a mask to etch the substrate layer 31 to obtain a trench 33 in the substrate layer 31. The trench 33 spans horizontally between two adjacent gate structures 32. The trench 33 includes a plurality of sequentially connected inclined inner walls, forming a concave angle between two connected inclined inner walls. At least one concave angle retains particulate byproducts 34 generated during the formation of the trench 33. Because the trench 33 has a different morphology from traditional trenches, it can also be called a diamond trench or a sigma trench. The epitaxial layer based on the trench 33 significantly improves the stability and consistency of device performance parameters (such as drive current).

[0061] As an example, the method of forming the trench 33 includes wet etching or other suitable methods that can produce trenches with similar morphology.

[0062] Please see Figure 6 Step S3 is executed, in-situ etching is performed based on the trench 33 to remove the byproduct 34. The mechanism of in-situ etching to remove the byproduct is to utilize the selective etching characteristics of the etching gas, that is, in situations such as... Figure 6 The etching rates of the substrate lattice surfaces around the trench shown are different. During the etching process, in addition to chemically reacting with the byproducts, the etching gas also reacts with the substrate material to which the byproducts are attached, causing the byproducts to lose their attachment points. After fully reacting with the etching gas, the byproducts are carried out of the reaction chamber with the carrier gas. In this process, due to the selectivity of etching, only the substrate around the concave corner of the trench 33 is damaged, and the overall morphology of the trench 33 is not significantly affected.

[0063] As an example, the chamber pressure range for the reaction chamber during the in-situ etching is 5 Torr-50 Torr. The chamber pressure range during the in-situ etching process needs to be set appropriately. The etching rate increases with increasing chamber pressure. Too low a chamber pressure may result in slow in-situ etching progress, affecting production efficiency, while too high a chamber pressure may lead to over-etching, causing defects in the subsequently grown epitaxial layer. In this embodiment, 30 Torr is preferred, but the chamber pressure can also be set to 15 Torr, 25 Torr, 35 Torr, or 45 Torr according to actual needs.

[0064] As an example, the temperature range of the reaction chamber during the in-situ etching is 600℃-800℃. The chamber temperature range during the in-situ etching process also needs to be reasonably set based on actual needs. In this embodiment, 650℃ is preferred to ensure that the etching rate is not too high, making the etching process uncontrollable, nor that the etching time is too long due to a too low etching rate, affecting efficiency. Furthermore, the temperature of the reaction chamber can also be set to 700℃ or 750℃.

[0065] As an example, the etching gases used in the in-situ etching include GeH4 and HCl. Besides the etching gases mentioned above, other etchants can also be selected to complete the in-situ etching process, as long as they can selectively etch along a specific plane or angle according to the specific morphology of the trench 33 to achieve the effect of removing the byproduct 34 at the concave corner.

[0066] As an example, the flow ratio of GeH4 to HCl is 0.1:1 to 0.5:1. In the mixed gas composed of the two reactant gases, HCl is the main reactant gas, while GeH4 is used as an additive. The Cl in the HCl gas... - High anisotropy can be achieved during the etching process, and Cl - The etching rate is relatively slow, which is beneficial for controlling the etching process, while the role of additives can improve the etching rate, selectivity and uniformity during the etching process.

[0067] As an example, the carrier gas used in the in-situ etching process includes H2. The role of H2 in the in-situ etching process is to remove residual silicon raw materials, dopants, etc., from the process steps prior to epitaxial growth, and also to carry away the byproduct 34 generated in the in-situ etching process with H2.

[0068] Please see Figure 7 The diagram shows the chemical structures of GeH4 and HCl after the etching gas is introduced into the cavity. Please refer to [link / reference] for the entire isotopic etching process. Figures 8 to 10 The diagram illustrates the chemical reaction principle of the in-situ etching step. The etching gas introduced into the cavity undergoes the following step-by-step chemical reactions:

[0069] (1) GeH4→Ge+H2;

[0070] (2) HCl + Ge → GeCl4 + H2;

[0071] (3) Si + GeCl4 → SiCl4 + Ge.

[0072] First, such as Figure 8 As shown, the GeH4 gas introduced into the cavity will undergo a decomposition reaction at high temperature to produce Ge and H2, and so on. Figure 9 As shown, the HCl gas introduced into the cavity will subsequently react chemically with Ge to form GeCl4. Finally, as... Figure 10 As shown, GeCl4 generated in the previous reaction is adsorbed onto Si in the byproducts at the concave corner and reacts further to generate SiCl4. Through the above series of reactions, an etching effect on Si is produced, thereby achieving different etching rates on different surfaces of the trench 33 before epitaxial growth to avoid the byproducts remaining and causing irreversible defects in the epitaxial layer subsequently grown in the trench 33. Specifically, in the above reaction, Ge acts as a catalyst, which can accelerate the etching rate along the lattice plane (110) > (100) > (111) of the trench 33. The (111) plane is not marked in the figure.

[0073] Please see Figure 11 Step S4 is executed to grow an epitaxial layer 35 inside and outside the trench. The nucleation energy is reduced within the trench 33, thereby achieving selective epitaxial growth of the epitaxial layer 35. The epitaxial layer 35 may or may not completely fill the trench 33. When the epitaxial layer 35 is fully filled, the top surface of the epitaxial layer 35 may be flush with or higher than the surface of the substrate layer 31. The appropriate choice is made according to the actual device performance requirements. In this embodiment, the epitaxial layer 35 fills the trench 33 and its surface is higher than the surface of the substrate layer 31, which can achieve better compressive stress technology effects.

[0074] As an example, the material of the epitaxial layer 35 includes SiGe or other materials that can produce a strain effect. In this embodiment, the material of the epitaxial layer 35 is SiGe, while in other types of semiconductor structures, the material of the epitaxial layer 35 can also be Si or SiC, etc.

[0075] As an example, the method for forming the epitaxial layer 35 includes at least one of chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). In this embodiment, low-pressure chemical vapor deposition (LPCVD) is preferred for forming the epitaxial layer 35. This method allows for the direct introduction of the gas source for epitaxial growth into the reaction chamber after the in-situ etching without changing the chamber pressure, thus initiating epitaxial growth. Furthermore, under low-pressure conditions, the diffusion capacity of the reaction gas and reaction products through the boundary layer is improved, increasing the gas concentration and effectively controlling the surface reaction rate, resulting in better film performance and thus effectively improving the thickness 35 and resistivity of the epitaxial layer.

[0076] In summary, the method for fabricating a silicon-based strained semiconductor structure according to the present invention includes the following steps: providing a semiconductor layer, the semiconductor layer including a substrate layer and a plurality of gate structures disposed horizontally on the substrate; etching the substrate layer using the gate structures as a mask to obtain trenches in the substrate layer, the trenches spanning horizontally between two adjacent gate structures, the trenches including a plurality of sequentially connected inclined inner walls, a concave angle being formed between two connected inclined inner walls, wherein at least one concave angle retains byproducts generated during trench formation; performing in-situ etching based on the trenches to remove the byproducts; and epitaxially growing an epitaxial layer inside and outside the trenches. The fabrication method of the present invention, by adding an in-situ etching step between etching to form the trenches and epitaxial growth inside and outside the trenches, avoids defects caused by byproducts remaining in the trenches during epitaxial growth, which could adversely affect device performance, thereby improving the product yield and performance stability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon-based strained semiconductor structure, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer including a substrate layer and a plurality of gate structures located on the substrate layer and spaced apart in a horizontal direction; The substrate layer is etched using the gate structure as a mask to obtain a trench in the substrate layer. The trench spans horizontally between two adjacent gate structures. The trench includes a plurality of inclined inner walls that are connected in sequence. A concave angle is formed between two connected inclined inner walls. At least one concave angle has residual byproducts generated during the formation of the trench. In-situ etching is performed on the trench to remove the byproducts. The etching gases used in the in-situ etching include GeH4 and HCl. A catalytic etching method is used to selectively remove the byproducts while maintaining the morphology of the trench. An epitaxial layer is obtained by epitaxial growth inside and outside the trench.

2. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The method for forming the trench includes wet etching.

3. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The chamber pressure range for the reaction chamber during the isotopic etching is 5 Torr-50 Torr.

4. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The temperature range of the reaction chamber during the in-situ etching is 600℃-800℃.

5. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The flow rate ratio of GeH4 to HCl is 0.1:1 to 0.5:

1.

6. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The carrier gas used in the in-situ etching includes H2.

7. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The epitaxial layer is made of SiGe.

8. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The method for forming the epitaxial layer includes at least one of chemical vapor deposition and molecular beam epitaxy.

9. The method for fabricating a silicon-based strained semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a gate conductive layer and a hard mask layer stacked sequentially from bottom to top, and includes gate sidewalls located on both sides of the gate conductive layer.

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