A semiconductor structure, a method for fabricating the semiconductor structure, and a memory.

Abstract

This application discloses a semiconductor structure, a method for fabricating a semiconductor structure, and a memory. The semiconductor structure includes: a substrate comprising a substrate, a first isolation layer, a first dielectric layer, and a stop layer formed by stacking; wherein a first contact hole is formed on the substrate, the opening of the first contact hole being flush with the upper surface of the stop layer; a first insulating layer and a first barrier layer are sequentially formed on the inner wall of the first contact hole, and a first contact structure is disposed within the first contact hole; a protective layer is formed to cover the upper surface of the first contact structure; a second dielectric layer and a second isolation layer are sequentially stacked on the protective layer; wherein a second contact hole is formed on the substrate, the second contact hole being formed to penetrate the second dielectric layer, the second isolation layer, and the protective layer, and stopping at the first contact structure; a second barrier layer and a second contact structure are also included, the second barrier layer being formed on the inner wall of the second contact hole, and the second contact structure being disposed within the second contact hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure, a method for fabricating a semiconductor structure, and a memory. Background Technology

[0002] With the development and advancement of technology, chips are being used more and more widely. Chips are interconnected through TSVs (Through-Silicon Vias). One type of Middle TSV structure involves the TSV fabrication process occurring in the later stages of the manufacturing process; that is, the TSV fabrication process follows the CT (contact hole) process but precedes the wiring process. However, this design presents two problems in the manufacturing process:

[0003] (1) In the TSV CMP (Chemical Mechanical Polishing) process, the film thickness changes significantly after the process because the CMP process cannot be well controlled.

[0004] (2) During the cabling process, there is an electromigration contamination problem in the cabling area.

[0005] Therefore, how to solve the above-mentioned technical problems has become an urgent issue for those skilled in the art. Summary of the Invention

[0006] The purpose of this application is to provide a semiconductor structure, a semiconductor manufacturing method, and a memory that can solve the above-mentioned technical problems.

[0007] To address the aforementioned problems, a first aspect of this application provides a semiconductor structure, comprising:

[0008] The substrate includes a substrate, a first isolation layer, a first dielectric layer and a stop layer formed by stacking; wherein a first contact hole is formed on the substrate, the first contact hole being formed to extend from the stop layer into the substrate, and the opening of the first contact hole being flush with the upper surface of the stop layer;

[0009] A first insulating layer, a first barrier layer, and a first contact structure are provided, wherein the first insulating layer and the first barrier layer are sequentially formed on the inner wall of the first contact hole, and the first contact structure is disposed inside the first contact hole;

[0010] A protective layer is formed to cover the upper surface of the first contact structure;

[0011] A second dielectric layer and a second isolation layer are sequentially stacked on the protective layer; wherein a second contact hole is formed on the substrate, the second contact hole being formed to penetrate the second dielectric layer, the second isolation layer and the protective layer, and ending at the first contact structure;

[0012] The second barrier layer is formed on the inner wall of the second contact hole, and the second contact structure is disposed inside the second contact hole.

[0013] In some embodiments, the protective layer is made of tantalum or silicon nitride.

[0014] In some embodiments, the protective layer is formed using a deposition process, the protective layer being formed to cover the upper surface of the first contact structure and the surface of the stop layer.

[0015] In some embodiments, the stop layer is formed using a deposition process, the stop layer being formed to cover the surface of the first dielectric layer, wherein the material of the stop layer includes silicon nitride.

[0016] A second aspect of this application provides a method for fabricating a semiconductor structure, including:

[0017] A substrate is provided, the substrate comprising a substrate, a first isolation layer, a first dielectric layer and a stop layer formed by stacking;

[0018] A first contact hole is formed on the substrate, the first contact hole being formed to extend from the stop layer into the substrate, and the opening of the first contact hole being flush with the upper surface of the stop layer;

[0019] A first insulating layer and a first barrier layer are sequentially formed on the inner wall of the first contact hole, and a first contact structure is formed to fill the first contact hole, wherein the upper surface of the first contact structure is exposed.

[0020] A protective layer is formed to cover the upper surface of the first contact structure;

[0021] A second dielectric layer and a second isolation layer are stacked on the protective layer;

[0022] A second contact hole is formed, which penetrates the second dielectric layer, the second isolation layer and the protective layer, stops at the first contact structure and exposes the upper surface of the first contact structure;

[0023] A second barrier layer is formed on the inner wall of the second contact hole, and a second contact structure is formed to fill the second contact hole.

[0024] In some embodiments, the step of sequentially forming a first insulating layer and a first barrier layer on the inner wall of the first contact hole, and filling the first contact hole with a first contact structure, includes:

[0025] A first insulating layer is formed covering the upper surface of the stop layer and the inner wall of the first contact hole;

[0026] A first barrier layer is formed covering the upper surface of the first insulating layer;

[0027] A semiconductor material is deposited on the surface of the first barrier layer to form a first contact structure that covers the first barrier layer and fills the first contact hole;

[0028] Remove the first insulating layer, the first blocking layer, and the first contact structure on the upper surface of the stop layer, so that the upper surface of the first contact structure in the first contact hole is flush with the upper surface of the stop layer.

[0029] In some embodiments, removing the first insulating layer, the first blocking layer, and the first contact structure at the upper surface of the stop layer, so that the upper surface of the first contact structure within the first contact hole is flush with the upper surface of the stop layer, includes:

[0030] By using a grinding process, the first insulating layer and the first blocking layer on the upper surface of the stop layer, as well as part of the structure of the first contact structure, are removed, so that the upper surface of the first contact structure is flush with the upper surface of the stop layer.

[0031] In some embodiments, the formation of a protective layer, the protective layer being formed to cover the upper surface of the first contact structure, includes:

[0032] A protective layer is formed by a deposition process to cover the upper surface of the first contact structure, wherein the material of the protective layer includes tantalum or silicon nitride.

[0033] In some embodiments, the formation of a protective layer, the protective layer being formed to cover the upper surface of the first contact structure, includes:

[0034] The protective layer is formed using a deposition process, and the protective layer is formed to cover the upper surface of the first contact structure and the surface of the stop layer.

[0035] In some embodiments, forming a second contact hole, the second contact hole being formed to penetrate the second dielectric layer, the second isolation layer, and the protective layer, ending at the first contact structure, and exposing the upper surface of the first contact structure, includes:

[0036] An etching process is performed to sequentially remove a portion of the second dielectric layer, the second isolation layer, and the protective layer, forming a second contact hole that stops at the first contact structure and exposes the upper surface of the first contact structure.

[0037] In some embodiments, forming a second barrier layer on the inner wall of the second contact hole and filling the second contact hole with a second contact structure includes:

[0038] A second barrier layer is formed, covering the surface of the second isolation layer and the inner wall of the second contact hole;

[0039] A semiconductor material is deposited on the surface of the second barrier layer to form a second contact structure that covers the second barrier layer and fills the second contact hole;

[0040] Remove the second barrier layer and the second contact structure on the upper surface of the second isolation layer, so that the upper surface of the second contact structure in the second contact hole is flush with the upper surface of the second isolation layer.

[0041] In some embodiments, removing the second barrier layer and the second contact structure at the upper surface of the second isolation layer, so that the upper surface of the second contact structure within the second contact hole is flush with the upper surface of the second isolation layer, includes:

[0042] By using a grinding process, the second barrier layer on the upper surface of the second isolation layer and part of the structure of the second contact structure are removed, so that the upper surface of the second contact structure is flush with the upper surface of the second isolation layer.

[0043] In some embodiments, the stop layer is formed using a deposition process, the stop layer being formed to cover the surface of the first dielectric layer, wherein the material of the stop layer includes silicon nitride.

[0044] In some embodiments, it also includes:

[0045] A conductive via is formed on the substrate, the conductive via being formed to stop at a semiconductor device and expose the upper surface of the semiconductor device, and / or the conductive via being formed to stop at a conductive structure and expose the upper surface of the conductive structure;

[0046] An electrical contact structure is formed that fills the conductive hole.

[0047] In some embodiments, forming a conductive via on the substrate, the conductive via being formed to terminate at a semiconductor device and expose the upper surface of the semiconductor device, and / or the conductive via being formed to terminate at a conductive structure and expose the upper surface of the conductive structure, includes:

[0048] A sacrificial layer is formed covering the stop layer;

[0049] An etching process is performed to sequentially remove a portion of the sacrificial layer, the stop layer, and the first dielectric layer, forming a conductive hole that stops at the semiconductor device and / or the conductive structure, wherein the opening of the conductive hole is formed on the upper surface of the sacrificial layer.

[0050] In some embodiments, the electrical contact structure forming the conductive hole includes:

[0051] Semiconductor material is deposited on the surface of the sacrificial layer to form an electrical contact structure that covers the sacrificial layer and fills the conductive hole;

[0052] Remove the electrical contact structure and sacrificial layer from the upper surface of the stop layer, so that the upper surface of the electrical contact structure in the conductive hole is flush with the upper surface of the stop layer.

[0053] In some embodiments, removing the electrical contact structure and sacrificial layer from the upper surface of the stop layer, so that the upper surface of the electrical contact structure within the conductive hole is flush with the upper surface of the stop layer, includes:

[0054] The sacrificial layer on the upper surface of the stop layer and part of the electrical contact structure are removed by a grinding process, so that the upper surface of the electrical contact structure is flush with the upper surface of the stop layer.

[0055] In some embodiments, forming a conductive via on the substrate, the conductive via being formed to terminate at a semiconductor device and expose the upper surface of the semiconductor device, and / or the conductive via being formed to terminate at a conductive structure and expose the upper surface of the conductive structure, includes:

[0056] An etching process is performed to remove part of the structure of the first dielectric layer, forming a conductive hole that stops at the semiconductor device and / or the conductive structure, wherein the opening of the conductive hole is formed on the upper surface of the first dielectric layer.

[0057] In some embodiments, the electrical contact structure forming the conductive hole includes:

[0058] Semiconductor material is deposited on the surface of the first dielectric layer to form an electrical contact structure that covers the first dielectric layer and fills the conductive hole;

[0059] Remove the electrical contact structure on the upper surface of the first dielectric layer so that the upper surface of the electrical contact structure inside the conductive hole is flush with the upper surface of the first dielectric layer.

[0060] In some embodiments, removing the electrical contact structure on the upper surface of the first dielectric layer, so that the upper surface of the electrical contact structure within the conductive hole is flush with the upper surface of the first dielectric layer, includes:

[0061] The electrical contact structure on the upper surface of the first dielectric layer is removed by a grinding process, so that the upper surface of the electrical contact structure is flush with the upper surface of the first dielectric layer.

[0062] A third aspect of the embodiments of this application provides a memory including the semiconductor structure described in any of the preceding claims.

[0063] The above-mentioned technical solution of this application has the following beneficial technical effects: On the one hand, in semiconductor fabrication, before forming the second dielectric layer, a stop layer is formed on the upper surface of the first dielectric layer, which can be used to control the thickness of the substrate in semiconductor structure fabrication; on the other hand, by forming a protective layer on the upper surface of the first contact structure, the first contact structure can be prevented from directly contacting the second dielectric layer on the protective layer, thus avoiding the problem of electromigration. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of the semiconductor structure in the related technology;

[0065] Figure 2 for Figure 1 A partially enlarged schematic diagram of the semiconductor structure;

[0066] Figure 3 for Figure 1 A top view of a semiconductor structure;

[0067] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0068] Figures 5-17 This is a schematic diagram illustrating the structure presented in each step of a semiconductor structure fabrication method flowchart according to an exemplary embodiment;

[0069] Figures 18-29 This is a schematic diagram illustrating the structure presented in each step of a semiconductor structure fabrication method flowchart according to another exemplary embodiment;

[0070] Figure label:

[0071] 10. Substrate; 20. First insulating layer; 30. First barrier layer; 40. First contact structure; 50. Protective layer; 60. Second dielectric layer; 70. Second isolation layer; 80. Second barrier layer; 90. Second contact structure; 100. Sacrificial layer; 110. Semiconductor device; 120. Conductive structure; 130. Electrical contact structure; 11. Substrate; 12. First isolation layer; 13. First dielectric layer; 14. Stop layer; 15. First contact hole; 21. Second contact hole; 22. Conductive hole. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0073] In the description of this application, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0075] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0076] like Figures 1-3 As shown, the semiconductor structure includes a substrate 10a, an interlayer insulating layer 20a, an interlayer barrier layer 30a, a via contact structure 40a, a top barrier layer 80a, and a top contact structure 90a. (Reference) Figure 1 The substrate 10a includes a substrate 11a, an isolation layer 12a, a dielectric layer 13a, and a top insulating layer 14a, all formed in a stacked manner. A bottom contact hole 15a is formed on the substrate 10a, extending from the dielectric layer 13a into the substrate 11a. An interlayer insulating layer 20a covers the inner wall of the bottom contact hole 15a, and the top insulating layer 14a covers the upper surface of the dielectric layer 13a. An interlayer barrier layer 30a covers the surface of the interlayer insulating layer 20a, and a hole contact structure 40a is disposed within the bottom contact hole 15a. A semiconductor structure has a top contact hole 21a, extending through the top insulating layer 14a and stopping at the upper surface of the hole contact structure 40a. A top barrier layer 80a is formed on the inner wall of the top contact hole 21a and connected to the hole contact structure 40a, and a top contact structure 90a is disposed within the top contact hole 21a.

[0077] It should be noted that before forming the top insulating layer 14a, the upper surface of the dielectric layer 13a needs to undergo CMP (Chemical Mechanical Polishing), i.e., planarization, to remove part of the interlayer insulating layer 20a, interlayer barrier layer 30a, and via contact structure 40a formed on the upper surface of the dielectric layer 13a. However, in related technologies, the CMP process cannot be well controlled, resulting in significant variations in the thickness of the semiconductor structure, i.e., a large difference in the thickness of the substrate 10a after fabrication. Additionally, refer to... Figure 2 ,Depend on Figure 2 It can be seen that the structure of the top insulating layer 14a formed between the top contact holes 21a is in direct contact with the upper surface of the hole contact structure 40a. (Reference) Figure 3 It is important to understand that the top barrier layer 80a and the top contact structure 90a constitute the wiring structure 1. Multiple wiring structures 1 are spaced apart on the substrate 10a, and the top insulating layer 14a fills the gaps in the wiring structures 1. It is understood that the top insulating layer 14a, formed within the gaps in the wiring structures 1, is in direct contact with the hole contact structure 40a. The top insulating layer 14a is made of silicon dioxide, and the hole contact structure 40a is made of copper. Due to the direct contact between the top insulating layer 14a and the upper surface of the hole contact structure 40a, electromigration occurs, thus affecting the reliability of the fabricated semiconductor.

[0078] Therefore, how to solve the above problems has become an urgent issue for those skilled in the art.

[0079] This application provides a semiconductor structure including a substrate, a first insulating layer, a first barrier layer, a first contact structure, a protective layer, a second dielectric layer, a second isolation layer, a second barrier layer, and a second contact structure. The substrate includes a stacked substrate, a first isolation layer, a first dielectric layer, and a stop layer. A first contact hole is formed on the substrate, extending from the stop layer into the substrate, with its opening flush with the upper surface of the stop layer. The first insulating layer and the first barrier layer are sequentially formed on the inner wall of the first contact hole, and the first contact structure is disposed within the first contact hole. The protective layer covers the upper surface of the first contact structure, and the second dielectric layer and the second isolation layer are sequentially stacked on the protective layer. A second contact hole is formed on the substrate, penetrating the second dielectric layer, the second isolation layer, and the protective layer, and ending at the first contact structure. The second barrier layer is formed on the inner wall of the second contact hole, and the second contact structure is disposed within the second contact hole.

[0080] In this embodiment of the application, on the one hand, before forming the second dielectric layer, a stop layer is formed on the upper surface of the first dielectric layer during the fabrication of the semiconductor structure, which can be used to control the thickness dimension during the fabrication of the semiconductor structure; on the other hand, by forming a protective layer on the upper surface of the first contact structure, direct contact between the first contact structure and the second dielectric layer on the protective layer can be prevented, thus avoiding the problem of electromigration.

[0081] In some embodiments, the protective layer is made of tantalum or silicon nitride.

[0082] In some embodiments, a protective layer is formed using a deposition process, which is formed to cover the upper surface of the first contact structure and the surface of the stop layer.

[0083] In some embodiments, a stop layer is formed using a deposition process, the stop layer being formed as a surface covering the first dielectric layer, wherein the material of the stop layer includes silicon nitride.

[0084] A second aspect of this application provides a method for fabricating a semiconductor structure, including:

[0085] A substrate is provided, the substrate comprising a substrate, a first isolation layer, a first dielectric layer and a stop layer formed by stacking;

[0086] A first contact hole is formed on the substrate, the first contact hole being formed to extend from the stop layer into the substrate, and the opening of the first contact hole being flush with the upper surface of the stop layer;

[0087] A first insulating layer and a first barrier layer are sequentially formed on the inner wall of the first contact hole, and a first contact structure is formed to fill the first contact hole, wherein the upper surface of the first contact structure is exposed.

[0088] A protective layer is formed, which covers the upper surface of the first contact structure;

[0089] A second dielectric layer and a second isolation layer are formed by stacking on the protective layer;

[0090] A second contact hole is formed, which penetrates the second dielectric layer, the second isolation layer and the protective layer, stops at the first contact structure and exposes the upper surface of the first contact structure;

[0091] A second barrier layer is formed on the inner wall of the second contact hole, and a second contact structure is formed to fill the second contact hole.

[0092] In this embodiment of the application, on the one hand, in semiconductor fabrication, before forming the second dielectric layer, a stop layer is formed on the upper surface of the first dielectric layer, which can be used to control the thickness dimension in semiconductor structure fabrication; on the other hand, by forming a protective layer on the upper surface of the first contact structure, direct contact between the first contact structure and the second dielectric layer on the protective layer can be prevented, thus avoiding electromigration problems.

[0093] A specific embodiment of this application will be described in detail below:

[0094] refer to Figure 4 and Figures 5-17 A method for fabricating a semiconductor structure according to an embodiment of this application includes:

[0095] S101. Provide a substrate 10, the substrate 10 including a substrate 11, a first isolation layer 12, a first dielectric layer 13 and a stop layer 14 formed by stacking;

[0096] S103. A first contact hole 15 is formed on the substrate 10. The first contact hole 15 is formed to extend from the stop layer 14 into the substrate 11, and the opening of the first contact hole 15 is flush with the upper surface of the stop layer 14.

[0097] S105, a first insulating layer 20 and a first blocking layer 30 are sequentially formed on the inner wall of the first contact hole 15, and a first contact structure 40 is filled in the first contact hole 15, wherein the upper surface of the first contact structure 40 is exposed.

[0098] S107. A protective layer 50 is formed, which is formed to cover the upper surface of the first contact structure 40;

[0099] S109. A second dielectric layer 60 and a second isolation layer 70 are laminated on the protective layer 50;

[0100] S111, Form a second contact hole 21, the second contact hole 21 is formed to penetrate the second dielectric layer 60, the second isolation layer 70 and the protective layer 50, stop at the first contact structure 40, and expose the upper surface of the first contact structure 40;

[0101] S113, A second barrier layer 80 and a second contact structure 90 are formed on the inner wall of the second contact hole 21.

[0102] In this embodiment, on the one hand, before forming the second dielectric layer 60, a stop layer 14 is formed on the upper surface of the first dielectric layer 13, which can be used to control the thickness of the substrate 10 in the semiconductor structure fabrication; on the other hand, by forming a protective layer 50 on the upper surface of the first contact structure 40, the first contact structure 40 can be prevented from directly contacting the second dielectric layer 60 on the protective layer 50, thus avoiding electromigration problems.

[0103] In some embodiments, step S105 involves sequentially forming a first insulating layer 20 and a first barrier layer 30 on the inner wall of the first contact hole 15, and filling the first contact hole 15 with a first contact structure 40, including:

[0104] S1051, A first insulating layer 20 is formed covering the upper surface of the stop layer 14 and the inner wall of the first contact hole 15;

[0105] refer to Figure 9 The first insulating layer 20 is formed to cover the upper surface of the stop layer 14 and the inner wall of the first contact hole 15. It is understood that the inner wall of the first contact hole 15 includes a bottom wall and a side wall. The first insulating layer 20 is made of silicon dioxide, which serves as a buffer layer when the first contact structure 40 is thermally expanded.

[0106] S1053, Form a first barrier layer 30 covering the upper surface of the first insulating layer 20;

[0107] refer to Figure 10 The first barrier layer 30 covers the surface of the structural layer of the first insulating layer 20 on the stop layer 14, and the surface of the structural layer of the first insulating layer 20 within the first contact hole 15; wherein the thickness of the first barrier layer 30 is smaller than the thickness of the first insulating layer 20. The material of the first barrier layer 30 is thallium.

[0108] S1055, deposit semiconductor material on the surface of the first barrier layer 30 to form a first contact structure 40 covering the first barrier layer 30 and filling the first contact hole 15;

[0109] Continue to refer to Figure 10 The first contact structure 40 fills the first contact hole 15 and covers the first barrier layer 30. The material of the first contact structure 40 is copper.

[0110] S1057. Remove the first insulating layer 20, the first blocking layer 30 and the first contact structure 40 on the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40 in the first contact hole 15 is flush with the upper surface of the stop layer 14.

[0111] refer to Figure 11 Remove the first insulating layer 20, the first blocking layer 30 and the first contact structure 40 on the upper surface of the stop layer 14 to expose the upper surface of the stop layer 14. After the removal process, the upper surface of the first contact structure 40 in the first contact hole 15 and the exposed surfaces of the first insulating layer 20 and the first blocking layer 30 are flush with the upper surface of the stop layer 14.

[0112] In some embodiments, step S1057, removing the first insulating layer 20, the first blocking layer 30, and the first contact structure 40 from the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40 within the first contact hole 15 is flush with the upper surface of the stop layer 14, includes:

[0113] By using a grinding process, the first insulating layer 20 and the first barrier layer 30, as well as part of the structure of the first contact structure 40, are removed from the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40, the surface of the first insulating layer 20 and the surface of the first barrier layer 30 are exposed and are flush with the upper surface of the stop layer 14.

[0114] In this embodiment, by forming a stop layer 14 on the upper surface of the first dielectric layer 13 and using the stop layer 14 as the stop layer 14 in the polishing process, it is beneficial to control the thickness dimension in the semiconductor structure fabrication and ensure the product yield of the semiconductor fabrication.

[0115] In some embodiments, step S107, forming a protective layer 50, wherein the protective layer 50 is formed to cover the upper surface of the first contact structure 40, includes:

[0116] A protective layer 50 is formed covering the upper surface of the first contact structure 40 using a deposition process. (Reference) Figure 12 The protective layer 50 is formed to cover the exposed surfaces of the stop layer 14, the first insulating layer 20, the first barrier layer 30, and the first contact structure 40; wherein the material of the protective layer 50 is thallium.

[0117] refer to Figure 13 The protective layer 50 is removed using an etching process to remove the protective layer 50 on the stop layer 14. Figure 13 It can be seen that the protective layer 50 above the first contact structure 40 covers the exposed surface of the first contact structure 40, as well as the exposed surfaces of the first insulating layer 20 and the first barrier layer 30.

[0118] In this embodiment, by forming a protective layer 50 on the upper surface of the first contact structure 40, direct contact between the first contact structure 40 and the second dielectric layer 60 on the protective layer 50 can be prevented, thus avoiding electromigration problems.

[0119] In some embodiments, a second dielectric layer 60 and a second insulating layer 70 are sequentially formed on the upper surface of the protective layer 50 using a deposition process. (See reference...) Figure 14 The second dielectric layer 60 is formed to cover the upper surface of the protective layer 50 and the exposed surface of the stop layer 14, and the second isolation layer 70 is formed to cover the upper surface of the second dielectric layer 60. The material of the second dielectric layer 60 is silicon dioxide, and the material of the second isolation layer 70 is silicon nitride.

[0120] In some embodiments, step S111, forming a second contact hole 21, wherein the second contact hole 21 is formed to penetrate the second dielectric layer 60, the second isolation layer 70, and the protective layer 50, stopping at the first contact structure 40, and exposing the upper surface of the first contact structure 40, includes:

[0121] refer to Figure 15 In this embodiment, etching can be performed to sequentially remove portions of the second isolation layer 70, the second dielectric layer 60, and the protective layer 50, forming a second contact hole 21 that stops at the first contact structure 40 and exposes the upper surface of the first contact structure 40. In this embodiment, three second contact holes 21 are formed on the upper part of the first contact structure 40, and the three second contact holes 21 are arranged at intervals, each exposing the upper surface of the first contact structure 40.

[0122] In some embodiments, step S113, which involves forming a second barrier layer 80 on the inner wall of the second contact hole 21 and filling the second contact structure 90 within the second contact hole 21, includes:

[0123] S1131, A second barrier layer 80 is formed covering the surface of the second isolation layer 70 and the inner wall of the second contact hole 21;

[0124] refer to Figure 16 A second barrier layer 80 is formed using a deposition process. The second barrier layer 80 is formed to cover the upper surface of the second isolation layer 70 and the inner wall of the second contact hole 21. It is understood that, with reference to... Figure 15 The inner wall of the second contact hole 21 includes a bottom wall and a side wall. The side wall of the second contact hole 21 is composed of the exposed side wall of the second isolation layer 70, the exposed side wall of the second dielectric layer 60, and the exposed side wall of the protective layer 50. The bottom wall of the second contact hole 21 is the exposed surface of the first contact structure 40. The material of the second barrier layer 80 is thallium.

[0125] S1133, deposit semiconductor material on the surface of the second barrier layer 80 to form a second contact structure 90 covering the second barrier layer 80 and filling the second contact hole 21;

[0126] Continue to refer to Figure 16 The formed second contact structure 90 covers the surface of the second barrier layer 80 and completely fills the second contact hole 21. The structural layer of the second isolation structure at the upper surface of the second isolation layer 70 has a certain thickness. The material of the second contact structure 90 is copper.

[0127] S1135. Remove the second blocking layer 80 and the second contact structure 90 on the upper surface of the second isolation layer 70, so that the upper surface of the second contact structure 90 in the second contact hole 21 is flush with the upper surface of the second isolation layer 70.

[0128] In some embodiments, removing the second barrier layer 80 and the second contact structure 90 at the upper surface of the second isolation layer 70, so that the upper surface of the second contact structure 90 within the second contact hole 21 is flush with the upper surface of the second isolation layer 70, includes:

[0129] refer to Figure 17 A grinding process is used to remove part of the second barrier layer 80 and the second contact structure 90 from the upper surface of the second isolation layer 70. (Reference) Figure 17 As can be seen, after the grinding process, the upper surface of the second isolation layer 70 and the upper surface of the second contact structure 90 are both exposed, and the upper surface of the second contact structure 90 is flush with the upper surface of the second isolation layer 70.

[0130] In some embodiments, a stop layer 14 is formed using a deposition process, the stop layer 14 being formed to cover the surface of the first dielectric layer 13, wherein the material of the stop layer 14 includes silicon nitride.

[0131] In some embodiments, prior to the formation of the first contact hole 15, the following steps are also included:

[0132] Conductive holes 22 are formed on the substrate 10, the conductive holes 22 are formed to stop at the semiconductor device 110 and expose the upper surface of the semiconductor device 110, and / or the conductive holes 22 are formed to stop at the conductive structure 120 and expose the upper surface of the conductive structure 120.

[0133] refer to Figure 7-17 Semiconductor device 110 and conductive structure 120 are formed within substrate 10. Semiconductor device 110 is disposed on the upper surface of substrate 11 and embedded within first dielectric layer 13, and conductive structure 120 is formed within first dielectric layer 13. (Continue to refer to...) Figure 7-17 The orifice of the conductive hole 22 is formed on the upper surface of the stop layer 14, which is formed to extend from the stop layer 14 toward the substrate 11 and stop at the upper surface of the semiconductor device 110 and / or the upper surface of the conductive structure 120.

[0134] An electrical contact structure 130 is formed to fill the conductive hole 22.

[0135] Continue to refer to Figure 5 and Figure 7-17 An electrical contact structure 130 is disposed within a conductive hole 22. In this embodiment, three conductive holes 22, one semiconductor device 110, and two conductive structures 120 are specifically illustrated. A conductive hole 22 is formed on the upper surface of one semiconductor device 110 and two conductive structures 120 respectively, and an electrical contact structure 130 is disposed within each conductive hole 22.

[0136] In some embodiments, reference is made to Figure 5A conductive via 22 is formed on the substrate 10, wherein the conductive via 22 is formed to terminate at the semiconductor device 110 and expose the upper surface of the semiconductor device 110, and / or the conductive via 22 is formed to terminate at the conductive structure 120 and expose the upper surface of the conductive structure 120, including:

[0137] A sacrificial layer 100 is formed to cover the stopping layer 14;

[0138] An etching process is performed to sequentially remove a portion of the sacrificial layer 100, the stop layer 14, and the first dielectric layer 13, forming a conductive hole 22 that stops at the semiconductor device 110 and / or the conductive structure 120, wherein the opening of the conductive hole 22 is formed on the upper surface of the sacrificial layer 100.

[0139] refer to Figure 5 A sacrificial layer 100 is formed on the upper surface of the stop layer 14. In this embodiment, the cross-sectional size of the conductive hole 22 is reduced along the direction from the sacrificial layer 100 to the substrate 11. The material of the sacrificial layer 100 is silicon dioxide.

[0140] In some embodiments, the electrical contact structure 130 forming the conductive via 22 includes:

[0141] Semiconductor material is deposited on the surface of the sacrificial layer 100 to form an electrical contact structure 130 covering the sacrificial layer 100 and filling the conductive hole 22;

[0142] refer to Figure 6 The deposited semiconductor material completely fills the conductive hole 22 and forms a structural layer of a certain thickness on the upper surface of the stop layer 14. The material of the electrical contact structure 130 is tungsten or titanium nitride.

[0143] Remove the electrical contact structure 130 and sacrificial layer 100 from the upper surface of the stop layer 14, so that the upper surface of the electrical contact structure 130 in the conductive hole 22 is flush with the upper surface of the stop layer 14.

[0144] In some embodiments, the electrical contact structure 130 and the sacrificial layer 100 on the upper surface of the stop layer 14 are removed, so that the upper surface of the electrical contact structure 130 in the conductive hole 22 is flush with the upper surface of the stop layer 14, including:

[0145] refer to Figure 7 By using a grinding process, the sacrificial layer 100 and part of the electrical contact structure 130 on the upper surface of the stop layer 14 are removed, so that the upper surface of the electrical contact structure 130 and the surface of the stop layer 14 are exposed, and the upper surface of the electrical contact structure 130 is flush with the upper surface of the stop layer 14.

[0146] It is understood that in some embodiments, references Figures 13-17When removing the protective layer 50, the protective layer 50 formed on the upper surface of the electrical contact structure 130 is retained. During the fabrication of the second contact hole 21 on the upper surface of the first contact structure 40, a second contact hole 21 is formed correspondingly above the electrical contact structure 130. Simultaneously, using the above fabrication steps, a second barrier layer 80 and a second contact structure 90 are formed within the second contact hole 21 corresponding to the electrical contact structure 130. The specific fabrication method has been described above and will not be repeated here.

[0147] This application will be described in detail with reference to another embodiment:

[0148] refer to Figure 4 and Figures 18-29 A method for fabricating a semiconductor structure according to an embodiment of this application includes:

[0149] S101. Provide a substrate 10, the substrate 10 including a substrate 11, a first isolation layer 12, a first dielectric layer 13 and a stop layer 14 formed by stacking;

[0150] S103. A first contact hole 15 is formed on the substrate 10. The first contact hole 15 is formed to extend from the stop layer 14 into the substrate 11, and the opening of the first contact hole 15 is flush with the upper surface of the stop layer 14.

[0151] S105, a first insulating layer 20 and a first blocking layer 30 are sequentially formed on the inner wall of the first contact hole 15, and a first contact structure 40 is filled in the first contact hole 15, wherein the upper surface of the first contact structure 40 is exposed.

[0152] S107. A protective layer 50 is formed, which is formed to cover the upper surface of the first contact structure 40;

[0153] S109. A second dielectric layer 60 and a second isolation layer 70 are laminated on the protective layer 50;

[0154] S111, Form a second contact hole 21, the second contact hole 21 is formed to penetrate the second dielectric layer 60, the second isolation layer 70 and the protective layer 50, stop at the first contact structure 40, and expose the upper surface of the first contact structure 40;

[0155] S113, A second barrier layer 80 and a second contact structure 90 are formed on the inner wall of the second contact hole 21.

[0156] In this embodiment, on the one hand, before forming the second dielectric layer 60, a stop layer 14 is formed on the upper surface of the first dielectric layer 13, which can be used to control the thickness dimension in the semiconductor structure fabrication; on the other hand, by forming a protective layer 50 on the upper surface of the first contact structure 40, the first contact structure 40 can be prevented from directly contacting the second dielectric layer 60 on the protective layer 50, thus avoiding electromigration problems.

[0157] In some embodiments, step S105 involves sequentially forming a first insulating layer 20 and a first barrier layer 30 on the inner wall of the first contact hole 15, and filling the first contact hole 15 with a first contact structure 40, including:

[0158] S1051, A first insulating layer 20 is formed covering the upper surface of the stop layer 14 and the inner wall of the first contact hole 15;

[0159] refer to Figure 22 The first insulating layer 20 is formed to cover the upper surface of the stop layer 14 and the inner wall of the first contact hole 15. It is understood that the inner wall of the first contact hole 15 includes a bottom wall and a side wall. The first insulating layer 20 is made of silicon dioxide, which serves as a buffer layer when the first contact structure 40 is thermally expanded.

[0160] S1053, Form a first barrier layer 30 covering the upper surface of the first insulating layer 20;

[0161] refer to Figure 23 The first barrier layer 30 covers the surface of the structural layer of the first insulating layer 20 on the stop layer 14, and the surface of the structural layer of the first insulating layer 20 within the first contact hole 15; wherein the thickness of the first barrier layer 30 is smaller than the thickness of the first insulating layer 20. The material of the first barrier layer 30 is thallium.

[0162] S1055, deposit semiconductor material on the surface of the first barrier layer 30 to form a first contact structure 40 covering the first barrier layer 30 and filling the first contact hole 15;

[0163] Continue to refer to Figure 23 The first contact structure 40 fills the first contact hole 15 and covers the first barrier layer 30. The material of the first contact structure 40 is copper.

[0164] S1057. Remove the first insulating layer 20, the first blocking layer 30 and the first contact structure 40 on the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40 in the first contact hole 15 is flush with the upper surface of the stop layer 14.

[0165] refer to Figure 24Remove the first insulating layer 20, the first blocking layer 30 and the first contact structure 40 on the upper surface of the stop layer 14 to expose the upper surface of the stop layer 14. After the removal process, the upper surface of the first contact structure 40 in the first contact hole 15 and the exposed surfaces of the first insulating layer 20 and the first blocking layer 30 are flush with the upper surface of the stop layer 14.

[0166] In some embodiments, step S1057, removing the first insulating layer 20, the first blocking layer 30, and the first contact structure 40 from the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40 within the first contact hole 15 is flush with the upper surface of the stop layer 14, includes:

[0167] By using a grinding process, the first insulating layer 20 and the first barrier layer 30, as well as part of the structure of the first contact structure 40, are removed from the upper surface of the stop layer 14, so that the upper surface of the first contact structure 40, the surface of the first insulating layer 20 and the surface of the first barrier layer 30 are exposed and are flush with the upper surface of the stop layer 14.

[0168] In this embodiment, by forming a stop layer 14 on the upper surface of the first dielectric layer 13 and using the stop layer 14 as the stop layer 14 in the polishing process, it is beneficial to control the thickness dimension in the semiconductor structure fabrication and ensure the product yield of the semiconductor fabrication.

[0169] In some embodiments, step S107, forming a protective layer 50, wherein the protective layer 50 is formed to cover the upper surface of the first contact structure 40, includes:

[0170] A protective layer 50 is formed covering the upper surface of the first contact structure 40 using a deposition process. (Reference) Figure 25 The protective layer 50 is formed to cover the exposed surfaces of the stop layer 14, the first insulating layer 20, the first barrier layer 30, and the first contact structure 40; wherein the material of the protective layer 50 is silicon nitride.

[0171] In this embodiment, by forming a protective layer 50 on the upper surface of the first contact structure 40, direct contact between the first contact structure 40 and the second dielectric layer 60 on the protective layer 50 can be prevented, thus avoiding electromigration problems.

[0172] In some embodiments, a second dielectric layer 60 and a second insulating layer 70 are sequentially formed on the upper surface of the protective layer 50 using a deposition process. (See reference...) Figure 26 The second dielectric layer 60 is formed to cover the upper surface of the protective layer 50, and the second isolation layer 70 is formed to cover the upper surface of the second dielectric layer 60. The material of the second dielectric layer 60 is silicon dioxide, and the material of the second isolation layer 70 is silicon nitride.

[0173] In some embodiments, step S111, forming a second contact hole 21, wherein the second contact hole 21 is formed to penetrate the second dielectric layer 60, the second isolation layer 70, and the protective layer 50, stopping at the first contact structure 40, and exposing the upper surface of the first contact structure 40, includes:

[0174] refer to Figure 27 In this embodiment, etching can be performed to sequentially remove portions of the second dielectric layer 60, the second isolation layer 70, and the protective layer 50, forming a second contact hole 21 that stops at the first contact structure 40 and exposes the upper surface of the first contact structure 40. In this embodiment, three second contact holes 21 are formed on the upper part of the first contact structure 40, and the three second contact holes 21 are arranged at intervals, each exposing the upper surface of the first contact structure 40.

[0175] In some embodiments, step S113, which involves forming a second barrier layer 80 on the inner wall of the second contact hole 21 and filling the second contact structure 90 within the second contact hole 21, includes:

[0176] S1131, A second barrier layer 80 is formed covering the surface of the second isolation layer 70 and the inner wall of the second contact hole 21;

[0177] refer to Figure 28 A second barrier layer 80 is formed using a deposition process. The second barrier layer 80 is formed to cover the upper surface of the second isolation layer 70 and the inner wall of the second contact hole 21. It is understood that, with reference to... Figure 28 The inner wall of the second contact hole 21 includes a bottom wall and a side wall. The side wall of the second contact hole 21 is composed of the exposed side wall of the second isolation layer 70, the exposed side wall of the second dielectric layer 60, and the exposed side wall of the protective layer 50. The bottom wall of the second contact hole 21 is the exposed surface of the first contact structure 40. The material of the second barrier layer 80 is thallium.

[0178] S1133, deposit semiconductor material on the surface of the second barrier layer 80 to form a second contact structure 90 covering the second barrier layer 80 and filling the second contact hole 21;

[0179] Continue to refer to Figure 28 The formed second contact structure 90 covers the surface of the second barrier layer 80 and completely fills the second contact hole 21. The structural layer of the second isolation structure at the upper surface of the second isolation layer 70 has a certain thickness. The material of the second contact structure 90 is copper.

[0180] S1135. Remove the second blocking layer 80 and the second contact structure 90 on the upper surface of the second isolation layer 70, so that the upper surface of the second contact structure 90 in the second contact hole 21 is flush with the upper surface of the second isolation layer 70.

[0181] In some embodiments, removing the second barrier layer 80 and the second contact structure 90 at the upper surface of the second isolation layer 70, so that the upper surface of the second contact structure 90 within the second contact hole 21 is flush with the upper surface of the second isolation layer 70, includes:

[0182] refer to Figure 29 By using a grinding process, the second barrier layer 80 and part of the structure of the second contact structure 90 on the upper surface of the second isolation layer 70 are removed, making the upper surface of the second contact structure 90 flush with the upper surface of the second isolation layer 70. (Reference) Figure 29 As can be seen, after the grinding process, the upper surface of the second isolation layer 70 and the upper surface of the second contact structure 90 are both exposed, and the upper surface of the second contact structure 90 is flush with the upper surface of the second isolation layer 70.

[0183] In some embodiments, prior to the formation of the first contact hole 15, the following steps are also included:

[0184] Conductive holes 22 are formed on the substrate 10, the conductive holes 22 are formed to stop at the semiconductor device 110 and expose the upper surface of the semiconductor device 110, and / or the conductive holes 22 are formed to stop at the conductive structure 120 and expose the upper surface of the conductive structure 120.

[0185] refer to Figure 21-29 Semiconductor device 110 and conductive structure 120 are formed within substrate 10. Semiconductor device 110 is disposed on the upper surface of substrate 11 and embedded within first dielectric layer 13, and conductive structure 120 is formed within first dielectric layer 13. (Continue to refer to...) Figure 21-29 The opening of the conductive hole 22 is formed on the upper surface of the first dielectric layer 13, and it is formed to extend from the first dielectric layer 13 toward the substrate 11 and stop at the upper surface of the semiconductor device 110 and / or the upper surface of the conductive structure 120.

[0186] An electrical contact structure 130 is formed to fill the conductive hole 22.

[0187] Continue to refer to Figure 21-29 An electrical contact structure 130 is disposed within a conductive hole 22. In this embodiment, three conductive holes 22, one semiconductor device 110, and two conductive structures 120 are specifically illustrated. A conductive hole 22 is formed on the upper surface of one semiconductor device 110 and two conductive structures 120 respectively, and an electrical contact structure 130 is disposed within each conductive hole 22.

[0188] In some embodiments, a conductive via 22 is formed on the substrate 10, the conductive via 22 being formed to terminate at the semiconductor device 110 and expose the upper surface of the semiconductor device 110, and / or the conductive via 22 being formed to terminate at the conductive structure 120 and expose the upper surface of the conductive structure 120, including:

[0189] An etching process is performed to remove part of the structure of the first dielectric layer 13, forming a conductive hole 22 that stops at the semiconductor device 110 and / or the conductive structure 120, wherein the opening of the conductive hole 22 is formed on the upper surface of the first dielectric layer 13.

[0190] refer to Figure 18 In this embodiment, the first dielectric layer 13 is etched using an etching process to form a conductive hole 22 with a gradually decreasing cross-sectional size along the direction from the first dielectric layer 13 to the substrate 11.

[0191] In some embodiments, the electrical contact structure 130 forming the conductive via 22 includes:

[0192] Semiconductor material is deposited on the surface of the first dielectric layer 13 to form an electrical contact structure 130 covering the first dielectric layer 13 and filling the conductive hole 22;

[0193] refer to Figure 19 The deposited semiconductor material completely fills the conductive hole 22 and forms a structural layer of a certain thickness on the upper surface of the first dielectric layer 13. The material of the electrical contact structure 130 is tungsten.

[0194] Remove the electrical contact structure 130 on the upper surface of the first dielectric layer 13 so that the upper surface of the electrical contact structure 130 in the conductive hole 22 is flush with the upper surface of the first dielectric layer 13.

[0195] In some embodiments, removing the electrical contact structure 130 on the upper surface of the first dielectric layer 13, so that the upper surface of the electrical contact structure 130 within the conductive hole 22 is flush with the upper surface of the first dielectric layer 13, includes:

[0196] refer to Figure 20 The electrical contact structure 130 on the upper surface of the first dielectric layer 13 is removed by a grinding process, so that the upper surface of the electrical contact structure 130 is flush with the upper surface of the first dielectric layer 13.

[0197] It is understood that in some embodiments, references Figures 21-29 The difference lies in that, in this embodiment, when removing the protective layer 50, the protective layer 50 and the stop layer 14 formed on the upper surface of the electrical contact structure 130 are removed. Furthermore, during the fabrication of the second contact hole 21 on the upper surface of the first contact structure 40, a second contact hole 21 is formed correspondingly above the electrical contact structure 130. Simultaneously, using the aforementioned fabrication steps, a second barrier layer 80 and a second contact structure 90 are formed within the second contact hole 21 corresponding to the electrical contact structure 130. The specific fabrication method has been described above and will not be repeated here.

[0198] A third aspect of this application provides a memory including the semiconductor structure described above.

[0199] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this application and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this application should be included within the protection scope of this application. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a first isolation layer, a first dielectric layer and a stop layer formed by stacking; wherein a first contact hole is formed on the substrate, the first contact hole being formed to extend from the stop layer into the substrate, and the opening of the first contact hole being flush with the upper surface of the stop layer; A first insulating layer, a first barrier layer, and a first contact structure are provided, wherein the first insulating layer and the first barrier layer are sequentially formed on the inner wall of the first contact hole, and the first contact structure is disposed inside the first contact hole; An electrical contact structure is located in the substrate, and the upper surface of the electrical contact structure is flush with the upper surface of the stop layer; A protective layer is formed to cover the upper surface of the first contact structure, the protective layer is located on the upper surface covering the electrical contact structure, and the material of the protective layer is tantalum; A second dielectric layer and a second isolation layer are sequentially stacked on the protective layer; wherein a second contact hole is formed on the substrate, the second contact hole being formed to penetrate the second dielectric layer, the second isolation layer and the protective layer, and ending at the first contact structure; The second barrier layer is formed on the inner wall of the second contact hole, and the second contact structure is disposed inside the second contact hole; The second contact structure is also located on the electrical contact structure, and the second barrier layer is in contact with the protective layer on the upper surface of the electrical contact structure.

2. The semiconductor structure according to claim 1, characterized in that, The protective layer is formed using a deposition process, and the protective layer is formed to cover the upper surface of the first contact structure and the surface of the stop layer.

3. The semiconductor structure according to claim 1, characterized in that, The stop layer is formed using a deposition process, the stop layer being formed to cover the surface of the first dielectric layer, wherein the material of the stop layer includes silicon nitride.

4. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a substrate, a first isolation layer, a first dielectric layer and a stop layer formed by stacking; A first contact hole is formed on the substrate, the first contact hole being formed to extend from the stop layer into the substrate, and the opening of the first contact hole being flush with the upper surface of the stop layer; A first insulating layer and a first barrier layer are sequentially formed on the inner wall of the first contact hole, and a first contact structure is formed to fill the first contact hole, wherein the upper surface of the first contact structure is exposed. An electrical contact structure is formed, wherein the upper surface of the electrical contact structure is flush with the upper surface of the stop layer; A protective layer is formed to cover the upper surface of the first contact structure, the protective layer is located on the upper surface covering the electrical contact structure, and the material of the protective layer is tantalum; A second dielectric layer and a second isolation layer are stacked on the protective layer; A second contact hole is formed, which penetrates the second dielectric layer, the second isolation layer and the protective layer, stops at the first contact structure and exposes the upper surface of the first contact structure; A second barrier layer is formed on the inner wall of the second contact hole, and a second contact structure is formed to fill the second contact hole; The second contact structure is also located on the electrical contact structure, and the second barrier layer is in contact with the protective layer on the upper surface of the electrical contact structure.

5. The semiconductor structure fabrication method according to claim 4, characterized in that, The step of sequentially forming a first insulating layer and a first barrier layer on the inner wall of the first contact hole, and filling the first contact hole with a first contact structure, includes: A first insulating layer is formed covering the upper surface of the stop layer and the inner wall of the first contact hole; A first barrier layer is formed covering the upper surface of the first insulating layer; A semiconductor material is deposited on the surface of the first barrier layer to form a first contact structure that covers the first barrier layer and fills the first contact hole; Remove the first insulating layer, the first blocking layer, and the first contact structure on the upper surface of the stop layer, so that the upper surface of the first contact structure in the first contact hole is flush with the upper surface of the stop layer.

6. The semiconductor structure fabrication method according to claim 5, characterized in that, The step of removing the first insulating layer, the first blocking layer, and the first contact structure at the upper surface of the stop layer, so that the upper surface of the first contact structure within the first contact hole is flush with the upper surface of the stop layer, includes: By using a grinding process, the first insulating layer and the first blocking layer on the upper surface of the stop layer, as well as part of the structure of the first contact structure, are removed, so that the upper surface of the first contact structure is flush with the upper surface of the stop layer.

7. The semiconductor structure fabrication method according to claim 4, characterized in that, The formation of a protective layer, wherein the protective layer is formed to cover the upper surface of the first contact structure, includes: A protective layer is formed by a deposition process to cover the upper surface of the first contact structure, wherein the material of the protective layer includes tantalum or silicon nitride.

8. The semiconductor structure fabrication method according to claim 4, characterized in that, The formation of a protective layer, wherein the protective layer is formed to cover the upper surface of the first contact structure, includes: The protective layer is formed using a deposition process, and the protective layer is formed to cover the upper surface of the first contact structure and the surface of the stop layer.

9. The semiconductor structure fabrication method according to claim 4, characterized in that, The formation of the second contact hole, which penetrates the second dielectric layer, the second isolation layer, and the protective layer, terminates at the first contact structure, and exposes the upper surface of the first contact structure, includes: An etching process is performed to sequentially remove a portion of the second dielectric layer, the second isolation layer, and the protective layer, forming a second contact hole that stops at the first contact structure and exposes the upper surface of the first contact structure.

10. The semiconductor structure fabrication method according to claim 4, characterized in that, The formation of a second barrier layer on the inner wall of the second contact hole and the filling of the second contact hole with a second contact structure include: A second barrier layer is formed, covering the surface of the second isolation layer and the inner wall of the second contact hole; A semiconductor material is deposited on the surface of the second barrier layer to form a second contact structure that covers the second barrier layer and fills the second contact hole; Remove the second barrier layer and the second contact structure on the upper surface of the second isolation layer, so that the upper surface of the second contact structure in the second contact hole is flush with the upper surface of the second isolation layer.

11. The semiconductor structure fabrication method according to claim 10, characterized in that, The step of removing the second barrier layer and the second contact structure at the upper surface of the second isolation layer, so that the upper surface of the second contact structure within the second contact hole is flush with the upper surface of the second isolation layer, includes: By using a grinding process, the second barrier layer on the upper surface of the second isolation layer and part of the structure of the second contact structure are removed, so that the upper surface of the second contact structure is flush with the upper surface of the second isolation layer.

12. The semiconductor structure fabrication method according to claim 4, characterized in that, The stop layer is formed using a deposition process, the stop layer being formed to cover the surface of the first dielectric layer, wherein the material of the stop layer includes silicon nitride.

13. The semiconductor structure fabrication method according to claim 4, characterized in that, Also includes: A conductive via is formed on the substrate, the conductive via being formed to stop at a semiconductor device and expose the upper surface of the semiconductor device, and / or the conductive via being formed to stop at a conductive structure and expose the upper surface of the conductive structure; The electrical contact structure that fills the conductive hole is formed.

14. The semiconductor structure fabrication method according to claim 13, characterized in that, The formation of a conductive via on the substrate, wherein the conductive via is formed to terminate at a semiconductor device and expose the upper surface of the semiconductor device, and / or the conductive via is formed to terminate at a conductive structure and expose the upper surface of the conductive structure, includes: A sacrificial layer is formed covering the stop layer; An etching process is performed to sequentially remove a portion of the sacrificial layer, the stop layer, and the first dielectric layer, forming a conductive hole that stops at the semiconductor device and / or the conductive structure, wherein the opening of the conductive hole is formed on the upper surface of the sacrificial layer.

15. The semiconductor structure fabrication method according to claim 14, characterized in that, The electrical contact structure forming the conductive hole includes: Semiconductor material is deposited on the surface of the sacrificial layer to form an electrical contact structure that covers the sacrificial layer and fills the conductive hole; Remove the electrical contact structure and sacrificial layer from the upper surface of the stop layer, so that the upper surface of the electrical contact structure in the conductive hole is flush with the upper surface of the stop layer.

16. The semiconductor structure fabrication method according to claim 15, characterized in that, The step of removing the electrical contact structure and sacrificial layer from the upper surface of the stop layer, so that the upper surface of the electrical contact structure within the conductive hole is flush with the upper surface of the stop layer, includes: The sacrificial layer on the upper surface of the stop layer and part of the electrical contact structure are removed by a grinding process, so that the upper surface of the electrical contact structure is flush with the upper surface of the stop layer.

Images