Battery management chip packaging method, chip, system and electronic device

Abstract

The present invention discloses a battery management chip packaging method, a chip, a system and an electronic device. The battery management chip packaging method includes: processing at least two battery management units on a wafer, each battery management unit including a switching transistor, and the switching transistors in two adjacent battery management units being connected in parallel; dicing the wafer to obtain target die, each target die including at least one battery management unit; and packaging each target die to obtain a battery management chip. This technical solution can reduce the internal resistance of two battery management units after parallel connection, thereby reducing the heat dissipation of the two battery management units after parallel connection, improving the efficiency of the two battery management units after parallel connection, and further improving the working efficiency of the power management chip.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and in particular, to a battery management chip packaging method, a chip, a system, and an electronic device. Background Art

[0002] A power management chip is a chip that takes on the responsibilities of power conversion, distribution, detection, and other power management in an electronic device system. It is mainly responsible for identifying the CPU power supply amplitude, generating corresponding short rectangular waves, and driving the subsequent load for power output.

[0003] In existing power management chips, there are switching transistors. When the power management chip detects abnormal charging and discharging states of the battery, it controls the switching transistors to cut off the charging and discharging circuit to prevent potential safety hazards. However, there is a large Rds(ON) in the power management chip. The Rds(ON) refers to the resistance value between the drain and source of the switching transistor in the power management chip when the switching transistor is conducting, with the unit of ohm. Generally speaking, a large Rds(ON) will cause the power management chip to heat up severely, thereby affecting the efficiency of the power management chip.

[0004] In order to reduce the Rds(ON) in the power management chip, the prior art generally adopts the method of paralleling two power management chips to reduce the Rds(ON). However, due to the influence of the existing packaging process, the Rds(ON) of the two power management chips is different. For example, the Rds(ON) of one power management chip is large, and the Rds(ON) of one power management chip is small. As a result, the overall Rds(ON) after the two power management chips are paralleled is still too large, which is not conducive to reducing heat generation and improving the working efficiency of the power management chip. Summary of the Invention

[0005] Embodiments of the present invention provide a battery management chip packaging method, a chip, a system, and an electronic device to solve the problem of low working efficiency of existing power management chips.

[0006] A battery management chip packaging method includes:

[0007] Processing at least two battery management units on a wafer, each of the battery management units including a switching transistor, and the switching transistors in adjacent two battery management units being paralleled;

[0008] Performing dicing on the wafer to obtain target die, each of the target die including at least one of the battery management units;

[0009] Performing packaging on each target die to obtain a battery management chip.

[0010] Further, at least two of the battery management units are distributed on the wafer in an array form.

[0011] Further, the spacing distance between two adjacent battery management units is equal.

[0012] Further, each of the battery management units includes a control circuit and a switching transistor;

[0013] The input end of the control circuit is the chip power supply end of the battery management unit, and is used for connecting to the positive electrode of the battery;

[0014] The output end of the control circuit is connected to the control end of the switching transistor;

[0015] The first connection end of the switching transistor is the grounding end of the battery management unit, and is used for connecting to the negative electrode of the battery;

[0016] The second connection end of the switching transistor is the load connection end of the battery management unit, and is used for connecting to an electrical load.

[0017] Further, each of the battery management units includes a control circuit, a first switching transistor, and a second switching transistor;

[0018] The input end of the control circuit is the chip power supply end of the battery management unit, and is used for connecting to the positive electrode of the battery;

[0019] The output end of the control circuit is connected to the control end of the first switching transistor and is also connected to the control end of the second switching transistor;

[0020] The first connection end of the first switching transistor is the grounding end of the battery management unit, and is used for connecting to the negative electrode of the battery; the second connection end of the first switching transistor is connected to the second connection end of the second switching transistor; the first connection end of the switching transistor is the load connection end of the battery management unit, and is used for connecting to an electrical load.

[0021] Further, the switching transistors in two adjacent battery management units are connected in parallel, including:

[0022] The chip power supply ends of two adjacent battery management units are connected by a first signal line, the grounding ends of two adjacent battery management units are connected by a second signal line, and the load connection ends of two adjacent battery management units are connected by a third signal line;

[0023] The control ends of the switching transistors in two adjacent battery management units are connected by a fourth signal line.

[0024] Further, the process of dicing the wafer to obtain the target die includes:

[0025] Determine the area to be scribed in the wafer;

[0026] Determine at least one target battery management unit located within the area to be scribed, and determine an adjacent battery management unit located outside the area to be scribed and connected to the target battery management unit through a signal line;

[0027] Cut off the signal line between the target battery management unit and the adjacent battery management unit to obtain a target die corresponding to the area to be scribed.

[0028] Further, the encapsulating each target die to obtain a battery management chip includes:

[0029] Process connection pads on the battery management chip;

[0030] Electrically connect the battery management unit to the connection pads.

[0031] Further, the connection pads include a target selection pad and a target control pad; the battery management unit includes a target control loop, and the target control loop includes a target drive circuit and at least one target switch;

[0032] The target drive circuit is connected to the target selection pad, the target control pad, and the control end of each target switch;

[0033] If the target selection pad is floating or coupled to the battery negative electrode, and the battery management chip detects a battery abnormal signal, the target drive circuit controls each target switch to turn off;

[0034] If the target selection pad is coupled to the battery positive electrode, each target switch is controlled to turn off according to the target control signal received by the target control pad, and the target control signal is a control signal output when an external circuit detects a battery abnormality.

[0035] Further, the connection pads further include a signal detection pad and a battery negative pad;

[0036] The first end of the target switch is connected to the signal detection pad; the second end of the target switch is connected to the battery negative pad, and the third end of the target switch is the control end.

[0037] Further, the connection pads further include a battery positive pad;

[0038] The target control loop further includes a logic control circuit. The input end of the logic control circuit is coupled to the battery positive pad and the signal detection pad of the battery management chip. The output end of the logic control circuit is connected to the target drive circuit, and is used to detect the battery abnormal signal and output a target control signal.

[0039] Further, the target drive circuit includes a first signal conversion circuit, a second signal conversion circuit, a level shift circuit, and a transistor network;

[0040] The first input end of the first signal conversion circuit is connected to the output end of the logic control circuit. The second signal conversion circuit is connected to the target selection pad. The output end of the first signal conversion circuit is connected to the input end of the level shift circuit, and is used to output a first conversion signal according to the target control signal output by the logic control circuit and the level signal corresponding to the target selection pad.

[0041] The first input end of the second signal conversion circuit is connected to the target selection pad. The second input end of the second signal conversion circuit is connected to the battery negative pad. The output end of the second signal conversion circuit is connected to the first input end of the transistor network, and is used to output a second conversion signal according to the level signal corresponding to the target selection pad.

[0042] The second input end of the transistor network is connected to the output end of the level shift circuit. The third input end of the transistor network is connected to the target selection pad. The transistor network is used to enter the target working mode according to the first conversion signal, the second conversion signal, and the level signal corresponding to the target selection pad, and output a transistor drive signal to the target control pad in the target working mode.

[0043] Further, the first signal conversion circuit includes a first inverter and a NOR gate circuit;

[0044] The input end of the first inverter is connected to the output end of the logic control circuit. The output end of the first inverter is connected to the first input end of the NOR gate circuit. The second input end of the NOR gate circuit is connected to the target selection pad. The output end of the NOR gate circuit is connected to the input end of the level shift circuit.

[0045] Further, the second signal conversion circuit includes a second inverter and a first resistor;

[0046] The first end of the first resistor is connected to the battery negative pad. The second end of the first resistor is connected to the target selection pad and the input end of the second inverter. The output end of the second inverter is connected to the first input end of the transistor network.

[0047] A battery management chip is packaged using the above-mentioned battery management chip packaging method.

[0048] A battery protection system comprises the above-mentioned battery management chip and a battery connected to the battery management chip.

[0049] An electronic device includes the above-mentioned battery protection system.

[0050] The above-mentioned battery management chip packaging method, chip, system and electronic device process at least two battery management units on a wafer, each battery management unit includes a switching transistor, and the switching transistors in two adjacent battery management units are connected in parallel to ensure that the Rds (ON) of the two battery management units after parallel connection is reduced, thereby reducing the internal resistance of the two battery management units after parallel connection, and then reducing the heat dissipation of the two battery management units after parallel connection, and improving the efficiency of the two battery management units after parallel connection, and dicing the wafer to obtain target bare chips, each target bare chip includes at least one battery management unit, and each target bare chip is packaged to obtain a battery management chip. Not only can battery management chips with high internal resistance be produced, but also battery management chips with low internal resistance can be produced, thereby meeting the different internal resistance requirements of battery management chips, that is, battery management chips with different internal resistance are produced based on one wafer, thereby improving the production efficiency of battery management chips and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0052] Figure 1 This is a flow chart of a battery management chip packaging method according to an embodiment of the present invention;

[0053] Figure 2 is another flow chart of a battery management chip packaging method according to an embodiment of the present invention;

[0054] Figure 3 is another flow chart of a battery management chip packaging method according to an embodiment of the present invention;

[0055] Figure 4 is a circuit diagram of a battery management unit according to an embodiment of the present invention;

[0056] Figure 5 is another circuit diagram of a battery management unit according to an embodiment of the present invention;

[0057] Figure 6 is another circuit schematic diagram of the battery management unit in an embodiment of the present invention;

[0058] Figure 7 is another circuit schematic diagram of the battery management unit in an embodiment of the present invention;

[0059] Figure 8 is a circuit schematic diagram of the battery management chip in an embodiment of the present invention;

[0060] Figure 9 is a circuit schematic diagram of the target control loop in an embodiment of the present invention;

[0061] Figure 10 is a circuit schematic diagram of the target drive circuit in an embodiment of the present invention.

[0062] In the figure: 1, wafer; 2, battery management chip; 20, battery management unit; 21, control circuit; 22, switching transistor; 221, first switching transistor; 222, second switching transistor; 23, target control loop; 231, target drive circuit; 2311, first signal conversion circuit; 2312, second signal conversion circuit; 2313, level shift circuit; 2314, transistor network; 232, target switch tube; 233, overcharge and over-discharge detection circuit; 234, logic control circuit; 235, over-current protection circuit; 30, signal line. Detailed implementation manners

[0063] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0064] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout the drawings.

[0065] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be denoted as the second element, component, region, layer or part.

[0066] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0067] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0068] To fully understand the present invention, detailed structures and steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0069] This embodiment provides a method for packaging a battery management chip, asFigure 1 , including:

[0070] S101: Process at least two battery management units 20 on the wafer 1. Each battery management unit 20 includes a switching transistor 22, and the switching transistors 22 in two adjacent battery management units 20 are connected in parallel.

[0071] S102: Perform dicing on the wafer 1 to obtain target die. Each target die includes at least one battery management unit 20.

[0072] S103: Package each target die to obtain the battery management chip 2.

[0073] Among them, the wafer 1 refers to the silicon wafer used to fabricate silicon semiconductor circuits. Exemplarily, the wafer 1 can be obtained through existing wafer 1 processing technologies, and no limitation is made here. The battery management unit 20 refers to the unit for managing battery charging and discharging. The battery management unit 20 includes a switching transistor 22. The switching transistor 22 conducts during normal battery charging and discharging, so that the battery management chip 2 can charge and discharge normally; the switching transistor 22 turns off during abnormal charging and discharging to protect the battery management chip 2. The switching transistor 22 is a field effect transistor.

[0074] As an example, in step S101, at least two battery management units 20 are processed on the wafer 1. Each battery management unit 20 includes a switching transistor 22, and the switching transistors 22 in two adjacent battery management units 20 are connected in parallel. Exemplarily, a lithography process can be used to process at least two battery management units 20 on the wafer 1, or other processing processes can be used, as long as it is ensured that at least two battery management units 20 can be processed on the wafer 1.

[0075] As an example, in step S101, each battery management unit 20 includes a switching transistor 22, and the switching transistors 22 in two adjacent battery management units 20 are connected in parallel. In this example, since the Rds(ON) of the switching transistor 22 in each battery management unit 20 is too large when it is turned on, resulting in too large an internal resistance in each battery management unit 20. Therefore, by connecting the switching transistors 22 in two adjacent battery management units 20 in parallel, the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced. At the same time, the consistency of the switching transistors 22 in the two adjacent battery management units 20 is relatively high. Connecting the switching transistors 22 in the two adjacent battery management units 20 in parallel can avoid a large difference in Rds(ON) between the switching transistors 22 in the two parallel-connected battery management units 20, so as to ensure that the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced, thereby reducing the internal resistance of the two parallel-connected battery management units 20, further reducing the heat dissipation of the two parallel-connected battery management units 20, and improving the efficiency of the two parallel-connected battery management units 20.

[0076] The target die refers to the die of the wafer 1 obtained by dicing the wafer 1.

[0077] As an example, in step S102, the wafer 1 is diced to obtain a target die, and the target die includes at least one battery management unit 20. The number of battery management units 20 in the target die can be selected according to actual requirements or experience. Exemplarily, when the battery management chip 2 is required to have a large internal resistance, that is, a large Rds(ON) is required, one battery management unit 20 can be selected from the wafer 1 and diced to obtain a target die including one battery management unit 20. When the battery management chip 2 is required to have a small internal resistance, that is, a small Rds(ON) is required, at least two adjacent and parallel-connected battery management units 20 can be selected from the wafer 1 to obtain a target die including at least two battery management units 20. Since the switching transistors 22 in the two adjacent battery management units 20 are connected in parallel, the Rds(ON) presented by the at least two parallel-connected battery management units 20 can be reduced, thus meeting the low internal resistance requirement of the battery management chip 2. In this example, by dicing the wafer 1 to obtain a target die and ensuring that each target die includes at least one battery management unit 20, not only can a battery management chip 2 with a high internal resistance be produced in the subsequent steps, but also a battery management chip 2 with a low internal resistance can be produced, so as to meet different internal resistance requirements, that is, produce battery management chips 2 with different internal resistances based on one wafer 1, improve the production efficiency of the battery management chip 2, and reduce costs at the same time.

[0078] It should be noted that the wafer 1 can be diced using existing conventional dicing processes, as long as it is ensured that the obtained target die includes at least one battery management unit 20, and there is no limitation here.

[0079] As an example, in step S103, each target die is encapsulated to obtain a battery management chip 2. In this example, after step S102, since at least two battery management units 20 are processed on the wafer 1, after dicing the wafer 1, at least one target die can be obtained, and each target die includes at least one battery management unit 20. Therefore, after encapsulating each target die, at least one battery management chip 2 can be obtained. The at least one battery management chip 2 is a battery management chip 2 with one battery management unit 20 and / or a battery management chip 2 with at least two battery management units 20. In this example, existing chip packaging technologies can be used to encapsulate each target die, and there is no limitation here.

[0080] In this embodiment, at least two battery management units 20 are processed on the wafer 1. Each battery management unit 20 includes a switching transistor 22. The switching transistors 22 in two adjacent battery management units 20 are connected in parallel to ensure that the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced, thereby reducing the internal resistance of the two parallel-connected battery management units 20, further reducing the heat dissipation of the two parallel-connected battery management units 20, improving the efficiency of the two parallel-connected battery management units 20, and then dicing the wafer 1 to obtain a target die, where each target die includes at least one battery management unit 20, and encapsulating each target die to obtain a battery management chip 2, so that the battery management chip 2 can include one battery management unit 20 or at least two battery management units 20, thereby not only being able to produce battery management chips 2 with high internal resistance, but also being able to produce battery management chips 2 with low internal resistance, thus meeting different internal resistance requirements of the battery management chip 2, that is, producing battery management chips 2 with different internal resistances based on one wafer 1, improving the production efficiency of the battery management chip 2, and at the same time reducing costs.

[0081] In one embodiment, as Figure 4 shown, at least two battery management units 20 are distributed on the wafer 1 in an array form.

[0082] In this embodiment, distributing at least two battery management units 20 on the wafer 1 in an array form can reduce the occupied area of the wafer 1, improve the utilization rate of the wafer 1, reduce costs, and at the same time facilitate subsequent dicing of the wafer 1.

[0083] In one embodiment, as Figure 4As shown, the spacing distances between adjacent two battery management units 20 are equal.

[0084] In this embodiment, making the spacing distances between adjacent two battery management units 20 equal enables the battery management units 20 to be more evenly distributed on the wafer 1 and results in higher consistency for each finally generated battery management chip 2.

[0085] In one embodiment, as Figure 5 shown, each battery management unit 20 includes a control circuit 21 and a switching transistor 22; the input terminal of the control circuit 21 is the chip power supply terminal VDD of the battery management unit 20 for connecting to the positive electrode of the battery; the output terminal of the control circuit 21 is connected to the control terminal of the switching transistor 22; the first connection terminal of the switching transistor 22 is the ground terminal VSS of the battery management unit 20 for connecting to the negative electrode of the battery; the second connection terminal of the switching transistor 22 is the load connection terminal VM of the battery management unit 20 for connecting to an electrical load.

[0086] As an example, each battery management unit 20 includes a control circuit 21 and a switching transistor 22, and the control circuit 21 is used to control the charging and discharging processes of the battery. The switching transistor 22 conducts during normal charging and discharging of the battery so that the battery management chip 2 can charge and discharge normally; the switching transistor 22 turns off during abnormal charging and discharging to protect the battery management chip 2.

[0087] As an example, the input terminal of the control circuit 21 is the chip power supply terminal VDD of the battery management unit 20 for connecting to the positive electrode of the battery; the output terminal of the control circuit 21 is connected to the control terminal of the switching transistor 22; the first connection terminal of the switching transistor 22 is the ground terminal VSS of the battery management unit 20 for connecting to the negative electrode of the battery; the second connection terminal of the switching transistor 22 is the load connection terminal VM of the battery management unit 20 for connecting to an electrical load. In this example, during normal charging and discharging of the battery, the control circuit 21 controls the switching transistor 22 to conduct so that the battery can charge and discharge normally; when the battery is charging or discharging abnormally, such as overcharging, over-discharging, and overcurrent, the switching transistor 22 is controlled to turn off to protect the battery management chip 2.

[0088] As an example, the switching transistor 22 is a field effect transistor. The control terminal of the switching transistor 22 is the gate, the second connection terminal of the switching transistor 22 is the source, and the third connection terminal of the switching transistor 22 is the drain.

[0089] In this embodiment, the battery management unit 20 includes a control circuit 21 and a switching transistor 22. The battery management unit 20 in this embodiment can achieve charge and discharge control of the battery based on the control circuit 21 and a switching transistor 22, and can protect the battery during the charge and discharge processes.

[0090] In one embodiment, as Figure 6 shown, each battery management unit 20 includes a control circuit 21, a first switching transistor 221, and a second switching transistor 222. The input terminal of the control circuit 21 is the chip power supply terminal VDD of the battery management unit 20, and is used to connect to the positive electrode of the battery. The output terminal of the control circuit 21 is connected to the control terminal of the first switching transistor 221 and is also connected to the control terminal of the second switching transistor 222. The first connection terminal of the first switching transistor 221 is the ground terminal VSS of the battery management unit 20, and is used to connect to the negative electrode of the battery. The second connection terminal of the first switching transistor 221 is connected to the second connection terminal of the second switching transistor 222. The first connection terminal of the switching transistor 22 is the load connection terminal VM of the battery management unit 20, and is used to connect to an electrical load.

[0091] As an example, each battery management unit 20 includes a control circuit 21, a first switching transistor 221, and a second switching transistor 222. The control circuit 21 is used to control the charge and discharge processes of the battery. Any one of the first switching transistor 221 and the second switching transistor 222 participates in the battery charging process, and the other participates in the battery discharging process. For example, the first switching transistor 221 is used to participate in the battery charging process, and the second switching transistor 222 is used to participate in the battery discharging process.

[0092] As an example, the input terminal of the control circuit 21 is the power supply terminal VDD of the chip of the battery management unit 20, which is used to connect to the positive electrode of the battery; the output terminal of the control circuit 21 is connected to the control terminal of the first switching transistor 221 and is also connected to the control terminal of the second switching transistor 222; the first connection terminal of the first switching transistor 221 is the ground terminal VSS of the battery management unit 20, which is used to connect to the negative electrode of the battery; the second connection terminal of the first switching transistor 221 is connected to the second connection terminal of the second switching transistor 222; the first connection terminal of the switching transistor 22 is the load connection terminal VM of the battery management unit 20, which is used to connect to the electrical load. In this example, when the battery is normally charging and discharging, the control circuit 21 controls both the first switching transistor 221 and the second switching transistor 222 to conduct, so that the battery can be normally charged and discharged. When the battery is overcharged, the control circuit 21 controls the first switching transistor 221 to turn off, thereby protecting the battery from overcharging. When the battery is overdischarged, the control circuit 21 controls the second switching transistor 222 to turn off, thereby protecting the battery from overdischarging. When the control circuit 21 detects overcurrent through the load connection terminal VM, the control circuit 21 controls the second switching transistor 222 to turn off, thereby protecting the battery from overcurrent.

[0093] As an example, the first switching transistor 221 and the second switching transistor 222 are field effect transistors. The control terminal of the first switching transistor 221 is the gate, the first connection terminal of the first switching transistor 221 is the drain, and the second connection terminal of the first switching transistor 221 is the source. The control terminal of the second switching transistor 222 is the gate, the first connection terminal of the second switching transistor 222 is the drain, and the second connection terminal of the second switching transistor 222 is the source.

[0094] In this embodiment, the battery management unit 20 includes a control circuit 21, a first switching transistor 221, and a second switching transistor 222. Based on the control circuit 21, the first switching transistor 221, and the second switching transistor 222, the charging and discharging control of the battery can be realized, and the protection of the charging and discharging process of the battery can be realized.

[0095] In one embodiment, the switching transistors 22 in two adjacent battery management units 20 are connected in parallel, including: the power supply terminals VDD of the chips of two adjacent battery management units 20 are connected by a first signal line, the ground terminals VSS of two adjacent battery management units 20 are connected by a second signal line, the load connection terminals VM of two adjacent battery management units 20 are connected by a third signal line; the control terminals of the switching transistors 22 in two adjacent battery management units 20 are connected by a fourth signal line.

[0096] As an example, the chip power supply terminals VDD of two adjacent battery management units 20 are connected by a first signal line, the ground terminals VSS of two adjacent battery management units 20 are connected by a second signal line, and the load connection terminals VM of two adjacent battery management units 20 are connected by a third signal line; the control terminals of the switching transistors 22 in two adjacent battery management units 20 are connected by a fourth signal line, so that when any one of the two battery management units 20 detects an abnormal battery charge or discharge, the switching transistors 22 of the two battery management units 20 can be simultaneously controlled to turn off, realizing synchronous control of the switching transistors 22, avoiding the situation where one switching transistor 22 is turned on and the other switching transistor 22 is turned off, so as to ensure that the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced and the efficiency of the two parallel-connected battery management units 20 is improved.

[0097] As an example, since the switching transistors 22 in two battery management chips 2 are connected in parallel after packaging, additional wire bonding is required outside the battery management chips 2, and the additional wire bonding will bring parasitic resistance or inductance, etc., affecting the synchronous turn-off of the parallel-connected switching transistors 22. In this example, the switching transistors 22 in two adjacent battery management units 20 are pre-connected in parallel on the wafer 1, thereby avoiding the parasitic resistance or inductance, etc. brought by the additional wire bonding, ensuring that the switching transistors 22 in two adjacent parallel-connected battery management units 20 can be synchronously turned off when the battery charge or discharge is abnormal, so as to ensure that the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced and the efficiency of the two parallel-connected battery management units 20 is improved.

[0098] In this embodiment, the switching transistors 22 in two adjacent battery management units 20 are connected in parallel, including: the chip power supply terminals VDD of two adjacent battery management units 20 are connected by a first signal line, the ground terminals VSS of two adjacent battery management units 20 are connected by a second signal line, and the load connection terminals VM of two adjacent battery management units 20 are connected by a third signal line; the control terminals of the switching transistors 22 in two adjacent battery management units 20 are connected by a fourth signal line, avoiding the situation where one switching transistor 22 is turned on and the other switching transistor 22 is turned off, so as to ensure that the Rds(ON) presented by the two parallel-connected battery management units 20 is reduced and the efficiency of the two parallel-connected battery management units 20 is improved.

[0099] In one embodiment, the wafer 1 is diced to obtain a target die, as Figure 2 shown, including:

[0100] S201: Determine the area to be diced in the wafer 1.

[0101] S202: Determine at least one target battery management unit 20 located within the area to be scribed, and determine the adjacent battery management unit 20 located outside the area to be scribed and connected to the target battery management unit 20 through a signal line.

[0102] S203: Cut off the signal line between the target battery management unit 20 and the adjacent battery management unit 20 to obtain the target die corresponding to the area to be scribed.

[0103] Wherein, the area to be scribed refers to the area on the wafer 1 that needs to be scribed.

[0104] As an example, in step S201, the area to be scribed can be determined on the wafer 1 according to actual requirements or experience, so as to scribe the wafer 1 in subsequent steps.

[0105] Wherein, the target battery management unit 20 refers to the battery management unit 20 in the area to be scribed. The adjacent battery management unit 20 refers to the battery management unit 20 located outside the area to be scribed and connected to the target battery management unit 20 through a signal line.

[0106] As an example, in step S202, as Figure 7 shown, when a battery management chip 2 with a higher internal resistance is required, a target battery management unit 20 can be determined within the area to be scribed, and the adjacent battery management unit 20 located outside the area to be scribed and connected to the target battery management unit 20 through the signal line 30 can be determined. Or when a battery management chip 2 with a lower internal resistance is required, at least two target battery management units 20 can be determined within the area to be scribed, and the adjacent battery management unit 20 located outside the area to be scribed and connected to the at least two target battery management units 20 through the signal line 30 can be determined. Wherein, the signal line 30 includes the first signal line, the second signal line, the third signal line and the fourth signal line in the above embodiments, which will not be elaborated here.

[0107] As an example, in step S203, cut off the signal line 30 between the target battery management unit 20 and the adjacent battery management unit 20 to obtain the target die corresponding to the area to be scribed. In this example, by cutting off the signal line 30 between the target battery management unit 20 and the adjacent battery management unit 20 to obtain the target die corresponding to the area to be scribed, a target die with a high internal resistance or a low internal resistance can be obtained according to actual requirements, so as to generate battery management chips 2 with different internal resistances in subsequent steps and improve the production efficiency of the battery management chips 2.

[0108] In this embodiment, first determine the area to be scribed in the wafer 1, then determine at least one target battery management unit 20 located within the area to be scribed, and determine the adjacent battery management unit 20 located outside the area to be scribed and connected to the target battery management unit 20 through the signal line 30. Finally, scribe the signal line 30 between the target battery management unit 20 and the adjacent battery management unit 20 to obtain the target die corresponding to the area to be scribed, so that a target die with high internal resistance or a target die with low internal resistance can be obtained according to actual needs, and battery management chips 2 with different internal resistances can be generated in subsequent steps, improving the production efficiency of the battery management chips 2.

[0109] In one embodiment, as Figure 3 , in step S103, perform a packaging process on each target die to obtain the battery management chip 2, including:

[0110] S301: Process connection pads on the battery management chip 2.

[0111] S302: Electrically connect the battery management unit 20 to the connection pads.

[0112] Among them, the connection pads refer to the pads processed on the battery management chip 2, which are used to electrically connect the circuit units inside the battery management chip 2 to the circuit units outside the battery management chip 2.

[0113] As an example, in step S301, existing pad processing technologies can be used to process connection pads on the battery management chip 2. Optionally, the number of the connection pads can be set according to actual experience and is not limited here.

[0114] As an example, in step S302, electrically connect the battery management unit 20 to the connection pads to facilitate the electrical connection between the battery management unit 20 and the external circuit units.

[0115] In this embodiment, by processing connection pads on the battery management chip 2 and electrically connecting the battery management unit 20 to the connection pads, the electrical connection between the battery management unit 20 and the external circuit units can be achieved.

[0116] In one embodiment, as Figure 8As shown, the connection pad includes a target selection pad and a target control pad; the battery management unit 20 includes a target control circuit 23, and the target control circuit 23 includes a target drive circuit 231 and at least one target switch tube 232; the target drive circuit 231 is connected to the target selection pad, the target control pad, and the control end of each target switch tube 232; if the target selection pad is floating or coupled to the battery negative electrode, and the battery management chip 2 detects a battery abnormal signal, the target drive circuit 231 controls each target switch tube 232 to turn off; if the target selection pad is coupled to the battery positive electrode, according to the target control signal received by the target control pad, each target switch tube 232 is controlled to turn off, and the target control signal is a control signal output when an external circuit detects a battery abnormality.

[0117] As an example, the battery management unit 20 includes a target control circuit 23, and the target control circuit 23 is a circuit for controlling the battery to charge or discharge. The battery management unit 20 further includes a target selection pad sel and a target control pad sw. Exemplarily, the battery may be a lithium battery. The target control circuit 23 includes a target drive circuit 231 and at least one target switch tube 232.

[0118] Specifically, the connection pads on the battery management chip 2 include a target selection pad sel, a target control pad sw, a battery positive electrode pad vdd, a battery negative electrode pad vss, and a signal detection pad vm.

[0119] Exemplarily, the battery management chip 2 can be applied to a battery protection system, and the battery protection system includes a battery protector and a battery. The battery management chip 2 can be specifically applied to the battery protector. Preferably, the battery protector includes at least two parallel-connected battery management chips 2 to reduce the Rds(ON) in the battery protector, thereby reducing the overall impedance of the battery protector and avoiding the situation of overheating of the battery protector, so as to improve the efficiency of the battery protector.

[0120] Exemplarily, when the battery protector includes at least two battery management chips 2, the battery positive electrode pads vdd of the at least two battery management chips 2 are commonly connected to the battery positive electrode pin VDD of the battery protector, the battery negative electrode pads vss of the at least two battery management chips 2 are commonly connected to the battery negative electrode pin VSS of the battery protector, and the signal detection pads vm of the at least two battery management chips 2 are commonly connected to the signal detection pin VM of the battery protector.

[0121] As an example, the input terminal of the target driving circuit 231 is coupled to the battery positive pad vdd and the signal detection pad vm of the battery management chip 2, the output terminal of the target driving circuit 231 is coupled to the control terminal of each target switching transistor 232, the first terminal of each target switching transistor 232 is coupled to the battery negative pad vss, and the second terminal of each target switching transistor 232 is coupled to the signal detection pad vm. Wherein, the target switching transistor 232 is a field effect transistor, the first terminal of the target switching transistor 232 is the drain, the second terminal of the target switching transistor 232 is the source, and the third terminal of the target switching transistor 232 is the gate.

[0122] As an example, the battery protector includes at least two battery management chips 2 connected in parallel. When the target selection pad sel is floating or coupled to the battery negative electrode, and the battery management chip 2 detects an abnormal battery signal, the battery management chip 2 corresponding to the target selection pad sel floating or coupled to the battery negative electrode is the main chip, and the other battery management chips 2 in the battery protector are slave chips, then the target driving circuit 231 in the main chip controls each target switching transistor 232 to turn off.

[0123] As another example, when the target selection pad sel is coupled to the battery positive electrode, the battery management chip 2 corresponding to the target selection pad sel coupled to the battery positive electrode is a slave chip, then according to the target control signal received by the target control pad sw, each target switching transistor 232 is controlled to turn off, and the target control signal is a control signal output when an external circuit detects an abnormal battery. The external circuit is the main chip in the battery protector.

[0124] In this embodiment, by connecting the target driving circuit 231 to the target selection pad sel, the target control pad sw and the control terminals of each target switching transistor 232, and ensuring that when the target selection pad sel is floating or coupled to the battery negative electrode, and the battery management chip 2 detects an abnormal battery signal, the target driving circuit 231 controls each target switching transistor 232 to turn off, and at the same time when the target selection pad sel is coupled to the battery positive electrode, according to the target control signal received by the target control pad sw, each target switching transistor 232 is controlled to turn off, and the target control signal is a control signal output when an external circuit detects an abnormal battery, so that when the battery protector includes at least two parallel-connected battery management chips 2, the Rds(ON) in the battery protector is reduced, and further the overall impedance of the battery protector is reduced, avoiding the situation that the temperature of the battery protector is too high, and at the same time avoiding the situation that the target switching transistor 232 in one battery management chip 2 is turned on and the target switching transistor 232 in another battery management chip 2 is turned off, so as to reduce the overall impedance of the battery protector and avoid the situation that the temperature is too high, thereby improving the efficiency of the battery protector.

[0125] In one embodiment, the connection pad further includes a battery positive electrode pad; the target control loop 23 further includes a logic control circuit 234. The input end of the logic control circuit 234 is coupled to the battery positive electrode pad and the signal detection pad of the battery management chip 2. The output end of the logic control circuit 234 is connected to the target drive circuit 231, and is used for detecting battery abnormal signals and outputting target control signals.

[0126] As an example, the target control loop 23 further includes a logic control circuit 234. The input end of the logic control circuit 234 is coupled to the battery positive electrode pad vdd and the signal detection pad vm of the battery management chip 2. The output end of the logic control circuit 234 is connected to the target drive circuit 231, and is used for detecting battery abnormal signals and outputting target control signals. In this embodiment, when the target selection pad sel in the battery management chip 2 is floating or coupled to the battery negative electrode, and the battery management chip 2 detects a battery abnormal signal, the logic control circuit 234 receives this battery abnormal signal and outputs a target control signal to control the target switch tube 232 to turn off.

[0127] Further, in one embodiment, as Figure 9 shown, the target control loop 23 further includes an overcharge and overdischarge detection circuit 233 and an overcurrent protection circuit 235; the first end of the overcharge and overdischarge detection circuit 233 is connected to the battery positive electrode pad vdd, and the second end of the overcharge and overdischarge detection circuit 233 is connected to the logic control circuit 234, and is used for overcharge and overdischarge detection and outputting overcharge and overdischarge detection signals; the first end of the overcurrent protection circuit 235 is connected to the second end of the target switch tube 232 and the battery negative electrode pad vss, and the second end of the overcurrent protection circuit 235 is connected to the logic control circuit 234, and is used for overcurrent detection and outputting overcurrent detection signals. The logic control circuit 234 is connected to the target drive circuit 231, and is used for outputting target control signals according to the overcharge and overdischarge detection signals and / or the overcurrent detection signals; the target drive circuit 231 is connected to the target control pad sw and the target selection pad sel, and is used for outputting transistor drive signals to the target control pad sw according to the target control signals.

[0128] In this embodiment, the overcharge and over-discharge detection circuit 233 determines whether the battery is overcharged or over-discharged by detecting the charging voltage or discharging voltage of the battery, and outputs an overcharge and over-discharge detection signal according to the charging voltage or discharging voltage of the battery. Among them, overcurrent detection refers to detecting the charging current or discharging current of the battery. The logic control circuit 234 receives the overcharge and over-discharge detection signal and / or the overcurrent detection signal, and performs logic processing on the overcharge and over-discharge detection signal and / or the overcurrent detection signal. When the battery charging and discharging is abnormal, a target control signal is output. If the target selection pad sel is floating or coupled to the negative electrode of the battery, and the battery management chip 2 detects an abnormal battery signal, the target drive circuit 231 controls each target switch 232 to turn off; if the target selection pad sel is coupled to the positive electrode of the battery, then according to the target control signal received by the target control pad sw, each target switch 232 is controlled to turn off, and the target control signal is a control signal output when an external circuit detects an abnormal battery.

[0129] In one embodiment, as Figure 10 shown, the target drive circuit 231 includes a first signal conversion circuit 2311, a second signal conversion circuit 2312, a level shift circuit 2313, and a transistor network 2314; the first input end of the first signal conversion circuit 2311 is connected to the output end of the logic control circuit 234, the second signal conversion circuit 2312 is connected to the target selection pad, and the output end of the first signal conversion circuit 2311 is connected to the input end of the level shift circuit 2313, and is used to output a first conversion signal according to the target control signal output by the logic control circuit 234 and the level signal corresponding to the target selection pad; the first input end of the second signal conversion circuit 2312 is connected to the target selection pad, the second input end of the second signal conversion circuit 2312 is connected to the negative electrode pad of the battery, and the output end of the second signal conversion circuit 2312 is connected to the first input end of the transistor network 2314, and is used to output a second conversion signal according to the level signal corresponding to the target selection pad; the second input end of the transistor network 2314 is connected to the output end of the level shift circuit 2313, the third input end of the transistor network 2314 is connected to the target selection pad, and the transistor network 2314 is used to enter the target working mode according to the first conversion signal, the second conversion signal, and the level signal corresponding to the target selection pad, and outputs a transistor drive signal to the target control pad in the target working mode.

[0130] Among them, the target working mode of the transistor network 2314 is the normal working mode. The transistor network 2314 further includes a high impedance working mode.

[0131] As an example, when the battery management chip 2 serves as the main chip in the battery protector, that is, when the target selection pad sel in the battery management chip 2 floats or is connected to the battery negative pad vss, the transistor network 2314 in the target drive circuit 231 is used to enter the normal working mode according to the first conversion signal, the second conversion signal, and the level signal corresponding to the target selection pad sel. When the battery management chip 2 detects an abnormal battery signal, it controls the target switch 232 to turn off.

[0132] As another example, when the battery management chip 2 serves as the slave chip in the battery protector, that is, when the target selection pad sel is connected to the battery positive pad vdd, the transistor network 2314 in the battery management chip 2 is used to enter the high-impedance working mode according to the first conversion signal, the second conversion signal, and the level signal corresponding to the target selection pad sell. When the external circuit detects an abnormal battery output, that is, when the main chip in the battery protection device detects an abnormal battery output, the main chip outputs a target control signal to the target control pad sw to control the target switch 232 to turn off.

[0133] In this example, according to different electrical connection methods of the target selection pad sel, among at least two battery chips in the battery protector, one chip is the main chip and the remaining chips are slave chips. When the main chip detects an abnormal battery signal, it controls the switches in all chips to turn off, avoiding the situation where some switches are on and some are off, so as to reduce the Rds(ON) in the battery protector, thereby reducing the overall impedance of the battery protector and preventing the battery protector from overheating.

[0134] In one embodiment, as Figure 10 shown, the first signal conversion circuit 2311 includes a first inverter P11 and a nor gate circuit NG1; the input end of the first inverter P11 is connected to the output end of the logic control circuit 234, the output end of the first inverter P11 is connected to the first input end of the nor gate circuit NG1, the second input end of the nor gate circuit NG1 is connected to the target selection pad, and the output end of the nor gate circuit NG1 is connected to the input end of the level shift circuit 2313.

[0135] As an example, when the battery management chip 2 serves as the main chip, that is, when the target selection pad sel is floating or connected to the battery negative pad vss, the level signal corresponding to the target selection pad sel is low. When the battery management chip 2 does not detect an abnormal battery signal, the target control signal is high. After passing through the first inverter P11, the target control signal becomes low. The level signal corresponding to the target selection pad sels received by the first input terminal of the NOR gate circuit NG1 is low, and the level signal output by the first inverter P11 received by the second input terminal of the NOR gate circuit NG1 is low. Therefore, the first conversion signal output by the NOR gate circuit NG1 is high. Similarly, when the battery management chip 2 detects an abnormal battery signal, the target control signal is low. After passing through the first inverter P11, the target control signal becomes high. The level signal corresponding to the first selection pad sel received by the first input terminal of the NOR gate circuit NG1 is low, and the level signal output by the first inverter P11 received by the second input terminal of the NOR gate circuit NG1 is high. Therefore, the first conversion signal output by the NOR gate circuit NG1 is low.

[0136] As an example, when the battery management chip 2 serves as a slave chip, that is, when the target selection pad sel is connected to the battery positive pad vdd, the level signal corresponding to the target selection pad sel is high. When the battery management chip 2 does not detect an abnormal battery signal, the target control signal is high. After passing through the first inverter P11, the target control signal becomes low. The level signal corresponding to the target selection pad sel received by the first input terminal of the NOR gate circuit NG1 is high, and the level signal output by the first inverter P11 received by the second input terminal of the NOR gate circuit NG1 is low. Therefore, the first conversion signal output by the NOR gate circuit NG1 is low. When the battery management chip 2 does not detect an abnormal battery signal, the target control signal is low. After passing through the first inverter P11, the target control signal becomes high. The level signal corresponding to the target selection pad sel received by the first input terminal of the NOR gate circuit NG1 is high, and the level signal output by the first inverter P11 received by the second input terminal of the NOR gate circuit NG1 is high. Therefore, the first conversion signal output by the NOR gate circuit NG1 is low. That is, when the battery management chip 2 serves as a slave chip, regardless of whether the battery management chip 2 detects an abnormal battery signal, the first signal conversion circuit 2311 outputs a low level. Therefore, by using the battery management chip 2 in the external circuit as the main chip, when an abnormal signal is detected, the target control signal is output to control each target switch 232 to turn off.

[0137] In one embodiment, as Figure 10As shown in the figure, the second signal conversion circuit 2312 includes a second inverter P12 and a first resistor R1; the first end of the first resistor R1 is connected to the battery negative pad, the second end of the first resistor R1 is connected to the target selection pad and the input end of the second inverter P12, and the output end of the second inverter P12 is connected to the first input end of the transistor network 2314.

[0138] As an example, when the battery management chip 2 serves as the main chip, that is, when the target selection pad selsel is floating or connected to the battery negative pad vss, the level signal corresponding to the target selection pad sel is low, and the input end of the second inverter P12 is low due to the weak pull-down of the first resistor R1. Therefore, the second conversion signal output by the output end of the second inverter P12 is high.

[0139] As an example, when the battery management chip 2 serves as the main chip, that is, when the target selection pad sel is connected to the battery positive pad vdd, the level signal corresponding to the target selection pad sel is high. Therefore, the second conversion signal output by the output end of the second inverter P12 is low.

[0140] In this example, by connecting the first end of the first resistor R1 to the battery negative pin VSS, the second end of the first resistor R1 to the first selection pad sel and the input end of the second inverter P12, and the output end of the second inverter P12 to the first input end of the transistor network 2314, the second signal conversion circuit 2312 outputs second conversion signals of different levels according to different electrical connection modes of the target selection pad sel.

[0141] This embodiment provides a battery management chip 2, which is a chip encapsulated by using the above-mentioned battery management chip encapsulation method.

[0142] This embodiment provides a battery protection system, including the above-mentioned battery management chip 2 and a battery connected to the battery management chip 2.

[0143] This embodiment provides an electronic device, including the above-mentioned battery protection system.

[0144] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for packaging a battery management chip, characterized in that Comprising: Processing at least two battery management units on a wafer, each of the battery management units including a switching transistor, and the switching transistors in two adjacent battery management units being connected in parallel; Performing dicing on the wafer to obtain target dies, each of the target dies including at least one of the battery management units; Performing packaging on each target die to obtain a battery management chip; The performing dicing on the wafer to obtain target dies includes: Selecting one of the battery management units from the wafer and performing dicing to obtain a target die including one of the battery management units; Or, selecting at least two adjacent and parallel-connected battery management units from the wafer to obtain a target die including at least two of the battery management units; Each of the battery management units includes a control circuit, a first switching transistor, and a second switching transistor; An input terminal of the control circuit is a chip power supply terminal of the battery management unit and is used for connecting to a positive electrode of a battery; An output terminal of the control circuit is connected to a control terminal of the first switching transistor and is also connected to a control terminal of the second switching transistor; A first connection terminal of the first switching transistor is a grounding terminal of the battery management unit and is used for connecting to a negative electrode of a battery; a second connection terminal of the first switching transistor is connected to a second connection terminal of the second switching transistor; a first connection terminal of the second switching transistor is a load connection terminal of the battery management unit and is used for connecting to an electrical load.

2. The battery management chip packaging method according to claim 1, wherein At least two of the battery management units are distributed on the wafer in an array form.

3. The battery management chip packaging method according to claim 2, wherein, The spacing distance between two adjacent battery management units is equal.

4. The battery management chip packaging method according to claim 1, characterized in that The switching transistors in two adjacent battery management units being connected in parallel includes: The chip power supply terminals of two adjacent battery management units are connected by a first signal line, the grounding terminals of two adjacent battery management units are connected by a second signal line, and the load connection terminals of two adjacent battery management units are connected by a third signal line; The control terminals of the switching transistors in two adjacent battery management units are connected by a fourth signal line.

5. The battery management chip packaging method according to claim 1, wherein The performing dicing on the wafer to obtain target dies includes: Determining a to-be-diced area in the wafer; Determining at least one target battery management unit located in the to-be-diced area and determining an adjacent battery management unit located outside the to-be-diced area and connected to the target battery management unit by a signal line; Cutting off the signal line between the target battery management unit and the adjacent battery management unit to obtain a target die corresponding to the to-be-diced area.

6. The battery management chip packaging method according to claim 1, wherein, The performing packaging on each target die to obtain a battery management chip includes: Processing connection pads on the battery management chip; Electrically connecting the battery management unit to the connection pads.

7. The battery management chip packaging method according to claim 6, characterized in that, The connection pads include target selection pads and target control pads; the battery management unit includes a target control loop, and the target control loop includes a target drive circuit and at least one target switching tube; The target drive circuit is connected to the target selection pads, the target control pads, and the control terminals of each of the target switching tubes; If the target selection pad is floating or coupled to the negative electrode of the battery, and the battery management chip detects an abnormal battery signal, the target drive circuit controls each of the target switching tubes to turn off; If the target selection pad is coupled to the positive electrode of the battery, each of the target switching tubes is controlled to turn off according to the target control signal received by the target control pad, and the target control signal is a control signal output when an external circuit detects an abnormal battery.

8. The battery management chip packaging method according to claim 7, wherein, The connection pad further includes a signal detection pad and a battery negative pad; The first end of the target switching tube is connected to the signal detection pad; the second end of the target switching tube is connected to the battery negative pad, and the third end of the target switching tube is a control end.

9. The battery management chip packaging method according to claim 8, wherein, The connection pad further includes a battery positive pad; The target control loop further includes a logic control circuit, the input end of the logic control circuit is coupled to the battery positive pad and the signal detection pad of the battery management chip, and the output end of the logic control circuit is connected to the target drive circuit, and is used to detect the abnormal battery signal and output a target control signal.

10. The battery management chip packaging method according to claim 9, wherein, The target drive circuit includes a first signal conversion circuit, a second signal conversion circuit, a level shift circuit and a transistor network; The first input end of the first signal conversion circuit is connected to the output end of the logic control circuit, the second signal conversion circuit is connected to the target selection pad, and the output end of the first signal conversion circuit is connected to the input end of the level shift circuit, and is used to output a first conversion signal according to the target control signal output by the logic control circuit and the level signal corresponding to the target selection pad; The first input end of the second signal conversion circuit is connected to the target selection pad, the second input end of the second signal conversion circuit is connected to the battery negative pad, and the output end of the second signal conversion circuit is connected to the first input end of the transistor network, and is used to output a second conversion signal according to the level signal corresponding to the target selection pad; The second input end of the transistor network is connected to the output end of the level shift circuit, the third input end of the transistor network is connected to the target selection pad, and the transistor network is used to enter a target working mode according to the first conversion signal, the second conversion signal and the level signal corresponding to the target selection pad, and output a transistor drive signal to the target control pad in the target working mode.

11. The battery management chip packaging method according to claim 10, wherein, The first signal conversion circuit includes a first inverter and a NOR gate circuit; The input end of the first inverter is connected to the output end of the logic control circuit, the output end of the first inverter is connected to the first input end of the NOR gate circuit, the second input end of the NOR gate circuit is connected to the target selection pad, and the output end of the NOR gate circuit is connected to the input end of the level shift circuit.

12. The battery management chip packaging method according to claim 11, wherein, The second signal conversion circuit includes a second inverter and a first resistor; The first end of the first resistor is connected to the negative electrode pad of the battery, the second end of the first resistor is connected to the target selection pad and the input end of the second inverter, and the output end of the second inverter is connected to the first input end of the transistor network.

13. A battery management chip, characterized in that, The battery management chip is a chip encapsulated by using the battery management chip encapsulation method according to any one of claims 1 to 12.

14. A battery protection system, characterized in that, It includes the battery management chip according to claim 13 and a battery connected to the battery management chip.

15. An electronic device, characterized in that, It includes a battery protection system according to claim 14.

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