Display panel and preparation method of display panel

Abstract

Embodiments of the present application provide a display panel and a preparation method of the display panel. The display panel comprises an active layer, a gate, a source / drain metal layer and a first conductive layer, wherein the source / drain metal layer is stacked with the first conductive layer in the non-display area. The first conductive layer is arranged in the light-emitting area and the non-light-emitting area, and the thickness of the first conductive layer is smaller than that of the source / drain metal layer. In the embodiments of the present application, by reducing the thickness of the corresponding first conductive layer in the light-emitting area, a flat anode can be obtained after depositing other film layers on the thinner first conductive layer, so that the light-emitting film layers have the same thickness, and the light-emitting effect of the panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Technology

[0002] With the development of display technology, organic light-emitting diode (OLED) display devices have become increasingly mature and are being used more and more in various display fields.

[0003] The fabrication of the aforementioned OLED devices requires multiple processing steps, and the quality of each step significantly impacts the overall performance of the display panel. Typically, an array substrate is first fabricated, and multiple signal lines corresponding to thin-film transistors are then positioned on this substrate. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of the wiring structure of an array substrate provided in the prior art. The array substrate includes a light-emitting region 100 and a non-light-emitting region 101. Multiple signal lines 102 are disposed within the non-light-emitting region 101. Simultaneously, different functional layers, such as different first functional layers 103 and second functional layers 104, and a planarization layer, are disposed at the corresponding light-emitting pixel regions within the light-emitting region. These different functional layers form a certain stacking structure, which causes unevenness on the surface of the film layers within the light-emitting pixel region, such as height discontinuities. When other film layers are deposited on these discontinuous film layers, such as when a light-emitting layer is deposited within the light-emitting region, the resulting light-emitting layer exhibits inconsistent thickness after deposition. When the display panel is emitting light normally, the uneven thickness of the light-emitting layer results in different light-emitting effects in different areas, thereby reducing the display effect of the display panel.

[0004] In summary, in existing display panels, during the fabrication of the array substrate, there are discontinuities on the array substrate. When other film layers are fabricated on the array substrate with discontinuities, the fabricated film layers have different thicknesses in different areas, thereby reducing the display effect of the display panel. Summary of the Invention

[0005] This invention provides a display panel and a method for manufacturing the display panel. It effectively addresses the technical problem in OLED display panels where discontinuities exist on the array substrate within the light-emitting pixel region. These discontinuities cause the corresponding light-emitting layer in the light-emitting region to have different thicknesses at different locations, leading to unsatisfactory light-emitting performance in the display panel.

[0006] To address the aforementioned technical problems, the present invention provides a display panel comprising a plurality of pixel units, each pixel unit including a light-emitting region and a non-light-emitting region disposed on at least one side of the light-emitting region, characterized in that it comprises:

[0007] Substrate;

[0008] An active layer is disposed on the substrate;

[0009] A gate, wherein the gate is disposed on the active layer;

[0010] An interlayer dielectric layer disposed on the gate; and,

[0011] A source / drain metal layer is disposed on the interlayer dielectric layer and electrically connected to the active layer;

[0012] A first conductive layer is disposed on the interlayer dielectric layer;

[0013] The source / drain metal layer is disposed in the non-light-emitting area, and is disposed on the first conductive layer and electrically connected to the first conductive layer. The thickness of the first conductive layer is less than the thickness of the source / drain metal layer.

[0014] According to one embodiment of the present invention, the first conductive layer is disposed in the light-emitting region and the non-light-emitting region, and the orthographic projection of the source / drain metal layer on the interlayer dielectric layer is located within the orthographic projection of the first conductive layer on the interlayer dielectric layer.

[0015] According to one embodiment of the present invention, the thickness of the first conductive layer in the light-emitting region is less than the thickness of the first conductive layer in the non-light-emitting region.

[0016] According to one embodiment of the present invention, the material of the first conductive layer includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide, and the material of the source / drain metal layer includes any one of Cu, Al, Ag, and copper / molybdenum-titanium alloy.

[0017] According to one embodiment of the present invention, the display panel further includes a first via, and the first conductive layer is disposed in the first via and electrically connected to the active layer.

[0018] According to one embodiment of the present invention, the drain electrode in the source / drain metal layer is at least partially disposed on the first conductive layer and electrically connected to the first conductive layer.

[0019] According to one embodiment of the present invention, the display panel further includes a light-shielding layer disposed between the substrate and the active layer.

[0020] According to one embodiment of the present invention, the light-shielding layer is provided in at least two layers in the light-emitting area and the non-light-emitting area.

[0021] According to one embodiment of the present invention, the display panel further includes a second via, the second via being disposed on one side of the drain electrode, and the first conductive layer being electrically connected to the light-shielding layer through the second via.

[0022] According to one embodiment of the present invention, the display panel further includes a passivation layer disposed on the interlayer dielectric layer;

[0023] A planarization layer is disposed on the passivation layer;

[0024] An electrode layer is disposed at least in the light-emitting area, the electrode layer is disposed on the planarization layer, and the electrode layer is electrically connected to the first conductive layer through a third via.

[0025] The passivation layer has a thickness in the light-emitting region that is less than that in the non-light-emitting region, and the upper surface of the electrode layer in the light-emitting region is a plane.

[0026] According to one embodiment of the present invention, the display panel further includes a barrier wall disposed in the non-light-emitting area and disposed on the planarization layer.

[0027] According to a second aspect of the present invention, a display panel is also provided, including a light-emitting area and a non-light-emitting area disposed on one side above the light-emitting area, comprising:

[0028] Display panel;

[0029] An electrode layer, the electrode layer being disposed on the display panel; and,

[0030] A light-emitting layer is disposed on the electrode layer and correspondingly disposed within the light-emitting area;

[0031] The display panel mentioned herein is the display panel provided in the embodiments of this application.

[0032] According to a third aspect of the present invention, a method for manufacturing a display panel is also provided, comprising the following steps:

[0033] A substrate is provided, and a thin-film transistor device layer is formed on the substrate, wherein the thin-film transistor device layer includes an active layer, a gate disposed on the active layer, and an interlayer dielectric layer disposed on the gate.

[0034] Etching and forming vias on the thin-film transistor device layer, and fabricating a first conductive layer on the thin-film transistor device layer, so that the first conductive layer is electrically connected to the active layer through the vias;

[0035] A source / drain metal layer is prepared on the first conductive layer, and a photoresist is prepared on the source / drain metal layer. The first conductive layer and the source / drain metal layer are etched for the first time using the photoresist to form multiple openings. The photoresist has a different thickness in different regions.

[0036] Another photoresist is fabricated on the source / drain metal layer, and the source / drain metal layer is etched a second time using a half-mask process to fabricate the source and drain of the thin film transistor.

[0037] A passivation layer is prepared on the source / drain metal layer and the first conductive layer, and a planarization layer is prepared on the passivation layer, and a third via is etched to form the via.

[0038] An electrode layer is formed on the planarization layer, wherein the electrode layer is electrically connected to the first conductive layer through the third via;

[0039] An inkjet-printed light-emitting layer is formed on the electrode layer, and the light-emitting layer is then dried and cured.

[0040] The beneficial effects of the embodiments of the present invention: The embodiments of the present invention provide an array substrate, a display panel, and a method for fabricating the array substrate. The array substrate includes a substrate, an active layer, a gate, a source / drain metal layer, and a first conductive layer, wherein the source / drain metal layer is stacked with the first conductive layer in the non-display area. The first conductive layer is disposed in both the light-emitting area and the non-light-emitting area, and the thickness of the first conductive layer is less than the thickness of the source / drain metal layer. In the embodiments of this application, by reducing the thickness of the first conductive layer corresponding to the light-emitting area, a planarized anode can be obtained after depositing other film layers on the thinner first conductive layer, thereby ensuring that the thickness of the light-emitting film layers is the same. This improves the light-emitting effect and overall performance of the display panel. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the wiring structure of an array substrate provided in the prior art;

[0043] Figure 2 This is a schematic diagram of the planar wiring of an array substrate provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the film structure corresponding to the array substrate provided in the embodiments of this application;

[0045] Figures 4-7 This is a schematic diagram of the film structure corresponding to the array substrate fabrication process provided in the embodiments of this application. Detailed Implementation

[0046] The following description, in conjunction with the accompanying drawings of the embodiments of the present invention, provides different implementation methods or examples to realize different structures of the present invention. To simplify the present invention, the components and arrangements of specific examples are described below. Furthermore, the various specific processes and materials provided in the present invention are examples that those skilled in the art will recognize for the application of other processes. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0048] The performance of a display panel depends on various factors, such as the manufacturing process and the performance of the functional films within the panel. Maintaining high luminous efficacy requires optimizing the performance of the corresponding films. However, in existing technologies, significant discontinuities exist during the fabrication of the luminescent layer, particularly in the production of the light-emitting layer. This results in uneven thickness of the luminescent layer across different luminescent regions, ultimately reducing the panel's luminous efficacy and overall performance.

[0049] This application provides an array substrate and a display panel to effectively improve problems such as large film layer discontinuities and inconsistent film layer thicknesses in different areas of the display panel.

[0050] like Figure 2 As shown, Figure 2This is a schematic diagram of planar wiring for a display panel provided in an embodiment of this application. In this embodiment, the display panel includes multiple pixel units, wherein each pixel unit includes a light-emitting region 100 and a non-light-emitting region 101. The non-light-emitting region 101 may be disposed at least on one side of the light-emitting region 100. In this embodiment, the array substrate includes a substrate (the substrate film layer diagram is not shown in the figure) and signal lines 102 disposed on the substrate. In this embodiment, the wiring layer corresponding to the signal line 102 may be various different signal lines, such as scan signal lines, data signal lines, and other different signal lines such as common electrodes.

[0051] During the fabrication process, other functional film layers, such as a first functional layer 103 and a second functional layer 104, need to be formed within the light-emitting region 100 of the array substrate. The first functional layer 103 can be a metal layer, and the second functional layer 104 is a light-emitting layer. Control signals are provided to the second functional layer 104 through the first functional layer 103. The light-emitting layer is used to realize the light-emitting display function of the display panel.

[0052] However, in existing technologies, such as Figure 1 The substrate surface of the first functional layer 103 prepared in the process is not flat. When the second functional layer 104 is prepared on the uneven substrate surface, the second functional layer 104 will have a certain height difference or discontinuity difference. Therefore, when the second functional layer 104 is observed in the top view, the height difference at different positions will correspond to multiple cross-sectional lines 1041 in the view. In the embodiment of this application, by changing the film layer structure in the display panel, such as setting a thinner first conductive layer 307 in the display panel, when other film layers are deposited on the first conductive layer 307, since the thickness of the first conductive layer 307 is relatively thin, the surface of the first functional layer 103 obtained by deposition can be a horizontal plane. When the second functional layer 104 is prepared on this plane, the second functional layer 104 is also a planar structure, thereby solving the problem of the second functional layer 104 having the same thickness at different positions, effectively improving the manufacturing process of the display panel, and effectively improving the light emission display effect of the display panel.

[0053] like Figure 3 As shown, Figure 3 This is a schematic diagram of the film layer structure corresponding to the array substrate provided in an embodiment of this application. The array substrate includes a substrate 300 and a thin-film transistor (TFT) device layer. The TFT device layer is disposed on the substrate 300, and thin-film transistors and dielectric layers are disposed within the TFT device layer. Preferably, the substrate 300 can be a rigid layer or a flexible layer, such as a glass layer or a polyimide film layer. The substrate 300 provides effective support and cushioning.

[0054] Furthermore, in this embodiment, a thin-film transistor 38 is also disposed within the thin-film transistor device layer. The thin-film transistor 38 is used to transmit control signals. Specifically, the thin-film transistor device layer further includes: a first buffer layer 301, a light-shielding layer 312, an interlayer dielectric layer 302, and a gate insulating layer 310.

[0055] Meanwhile, the thin-film transistor 38 includes an active layer 311, a gate 309, and source / drain metal layers. In the following embodiment, the source / drain metal layers include a source 316 and a drain 315. The source 316 and drain 315 are electrically connected to the active layer 311 through vias.

[0056] Specifically, the light-shielding layer 312 is disposed on the substrate 300, and the first buffer layer 301 is disposed on the substrate 300, and the first buffer layer 301 covers the light-shielding layer 312. In this embodiment, the light-shielding layer 312 is a metal light-shielding layer, such as aluminum.

[0057] Furthermore, the active layer 311 is disposed on the first buffer layer 301, the gate insulating layer 310 is disposed on the active layer 311, and the gate 309 is disposed on the gate insulating layer 310. At the same time, the interlayer dielectric layer 302 is disposed on the gate 309 and completely covers the active layer 311, the gate insulating layer 310, and the gate 309.

[0058] In this embodiment, when setting the above-mentioned film layers, the source / drain metal layer is disposed in the non-light-emitting area, and the active layer 311 can be patterned and disposed on the first buffer layer 301. In this embodiment, the active layer 311 is disposed in the light-emitting area 100 and the non-light-emitting area 101. In the non-light-emitting area 101, a capacitor structure is formed between the active layer 311 and the gate 309 of the thin-film transistor. At the same time, in the light-emitting area 100, another capacitor structure is formed between the active layer 311 and other metal layers. For example, the active layer 311 can form another capacitor structure with the bottom light-shielding layer 312, or with the metal layer above it. When the device is working normally, the capacitor structure can further improve the device's anti-electrostatic interference capability and ensure that the display panel has good working performance.

[0059] Furthermore, the source 316 is disposed on the interlayer dielectric layer 302, and the drain 315 is disposed on the interlayer dielectric layer 302. At the same time, the source 316 is electrically connected to the active layer 311 through the first via 31, and the drain 315 is electrically connected to the active layer 311 through another first via 41, thereby realizing the normal operation of the thin-film transistor.

[0060] In this embodiment of the application, when setting the array substrate, the array substrate further includes a first conductive layer 307. Specifically, the first conductive layer 307 is disposed on the interlayer dielectric layer 302. The source / drain metal layer is disposed on the first conductive layer 307 and electrically connected to the first conductive layer 307.

[0061] In this embodiment, the first conductive layer 307 is disposed within the light-emitting region 100 and the non-light-emitting region 101 of the display panel, while the source electrode 316 and the drain electrode 315 are disposed within the corresponding region of the non-light-emitting region 101. Thus, the source / drain metal layer and the first conductive layer 307 form a stack with different thicknesses within the light-emitting region 100 and the non-light-emitting region 101.

[0062] In this embodiment, the thickness of the first conductive layer 307 can be [missing information]. Meanwhile, the thickness of the source / drain metal layer can be Specifically, in this embodiment of the application, the thickness of the first conductive layer 307 is set to... Meanwhile, the thickness of the source / drain metal layer is set to This achieves a thinner inner film layer in the display panel while ensuring the performance of the film layer, thereby improving the performance of the display panel. In this embodiment, since the thickness of the first conductive layer 307 is much smaller than the thickness of the source / drain metal layer, a relatively flat deposition surface can be obtained when other films are deposited on the first conductive layer 307, such as an anode with high flatness. Then, a light-emitting layer is deposited on the flat anode. The light-emitting layer has the same thickness at different locations, thereby ensuring the light-emitting effect of the display panel.

[0063] In this embodiment, within the non-light-emitting region 101, both the source electrode 316 and the drain electrode 315 form a stacked structure with the first conductive layer 307. On the corresponding stacked structure, the width of the source electrode 316 and the drain electrode 315 may be smaller than the width of the first conductive layer 307.

[0064] Furthermore, in this embodiment, the film thickness of the source 316 and drain 315 is greater than the thickness of the first conductive layer 307, thereby reducing the impact of etching on the source / drain metal layer and ensuring the reliability of the device. Simultaneously, the orthographic projections of the source 316 and drain 315 onto the interlayer dielectric layer 302 lie within the orthographic projection of the first conductive layer 307 onto the interlayer dielectric layer, ensuring that the source / drain metal layer is completely disposed on the first conductive layer and guaranteeing the contact effect between the two different metal layers.

[0065] Furthermore, at the corresponding positions of the first via 31 and the other first via 41, the first conductive layer 307 can fill the first via and be electrically connected to the active layer 311. At the same time, the source / drain metal layer also fills the first via and is electrically connected to the first conductive layer.

[0066] In this embodiment of the application, the location corresponding to the drain electrode 315 includes an overlapping region 381 and a non-overlapping region 382. The overlapping region 381 is disposed within the non-light-emitting region 101, and the non-overlapping region 382 is at least partially disposed within the light-emitting region, and the non-overlapping region 382 is disposed on the side closer to the light-emitting region 100.

[0067] Within the overlapping region 381, a drain 315 is disposed on the first conductive layer 307 to form a double-layer structure. Within the non-overlapping region 382, ​​only one layer of metal is disposed, such as only the first conductive layer 307.

[0068] In this embodiment, within the region corresponding to the drain 315 and the first conductive layer 307, the area where the drain 315 and the first conductive layer 307 are in contact is the overlapping area of ​​the two. The overlapping area corresponding to the overlapping region 381 may be smaller than the area corresponding to the non-overlapping region 382. Simultaneously, a second via 51 is also provided within the non-overlapping region, and the second via 51 is located at a corresponding position on the side of the drain near the light-emitting region.

[0069] Furthermore, within the overlapping region 381, the width of the drain 315 is smaller than the width of the first conductive layer 307 corresponding to the drain 315. In this embodiment, the drain 315 is disposed on the first conductive layer and on one side of the first conductive layer 307, while the non-overlapping region 382 is disposed on the side closer to the pixel opening 80. This avoids interference between the drain 315 and the pixel opening 80 and ensures that the pixel opening 80 of the display panel has a large opening area.

[0070] Specifically, the first conductive layer 307 is electrically connected to the light-shielding layer 312 through the second via 51. Simultaneously, one end of the first conductive layer 307 is also electrically connected to the active layer 311 of the thin-film transistor through the first via 41. That is, in this embodiment, the drain 315 of the thin-film transistor is electrically connected to both the active layer 311 and the light-shielding layer 312, thereby effectively improving the electrostatic shielding function of the array substrate.

[0071] In this embodiment, the first conductive layer 307 is also disposed within the light-emitting region 100, and a passivation layer 303 is disposed on the first conductive layer 307, and a planarization layer 304 is disposed on the passivation layer 303. In this embodiment, since the thickness of the first conductive layer 307 is less than the thickness of the source / drain metal layer, when other film layers are deposited on the thinner first conductive layer 307, a film layer with higher flatness can be obtained, such as preparing a highly flat anode, and then preparing a light-emitting layer on the anode. The light-emitting layer has the same thickness at different positions within the light-emitting region, thereby ensuring the light-emitting effect of subsequent light-emitting layers.

[0072] In this embodiment of the application, in order to ensure the contact effect between the first conductive layer 307 and the source / drain metal layer, etching can be performed at the position corresponding to the via on the first conductive layer 307. After etching is completed, the source / drain metal layer penetrates into the via formed by the first conductive layer 307.

[0073] In this embodiment, the first conductive layer 307 and the source / drain metal layer are made of different materials. By using different materials, the etching effect can be optimized when different film layers are etched. The material of the first conductive layer 307 may include any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide, while the material of the source / drain metal layer may include any one of Cu, Al, Ag, and copper / molybdenum-titanium alloy. Because the two metal layers are made of different materials, the capacitance values ​​formed between the conductive layer and other film layers in different regions differ, thereby effectively regulating the device performance within the display panel.

[0074] Furthermore, in this embodiment, the thickness of the first conductive layer 307 within the light-emitting region 100 can be less than the thickness of the corresponding first conductive layer 307 within the non-light-emitting region 101, thereby further improving the flatness of subsequent film layers. During film deposition, due to the presence of multiple stepped structures in the non-light-emitting region, the film layer in the non-light-emitting region is much higher than the film layer deposited in the light-emitting region. However, in this embodiment, by controlling the thickness of the first conductive layer 307 in different regions, and by ensuring a relatively small thickness of the first conductive layer 307, a flat surface can be obtained when other film layers are deposited on the first conductive layer 307. This results in the film layer within the light-emitting region 100 having a flat upper surface, ensuring the planarization of the subsequently prepared light-emitting layer.

[0075] In this embodiment, the display panel further includes a second passivation layer 303, a planarization layer 304, and an electrode layer 306. Specifically, the second passivation layer 303 is disposed above the thin-film transistor device layer, such as on the interlayer dielectric layer 302, and covers the second metal layer. Meanwhile, the planarization layer 304 is disposed on the interlayer dielectric layer 302, and the electrode layer 306 is disposed on the planarization layer 304.

[0076] Specifically, the electrode layer 306 is disposed on at least the film layer corresponding to the light-emitting region 100. The electrode layer 306 may be an anode, and a light-emitting layer is finally deposited on the anode.

[0077] In this embodiment, a second passivation layer and a planarization layer 304 are prepared to reduce the tomographic difference between different film layers. The thickness of the planarization layer 304 within the light-emitting region 100 is less than its thickness within the non-light-emitting region 101.

[0078] Meanwhile, in this embodiment of the application, within the light-emitting region 100, the surface of the planarization layer 304 is a plane, and the surface of the electrode layer 306 is also a plane.

[0079] Preferably, the array substrate further includes a third via 61. The third via 61 is disposed within the non-light-emitting region 101 and within the non-overlapping portion 382 corresponding to the drain 315. The third via 61 exposes the first conductive layer 307, and the electrode layer 306 is electrically connected to the first conductive layer 307 through the third via 61.

[0080] In this embodiment, the electrode layer 306 may contact the first conductive layer 307 at a location between the first via 41 and the second via 51.

[0081] Furthermore, the planarization layer 304 forms a plurality of protrusions 21 within the non-light-emitting region 101. Since the source / drain electrodes in this region are stacked, the protrusions 21 can correspond to the positions of the source / drain electrodes of the thin-film transistor. In this embodiment, the protrusions 21 can be positioned above the source and drain electrodes. By providing the protrusions 21, the contact area between the protrusions 21 and the barrier 305 is increased, thereby improving the adhesion between the film layers and the reliability of the panel.

[0082] Furthermore, in this embodiment, when setting the corresponding other wiring layers in the light-emitting region and the non-light-emitting region, the structure of the other wiring layers can also be set with reference to the structure of the first conductive layer and the source / drain metal layer described above. For example, the data signal lines, power signal lines, and other metal wirings in different regions can be set as partially stacked structures according to the structure provided in this embodiment, which will not be elaborated here. By changing the height of the metal wiring layers in different regions, the tomographic difference between film layers can be reduced, and the height of the tomographic difference between the corresponding film layers in the light-emitting region can be ensured to be less than or equal to 200 nm. Preferably, in this embodiment, the height of the tomographic difference between the corresponding film layers in the light-emitting region is 200 nm.

[0083] Furthermore, in this embodiment, the array substrate further includes a baffle 305. The baffle 305 is disposed within the non-light-emitting area 101, and the baffle 305 causes the light-emitting area 100 to form a pixel opening 80. The light-emitting layer is disposed within the pixel opening 80, thereby realizing the light-emitting display of the display panel.

[0084] In this embodiment, by setting different stacked structures in different areas, the discontinuity difference between the film layer and other films in the light-emitting area 100 is reduced, its flatness is improved, and a horizontal film layer is obtained. Ultimately, this ensures that the light-emitting layer in the light-emitting area 100 has a consistent thickness in different areas, thereby ensuring uniform light emission from the display panel.

[0085] Furthermore, in this embodiment of the application, when setting the light-shielding layer 312, it can be set as a double-layer light-shielding layer 312 to further improve its electrostatic protection effect and reduce the film layer discontinuity between different areas.

[0086] Furthermore, this application also provides a method for fabricating an array substrate. Specifically, the fabrication method includes the following steps:

[0087] A substrate is provided, and a thin-film transistor device layer is formed on the substrate, wherein the thin-film transistor device layer includes an active layer, a gate disposed on the active layer, and an interlayer dielectric layer disposed on the gate.

[0088] Etching and forming vias on the thin-film transistor device layer, and fabricating a first conductive layer on the thin-film transistor device layer, so that the first conductive layer is electrically connected to the active layer through the vias;

[0089] A source / drain metal layer is prepared on the first conductive layer, and a photoresist is prepared on the source / drain metal layer. The first conductive layer and the source / drain metal layer are etched for the first time using the photoresist to form multiple openings. The photoresist has a different thickness in different regions.

[0090] Another photoresist is fabricated on the source / drain metal layer, and the source / drain metal layer is etched a second time using a half-mask process to fabricate the source and drain of the thin film transistor.

[0091] A passivation layer is prepared on the source / drain metal layer and the first conductive layer, and a planarization layer is prepared on the passivation layer, and a third via is etched to form the via.

[0092] An electrode layer is formed on the planarization layer, wherein the electrode layer is electrically connected to the first conductive layer through the third via;

[0093] An inkjet-printed light-emitting layer is formed on the electrode layer, and the light-emitting layer is then dried and cured.

[0094] Specifically, in combination with, for example Figures 4-7 As shown, Figures 4-7 This is a schematic diagram of the film structure corresponding to the manufacturing process of the display panel provided in the embodiments of this application.

[0095] Combination Figure 3 For a structural diagram of the array substrate, see [link to diagram]. Figure 4 .exist Figure 4 First, a substrate is provided, and a thin-film transistor device layer is fabricated and formed on the substrate. In this embodiment, the thin-film transistor device layer can be fabricated according to the film layer structure in the prior art. For example, the active layer, gate, and dielectric layer between the film layers of the thin-film transistor are sequentially fabricated and formed on the substrate. Details will not be elaborated here. After the thin-film transistor device layer is fabricated, a source / drain metal layer 308 and a first conductive layer 307 are disposed on the thin-film transistor device layer. The source / drain metal layer 308 is disposed on the first conductive layer 307, and the first conductive layer 307 is disposed on the interlayer dielectric layer 302. The source / drain metal layer 308 covers the first conductive layer 307 within the light-emitting region 100 and the non-light-emitting region 101.

[0096] After fabrication, a photoresist 401 is fabricated on the source / drain metal layer 308. In this embodiment, the photoresist 401 is disposed in both the light-emitting region 100 and the non-light-emitting region 101. Specifically, a layer of photoresist 401 is disposed at the position corresponding to the source / drain of the thin-film transistor and at the position corresponding to the pixel opening 80 of the light-emitting region.

[0097] Specifically, the thickness of the photoresist 401 within the light-emitting region 100 is less than its thickness within the non-light-emitting region 101. Simultaneously, the photoresist 401 corresponding to the drain electrode 315 has different thicknesses. The thickness of the photoresist 401 near the non-light-emitting region is greater than the thickness of the photoresist near the light-emitting region 100, thereby ensuring that different film thicknesses can be etched during etching.

[0098] Meanwhile, the thickness of the photoresist 401 in the non-light-emitting region 101 is greater than the thickness of the photoresist 401 in the light-emitting region 100. After the photoresist 401 is fabricated, it is etched, such as by photolithography. In this embodiment, within the light-emitting region 100, within the region corresponding to the photoresist 401, etching is performed using a half-mask process.

[0099] See details Figure 5 After the first etching is completed, the first conductive layer 307 and the source / drain metal layer 308 are partially etched away, forming multiple openings.

[0100] Etching continues. In this embodiment, since the photoresist 401 has a different thickness in the area corresponding to the drain 315, a second etching is performed.

[0101] See details Figure 6 The second etching is performed using a half-mask etching process. After etching, part of the second conductive layer in the area corresponding to the drain 315 is etched away, thus exposing part of the first conductive layer 307. Simultaneously, in the light-emitting area 100, the source / drain metal layer 308 is completely etched. At this point, after etching, only a single layer of the first conductive layer 307 remains in the light-emitting area 100, while in the non-light-emitting area 101, there is a stacked structure of the source / drain metal layer 308 and the first conductive layer.

[0102] Specifically, in this embodiment, the thickness of the first conductive layer 307 within the light-emitting region can be [missing information]. Meanwhile, the thickness of the source / drain metal layer 308 can be

[0103] See details Figure 7 As shown, after etching, the source / drain metal layer 308 and the first conductive layer 307 have different stacked structures in the light-emitting and non-light-emitting regions. Further fabrication continues, with a second passivation layer 303 formed on the source / drain metal layer 308, and a planarization layer 304 formed on the second passivation layer 303. Simultaneously, vias are etched at corresponding locations. In this embodiment, a third via 61 is etched and formed on the planarization layer, while an electrode layer 306 is formed on the planarization layer 304 corresponding to the light-emitting region 100. In this embodiment, the electrode layer 306 is electrically connected to the first conductive layer through the third via 61.

[0104] In this embodiment, the electrode layer 306 is located within the light-emitting region 100, and its upper surface is a horizontal plane. Simultaneously, a barrier 305 is provided within the non-light-emitting region 101. After the barrier 305 is fabricated, it is etched within the light-emitting region 100 to form a pixel opening 80.

[0105] Simultaneously, a light-emitting layer is fabricated within the pixel opening 80. In this embodiment, the light-emitting layer can be fabricated using a vapor deposition process. The substrate corresponding to the light-emitting layer is an electrode layer 306, and the surface of the electrode layer 306 is a plane. Therefore, when the light-emitting layer and other film layers are formed by vapor deposition, the resulting film layers can have the same thickness in different areas. This effectively ensures the consistency of the light-emitting performance of the display panel and improves its overall performance.

[0106] Furthermore, in this embodiment of the application, a display panel is also provided, in which the aforementioned array substrate is disposed. For details, please refer to... Figure 3 The corresponding array substrate structure is described. In this embodiment, the array substrate includes a substrate, an active layer 311, a gate 309, an interlayer dielectric layer 302, and a source / drain metal layer 308. The active layer 311 is disposed on the substrate, the gate 309 is disposed on the active layer 311, the interlayer dielectric layer 302 is disposed on the gate 309, and the source / drain metal layer 308 is disposed on the interlayer dielectric layer 302. Furthermore, the display panel may also include a light-emitting layer disposed on the array substrate and an encapsulation layer disposed on the light-emitting layer.

[0107] In this embodiment, the array substrate further includes a first conductive layer 307, which is disposed on the interlayer dielectric layer 302. A source / drain metal layer 308 is disposed in the non-light-emitting area and correspondingly disposed on the first conductive layer 307. In this embodiment, by setting different stacked structures in different areas, the discontinuity difference between the film layer and other films in the light-emitting area is reduced, improving its planarization. Ultimately, this ensures that the light-emitting layer in the light-emitting area has a consistent thickness in different areas, thereby guaranteeing the display panel's display effect.

[0108] Specifically, the display panel can be any product or component with display and touch functions, such as mobile phones, computers, electronic paper, monitors, laptops, and digital photo frames, without any specific restrictions on its type.

[0109] In summary, the present invention has provided a detailed description of a display panel and a method for preparing the display panel. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on the scope defined by the claims.

Claims

1. A display panel comprising a plurality of pixel units, each pixel unit including a light-emitting area and a non-light-emitting area disposed on at least one side of the light-emitting area, characterized in that, include: Substrate; An active layer is disposed on the substrate; A gate, wherein the gate is disposed on the active layer; An interlayer dielectric layer is disposed on the gate; as well as, A source / drain metal layer is disposed on the interlayer dielectric layer and electrically connected to the active layer; A first conductive layer is disposed on the interlayer dielectric layer; The source / drain metal layer is disposed in the non-light-emitting area, and is disposed on the first conductive layer and electrically connected to the first conductive layer. The thickness of the first conductive layer is less than the thickness of the source / drain metal layer.

2. The display panel according to claim 1, characterized in that, The first conductive layer is disposed in the light-emitting area and the non-light-emitting area, and the orthographic projection of the source / drain metal layer on the interlayer dielectric layer is located within the orthographic projection of the first conductive layer on the interlayer dielectric layer.

3. The display panel according to claim 2, characterized in that, The thickness of the first conductive layer in the light-emitting area is less than the thickness of the first conductive layer in the non-light-emitting area.

4. The display panel according to claim 1, characterized in that, The material of the first conductive layer includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide, and the material of the source / drain metal layer includes any one of Cu, Al, Ag, and copper / molybdenum-titanium alloy.

5. The display panel according to claim 1, characterized in that, The display panel further includes a first via, through which the first conductive layer is electrically connected to the active layer.

6. The display panel according to claim 1, characterized in that, The display panel further includes a light-shielding layer disposed between the substrate and the active layer.

7. The display panel according to claim 6, characterized in that, The light-shielding layer is configured in at least two layers in both the luminescent area and the non-luminescent area.

8. The display panel according to any one of claims 6-7, characterized in that, The display panel further includes a second via, the source / drain metal layer includes a drain electrode, the second via is disposed on the side of the drain electrode near the light-emitting area, and the first conductive layer is electrically connected to the light-shielding layer through the second via.

9. The display panel according to claim 1, characterized in that, The display panel further includes a passivation layer, which is disposed on the interlayer dielectric layer; A planarization layer is disposed on the passivation layer; An electrode layer is disposed at least in the light-emitting area, the electrode layer is disposed on the planarization layer, and the electrode layer is electrically connected to the first conductive layer through a third via. The passivation layer has a thickness in the light-emitting region that is less than that in the non-light-emitting region, and the upper surface of the electrode layer in the light-emitting region is a plane.

10. The display panel according to claim 9, characterized in that, The display panel also includes a barrier wall disposed in the non-light-emitting area and on the planarization layer.

11. A method for manufacturing a display panel, comprising the following steps: A substrate is provided, and a thin-film transistor device layer is formed on the substrate, wherein the thin-film transistor device layer includes an active layer, a gate disposed on the active layer, and an interlayer dielectric layer disposed on the gate. Etching and forming vias on the thin-film transistor device layer, and fabricating a first conductive layer on the thin-film transistor device layer, so that the first conductive layer is electrically connected to the active layer through the vias; A source / drain metal layer is fabricated on the first conductive layer, and a photoresist is fabricated on the source / drain metal layer. The first conductive layer and the source / drain metal layer are then etched using the photoresist to form multiple openings. The thickness of the photoresist varies in different regions; Another photoresist is fabricated on the source / drain metal layer, and the source / drain metal layer is etched a second time using a half-mask process to fabricate the source and drain of the thin film transistor. A passivation layer is prepared on the source / drain metal layer and the first conductive layer, a planarization layer is prepared on the passivation layer, and a third via is etched to form the via. An electrode layer is formed on the planarization layer, wherein the electrode layer is electrically connected to the first conductive layer through the third via; An inkjet-printed light-emitting layer is formed on the electrode layer, and the light-emitting layer is then dried and cured.

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