Thin film transistor device and manufacturing method, display substrate

Abstract

This disclosure provides a thin-film transistor device, its manufacturing method, and a display substrate. The thin-film transistor device includes: a substrate; a gate, an active layer, a source, and a drain located on the substrate; characterized in that the active layer is a multi-layer stacked structure, including at least one first oxide semiconductor layer and at least one second oxide semiconductor layer stacked thereon, wherein the composition ratio of the first oxide semiconductor layer is different from that of the second oxide semiconductor layer; wherein the proportion of elements that can improve the stability of the film layer in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer, and the proportion of elements with more free electrons in the first oxide semiconductor layer is higher than that in the second oxide semiconductor layer. The thin-film transistor device, its manufacturing method, and the display substrate provided by the embodiments of this disclosure can exhibit a sharp increase in photocurrent under certain illumination conditions, and can be used as an effective photosensor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a thin-film transistor device, its manufacturing method, and a display substrate. Background Technology

[0002] In recent years, the development of TFT (Thin Film Transistor) devices, especially the research on characteristic optimization and improvement, has become increasingly in-depth. Amorphous oxide TFTs, represented by indium gallium zinc oxide (IGZO), have been widely used in the display field due to their high mobility, low leakage current, and simple fabrication process. Under illumination, amorphous oxide TFTs generate photogenerated holes. When a negative gate voltage is applied, these photogenerated holes act as charge carriers, increasing the photocurrent. However, in related technologies, TFTs with a single-layer oxide active layer, although the current increases somewhat when a negative gate voltage is applied, the change is not significant compared to when no light is applied, making them unsuitable as photosensitive sensor devices. Summary of the Invention

[0003] This disclosure provides a thin-film transistor device and its manufacturing method, as well as a display substrate, which can exhibit a sharp increase in photocurrent under certain illumination conditions, and can serve as an effective photosensitive sensor.

[0004] The technical solutions provided in this disclosure are as follows:

[0005] This disclosure provides a thin-film transistor device, including: a substrate; a gate, an active layer, a source, and a drain located on the substrate; the active layer is a multi-layer stacked structure, including at least one first oxide semiconductor layer and at least one second oxide semiconductor layer stacked thereon, wherein the composition ratio of the first oxide semiconductor layer is different from that of the second oxide semiconductor layer; wherein the proportion of elements that can improve the stability of the film layer in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer, and the proportion of elements with more free electrons in the first oxide semiconductor layer is higher than that in the second oxide semiconductor layer.

[0006] For example, the first oxide semiconductor layer is a first indium gallium zinc tin oxide layer;

[0007] The second oxide semiconductor layer is a second indium gallium zinc tin oxide layer; wherein,

[0008] The atomic percentage of indium in the first indium gallium zinc tin oxide layer is greater than that in the second indium gallium zinc tin oxide layer;

[0009] The atomic percentage of gallium in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of gallium in the first indium gallium zinc tin oxide layer; and / or,

[0010] The atomic percentage of zinc in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of zinc in the first indium gallium zinc tin oxide layer; and / or,

[0011] The atomic percentage of tin in the second indium gallium zinc tin oxide layer is greater than that in the first indium gallium zinc tin oxide layer.

[0012] For example, the multi-film stacked structure includes a first film layer located on the side closest to the substrate and a second film layer located on the side furthest from the substrate, wherein the first film layer is the first oxide semiconductor layer and the second film layer is the second oxide semiconductor layer.

[0013] For example, the multi-film stacked structure further includes an intermediate film layer located between the first film layer and the second film layer; the intermediate film layer is a single film layer, including one of the first oxide semiconductor layer or the second oxide semiconductor layer; or, the intermediate film layer is a multi-film layer, including at least one first oxide semiconductor layer and one second oxide semiconductor layer.

[0014] For example, the composition ratio of the first indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(0.2~0.4):(1.6~2.2):(0.3~0.5);

[0015] The composition ratio of the second indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(4.5~5.1):(3.3~3.9):(0.9~1.3).

[0016] For example, the gate is a stacked structure of a copper metal layer and a titanium metal layer.

[0017] For example, the source and the drain are stacked structures of a molybdenum-niobium alloy layer and a copper metal layer.

[0018] For example, the thin-film transistor device further includes a passivation layer covering the source and the drain on the side away from the substrate, the passivation layer being a stacked structure of silicon nitride and silicon oxide.

[0019] This disclosure also provides a method for manufacturing a thin-film transistor device, used to manufacture the thin-film transistor device provided in this disclosure, the method comprising:

[0020] A gate, an active layer, a source, and a drain are formed on a substrate, wherein the active layer is a multi-layer stacked structure, including at least one first oxide semiconductor layer and at least one second oxide semiconductor layer stacked together, and the composition ratio of the first oxide semiconductor layer is different from that of the second oxide semiconductor layer.

[0021] For example, the step of forming an active layer on the substrate in the method specifically includes:

[0022] At least one first indium gallium zinc tin oxide layer and at least one second indium gallium zinc tin oxide layer are deposited sequentially from the side closest to the substrate to the side furthest from the substrate. After annealing heat treatment, patterning processing is performed to form the active layer pattern.

[0023] This disclosure also provides a display substrate, including the thin-film transistor device provided in this disclosure.

[0024] The beneficial effects of the embodiments disclosed herein are as follows:

[0025] In the above scheme, the active layer of the thin-film transistor device adopts a stacked structure of at least one first oxide semiconductor layer and at least one second oxide semiconductor layer. The composition ratios of the first oxide semiconductor layer and the second oxide semiconductor layer are different. The proportion of elements that can improve film stability in the second oxide semiconductor layer is relatively higher than that in the first oxide semiconductor layer, and the proportion of elements with more free electrons in the first oxide semiconductor layer is relatively higher than that in the second oxide semiconductor layer. For oxide TFT devices, photogenerated holes are generated in the channel under illumination. These holes act as conductive charge carriers, resulting in enhanced photocurrent. The relatively high proportion of elements that can improve film stability in the second oxide semiconductor layer can improve the stability of the amorphous structure. Fewer photogenerated holes are generated under illumination, meaning fewer hole carriers participate in conduction, resulting in a smaller photocurrent, which is almost unchanged compared to no illumination. However, the relatively high proportion of elements with more free electrons in the first oxide semiconductor layer means that there are more free electrons in the first oxide semiconductor layer. The photogenerated holes generated under illumination are more likely to recombine with some of the free electrons, but overall, excess positive charge is still generated, thus enhancing the photocurrent to a certain extent. This active layer employs a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer. Under a negative gate voltage (Vgs), the relatively stable second oxide layer significantly reduces the number of photogenerated holes and free electrons recombination under illumination. This results in a higher number of hole carriers that facilitate conduction, leading to a larger photocurrent. In other words, thin-film transistor devices using this oxide semiconductor layer as the active layer exhibit a sharp increase in photocurrent under certain illumination conditions, making them effective photosensitive sensors. Attached Figure Description

[0026] Figure 1 A schematic diagram of the structure of step S1 in the manufacturing method of the thin-film transistor device provided in this disclosure, in which a gate and a gate insulating layer are formed on a substrate;

[0027] Figure 2 A schematic diagram of the structure in which an active layer is formed on the gate insulating layer in the manufacturing method of the thin-film transistor device provided in the embodiments of this disclosure;

[0028] Figure 3 A schematic diagram of the structure in step S3 of the manufacturing method of the thin-film transistor device provided in this embodiment of the present disclosure, in which the source and drain are formed on the active layer;

[0029] Figure 4 A schematic diagram of the structure in step S4 of the manufacturing method of the thin-film transistor device provided in this embodiment of the present disclosure, in which a passivation layer is formed on the source and drain electrodes;

[0030] Figure 5 This is a schematic diagram of the structure in which an organic resin layer is formed on the passivation layer in a method for manufacturing a thin-film transistor device according to an embodiment of the present disclosure.

[0031] Figure 6 The first group of the control group has a TFT device with a single active layer and a first oxide semiconductor layer as the transfer characteristic curve. a is the characteristic curve of the TFT device under the light-added condition, and b is the characteristic curve of the TFT device under the non-light-added condition.

[0032] Figure 7 The transfer characteristic curves of the TFT device with a single-layer second oxide semiconductor active layer in the second group of the control group are shown in Figure a. The characteristic curve of the TFT device under the light-added condition is shown in Figure b.

[0033] Figure 8 The above are the transfer characteristic curves of a TFT device with a first oxide semiconductor layer and a second oxide semiconductor layer as the active layer in the embodiments of this disclosure. a is the characteristic curve of the TFT device under the condition of adding light, and b is the characteristic curve of the TFT device under the condition of not adding light.

[0034] Figure 9 The above compares the light transfer characteristic curves of the TFT device of the present invention with those of the first group of TFT devices and the second group of TFT devices in the control group. Here, a' is the characteristic curve of the TFT device of the present invention under light conditions, b' is the characteristic curve of the TFT device of the first group of TFT devices in the control group under light conditions, and c' is the characteristic curve of the TFT device of the second group of TFT devices in the control group under light conditions. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] Before providing a detailed description of the embodiments disclosed herein, it is necessary to explain the related technologies as follows:

[0038] In related technologies, amorphous oxide TFTs, represented by indium gallium zinc oxide (IGZO), have been widely used in the display field due to their high mobility, low leakage current, and simple and easy manufacturing process. Furthermore, back channel etching (BCE) technology is becoming increasingly mature. Under illumination, amorphous oxide TFTs generate photogenerated holes. When a negative gate voltage is applied, these photogenerated holes act as charge carriers, increasing the photocurrent. However, in TFTs with a single-layer oxide active layer used in related technologies, although the current increases somewhat when a negative gate voltage is applied, the change is minimal compared to when no light is applied, with the photocurrent on the order of ≤10^(-10) A, making them unsuitable as photosensitive sensor devices.

[0039] In some related technologies, although there are also BCE-type TFTs with double active layers, for example, using two oxide layers of different densities as active layers, where the upper oxide layer acts as an anti-etching layer, they do not involve TFT characteristics; or, using carbon nanotubes, graphene, or organic materials as the bottom active layer and oxide as the top active layer, where the top oxide layer can act as an etch barrier layer to protect the bottom active layer and also give the active layer of the TFT device the excellent combined effect of two semiconductor materials, they do not characterize TFT characteristic curves or characteristic parameters.

[0040] Therefore, it is necessary to design a thin-film transistor device that can exhibit significant changes in photocurrent under certain illumination conditions, thus serving as an effective photosensor.

[0041] like Figure 5 As shown, the thin-film transistor device provided in this embodiment includes: a substrate 100; a gate 200, a gate insulating layer 210, an active layer 300, a source 400, and a drain 500 located on the substrate 100; the active layer 300 is a multi-layer stacked structure, including at least one first oxide semiconductor layer 310 and at least one second oxide semiconductor layer 320 stacked thereon, wherein the composition ratio of the first oxide semiconductor layer 310 is different from that of the second oxide semiconductor layer 320; wherein the proportion of elements that can improve the stability of the film layer in the second oxide semiconductor layer 320 is higher than that in the first oxide semiconductor layer 310, and the proportion of elements with more free electrons in the first oxide semiconductor layer 310 is higher than that in the second oxide semiconductor layer 320.

[0042] The thin-film transistor device provided in this embodiment has an active layer 300 that adopts a stacked structure of at least one first oxide semiconductor layer 310 and at least one second oxide semiconductor layer 320. The component ratios in the first oxide semiconductor layer 310 and the second oxide semiconductor layer 320 are different. The proportion of elements that can improve the stability of the film layer in the second oxide semiconductor layer 320 is higher than that in the first oxide semiconductor layer 310, and the proportion of elements with more free electrons in the first oxide semiconductor layer 310 is higher than that in the second oxide semiconductor layer 320.

[0043] For oxide TFT devices, photogenerated holes are generated in the channel under illumination. These holes act as conductive charge carriers, resulting in enhanced photocurrent. Therefore, in the thin-film transistor device provided in this embodiment, the proportion of elements that can improve film stability in the second oxide semiconductor layer 320 of the active layer 300 is relatively high, which can improve the stability of the amorphous structure. Fewer photogenerated holes are generated under illumination, meaning fewer hole carriers participate in conduction, and the photocurrent is also smaller, with almost no change compared to no light. On the other hand, the proportion of elements with more free electrons is relatively high in the first oxide semiconductor layer 310. Thus, the first oxide semiconductor layer 310 has more free electrons, and the photogenerated holes generated under illumination are more likely to recombine with some of the free electrons. However, overall, excess positive charge is still generated, resulting in a certain degree of enhancement in photocurrent. In this way, the active layer 300 adopts a stacked structure of a first oxide semiconductor layer 310 and a second oxide semiconductor layer 320. Under a negative gate voltage (Vgs), due to the relatively stable effect of the second oxide layer, the number of photogenerated holes and free electrons recombination generated under illumination is greatly reduced, resulting in more hole carriers that can conduct electricity and thus a larger photocurrent. In other words, thin-film transistor devices using this stacked structure of at least two oxide semiconductor layers as the active layer 300 exhibit a sharp increase in photocurrent under certain illumination conditions, making them an effective photosensitive sensor.

[0044] In some embodiments, the first oxide semiconductor layer 310 is a first indium gallium zinc tin oxide layer (IGZTO); the second oxide semiconductor layer 320 is a second indium gallium zinc tin oxide layer (IGZTO).

[0045] Wherein, the atomic percentage of indium (In) in the first indium gallium zinc tin oxide layer is greater than the atomic percentage of indium (In) in the second indium gallium zinc tin oxide layer;

[0046] The atomic percentage of gallium (Ga) in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of gallium (Ga) in the first indium gallium zinc tin oxide layer; and / or, the atomic percentage of zinc (Zn) in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of zinc (Zn) in the first indium gallium zinc tin oxide layer; and / or, the atomic percentage of tin (Sn) in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of tin (Sn) in the first indium gallium zinc tin oxide layer.

[0047] The mechanism by which the oxide semiconductor layer provided in the above embodiments, as the active layer 300 of a thin-film transistor device, changes in photocurrent after light is applied is analyzed as follows:

[0048] In the second oxide semiconductor layer 320, at least one of Ga, Zn, and Sn elements has a relatively high proportion. The high proportion of Ga and Zn elements can improve the stability of the amorphous structure, while Sn element has strong etching resistance, which can further enhance the overall stability of the film layer. There are fewer photogenerated holes generated under illumination, that is, fewer hole carriers participating in conduction, and the photocurrent is also smaller, with almost no change compared to no light. In the first oxide semiconductor layer 310, the proportion of In element is relatively high, and there are more free electrons. The photogenerated holes generated under illumination are more likely to recombine with some of the free electrons, but overall, excess positive charge is still generated, so the photocurrent is enhanced to a certain extent.

[0049] In this way, the thin-film transistor device uses a stacked structure of a first oxide semiconductor layer 310 and a second oxide semiconductor layer 320 as the active layer 300. Under the action of a negative gate voltage (Vgs), due to the relatively stable effect of the second oxide semiconductor layer 320, the number of photogenerated holes and free electrons recombination generated under illumination is greatly reduced, and there are more hole carriers that play a conductive role, resulting in a larger photocurrent. Therefore, under certain illumination conditions, the photocurrent can show a sharp increase, thus serving as an effective photosensitive sensor.

[0050] In some embodiments, the multi-film stack structure includes a first film layer located on the side closest to the substrate 100 and a second film layer located on the side furthest from the substrate 100, wherein the first film layer is the first oxide semiconductor layer 310 and the second film layer is the second oxide semiconductor layer 320.

[0051] In the above scheme, since the first oxide semiconductor layer 310 has more free electrons and the second oxide semiconductor layer 320 has a more stable amorphous structure, the first oxide semiconductor layer 310 should be disposed at the bottom of the stacked structure of the entire oxide semiconductor layer (i.e. the side closest to the TFT device substrate 100), while the second oxide semiconductor layer 320 should be disposed at the top of the stacked structure of the entire oxide semiconductor layer (i.e. the side furthest from the TFT device substrate 100).

[0052] In some embodiments, the multi-film stacked structure further includes an intermediate film layer located between the first film layer and the second film layer; the intermediate film layer is a single film layer, including one of the first oxide semiconductor layer 310 or the second oxide semiconductor layer 320; or, the intermediate film layer is a multi-film layer, including at least one first oxide semiconductor layer 310 and the second oxide semiconductor layer 320.

[0053] In the above scheme, the stacked structure of the active layer 300 is not limited to a two-layer structure, but may also include a multi-layer stacked structure with two or more layers. For example, between the first film layer and the second film layer, a first oxide semiconductor layer 310 or a second oxide semiconductor layer 320 may be provided; or, at least two first oxide semiconductor layers 310 or at least two second oxide semiconductor layers 320; or, at least one first oxide semiconductor layer 310 and at least one second oxide semiconductor layer 320.

[0054] It should be noted that when the active layer 300 includes a multilayer stacked structure, for example, when the active layer 300 includes at least two first oxide semiconductor layers 310, the distribution ratio of each group in the different first oxide semiconductor layers 310 can be the same or different; similarly, when the active layer 300 includes at least two second oxide semiconductor layers 320, the distribution ratio of each group in the different second oxide semiconductor layers 320 can be the same or different.

[0055] In some exemplary embodiments, the composition ratio of the first indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(0.2~0.4):(1.6~2.2):(0.3~0.5); and the composition ratio of the second indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(4.5~5.1):(3.3~3.9):(0.9~1.3).

[0056] In some exemplary embodiments, the gate 200 may be a stacked structure of copper metal layer and titanium metal layer; the source 400 and the drain 500 may be a stacked structure of molybdenum-niobium alloy layer and copper metal layer; the thin film transistor device may further include a passivation layer 600 covering the source 400 and the drain 500 on the side away from the substrate 100, the passivation layer being a stacked structure of silicon nitride and silicon oxide.

[0057] Furthermore, in some embodiments, the thin-film transistor device can be a bottom-gate structure or a top-gate structure, for example... Figure 5 The diagram shown is based on a bottom grid structure, but this is not a limitation in practical applications.

[0058] In addition, in some embodiments, an organic resin layer 700, such as an acrylic resin layer, may be covered on the passivation layer 600.

[0059] Furthermore, in this embodiment of the disclosure, the transfer characteristics of the thin-film transistor device provided in this embodiment and the thin-film transistor device in the control group were compared and verified under light-added and non-light-added conditions, as follows:

[0060] The gate 200, source 400 and drain 500 of the thin-film transistor device are subjected to characteristic testing through the extended test TEG (Test Element Group). The light source is 10000lx during the light characteristic test.

[0061] There are two control groups. The first group uses a first oxide semiconductor layer 310 for the active layer 300 of the thin-film transistor device. The second group uses a second oxide semiconductor layer 320 for the active layer 300 of the thin-film transistor device, while other structures remain unchanged.

[0062] First, the thin-film transistor device provided in the embodiments of this disclosure is manufactured through the following steps:

[0063] Step S1: A metal material, a stack of copper and titanium, is deposited on the substrate 100. Then, a patterning process is performed to form a gate 200. Next, a gate insulating layer 210 is deposited on the gate 200 using chemical vapor deposition. The gate insulating layer 210 is a stack of silicon nitride and silicon oxide. Figure 1 As shown;

[0064] Step S2: A first indium gallium zinc tin oxide layer is deposited on the gate insulating layer 210, wherein the component ratio is selected from In:Ga:Zn:Sn = 1:(0.2~0.4):(1.6~2.2):(0.3~0.5). Then, another first indium gallium zinc tin oxide layer is deposited. The component ratio of the second indium gallium zinc tin oxide layer is selected from In:Ga:Zn:Sn = 1:(4.5~5.1):(3.3~3.9):(0.9~1.3). After annealing heat treatment, patterning is performed to form the active layer 300, as shown below. Figure 2 As shown;

[0065] Step S3: Deposit source / drain metal layer material on the active layer 300. The source / drain metal layer material is a stack of molybdenum-niobium alloy and copper, and then pattern it to form source 400 and drain 500, as shown. Figure 3 As shown;

[0066] Step S4: Deposit a passivation layer on the source 400 and drain 500. The passivation layer material is a stack of silicon nitride and silicon oxide. The function of this passivation layer is to protect the TFT device, such as... Figure 4 As shown;

[0067] Step S5: Coat the top layer of the passivation layer with an acrylic resin layer, such as... Figure 5 As shown, the thin-film transistor device in the embodiments of this disclosure is formed.

[0068] Then, the thin-film transistor device of the first control group is manufactured. The only difference from the manufacturing steps of the thin-film transistor device in the embodiments of this disclosure is that in step S2, a first indium gallium zinc tin oxide layer is deposited on the gate insulating layer 210, wherein the component ratio of each group is selected from In:Ga:Zn:Sn = 1:(0.2~0.4):(1.6~2.2):(0.3~0.5), and the other steps remain unchanged. Similarly, the thin-film transistor device of the first control group is manufactured. The only difference from the manufacturing steps of the thin-film transistor device in the embodiments of this disclosure is that in step S2, a second indium gallium zinc tin oxide layer is deposited on the gate insulating layer 210, wherein the component ratio of the second indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(4.5~5.1):(3.3~3.9):(0.9~1.3), and the other steps remain unchanged.

[0069] The results of testing the transfer characteristics of the thin-film transistor device provided in this embodiment and the control group under conditions of no light and with light show that:

[0070] Figure 6 The first group of the control group shows the transfer characteristic curves of a TFT device with a single-layer first oxide semiconductor active layer. Curve a is the characteristic curve of the TFT device under illumination, and curve b is the characteristic curve of the TFT device without illumination. In the first group of the control group, the leakage current of the thin-film transistor device increases after illumination, and the threshold voltage shifts negatively. Figure 6 As shown, the current changes from 1.54E-12A without light to 3.50E-10A when the source-drain voltage Vds is 15.1V and the gate voltage Vgs is -12V.

[0071] Figure 7 The graphs show the transfer characteristic curves of the TFT device in the second control group, where the active layer is a single-layer second oxide semiconductor layer. Curve a shows the characteristic curve of the TFT device under illumination, and curve b shows the characteristic curve of the TFT device without illumination. The thin-film transistor device in the second control group showed almost no change in its curve after illumination, and the leakage current did not increase significantly. Figure 7 As shown, the current changes from 6.55E-12A without light to 1.09E-11A when the source-drain voltage Vds is 15.1V and the gate voltage Vgs is -12V.

[0072] Figure 8 The figures show the transfer characteristic curves of a TFT device with a first oxide semiconductor layer and a second oxide semiconductor layer as the active layer in this embodiment of the present disclosure. Figure a shows the characteristic curve of the TFT device under illumination, and figure b shows the characteristic curve of the TFT device without illumination. The thin-film transistor device provided in this embodiment experiences a sharp increase in leakage current after illumination, such as... Figure 8As shown, the source-drain voltage Vds is 15.1V and the gate voltage Vgs is -12V. The current changes from 2.0E-13A without light to 4.71E-07A. This characteristic of the TFT current changing suddenly after light is applied can make it an effective photosensitive sensor.

[0073] The light-emitting characteristics of the thin-film transistor device in this embodiment are compared with those of the control group as follows:

[0074] Figure 9 The above compares the light transfer characteristic curves of the TFT device of the present invention with those of the first group of TFT devices and the second group of TFT devices in the control group. Here, a' is the characteristic curve of the TFT device of the present invention under light conditions, b' is the characteristic curve of the TFT device of the first group of TFT devices in the control group under light conditions, and c' is the characteristic curve of the TFT device of the second group of TFT devices in the control group under light conditions.

[0075] like Figure 9 As shown, the leakage current of the thin-film transistor device in this embodiment after illumination is significantly greater than the leakage current of the thin-film transistor devices in the two control groups. The net residual photocurrent I of the thin-film transistor device after illumination is... pc =|I light |-|I dark |, where I light To add photocurrent, I dark No photocurrent is applied.

[0076] Table 1 shows the comparison data of net residual photocurrent between the thin-film transistor device of this embodiment and the control group:

[0077] Table 1

[0078] First group of TFT devices Second group of TFT devices This disclosure relates to TFT devices. <![CDATA[|I light |]]> 3.50E-10A 1.09E-11A 4.71E-07A <![CDATA[|I dark |]]> 1.54E-12A 6.55E-12A 2.00E-13A <![CDATA[I PC ]]> 3.5E-10A 1.09E-11A 4.71E-07A

[0079] As can be seen from Table 1, the net residual photocurrent of the thin-film transistor device in this embodiment is much greater than that of the thin-film transistor devices with a single active layer 300 in the other two control groups. Since the photoelectric gain factor G is proportional to the net residual photocurrent Ipc, the thin-film transistor device with a double active layer 300 in this embodiment can obtain a larger photoelectric gain, which is 10^3 to 10^4 times that of the thin-film transistor device with a single active layer 300.

[0080] Furthermore, this disclosure also provides a display substrate, including the thin-film transistor device provided in this disclosure, which can be applied to various display products, such as mobile phones, computers, tablets and other display products.

[0081] Furthermore, this disclosure also provides a method for manufacturing a thin-film transistor device, used to manufacture the thin-film transistor device provided in this disclosure, the method comprising:

[0082] A gate 200, an active layer 300, a source 400, and a drain 500 are formed on a substrate 100. The active layer 300 is a multi-layer stacked structure, including at least one first oxide semiconductor layer 310 and at least one second oxide semiconductor layer 320 stacked together. The composition ratio of the first oxide semiconductor layer 310 is different from that of the second oxide semiconductor layer 320.

[0083] For example, the step of forming an active layer 300 on the substrate 100 in the method specifically includes:

[0084] At least one first indium gallium zinc tin oxide layer and at least one second indium gallium zinc tin oxide layer are deposited sequentially from the side closest to the substrate 100 to the side furthest from the substrate 100. After annealing heat treatment, patterning processing is performed to form the active layer 300 pattern.

[0085] For example, the step of forming the gate 200 on the substrate 100 in the method specifically includes:

[0086] A metal material, consisting of a stack of copper and titanium, is deposited on the substrate 100 and patterned to form the gate 200 pattern.

[0087] For example, the method may further include, after forming the gate 200 on the substrate 100:

[0088] A gate insulating layer 210 is deposited on the gate 200 using chemical vapor deposition. The gate insulating layer 210 is a stack of silicon nitride and silicon oxide. Figure 1 As shown.

[0089] For example, the specific steps of forming the source 400 and drain 500 on the substrate 100 in the method include:

[0090] Source and drain metal layer materials are deposited on the active layer 300. The source and drain metal layer materials are a stack of molybdenum-niobium alloy and copper, and then patterned to form source 400 and drain 500, as shown below. Figure 3 As shown.

[0091] For example, the method further includes forming a passivation layer on the source 400 and the drain 500. The passivation layer material is a stack of silicon nitride and silicon oxide. The function of this passivation layer is to protect the TFT device, such as... Figure 4 As shown.

[0092] For example, in the method, an organic resin layer, such as an acrylic resin layer, is coated on the top layer of the passivation layer. Figure 5 As shown, this forms the thin-film transistor device in the embodiments of this disclosure.

[0093] The following points need to be explained:

[0094] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0095] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0096] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0097] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A thin-film transistor device, comprising: Substrate; The active layer, source, and drain are located on the substrate; characterized in that the active layer is a multi-layer stacked structure, including at least one first oxide semiconductor layer and at least one second oxide semiconductor layer stacked together, wherein the composition ratio of the first oxide semiconductor layer is different from that of the second oxide semiconductor layer; wherein the proportion of elements that can improve the stability of the film layer in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer, and the proportion of elements with more free electrons in the first oxide semiconductor layer is higher than that in the second oxide semiconductor layer; The first oxide semiconductor layer is a first indium gallium zinc tin oxide layer; The second oxide semiconductor layer is a second indium gallium zinc tin oxide layer; wherein, The atomic percentage of indium in the first indium gallium zinc tin oxide layer is greater than that in the second indium gallium zinc tin oxide layer; The atomic percentage of gallium in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of gallium in the first indium gallium zinc tin oxide layer; and / or, The atomic percentage of zinc in the second indium gallium zinc tin oxide layer is greater than the atomic percentage of zinc in the first indium gallium zinc tin oxide layer; and / or, The atomic percentage of tin in the second indium gallium zinc tin oxide layer is greater than that in the first indium gallium zinc tin oxide layer; The composition ratio of the first indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn=1:(0.2~0.4):(1.6~2.2):(0.3~0.5); The composition ratio of the second indium gallium zinc tin oxide layer is: In:Ga:Zn:Sn = 1:(4.5~5.1):(3.3~3.9):(0.9~1.3).

2. The thin-film transistor device according to claim 1, characterized in that, The multi-film stacked structure includes a first film layer located on the side closest to the substrate and a second film layer located on the side furthest from the substrate. The first film layer is the first oxide semiconductor layer, and the second film layer is the second oxide semiconductor layer.

3. The thin-film transistor device according to claim 2, characterized in that, The multi-film stacked structure further includes an intermediate film layer located between the first film layer and the second film layer; the intermediate film layer is a single film layer, including one of the first oxide semiconductor layer or the second oxide semiconductor layer; or, the intermediate film layer is a multi-film layer, including at least one first oxide semiconductor layer and one second oxide semiconductor layer.

4. The thin-film transistor device according to claim 1, characterized in that, The gate is a stacked structure of copper and titanium metal layers.

5. The thin-film transistor device according to claim 1, characterized in that, The source and the drain are a stacked structure of a molybdenum-niobium alloy layer and a copper metal layer.

6. The thin-film transistor device according to claim 1, characterized in that, The thin-film transistor device further includes a passivation layer covering the source and the drain on the side away from the substrate, the passivation layer being a stacked structure of silicon nitride and silicon oxide.

7. A method for manufacturing a thin-film transistor device, characterized in that, The method for manufacturing a thin-film transistor device as described in any one of claims 1 to 6 comprises: A gate, an active layer, a source, and a drain are formed on a substrate, wherein the active layer is a multi-layer stacked structure, including at least one first oxide semiconductor layer and at least one second oxide semiconductor layer stacked together, and the composition ratio of the first oxide semiconductor layer is different from that of the second oxide semiconductor layer.

8. The method for manufacturing a thin-film transistor device according to claim 7, characterized in that, The step of forming an active layer on the substrate in the method specifically includes: At least one first indium gallium zinc tin oxide layer and at least one second indium gallium zinc tin oxide layer are deposited sequentially from the side closest to the substrate to the side furthest from the substrate. After annealing heat treatment, patterning processing is performed to form the active layer pattern.

9. A display substrate, characterized in that, Includes the thin-film transistor device as described in any one of claims 1 to 6.

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