A control loop pulse width adjustable timer lock circuit and method

Abstract

A kind of control loop pulse width adjustable timer locking circuit and method, the circuit includes working power supply, first, second 555 timer chip U1, U2, three input or gate chip U3 and button switch S1;The power supply pin of working power supply VCC is connected to two 555 timers and three input or gate chip, the 2 number trigger pin of U1, U2 is connected;The 3 number output pin of U1, U2 and the pin of button switch S1 are respectively connected to the input end of U3, the output end of U3 is connected to the 2 number trigger pin of U1, U2, and is connected to VCC with a pull-up resistor R1, the other end of S1 is grounded;And the pulse width of U1 is less than U2.The control loop pulse width adjustable timer locking circuit and method of the present application can accurately modulate the test jump pulse width of control loop, and can only trigger once within a certain time, to avoid multiple triggers leading to undesirable consequences, effectively guarantee the stability of load control system.

Description

Technical Field

[0001] This invention relates to field testing instruments for load control systems, and in particular to a timer locking circuit and method with adjustable pulse width for the control loop. Background Technology

[0002] In recent years, control loop testing of load control systems such as dedicated transformer data acquisition terminals, energy controllers (dedicated transformers), control expansion modules, and load management control terminals has often been accompanied by power outages of many important loads. Once a problem occurs, the resulting losses will be incalculable.

[0003] Therefore, in order to make the control loop test experiment of the load control system terminal more reliable, a timer locking circuit with adjustable control loop pulse width is proposed. This circuit is used to precisely modulate the control loop test pulse width and can only be triggered once within a specific time period, thus avoiding adverse consequences caused by multiple triggers. Summary of the Invention

[0004] This invention addresses the trigger control problem of control loops in the background art by providing a timer locking circuit and method with adjustable pulse width for the control loop. It aims to solve the problem of unreliable control loop test jumps in existing load control system terminals and ensure the safety of the detector in the field.

[0005] The technical solution of this invention is:

[0006] This invention provides a timer lockout circuit with adjustable control loop pulse width, including a working power supply VCC, a first 555 timer chip U1, a second 555 timer chip U2, a three-input OR gate chip U3, and a push-button switch S1;

[0007] The operating power supply VCC is connected to the power supply pins of two 555 timers and a three-input OR gate chip; the trigger pin 2 of the first 555 timer chip U1 and the trigger pin 2 of the second 555 timer chip U2 are connected; the output pin 3 of the first 555 timer chip U1, the output pin 3 of the second 555 timer chip U2, and one pin of the push-button switch S1 are respectively connected to the input terminal of the three-input OR gate chip U3, and the output terminal of the OR gate chip U3 is connected to the trigger pin 2 of the two 555 timer chips, and a pull-up resistor R1 is connected to VCC; the other end of the push-button switch S1 is grounded.

[0008] The pulse width Tw1 of the first 555 timer chip U1 is smaller than the pulse width Tw2 of the second 555 timer chip U2.

[0009] Furthermore, the reset pin 4 of the first 555 timer chip U1 and the second 555 timer chip U2 are respectively connected to the power supply pin 8 of the corresponding timer, so that both timers are in normal working condition and are not cleared.

[0010] Furthermore, the voltage control pins 5 of the first 555 timer chip U1 and the second 555 timer chip U2 are respectively connected to external filter capacitors C2 and C4 and then grounded.

[0011] Furthermore, the filter capacitors C2 and C4 are 0.01 microfarads.

[0012] Furthermore, pins 7 and 6 of the first 555 timer chip U1 are grounded through capacitor C1 and then connected to the operating power supply VCC through resistor R2; pins 7 and 6 of the second 555 timer chip U2 are grounded through capacitor C3 and then connected to the operating power supply VCC through resistor R4.

[0013] Furthermore, the first 555 timer chip U1 and the second 555 timer chip U2 respectively constitute a monostable trigger circuit; the resistors R2 and R4 are both variable resistors, and by adjusting the resistance values, the pulse width Tw1 of the first 555 timer chip U1 is made smaller than the pulse width Tw2 of the second 555 timer chip U2.

[0014] Furthermore, the pin of the push-button switch S1 connected to the three-input OR gate chip U3 is connected to a pull-up resistor R3 to VCC.

[0015] A timer locking method with adjustable control loop pulse width, based on a locking circuit:

[0016] When the button switch S1 is operated, the first 555 timer chip U1 and the second 555 timer chip U2 work simultaneously.

[0017] Within the transient pulse time width Tw1 of the first 555 timer chip U1, a signal is input to the control loop to control the switch to close.

[0018] At this point, the circuit is locked, and the push-button switch S1 cannot be operated;

[0019] After the transient pulse duration Tw2 of the second 555 timer chip U2, the transient pulse of the second 555 timer chip U2 changes to a steady state;

[0020] At this point, the circuit is unlocked, and the push-button switch S1 is in an operable state.

[0021] The beneficial effects of this invention are:

[0022] The timer locking circuit and method with adjustable control loop pulse width of the present invention can accurately modulate the test pulse width of the control loop, and can only be triggered once within a specific time, avoiding adverse consequences caused by multiple triggers, and effectively ensuring the stability of the load control system.

[0023] When this invention is applied, it ensures that the control loop of the load control system terminal can accurately and safely complete the test jump experiment, thus guaranteeing the safety of the detector in the field.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0026] Figure 1 A circuit diagram of the present invention is shown. Detailed Implementation

[0027] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0028] Example 1: A timer lockout circuit with adjustable control loop pulse width includes a power supply VCC, a first 555 timer chip U1, a second 555 timer chip U2, a three-input OR gate chip U3, and a push-button switch S1. The power supply VCC is connected to the power pins of the two 555 timers and the three-input OR gate chip; the second trigger pin of the first 555 timer chip U1 and the second 555 timer chip U2 are connected together; the third output pin of the first 555 timer chip U1, the third output pin of the second 555 timer chip U2, and one pin of the push-button switch S1 are respectively connected to the input terminal of the three-input OR gate chip U3; the output terminal of the OR gate chip U3 is connected to the second trigger pin of the two 555 timers and connected to a pull-up resistor R1 to VCC; the other end of the push-button switch S1 is grounded.

[0029] The pulse width Tw1 of the first 555 timer chip U1 is smaller than the pulse width Tw2 of the second 555 timer chip U2.

[0030] In Example 2, as described in Example 1, the reset pin 4 of the 555 timer U1 is directly connected to the power supply pin 8, so the timer is in normal working condition and is not cleared. The reset pin 4 of the second 555 timer chip U2 is also connected in the same way as the first 555 timer chip U1.

[0031] In Example 3, as in Example 1, the voltage control pin 5 of the first 555 timer chip U1 and the voltage control pin 5 of the second 555 timer chip U2 are connected to a 0.01 microfarad capacitor and grounded to filter and eliminate external interference, thereby ensuring the stability of the reference level.

[0032] Example 4: As in Example 1, pins 7 and 6 of the first 555 timer chip U1 are grounded through capacitor C1 and then connected to the operating power supply VCC through resistor R2. C1 has a capacitance of 1 microfarad, and R2 has a resistance of 300 kΩ with a resistance accuracy of 1%. In this case, the pulse width Tw1 of the first 555 timer chip U1 is 330 ms. By changing the resistance of R2, the pulse width Tw1 can be changed to within 300 ms ± 100 ms.

[0033] Example 5: As in Example 1, pins 7 and 6 of the second 555 timer chip U2 are grounded through capacitor C3 and then connected to the operating power supply VCC through resistor R4. The capacitance of C3 is 22 microfarads, the resistance of R4 is 2.49 megohms, and the resistance accuracy is 1%. Therefore, the pulse width Tw2 of the second 555 timer chip U2 is 60.258s. By changing the resistance of R4, the pulse width Tw2 can be changed to within 60s ± 300 ms.

[0034] Example 6: As described in Example 1, the pin of the push button switch S1 connected to the three-input OR gate chip U3 is connected to a pull-up resistor R3 to VCC. The resistance value of R3 can be 10 kΩ, so as to ensure that the effective level of the push button switch S1 is low.

[0035] Example 7: As in Example 1, the first 555 timer chip U1 and the second 555 timer chip U2 respectively constitute a monostable trigger circuit, and the pulse width Tw1 of U1 is less than the pulse width Tw2 of U2.

[0036] Example 8: As described in Example 1, the validity of the next operation of the push button switch S1 only takes effect when the transient pulse of the second 555 timer chip U2 changes to a steady state. That is, after the last operation of the push button switch S1, the operation can only be performed after the transient pulse time width Tw2 of the second 555 timer chip U2 has elapsed. Otherwise, no matter how the push button switch S1 is operated, it will be invalid and neither of the two 555 timer chips will be triggered, thus ensuring the safety and reliability of the control circuit in the field.

[0037] Working principle:

[0038] The trigger pulse width of the 555 chip used to form a monostable multivibrator is: Tw = RCln3 ≈ 1.1RC, where R and C are the external resistors and capacitors of the 555 chip.

[0039] The power supply VCC charges capacitor C through resistor R. Based on the characteristics of the 555 chip, adjusting resistor R makes the charging and discharging times of capacitor C different, which can control the trigger pulse width and thus control the 555 chip to output the pulse required by this invention, as the input for testing the control loop circuit.

[0040] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A timer latching circuit with adjustable control loop pulse width, characterized in that, It includes the operating power supply VCC, the first 555 timer chip U1, the second 555 timer chip U2, the three-input OR gate chip U3, and the push button switch S1; The operating power supply VCC is connected to the power supply pins of two 555 timers and a three-input OR gate chip; the trigger pin 2 of the first 555 timer chip U1 and the trigger pin 2 of the second 555 timer chip U2 are connected; the output pin 3 of the first 555 timer chip U1, the output pin 3 of the second 555 timer chip U2, and one pin of the push-button switch S1 are respectively connected to the input terminal of the three-input OR gate chip U3, and the output terminal of the OR gate chip U3 is connected to the trigger pin 2 of the two 555 timer chips, and a pull-up resistor R1 is connected to VCC; the other end of the push-button switch S1 is grounded. The pulse width Tw1 of the first 555 timer chip U1 is smaller than the pulse width Tw2 of the second 555 timer chip U2; The first 555 timer chip U1 and the second 555 timer chip U2 respectively constitute monostable trigger circuits; When the timer locking circuit operates the push button switch S1, the first 555 timer chip U1 and the second 555 timer chip U2 work simultaneously. Within the transient pulse time width Tw1 of the first 555 timer chip U1, a signal is input to the control loop, and the control switch is closed. At this time, the circuit is locked, and the push button switch S1 cannot be operated. After the transient pulse duration Tw2 of the second 555 timer chip U2, the transient pulse of the second 555 timer chip U2 changes to a steady state; at this time, the circuit is unlocked and the push-button switch S1 is in an operable state.

2. The timer lockout circuit with adjustable control loop pulse width according to claim 1, characterized in that... The reset pin 4 of the first 555 timer chip U1 and the second 555 timer chip U2 are connected to the power supply pin 8 of the corresponding timer, so that both timers are in normal working condition and are not cleared.

3. A timer lockout circuit with adjustable control loop pulse width according to claim 1, characterized in that... The voltage control pins 5 of the first 555 timer chip U1 and the second 555 timer chip U2 are connected to external filter capacitors C2 and C4 respectively and then grounded.

4. A timer lockout circuit with adjustable control loop pulse width according to claim 3, characterized in that... The filter capacitors C2 and C4 are 0.01 microfarads.

5. A timer lockout circuit with adjustable control loop pulse width according to claim 1, characterized in that... The first 555 timer chip U1 has pins 7 and 6 grounded through capacitor C1 and then connected to the operating power supply VCC through resistor R2; the second 555 timer chip U2 has pins 7 and 6 grounded through capacitor C3 and then connected to the operating power supply VCC through resistor R4.

6. A timer lockout circuit with adjustable control loop pulse width according to claim 5, characterized in that... Both resistors R2 and R4 are variable resistors. By adjusting their resistance values, the pulse width Tw1 of the first 555 timer chip U1 is made smaller than the pulse width Tw2 of the second 555 timer chip U2.

7. A timer lockout circuit with adjustable control loop pulse width according to claim 1, characterized in that... The pin of the push-button switch S1 connected to the three-input OR gate chip U3 is connected to a pull-up resistor R3 to VCC.

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