Average current control circuit and method

Abstract

An average current control circuit and method are disclosed. A control circuit includes: an output terminal configured to be coupled to a control terminal of a transistor having a current path coupled to an inductor; a transconductance amplifier configured to generate a sense current based on a current flowing through the current path of the transistor; and a first capacitor. The control circuit is configured to: turn on the transistor based on a clock signal, integrate the sense current with an integration capacitor to generate a first voltage, generate a second voltage on the first capacitor based on the first current, generate a second current based on the second voltage, generate a third voltage based on the second current, turn off the transistor when the first voltage becomes higher than the third voltage, discharge the integration capacitor when the transistor is turned off, and adjust the average output current flowing through the inductor based on the first current.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to co-pending U.S. patent application No. 2000006677 filed on the same day as the present application and entitled “Average Current Control Circuit and Method”. 17 / 487,944 and is associated with attorney docket No. ST-19-AG-0939US01, and co-pending U.S. patent application No. filed on the same day as this application, entitled “QR-Operated Switching Converter Current Driver.” 17 / 487,966 and are associated with Docket No. ST-19-AG-0942US01, which applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and methods, and, in particular embodiments, to an average current control circuit and method. Background Art

[0004] A light emitting diode (LED) driver is configured to provide enough current to illuminate the LED. A switching voltage regulator can be used to drive the LED.

[0005] The intensity of light produced by an LED is related to the average current flowing through the LED. Generally, the higher the average current flowing through the LED, the higher the light intensity produced by the LED. Therefore, it is usually desirable to use a current driver to drive the LED in order to accurately control the average current flowing through the LED.

[0006] By controlling the average current flowing through the LED, the LED can be dimmed. For example, reducing the intensity of the light produced by the LED can be achieved by reducing the average current flowing through the LED.

[0007] Fluctuations in the average current flowing through the LED may result in fluctuations in the light emitted by the LED.Therefore, a switching converter current driver may be used to properly drive the LED by switching at a frequency above the flicker fusion threshold.

[0008] LED lamp drivers are typically specified with a rated output current (sometimes user programmable within a range) and an output voltage range to power different types / lengths of LED strings. It’s important to note that the rated output current is usually very precise, typically to within 5%.

[0009] It is also common for LED lamp drivers to provide dimming capability, that is, the ability to reduce the LED current from the rated value to a low value (sometimes less than 1%) to enable the user to reduce the light output intensity of the LED string. It is usually desirable that the LED current reduction and the resulting light modulation be seamless and flicker-free. Summary of the Invention

[0010] According to one embodiment, a control circuit includes: an output terminal configured to be coupled to a control terminal of a first transistor, the first transistor having a current path coupled to an inductor; a transconductance amplifier configured to generate a sense current based on a current flowing through the current path of the first transistor; and a first capacitor, wherein the control circuit is configured to: turn on the first transistor based on a clock signal, integrate the sense current using an integrating capacitor to generate a first voltage, generate a first current, generate a second voltage on the first capacitor based on the first current, generate a second current based on the second voltage, generate a third voltage based on the second current, turn off the first transistor when the first voltage becomes higher than the third voltage; discharge the integrating capacitor when the first transistor is turned off; and adjust an average output current flowing through the inductor based on the first current.

[0011] According to one embodiment, a method for regulating an average output current flowing through an inductor includes: turning on a power transistor based on a clock signal, wherein a current path of the power transistor is coupled to the inductor; generating a sense current based on a current flowing through the current path of the power transistor; integrating the sense current with an integrating capacitor to generate a first voltage; generating a first current; generating a second voltage on the first capacitor based on the first current; generating a second current based on the second voltage; generating a third voltage on the second capacitor based on the second current; turning off the power transistor when the first voltage becomes higher than the third voltage; discharging the integrating capacitor when the power transistor is turned off; and regulating the average output current based on the first current.

[0012] According to one embodiment, a switching converter includes: a power transistor; a sense resistor coupled to a current path of the power transistor; an inductor coupled to the current path of the power transistor; a driver having an output terminal coupled to a control terminal of the power transistor; a flip-flop having a first output coupled to an input of the driver and a first input configured to receive a clock signal, wherein the flip-flop is configured to generate a first signal at the first output terminal of the flip-flop, and wherein the flip-flop is configured to turn on the power transistor using the first signal based on the clock signal; a first comparator having an output coupled to a second input of the flip-flop, wherein the flip-flop is configured to turn off the power transistor using the first signal based on the output of the first comparator; a transconductance amplifier having a first input and a second input coupled to a first terminal and a second terminal of the sense resistor, respectively, and an output coupled to the first input of the first comparator; an integrating circuit; a capacitor coupled to the output of the transconductance amplifier and the first input of the first comparator; a first switch coupled to the integrating capacitor, the first switch being configured to discharge the integrating capacitor when the power transistor is turned off; a zero-crossing detection circuit having a current path coupled to the power transistor and an input of the inductor, wherein the zero-crossing detection circuit is configured to generate a freewheeling signal based on demagnetization of the inductor; a first current generator configured to generate a first current, the first current generator being coupled to the first capacitor at a first node; a first resistor coupled between the first node and a reference power supply terminal; a second switch coupled in series with the first resistor and configured to be controlled based on the freewheeling signal; the second current generator being configured to generate a second current based on a voltage at the first node; a third switch coupled between the second current generator and the second input of the transconductance amplifier; and a fourth switch coupled between the third switch and the reference power supply terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 An LED lamp driver according to an embodiment of the present invention is shown;

[0015] Figure 2 shows a schematic diagram of a buck converter according to an embodiment of the present invention;

[0016] Figure 3 and Figure 4 The embodiment of the present invention is shown Figure 2 Schematic diagram of the interface circuit (I / F);

[0017] Figure 5 1. A schematic diagram of a zero-crossing detection (ZCD) circuit according to an embodiment of the present invention is shown;

[0018] Figure 6shows a reference generator according to an embodiment of the present invention;

[0019] Figure 7 and Figure 8 The embodiment of the present invention is shown Figure 2 The waveforms associated with the buck converter, which consists of Figure 6 The reference generator is implemented and operates in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) respectively;

[0020] Figure 9 shows a schematic diagram of a control circuit according to an embodiment of the present invention;

[0021] Figure 10 and Figure 11 Schematic diagrams showing a clock circuit and related waveforms according to an embodiment of the present invention;

[0022] Figure 12 shows a schematic diagram of a reference generator according to an embodiment of the present invention;

[0023] Figure 13 Schematic diagram of a device coupled to a Figure 3 a schematic diagram of a portion of a control circuit of an interface circuit;

[0024] Figure 14 The embodiment of the present invention is shown Figure 13 A schematic diagram of a portion of a control circuit, the control circuit being coupled to Figure 4 Interface circuit;

[0025] Figure 15-17 A schematic diagram illustrating a reference generator according to an embodiment of the present invention; and

[0026] Figures 18-20 FIG. 1 is a schematic diagram of a switching converter according to an embodiment of the present invention.

[0027] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0028] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0029] The following description shows various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiments" in this specification indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific configurations, structures, or features may be combined in any appropriate manner.

[0030] Embodiments of the present invention will be described in a specific context, such as a current-switching converter (constant current source) LED driver for solid-state lighting (SSL), for example, driving one or more LEDs as a load. In some embodiments, the load may not include LEDs. Some embodiments may be implemented in applications other than SSL, such as industrial, consumer, ICT, white goods, etc., either "as is" or with minimal adaptation. Some embodiments may be used in voltage-switching converters.

[0031] In one embodiment of the present invention, the average inductor current of a buck converter operating in continuous conduction mode (CCM) is regulated by sensing only the current flowing through the power transistor, wherein the regulated current is independent of the switching frequency of the buck converter. Some embodiments are based on a charge mode control core that allows stable CCM operation with a fixed or quasi-fixed switching frequency. In some embodiments, a zero current detection (ZCD) circuit implements discontinuous conduction mode (DCM) operation with a nominally unchanged control scheme, which advantageously allows good accuracy of output current regulation during analog dimming. In some embodiments, a voltage feed-forward circuit compensates for propagation delays so that the regulated output current is less sensitive to input and output voltage variations.

[0032] Figure 1 FIG. 1 shows an LED lamp driver 100 according to an embodiment of the present invention. The LED lamp driver 100 includes a switch mode power supply (SMPS) 102 and an SMPS 104 for driving an LED string 106. The switching converter 102 provides a regulated DC output voltage V across a storage capacitor 108. 102 , the energy storage capacitor 108 supplies power to the cascade converter 104. The converter 104 provides a regulated output current that powers the LED string 106.

[0033] In some embodiments, the switching converter 102 can be implemented as a power factor corrector (PFC) front-end converter that can extract a sinusoidal current Imains from the power line that is in phase with the sinusoidal line voltage Vmains (e.g., 60 Hz, 110 Vrms; 50 Hz, 220 Vrms). Using a PFC front-end converter can advantageously achieve a high power factor and low distortion of the input current. In some embodiments, using the switching converter 102 implemented with PFC can advantageously help maintain low harmonic emissions, which can advantageously help comply with standards such as IEC61000-3-2, which sets Class C harmonic emission limits for applications such as LED lamp drivers. In some embodiments, implementing the converter 102 with PFC advantageously helps keep the total harmonic distortion (THD) of the input current Imains low.

[0034] The AC / DC switching converter 102 can output a current I 102 For example, the current I 102 The ripple may exhibit a high frequency component at the switching frequency of the converter 102 (typically above 50 kHz) and a low frequency component at twice the frequency of the AC power line (drawn from the power line and passed to its output by the pulsating nature of the power converter 102). If the low frequency ripple is provided to the LED string 106, it may result in an average LED current I LED The low frequency ripple may cause a decrease in the operating temperature of the LEDs in the LED string 106, which may shorten the life of the LEDs in the LED string 106. This low frequency ripple may also cause light fluctuations (flickering and shimmering), which may be undesirable if noticeable and has been reported to cause health problems even when not noticeable.

[0035] PFC output voltage V 102 may be affected by the output current I 102 The converter 102 typically regulates the output voltage V by using a low-bandwidth control loop. 102 The DC value of the input current can be adjusted to achieve high power factor and low distortion of the input current, but low frequency output ripple may not be suppressed.

[0036] In some embodiments, two-stage power conversion is used, such as Figure 1 The diagram shown (front-end PFC converter 102 supplies power to capacitor 108, and cascaded post-regulator converter 104 provides a regulated current to LED string 106) advantageously helps prevent LED string 106 from being exposed to ripple at the output of PFC converter 102. For example, in some embodiments, converter 104 provides a DC constant current I regulated by a wideband control loop that can suppress low-frequency input voltage ripple. LED, which advantageously optimizes the utilization of the LED string 106 and provides flicker-free operation of the LED string 106 .

[0037] In some embodiments, converter 102 may be implemented as a boost converter, while converter 104 may be implemented as a buck converter. For example, in some embodiments, to deliver less than 100W of power to LED string 106, voltage V 102 The voltage V may be, for example, between 100 V and 400 V, and the converter 104 provides the voltage V at a level suitable for the LED string 106. LED , for example, between 30 V and 60 V. In some embodiments, implementing converter 102 as a step-up converter and implementing converter 104 as a step-down converter can advantageously maintain the current I 102 (and the associated low frequency ripple) is low and may advantageously allow capacitor 108 to be implemented without using bulky, large value storage capacitors. Implementing converters 102 and 104 as step-up and step-down converters, respectively, may also advantageously facilitate compliance with safety extra low voltage (SELV) requirements that place V LED Limited to 60V.

[0038] In some embodiments, converter 102 may be implemented as a flyback converter, which may advantageously provide isolation from the mains. Isolation from the mains may advantageously facilitate compliance with electrical safety standards, such as IEC 60950, IEC 62368, and IEC 61347-1.

[0039] Figure 2 1 shows a schematic diagram of a buck converter 200 according to an embodiment of the present invention. Buck converter 200 includes a power transistor 202, an interface (I / F) circuit 210, a sense resistor 208, an inductor 204, and a control circuit 220. Control circuit 220 includes a transconductance amplifier (OTA) 222, a gate driver 218, a zero current detection (ZCD) circuit 212, a flip-flop 216, a clock circuit 214, a capacitor 230, a switch 228, a comparator 224, and a reference generator 226. SMPS 104 can be implemented as a buck converter 200 (e.g., where node N1 receives a voltage V 102 As V in ).

[0040] Although LED string 106 is shown as the load driven by buck converter 200, in some embodiments, other loads instead of or in addition to the LED string may be driven by buck converter 200. For example, in some embodiments, load 106 may be a rechargeable battery.

[0041] like Figure 2As shown, in some embodiments, power transistor 202 has a source connected to ground, freewheeling diode 206 is connected to node N1, and load 106 is attached to node N1 in series with inductor 204. Such a configuration can advantageously allow transistor 202 to be driven more easily than driving a floating power switch, and allows control circuit 220 to be referenced to ground, which can advantageously allow for simplified interfacing with lamp controls, such as remote on / off, dimming circuits, and the like.

[0042] Converter 202 can operate in continuous conduction mode (CCM). Operating converter 202 in CCM advantageously allows for a lower capacitance of output capacitor 232. Using a lower capacitance can advantageously allow for the use of ceramic capacitors rather than electrolytic capacitors, which can advantageously result in higher reliability and a shorter lifespan for converter 202. In some embodiments, output capacitor 232 can be omitted.

[0043] Converter 202 can operate in discontinuous conduction mode (DCM), which can advantageously allow the current I LED As will be described in more detail later, in some embodiments, the ZCD circuit 212 implements DCM operation with a nominally unchanged control scheme (eg, as given by Equation 11).

[0044] During normal operation (e.g., in CCM or DCM mode), power transistor 202 is turned on when a pulse delivered by clock 214 sets flip-flop 216. Power transistor 202 is turned off when flip-flop 216 is reset by comparator 224, which triggers when voltage Vq equals voltage Vqref. In some embodiments, the pulse delivered by clock 214 has a fixed switching period Ts.

[0045] Regardless of the operating mode, the current I delivered to the LED string 106 LED is the inductor current I L(t) During the on-time T of the power transistor 202 ON The inductor current I flowing through the power transistor 202 during L(t) The portion Isw(t) of the sense resistor 208 is read by the voltage drop Vcs(t) across the sense resistor 208 and brought to the non-inverting input of the OTA 222, the inverting input of which is connected to ground.

[0046] OTA 222 outputs a current Iq(t) that is proportional to Vcs(t). For example, in some embodiments, the current Iq(t) can be given by the following equation:

[0047] Iq(t)=g m ·Vcs(t) (1)

[0048] where g m is the transconductance of OTA 222.

[0049] The current Iq(t) charges the integration capacitor 230 during the time Ton. When the power transistor 202 is turned off, the capacitor 230 is reset by the switch 228 and is in the switching period T S The discharge is maintained during the remaining portion of the on-time, so that Vq starts to ramp up from 0V during the next on-time of the power transistor 202.

[0050] During normal operation, regardless of the operating mode (CCM or DCM), the voltage Vq developed across the integrating capacitor 230 can be given by the following equation:

[0051]

[0052] Where Cx represents the capacitance of the capacitor 230 , Ton represents the time instant when the power transistor 202 is turned off, and Rs represents the resistance of the sense resistor 208 .

[0053] When the buck converter 200 operates in CCM mode, the current Isw(t) flowing through the sense resistor 208 can be given by the following equation:

[0054]

[0055] Among them, I swCCM(t) Indicates the current Isw(t) in CCM mode, I LED_CCM Indicates the average current I in CCM mode LED , L represents the inductance of the inductor 204 .

[0056] From Equation 2 and Equation 3, it can be concluded that in CCM mode, the voltage Vq can be given by the following equation

[0057]

[0058] As will be described in more detail later, since the turn-off condition of the power transistor 202 is V qCCM = Vqref, so the reference generator 226 can be designed in a way to generate the reference voltage Vqref so that the current I LED_CCM Independent of voltage V LED Or input voltage Vin (so that current I LED_CCM Not based on voltage V LED or input voltage Vin). For example, in some embodiments, the current I LED CCM It can be given by the following equation

[0059]

[0060] Where α is a factor that may depend on internal fixed parameters, such as a resistor and / or a reference current internal to the controller 220 .

[0061] As shown in Equation 5, in some embodiments, I LED_CCM It can be determined by user-selected parameters (e.g., external resistor Rs) and internal fixed parameters (Cx, gm, α) and is independent of the voltage V of the LED string 106. LED , nor does it depend on the input voltage V in or the inductance L of the inductor 204, nor does it depend on the switching frequency F SW (in ).

[0062] When the buck converter 200 operates in DCM mode, the current Isw(t) flowing through the sense resistor 208 can be given by the following equation:

[0063]

[0064] Among them Isw DCM(t) The current I delivered to the LED string 106 is LED It can be given by the following equation

[0065]

[0066] Among them, I LED_DCM Indicates the average inductor current I in DCM mode LED , T R Indicates the demagnetization time T FW (For example, if the voltage V FW ) and the time between the power transistor 202 being turned on (thus, T R Indicates the inductor current I L The time to zero, T S -T R Indicates the inductor current I L greater than zero).

[0067] Substituting Equation 6 into Equation 2 and solving the integral yields

[0068]

[0069] where Vq DCM represents the voltage Vq in DCM mode. Considering Equation 7, Equation 8 can be rewritten as

[0070]

[0071] As will be described in more detail later, since the turn-off condition of the power transistor 202 is Vq DCM Equal to Vq ref So the reference generator 226 can generate the reference voltage Vq ref is designed so that the current I LED_DCM Independent of voltage V LED Or input voltage V in Or switching period T S (so that the current I LED_CCM Not based on voltage V LED Or input voltage V in Or switching period T S For example, in some embodiments, the current I LED_DCM It can be given by the following equation

[0072]

[0073] This is the same as Equation 5. Therefore, in some embodiments, the average current I LED is advantageously independent of the operating mode (CCM or DCM) of the buck converter 200, for example, as given by

[0074]

[0075] Advantages of some embodiments include allowing precise control of the output current I in CCM or DCM mode. LED , while only monitoring the current Isw(t) flowing through the power transistor 202. Therefore, some embodiments advantageously achieve accurate control of the output current I in a low-cost, low-complexity manner. LED , and does not dissipate excessive energy. For example, some embodiments advantageously avoid using a resistor in series with the inductor to measure the inductor current I L In some embodiments, avoiding the use of a series resistor to measure inductor current can advantageously reduce power consumption, avoid the use of differential sensing with large common-mode dynamics, and / or avoid the use of a level shifter.

[0076] Additional advantages of some embodiments include achieving high output current (I LED ) accuracy, which is sensitive to the inductance value L, operation mode (DCM or CCM), switching period T S 、Input voltage V in and LED string voltage V LED Some embodiments advantageously allow adaptation to different V LED setup without the need for external calibration or correction devices.

[0077] In some embodiments, control circuit 220 may be implemented in the same (e.g., monolithic) integrated circuit, while elements 202, 204, 206, 208, 210, and 106 are implemented external to the integrated circuit (e.g., such that the integrated circuit may include a circuit for receiving voltage V ZCD The demagnetization sensing input, for example, Figure 2 Thus, some embodiments advantageously allow a user to precisely control the current I by varying the resistance value Rs of the external component (208). LED In some embodiments, components 206 and 210 are integrated in the same package external to an integrated circuit including control circuit 220. In some embodiments, components 202 and / or 204 may be integrated in the same package external to an integrated circuit including control circuit 220.

[0078] In some embodiments, the circuitry of buck converter 200 can be integrated in different ways. For example, in some embodiments, components 202 and / or 204 can be integrated into the same package as components 206, 210, 212, 214, 216, and 218. In some embodiments, interface circuit 210 can be implemented within an integrated circuit. In some embodiments, each of components 106, 202, 204, 206, 208, 210, 212, 214, 216, 218, 222, 224, 226, 228, and 230 can be implemented in a discrete manner. Other implementations are also possible.

[0079] In some embodiments, control circuit 220 includes reference generator 226, comparator 224, switch 228, capacitor 230, and transconductance amplifier 222. Other implementations are also possible. For example, in some embodiments, part or all of reference generator 226 can be implemented outside of control circuit 220.

[0080] In some embodiments, capacitor 234 may be the output capacitor of a previous power stage. For example, in some embodiments, capacitor 108 is connected to node N1 and capacitor 234 may be omitted.

[0081] The power transistor 202 may be implemented as a metal oxide semiconductor field effect transistor (MOSFET). The power transistor 202 may also be implemented in other ways. For example, in some embodiments, the power transistor 202 may be implemented as a gallium nitride (GaN) transistor or as an insulated gate bipolar transistor (IGBT).

[0082] In some embodiments, clock 214 may be implemented in a conventional manner to generate a fixed frequency clock signal V S (For example, with period T SOperating the buck converter 200 at a fixed frequency, or substantially fixed frequency, advantageously allows the use of an optimized inductor that mitigates efficiency drops at low dimming levels.

[0083] The interface circuit 210 is configured to determine the current I flowing through the inductor 204 based on the current I L Generate voltage V ZCD Voltage V ZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0084] In some embodiments, the ZCD circuit 212 is configured to sense when the current I L The start of voltage ringing at the floating terminal of the inductor 204 (the drain terminal of the power transistor 202) occurs when the current reaches 0 mA, and generates an indication of the demagnetization time T FW The signal V FW For example, in some embodiments, the ZCD circuit 212 includes a circuit for receiving a voltage V ZCD The demagnetization sense input, and based on the voltage V ZCD Generate signal V FW , so that the signal V FW High during the demagnetization period of the inductor 204. In some embodiments, the ZCD circuit 212 can be implemented in a conventional manner.

[0085] Figure 3 2 is a schematic diagram of an interface circuit 300 according to an embodiment of the present invention. The interface circuit 210 may be implemented as the interface circuit 300. The interface circuit 300 includes an auxiliary winding 304 of the inductor 204 and resistors 306 and 308 forming a voltage divider.

[0086] In some embodiments, the auxiliary winding 304 tracks the voltage at the drain terminal of the power transistor 202 and has a polarity such that when the power transistor 202 is turned on (at T ON During this period) its voltage is negative.

[0087] like Figure 3 As shown, the interface circuit 300 is based on I flowing through the inductor 204. L Current generates voltage V ZCD Voltage V ZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0088] Figure 4FIG2 shows a schematic diagram of an interface circuit 400 according to an embodiment of the present invention. Interface circuit 210 can be implemented as interface circuit 400. Interface circuit 400 includes a DC blocking capacitor 404 (e.g., connected to the drain terminal of power transistor 202) and resistors 406 and 408 forming a voltage divider. Similar to interface circuit 300, voltage V ZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0089] Figure 5 Shown is a schematic diagram of a ZCD circuit 500 according to an embodiment of the present invention. ZCD circuit 212 can be implemented as ZCD circuit 500. ZCD circuit 500 includes a trigger 504, a comparator 502, an OR gate 506, and a low-pass filter 512 with a resistor 510 and a capacitor 508. Low-pass filter 512 and comparator 502 form a negative derivative detector.

[0090] In some embodiments, the ZCD circuit 500 can be used to determine the time from when the power transistor 202 is turned off to when the current I L Demagnetization time T to reach 0mA (in DCM mode) FW For example, Figure 5 As shown, the ZCD circuit 500 monitors the voltage V ZCD (eg, as generated by interface circuit 300 or 400) to sense the onset of voltage ringing at the floating terminal (drain) of power transistor 202, which occurs when inductor current I L Therefore, in some embodiments, when the current I L When the voltage V reaches zero FW is reset (eg, to logic low), and when the power transistor 202 is turned on (eg, according to the clock signal V S ), the voltage V FW is set (e.g., to logic high). For example, in some embodiments (e.g., Figure 5 As shown), since the inverting input of the comparator 502 receives the voltage V ZCD , and the non-inverting input receives the voltage V filtered by the low-pass filter 512 and shifted down by the offset Vth ZCD , when V ZCD When experiencing a negative edge, the output of the low-pass filter 512 lags behind, and when their difference exceeds Vth, the comparator 502 triggers, thereby resetting the flip-flop 504. In some embodiments, in CCM mode, the demagnetization time T FW Equal to the power transistor 202 turn-off time T OFF .

[0091] In some embodiments, the offset Vth can be a constant offset voltage, such as 25 mV. Other voltages (eg, higher than 25 mV, such as 30 mV, or higher, or lower than 25 mV, such as 20 mV, or lower) can also be used.

[0092] Figure 6 6 shows a reference generator 600 according to an embodiment of the present invention. The reference generator 226 can be implemented as the reference generator 600. The reference generator 600 includes current sources 602 and 616, 608, 618, 620, and 626, a resistor 606, capacitors 614, 628, and 630, an OR gate 610, an AND gate 612, a one-shot circuit 622, and a delay circuit 624. Figure 6 As shown, the reference generator 600 can be generated by the signal V Q and (e.g., from flip-flop 216) and signal V FW (eg, from ZCD circuit 212) control.

[0093] Figure 7 Waveforms 700 associated with a buck converter 200 implemented using reference generator 600 and operating in CCM mode are shown in accordance with an embodiment of the present invention.

[0094] like Figure 6 and Figure 7 As shown, during CCM mode, switch 608 is clocked at V S Each clock cycle remains closed, as signal V 608 As shown. Since the switch 608 remains closed during the CCM mode, the voltage V across the capacitor 614 CT It can be given by the following equation

[0095] V CT =R t I ch (12)

[0096] where R t represents the resistance of resistor 606, C t represents the capacitance of capacitor 614, I ch represents the current generated by the current source 602 .

[0097] Then the voltage V on the capacitor 614 is reduced by the voltage-controlled current source 616. CT Converted to current I ch2 Current I ch2 It can be given by the following equation

[0098] I ch2 =g m2 ·V CT (13)

[0099] where g m2 is the transconductance of the voltage-controlled current source 616 .

[0100] Since when the power transistor 202 is turned on (during the on time T ON During the on-time T ON As shown in the one-shot circuit 622, once the signal V Q When the signal V Q After a predetermined delay (eg, 100 ns determined by delay circuit 624 ) after being deasserted, capacitor 628 is discharged through switch 626 (eg, such that capacitor 628 is fully discharged the next time power transistor 202 turns on).

[0101] Assume that the capacitance C of capacitor 630 is H Substantially smaller than the capacitance C of capacitor 628 TR (e.g., less than 10 times), capacitor 630 is charged to the same voltage V as capacitor 628 CTR Thus, the circuit including capacitors 628 and 630 and switches 618, 626, and 620 may be understood as a track and hold circuit.

[0102] Since during the on-time T ON During this period, the voltage V CTR Linear increase (due to the constant current I ch2 charging), and considering equations 12 and 13, the reference voltage Vq ref It can be given by the following equation

[0103]

[0104] Since the power transistor 202 is at a voltage Vq equal to the voltage Vq ref When it is turned off, and considering equations 4 and 14, the current I LED_CCM It can be given by the following equation

[0105]

[0106] where α is given by

[0107]

[0108] Figure 8Waveforms 800 associated with buck converter 200 implemented using reference generator 600 and operating in DCM mode are shown in accordance with an embodiment of the present invention.

[0109] like Figure 6 and Figure 8 As shown, during DCM mode, the switch 608 only switches when the inductor current I L When it is greater than zero (in the time interval T s -T r During the switching period T S The rest of the circuit is disconnected. Assuming the time constant R t ·C t Much longer than the switching period T S (e.g., 10 times larger), the voltage V CT It can be given by the following equation

[0110]

[0111] Since the capacitor 628 is on during the conduction time T of the power transistor 202 ON During this period, the current I ch2 charging, and considering equations 13 and 17, the voltage Vq in DCM mode ref It can be given by the following equation

[0112]

[0113] It can be seen that Equation 18 is also valid in CCM mode (for example, if T R = zero, then Equation 18 is the same as Equation 14).

[0114] Based on Equations 9 and 18, in some embodiments, the current I LED_DCM It can be given by the following equation

[0115]

[0116] where α is given by Equation 16. As shown, Equations 15 and 19 are identical, resulting in an average current I that is independent of the operating mode (CCM, DCM) of the buck converter 200. LED The control scheme, in some embodiments, is captured by Equations 11 and 16.

[0117] In some embodiments, as can be seen in Equations 11 and 16, the average current I LED It can only rely on the resistor Rs (which can be user selectable) and the internal fixed parameter I ch 、R t 、C x 、g m 、CTR and g m2 , and does not depend on the voltage V LED or V in , or inductance L or switching period T S , regardless of the operating mode (CCM, DCM). For example, in some embodiments, the switching frequency F SW (e.g., between 130kHz and 230kHz), without causing the average current I LED substantial changes in the target average current value (e.g., less than 1% change in the target average current value).

[0118] like Figure 7 and Figure 8 As shown, in some embodiments, the voltage Vq ref is essentially constant with the switching cycle (e.g., based on Equation 18 and assuming R t ·C t Much longer than the switching period T S ).

[0119] Some embodiments increase the current I ch (which can be generated based on a resistor) and the resistor R t (e.g., resistance ratio) matching, by matching the transconductance g m and g m2 (which may also rely on identical (or matching) resistors (not shown)), and by matching capacitors C x and C TR (e.g., capacitance ratio), advantageously achieving an average current I LED High-precision control.

[0120] In some embodiments, the one-shot circuit 622 is configured to Q A pulse of a predetermined duration (e.g., 20 ns) is generated when the one-shot circuit 622 transitions from high to low. Pulses of different durations may also be used (e.g., greater than 20 ns, such as 25 ns, 30 ns, or more, or less than 20 ns, such as 18 ns, 15 ns, or less). One-shot circuit 622 may be implemented in any manner known in the art.

[0121] In some embodiments, the delay circuit 624 is configured to generate the signal V 626 , which is the signal V 620 The delayed form of the signal V 626 and V 620The delay between is a predetermined delay (e.g., 100 ns). Delays of different durations may also be used (e.g., greater than 100 ns, such as 120 ns, 150 ns, or more, or less than 100 ns, such as 90 ns, 85 ns, or less). Delay circuit 624 may be implemented in any manner known in the art.

[0122] In some embodiments, for example, by using the signal V Q The enable input of the control current source 616 can eliminate the need for switch 618 .

[0123] like Figure 2 As shown, the resettable integrator circuit including switch 228 and capacitor 230 forms the charge mode control core, where V q During the on-time T ON During the switching cycle of the buck converter 200, the input voltage V in When the buck converter 200 operates in CCM mode and a fixed frequency (constant T S ) operation, the charge mode control core may exhibit subharmonic instability issues.

[0124] In some embodiments, when the inductor current I L The peak-to-peak ripple is higher than the current I L When the voltage drop is twice the average value of , the buck converter 200 switches from the CCM mode to the DCM mode, which can advantageously help solve the subharmonic instability problem when the buck converter 200 operates in the CCM mode.

[0125] In some embodiments, when the inductor current I L The peak-to-peak ripple is higher than the current I L When the average value of V is twice that of CCM, the transition from CCM mode to DCM mode may result in a duty cycle of less than 50% for the power transistor 202. In some embodiments, it is possible to have a duty cycle higher than 50% (thus, V LED Higher than V in_min / 2). For example, Figure 9 FIG2 shows a schematic diagram of a control circuit 900 according to an embodiment of the present invention. The control circuit 900 includes a reference generator 926, a comparator 224, a current source 904, a switch 228, an integrating capacitor 230, and a transconductance amplifier 222. The reference generator 926 includes current sources 902, 602, and 616, switches 608, 618, and 626, a resistor 606, capacitors 614 and 628, an OR gate 610, an AND gate 612, a one-shot circuit 622, and a delay circuit 624. The control circuit 220 can be implemented as the control circuit 900.

[0126] like Figure 9 As shown, the integrating capacitor 230 is supplied by the current I q and I sc In some embodiments, the current I sc To meet this condition

[0127]

[0128] Make the charge mode control loop unconditionally stable.

[0129] In CCM mode, the current I LED_CCM It can be given by the following equation

[0130]

[0131] Among them, I sc represents the current generated by the current source 904. In some embodiments, the current I sc With current I ch matching, which can advantageously reduce or eliminate the current I LED In some embodiments, the current I k To meet this condition

[0132]

[0133] This can advantageously enable I LED_CCM is given by Equation 15, while still achieving slope compensation. In some embodiments, current generators 902 and 904 are always active, and Equation 21 also applies to DCM mode.

[0134] In some embodiments, since current generator 902 is connected in parallel with current generator 602, current generator 902 may be omitted and the current generated by generator 602 may be increased by I k To achieve the same result. In some such embodiments, the ch Replace with (I ch -I k ) to modify Equation 19.

[0135] In some embodiments, the buck converter 200 uses fixed off-time (FOT) PWM modulation. With FOT PWM modulation, during a switching cycle, when the current I L When the predetermined value is reached, the power transistor 202 is turned off and the power transistor 202 is switched off at a predetermined fixed time interval T. OFF After that (for example, determined by a timer circuit), it is restored to conduction. Using FOT can be advantageous by controlling the current I L The peak value of the average inductor current I is achieved by CCM operation.LED By making the charge mode control loop unconditionally stable, using FOT PWM modulation can advantageously help solve the subharmonic instability problem when the buck converter 200 operates in CCM mode.

[0136] In some embodiments, FOT quasi-fixed frequency (FOT-QFF) modulation is used. ON The measurement is based on T ON Slowly modulate T OFF , so that T ON and T OFF The sum is constant or substantially constant. In some embodiments, using FOT-QFF modulation can advantageously help resolve the subharmonic instability problem when the buck converter 200 operates in CCM mode by making the charge mode control loop unconditionally stable while keeping the operating frequency substantially fixed. For example, Figure 10 FIG2 is a schematic diagram of a clock circuit 1000 according to an embodiment of the present invention. The clock circuit 214 may be implemented as the clock circuit 1000 and may be used to operate the buck converter 200 with FOT-QFF modulation.

[0137] Figure 11 Waveforms 1100 associated with clock circuit 1000 are shown in accordance with an embodiment of the present invention. Figure 10 and Figure 11 They can be understood together.

[0138] from Figure 10 As can be seen, assuming the time constant R osc ·C osc Much longer than the switching period T S (For example, more than 10 times larger), then the reference voltage V th_ramp It can be given by the following equation

[0139]

[0140] Among them, I osc represents the current generated by the current source 1002, R osc represents the resistance of resistor 1004. Since T OFF Can be made with V th_ramp Crossover voltage V ramp To confirm, then

[0141]

[0142] Among them C R represents the capacitance of capacitor 1008, I R represents the current generated by the current source 1010. From equation 21, it can be concluded that the switching period T SIt can be given by the following equation

[0143]

[0144] In some embodiments, due to adjusting T OFF The mechanism responds to a switching period greater than T S Much larger time constant R osc ·C osc disturbance, so the dynamics of the FOT-QFF control system is basically similar to that of the FOT control system.

[0145] Some embodiments allow the current I to be varied in a continuous manner. LED In some embodiments, by reducing the current I ch To achieve analog dimming. For example, Figure 12 FIG. 2 is a schematic diagram of a reference generator 1200 according to an embodiment of the present invention. The reference generator 226 may be implemented as the reference generator 1200 .

[0146] The reference generator 1200 operates in a similar manner to the reference generator 600. However, the reference generator 1200 includes a circuit for generating a reference current I ch Subtract the current I dim Therefore, in some embodiments, the average current I LED It can be given by the following equation

[0147]

[0148] Among them, I dim represents the current generated by the current source 1202. As shown in Equation 26, the current I LED can be reduced to zero (by making I dim Equal to I ch In some embodiments, the current I ch and omitted current I dim To achieve dimming.

[0149] In some embodiments, the current source 1202 can be based on the voltage V dim Generated current I dim voltage-controlled current source, and where the voltage V dim For example, it is received from an input terminal of a control circuit (eg, 220 ).

[0150] In some embodiments, the reference generator 926 may be configured as follows: Figure 12 A similar approach is shown modified to include current source 1202 .

[0151] Reference again Figure 2, from the voltage Vq equal to Vq ref The propagation delay ΔT from the time when the power transistor 202 turns off to the time when the power transistor 202 turns off may not be negligible. Delaying the power transistor 202 from turning off by ΔT may cause the current I LED is greater than predicted by, for example, Equations 11 and 26. The additional inductor current I L (produced as a result of the additional time that power transistor 202 is on) may depend on the applied V in -V LED , so the V in and V LED For example, assuming that the turn-off condition of the power transistor 202 is at time t 202_off =T ON -ΔT occurs, then the time t 202_off Vq ref_202_off The value of is calculated as

[0152]

[0153] And I LED (in CCM mode) can be given by the following equation

[0154]

[0155] Among them, I LED0 represents the average current I determined by, for example, Equation 15 LED .

[0156] In some embodiments, voltage feed-forward is used to compensate for the propagation delay ΔT. For example, in some embodiments, the voltage feed-forward circuit may be based on the voltage V received from the interface circuit 210. ZCD , the injection will be with the current I sw The added current I FF .For example, Figure 13 1 shows a schematic diagram of a portion of a control circuit 1300 coupled to the interface circuit 300 according to an embodiment of the present invention. The control circuit 1300 includes a diode 1302, a current mirror 1304, a current source 1306, a resistor 1308, and a transconductance amplifier 222. The control circuit 220 may be implemented as the control circuit 1300.

[0157] In CCM mode, during the on-time T of the power transistor 202 ON During this period, the voltage V across the auxiliary winding 304 304 It can be given by the following equation

[0158]

[0159] Where n represents the turns ratio between the number of turns of the inductor 204 and the number of turns of the auxiliary winding 304. ZCD It can be given by the following equation

[0160]

[0161] where R 306 represents the resistance of the resistor 306 .

[0162] As shown by components 1304 and 1306, the current I ZCD is mirrored to produce the current I FF , which causes the offset V 1308 , the offset can be given by the following equation

[0163] V 1308 =R 1308 I FF (31)

[0164] where R 1308 represents the resistance of resistor 1308. Therefore, V qref_202_off It can be given by the following equation

[0165]

[0166] Current I LED It can be given by the following equation

[0167]

[0168] In some embodiments, R 306 Selected as

[0169]

[0170] To make I LED Equal to I LED0 , thereby advantageously compensating for the propagation delay ΔT. The same results also advantageously apply when the buck converter 200 operates in DCM mode.

[0171] like Figure 13 As shown, the interface circuit 210 can be implemented as an interface circuit 300. Other implementations are also feasible. For example, Figure 14 FIG. 1 is a schematic diagram illustrating a portion of a control circuit 1300 coupled to an interface circuit 400 according to an embodiment of the present invention.

[0172] In CCM mode, during the on-time T of the power transistor 202 ON During this period, the voltage V across the DC blocking capacitor 404 404 It can be given by the following equation

[0173] V 404 =-(V in -V LED ) (35)

[0174] Current I ZCD It can be given by the following equation

[0175]

[0176] where R 406 represents the resistance of the resistor 406 .

[0177] Equations 31-33 also apply to Figure 14 In some embodiments, R 406 Selected as

[0178]

[0179] To make I LED Equal to I LED0 , thereby advantageously compensating for the propagation delay ΔT. The same results also advantageously apply when the buck converter 200 operates in DCM mode.

[0180] Advantages of some embodiments include enabling lighting engineers to design LED lamp drivers that meet market and regulatory requirements with less effort and at lower cost.

[0181] In one embodiment, the buck converter 200 is designed to receive a V between 108V and 132V. in , generating a voltage V between 30V and 90V LED , generating an output current of 1A I LED , with a dimming range of 5% to 100% and a programmable switching frequency F above 100kHz SW (eg, at 130 kHz, 260 kHz, etc.), wherein the inductor 204 has an inductance L of 200 μH, wherein the output capacitor 232 has a capacitance of 2.2 μF, wherein the resistor 208 has a sense resistance R of 0.2Ω s In some embodiments, the buck converter 200 includes a current I ch , resistor R t 4MΩ, C t 、C x and C TR The capacitances are 50pF, 20pF and 20pF respectively, and the transconductance g m and g m2 The time intervals are 15 μS and 115 μS respectively, and the dimming gain is 1 / 100 A / A. Other implementations are also possible.

[0182] Figure 15 FIG. 1 shows a schematic diagram of a reference generator 1500 according to an embodiment of the present invention. The reference generator 1500 includes current sources 1502 and 1516, switches 608, 618, 620, and 626, a resistor 606, capacitors 614, 628, and 630, an OR gate 610, an AND gate 612, a one-shot circuit 622, and a delay circuit 624. Figure 15 As shown, the reference generator 1500 can be generated by the signals VQ and (e.g., from flip-flop 216) and signal V FW Reference generator 220 may be implemented as reference generator 1500 .

[0183] like Figure 15 As shown, the capacitor 628 is on during the conduction time T ON During this period, a constant current I ch Charging. At signal V Q At the falling edge, the voltage V on capacitor 628 CTR is transferred to capacitor 630. Therefore, the voltage V across capacitor 630 CH It can be given by the following equation

[0184]

[0185] Therefore, the current I ch2 It can be given by the following equation

[0186]

[0187] where g m2 is the transconductance of the voltage-controlled current source 1502.

[0188] For simplicity, consider DCM operation, when the inductor current I L When it is greater than zero (in the time interval T S -T R During this period, switch 608 is closed. Therefore, in DCM mode, Vq ref It can be given by Equation 18. Therefore, the reference generator 1500 can be understood as equivalent to the reference generator 600.

[0189] In some embodiments, for example, by implementing the current source 1516 as a Q The switch 618 can be omitted by controlling the voltage-controlled current source.

[0190] Figure 16FIG2 shows a schematic diagram of a reference generator 1600 according to an embodiment of the present invention. Reference generator 226 can be implemented as reference generator 1600. Reference generator 1600 includes current sources 602 and 616, switches 608, 620, and 626, resistor 606, capacitors 614, 628, and 630, an OR gate 610, an AND gate 612, a one-shot circuit 1622, and a delay circuit 624. Figure 16 As shown, the reference generator 1600 can be generated by the signal V Q and (e.g., from flip-flop 216) and signal V FW (eg, from ZCD current 212 ) control.

[0191] Reference generator 1600 operates in a similar manner to reference generator 600. However, in reference generator 1600, capacitor 628 is switched on and off during the entire switching period T S Therefore, the voltage V CTR It can be given by the following equation

[0192]

[0193] Since capacitor 614 (which controls the current I ch2 )The voltage V across the CT It can be given by the following equation

[0194]

[0195] Then, the voltage Vq ref It can be given by the following equation

[0196]

[0197] This is the same as Equation 18. Therefore, reference generator 1600 can be understood to be equivalent to reference generator 600.

[0198] In some embodiments, the one-shot circuit 1622 is configured to Q A transition from low to high generates a pulse of a predetermined duration (eg, 20 ns).

[0199] Figure 17 FIG2 shows a schematic diagram of a reference generator 1700 according to an embodiment of the present invention. Reference generator 226 can be implemented as reference generator 1700. Reference generator 1700 includes current sources 1502 and 1516, switches 608, 620, and 626, resistor 606, capacitors 614, 628, and 630, OR gate 610, AND gate 612, one-shot circuit 1622, and delay circuit 624. Figure 17 As shown, the reference generator 1700 can be generated by the signal VQ and (e.g., from flip-flop 216) and signal V FW (eg, from ZCD current 212 ) control.

[0200] Reference generator 1700 operates in a similar manner to reference generator 1500. However, in reference generator 1700, capacitor 628 is switched on and off during the entire switching period T S Therefore, Equations 40-42 apply to reference generator 1700. Therefore, reference generator 1700 can be understood as equivalent to reference generator 600.

[0201] At the current I ch is fixed in some embodiments and can be derived from equations 11 and 16

[0202]

[0203] Where β is a constant. Therefore, in some embodiments, the current I LED With a fixed internally generated current I ch The proportional coefficient β can be set by the user by selecting the resistor R S As shown earlier, the inductor current I L (the portion flowing through the power transistor 202), and based on the conduction of the power transistor 202 (T ON ) and cutoff (T OFF ) time (in CCM mode), and the time based on the power transistor 202 (T ON ) and demagnetization time (T FW ) (in DCM mode) to reconstruct the missing part to achieve the current I LED In some embodiments, the on and off time of the power transistor 202 and the demagnetization time T FW The information is encoded in the signal V Q 、 V FW and is used to control switches of reference generator 226 (eg, switches 608, 618, 620, 626) and other switches of the control circuit (eg, switches 228, 1012, 1014).

[0204] like Figure 6 As shown, in some embodiments, the switch 608 can be controlled by the signal V Q or( and V FW ) control to achieve a constant average current I L, for example, for LED driving or battery charging (eg, by replacing the LED string 106 with a rechargeable battery).

[0205] The inventors have recognized that changing the control logic of some of the switches of the control circuit 220 (e.g., switches 608, 618) may allow the control circuit 220 to be used to regulate the output current (I LED ).

[0206] Figures 18-20 FIG. 1 is a schematic diagram of a switching converter according to an embodiment of the present invention.

[0207] Figure 18 FIG2 shows a schematic diagram of a CCM / DCM boost converter 1800 according to an embodiment of the present invention. Boost converter 1800 includes a control circuit 1820, a power transistor 202, a diode 1810, an output capacitor 1812, an inductor 204, an interface circuit 210, and a resistor 208. In some embodiments, boost converter 1800 regulates the average current ILED, for example, to drive an LED string or recharge a battery, while maintaining a voltage V LED Higher than the voltage V in In some embodiments, the voltage V in It can be voltage V 102 (eg, received from converter 102).

[0208] like Figure 18 As shown, when reference generator 226 is implemented as reference generator 600, control circuit 1820 operates in a similar manner to control circuit 220. However, control circuit 1820 uses signal V FW Instead of using signal V 608 To control switch 608.

[0209] from Figure 18 It can be seen that the voltage Vq can be given by the following equation

[0210]

[0211] VQ ref It can be given by the following equation

[0212]

[0213] Therefore, the average output current I LED It can be given by the following equation

[0214]

[0215] When α is given by Equation 16, it is the same as Equation 11.

[0216] Figure 19 FIG2 shows a schematic diagram of a CCM / DCM buck-boost converter 1900 according to an embodiment of the present invention. Buck-boost converter 1900 includes a control circuit 1820, a power transistor 202, a diode 1810, an output capacitor 1812, an inductor 204, an interface circuit 210, and a resistor 208. In some embodiments, buck-boost converter 1900 regulates current I LED , for example, to drive an LED string or to recharge a battery. In some embodiments, the voltage V in It can be voltage V 102 (eg, received from converter 102).

[0217] like Figure 19 As shown, the same control circuit 1820 can be used for buck-boost operation by changing the connection of diode 1810, capacitor 1812, and load 106. Equations 44-46 also apply to buck-boost converter 1900.

[0218] Figure 20 FIG2 shows a schematic diagram of a CCM / DCM flyback converter 2000 according to an embodiment of the present invention. The flyback converter 2000 includes a control circuit 1820, a power transistor 202, a diode 1810, an output capacitor 1812, a transformer 2002, an interface circuit 210, and a resistor 208. In some embodiments, the flyback converter 2000 regulates the current I LED , for example, to drive an LED string or to recharge a battery. In some embodiments, the voltage V in It can be voltage V 102 (eg, received from converter 102).

[0219] like Figure 20 As shown, the same control circuit 1820 can be used for flyback operation by replacing the inductor 204 with the transformer 2002 and changing the connection of the diode 1810, the capacitor 1812 and the load 106.

[0220] Equations 44 and 45 also apply to the flyback converter 2000. The average output current I LED It can be given by the following equation

[0221]

[0222] Where n represents the turns ratio of transformer 2002 where N P Indicates the number of turns of the primary winding 204, N S Indicates the number of turns of the secondary winding 2004.

[0223] Advantages of some embodiments include using a single loop system, compared to conventional average current mode control methods that use two nested loops, each requiring frequency compensation. Using a single loop system can advantageously result in a simpler and lower cost implementation.

[0224] Additional advantages of some embodiments include greater versatility, as some embodiments can control the entire inductor current I L or only a portion thereof, which may advantageously allow some embodiments to be used for various purposes (e.g., controlling the output voltage V LED ).

[0225] Example embodiments of the invention are summarized herein. Other embodiments can be understood from a full understanding of the specification and claims submitted herein.

[0226] Embodiment 1. A control circuit comprises: an output terminal configured to be coupled to a control terminal of a first transistor, the first transistor having a current path coupled to an inductor; a transconductance amplifier configured to generate a sensing current based on a current flowing through the current path of the first transistor; and a first capacitor, wherein the control circuit is configured to: turn on the first transistor based on a clock signal, integrate the sensing current with an integrating capacitor to generate a first voltage, generate a first current, generate a second voltage on the first capacitor based on the first current, generate a second current based on the second voltage, generate a third voltage based on the second current, turn off the first transistor when the first voltage becomes higher than the third voltage; discharge the integrating capacitor when the first transistor is turned off; and adjust an average output current flowing through the inductor based on the first current.

[0227] Embodiment 2. The control circuit of embodiment 1, wherein the transconductance amplifier comprises a first input configured to receive a sensing voltage indicating a current flowing through a current path of the first transistor; a second input configured to receive a reference voltage; and an output configured to pass the sensing current.

[0228] Embodiment 3. The control circuit according to any one of embodiments 1 and 2 further includes: a first current generator configured to generate a first current, the first current generator being coupled to the first capacitor at a first node; and a first resistor coupled between the first node and a reference power supply terminal.

[0229] Embodiment 4. The control circuit of any one of Embodiments 1 to 3, further comprising a first switch coupled in series with the first resistor, wherein the control circuit is configured to control the first switch based on a freewheeling signal indicating demagnetization of the inductor.

[0230] Embodiment 5. The control circuit of any one of embodiments 1 to 4, wherein the control circuit is configured to: control the first transistor using the first signal; and control the first switch based on the freewheeling signal and based on the first signal.

[0231] Example 6. The control circuit according to any one of Examples 1 to 5 further includes a zero-crossing detection circuit having an input, the input being configured to be coupled to the first current path of the first transistor, wherein the zero-crossing detection circuit is configured to generate a freewheeling signal based on the input of the zero-crossing detection circuit.

[0232] Example 7. A control circuit according to any one of Examples 1 to 6, wherein the zero-crossing detection circuit includes: a first comparator having a first input coupled to the input of the zero-crossing detection circuit, and a second input coupled to the input of the zero-crossing detection circuit via a low-pass filter; and a second trigger having a first input coupled to the output of the first comparator, and an output configured to pass a freewheeling signal.

[0233] Example 8. A control circuit according to any one of Examples 1 to 7, wherein the control circuit is configured to generate a third voltage at the second node, and the control circuit further includes: a second current generator configured to generate a second current; a second switch coupled between the second current generator and the second node; and a third switch coupled between the second node and a reference power supply terminal.

[0234] Embodiment 9. The control circuit of any one of Embodiments 1 to 8, further comprising: a one-shot circuit having an output configured to control the second switch; and a delay circuit configured to control the third switch based on the output of the one-shot circuit.

[0235] Example 10. The control circuit according to any one of Examples 1 to 9 further includes: a fourth switch coupled between the second current generator and a third node, the third node coupled between the second switch and the third switch; a second capacitor coupled between the third node and a reference power supply terminal; and a third capacitor coupled between the second node and the reference power supply terminal, wherein the control circuit is configured to generate a third voltage across the third capacitor.

[0236] Example 11. A control circuit according to any one of Examples 1 to 10, wherein the control circuit is configured to generate a third voltage at the second node, and the control circuit further includes: a first current generator configured to generate a second current, the first current generator being coupled to the second node; a first resistor coupled between the second node and a reference power terminal; and a first switch coupled in series with the first resistor, wherein the control circuit is configured to control the first switch based on a freewheeling signal indicating demagnetization of the inductor.

[0237] Example 12. The control circuit according to any one of Examples 1 to 11 further includes: a first comparator having a first input configured to receive a first voltage and a second input configured to receive a third voltage; and a first trigger having a first output coupled to an output terminal, a first input configured to receive a clock signal and a second input coupled to the output of the first comparator.

[0238] Example 13. The control circuit according to any one of Examples 1 to 12 further includes a current mirror configured to be coupled to the first current path terminal of the first transistor via the interface circuit, wherein the current mirror is configured to inject a first current into the first input of the transconductance amplifier based on the current flowing through the interface circuit.

[0239] Embodiment 14 The control circuit of any one of Embodiments 1 to 13, further comprising a sense resistor coupled between the first input and the second input of the transconductance amplifier.

[0240] Embodiment 15 The control circuit according to any one of embodiments 1 to 14, further comprising a clock circuit configured to generate a clock signal.

[0241] Embodiment 16. The control circuit of any one of Embodiments 1 to 15, wherein the clock circuit is configured to generate a clock signal having a fixed frequency.

[0242] Example 17. A control circuit according to any one of Examples 1 to 16, wherein the clock circuit includes: a first switch having a first terminal configured to receive an oscillator current; a first resistor coupled to the second terminal of the first switch; a second capacitor coupled to the first resistor; a first comparator having a first input coupled to the second terminal of the first switch, and an output configured to pass a clock signal; a third capacitor coupled to the second input of the first comparator; a first current generator coupled to the third capacitor and the second input of the first comparator; and a second switch coupled across the third capacitor.

[0243] Embodiment 18. The control circuit of any one of Embodiments 1 to 17, wherein the control circuit is integrated into a single integrated circuit.

[0244] Example 19. The control circuit of any one of Examples 1 to 18, further comprising a gate driver having an input coupled to the output terminal, and wherein the first transistor is a power metal oxide semiconductor field effect transistor (MOSFET) or a GaN transistor having a gate coupled to the output of the gate driver.

[0245] Example 20. A method for regulating an average output current flowing through an inductor, the method comprising: turning on a power transistor based on a clock signal, wherein a current path of the power transistor is coupled to the inductor; generating a sensing current based on a current flowing through the current path of the power transistor; integrating the sensing current with an integrating capacitor to generate a first voltage; generating a first current; generating a second voltage on the first capacitor based on the first current; generating a second current based on the second voltage; generating a third voltage on the second capacitor based on the second current; turning off the power transistor when the first voltage becomes higher than the third voltage; discharging the integrating capacitor when the power transistor is turned off; and regulating the average output current based on the first current.

[0246] Embodiment 21. The method of embodiment 20 further includes generating a sense voltage based on a current flowing through a current path of the power transistor, wherein generating the sense current includes generating the sense current based on the sense voltage using a transconductance amplifier.

[0247] Embodiment 22. The method according to any one of embodiments 20 and 21 further includes: generating a first current using a first current generator; detecting a demagnetization time of an inductor; and controlling a first switch based on the detected demagnetization time, the first switch being coupled to the first current generator via a first resistor.

[0248] Embodiment 23. The method of any one of Embodiments 20 to 22, wherein the average output current is proportional to the first current.

[0249] Embodiment 24. The method of any one of Embodiments 20 to 23, further comprising varying the switching frequency of the power transistor without causing a substantial change in the magnitude of the average output current.

[0250] Embodiment 25. The method of any one of Embodiments 20 to 24, wherein the second voltage is substantially constant.

[0251] Embodiment 26. A switching converter comprising: a power transistor; a sense resistor coupled to a current path of the power transistor; an inductor coupled to the current path of the power transistor; a driver having an output coupled to a control terminal of the power transistor; a trigger having a first output coupled to an input of the driver, and a first input configured to receive a clock signal, wherein the trigger is configured to generate a first signal at the first output of the trigger, and wherein the trigger is configured to turn on the power transistor using the first signal based on the clock signal; a first comparator having an output coupled to a second input of the trigger, wherein the trigger is configured to turn off the power transistor using the first signal based on the output of the first comparator; a transconductance amplifier having a first input and a second input coupled to the first terminal and the second terminal of the sense resistor, respectively, and an output coupled to the first input of the first comparator; an integrating circuit a capacitor coupled to the output of the transconductance amplifier and the first input of the first comparator; a first switch coupled to the integrating capacitor, the first switch being configured to discharge the integrating capacitor when the power transistor is turned off; a zero-crossing detection circuit having a current path coupled to the power transistor and an input of the inductor, wherein the zero-crossing detection circuit is configured to generate a freewheeling signal based on demagnetization of the inductor; a first current generator configured to generate a first current, the first current generator being coupled to the first capacitor at a first node; a first resistor coupled between the first node and a reference power supply terminal; a second switch coupled in series with the first resistor and configured to be controlled based on the freewheeling signal; a second current generator configured to generate a second current based on a voltage at the first node; a third switch coupled between the second current generator and the second input of the transconductance amplifier; and a fourth switch coupled between the third switch and the reference power supply terminal.

[0252] Example 27. The switching converter according to Example 26 further includes: a one-shot circuit having an input configured to receive the first signal and an output configured to control the third switch; and a delay circuit configured to control the fourth switch based on the output of the one-shot circuit.

[0253] Example 28. A switching converter according to any one of Examples 26 and 27, further comprising: an input terminal configured to receive an input voltage, the input terminal configured to be coupled to a first terminal of a load; and a diode coupled between the first terminal of the inductor and the input terminal, wherein the second terminal of the inductor is configured to be coupled to a second terminal of the load.

[0254] Embodiment 29. The switching converter of any one of Embodiments 26 to 28, further comprising a load, wherein the load comprises a string of light emitting diodes (LEDs).

[0255] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art in light of the description. Accordingly, the appended claims include any such modifications or embodiments.

Claims

1. A control circuit comprising: an output terminal configured to be coupled to a control terminal of a first transistor having a current path coupled to an inductor; a transconductance amplifier configured to generate a sense current based on a current flowing through the current path of the first transistor; as well as a first capacitor, wherein the control circuit is configured to: turning on the first transistor based on a clock signal, integrating the sense current with an integrating capacitor to generate a first voltage, generating a first current, generating a second voltage on the first capacitor based on the first current, generating a second current based on the second voltage, generating a third voltage based on the second current, When the first voltage becomes higher than the third voltage, turning off the first transistor; discharging the integrating capacitor when the first transistor is turned off; as well as An average output current flowing through the inductor is adjusted based on the first current.

2. The control circuit according to claim 1, wherein the transconductance amplifier comprises: a first input configured to receive a sense voltage indicative of a current flowing through the current path of the first transistor; a second input configured to receive a reference voltage; and an output configured to deliver the sense current.

3. The control circuit according to claim 1 , further comprising: a first current generator configured to generate the first current, the first current generator being coupled to the first capacitor at a first node; as well as A first resistor is coupled between the first node and a reference power supply terminal. 4 . The control circuit of claim 3 , further comprising a first switch coupled in series with the first resistor, wherein the control circuit is configured to control the first switch based on a freewheeling signal indicating demagnetization of the inductor.

5. The control circuit according to claim 4, wherein the control circuit is configured to: controlling the first transistor using a first signal; and The first switch is controlled based on the freewheeling signal and based on the first signal.

6. The control circuit of claim 4 , further comprising a zero-crossing detection circuit having an input configured to be coupled to the first current path terminal of the first transistor, wherein the zero-crossing detection circuit is configured to generate the freewheeling signal based on the input of the zero-crossing detection circuit.

7. The control circuit according to claim 4, wherein the control circuit is configured to generate the third voltage at the second node, the control circuit further comprising: a second current generator configured to generate the second current; a second switch coupled between the second current generator and the second node; as well as A third switch is coupled between the second node and the reference power terminal.

8. The control circuit according to claim 7, further comprising: a one-shot circuit having an output configured to control the second switch; as well as A delay circuit is configured to control the third switch based on the output of the one-shot circuit.

9. The control circuit according to claim 7, further comprising: a fourth switch coupled between the second current generator and a third node, wherein the third node is coupled between the second switch and the third switch; a second capacitor coupled between the third node and the reference power supply terminal; as well as A third capacitor is coupled between the second node and the reference power terminal, wherein the control circuit is configured to generate the third voltage on the third capacitor.

10. The control circuit of claim 1 , wherein the control circuit is configured to generate the third voltage at the second node, the control circuit further comprising: a first current generator configured to generate the second current, the first current generator being coupled to the second node; a first resistor coupled between the second node and a reference power supply terminal; as well as A first switch is coupled in series with the first resistor, wherein the control circuit is configured to control the first switch based on a freewheeling signal indicating demagnetization of the inductor.

11. The control circuit according to claim 1 , further comprising: a first comparator having a first input configured to receive the first voltage and a second input configured to receive the third voltage; as well as A first flip-flop has a first output coupled to the output terminal, a first input configured to receive the clock signal, and a second input coupled to the output of the first comparator.

12. The control circuit of claim 1 , further comprising a current mirror configured to be coupled to the first current path terminal of the first transistor via an interface circuit, wherein the current mirror is configured to inject a first current into the first input of the transconductance amplifier based on a current flowing through the interface circuit. 13 . The control circuit of claim 1 , further comprising a sense resistor coupled between the first input and the second input of the transconductance amplifier. 14 . The control circuit of claim 1 , further comprising a clock circuit configured to generate the clock signal. 15 . The control circuit of claim 14 , wherein the clock circuit is configured to generate a clock signal having a fixed frequency.

16. The control circuit of claim 1 , further comprising a gate driver having an input coupled to the output terminal, and wherein the first transistor is a power metal oxide semiconductor field effect transistor (MOSFET) or a GaN transistor having a gate coupled to an output of the gate driver.

17. A method for regulating an average output current flowing through an inductor, the method comprising: turning on a power transistor based on a clock signal, wherein a current path of the power transistor is coupled to the inductor; generating a sense current based on a current flowing through the current path of the power transistor; integrating the sense current with an integrating capacitor to generate a first voltage; generating a first current; generating a second voltage on a first capacitor based on the first current; generating a second current based on the second voltage; generating a third voltage on a second capacitor based on the second current; When the first voltage becomes higher than the third voltage, turning off the power transistor; discharging the integrating capacitor when the power transistor is turned off; as well as The average output current is adjusted based on the first current.

18. The method according to claim 17, further comprising: A sense voltage is generated based on the current flowing through the current path of the power transistor, wherein generating the sense current includes generating the sense current based on the sense voltage using a transconductance amplifier.

19. The method according to claim 17, further comprising: generating the first current using a first current generator; detecting a demagnetization time of the inductor; as well as A first switch is controlled based on the detected demagnetization time, the first switch being coupled to the first current generator via a first resistor.

20. The method of claim 17, wherein the average output current is proportional to the first current.

21. The method of claim 17, further comprising varying a switching frequency of the power transistor without causing a substantial change in the magnitude of the average output current.

22. The method of claim 17, wherein the second voltage is substantially constant.

23. A switching converter comprising: Power transistors; a sense resistor coupled to a current path of the power transistor; an inductor coupled to the current path of the power transistor; a driver having an output coupled to a control terminal of the power transistor; a flip-flop having a first output coupled to an input of the driver and a first input configured to receive a clock signal, wherein the flip-flop is configured to generate a first signal at the first output of the flip-flop, and wherein the flip-flop is configured to turn on the power transistor using the first signal based on the clock signal; a first comparator having an output coupled to a second input of the flip-flop, wherein the flip-flop is configured to cause the power transistor to turn off using the first signal based on the output of the first comparator; a transconductance amplifier having first and second inputs coupled to the first and second terminals of the sense resistor, respectively, and an output coupled to the first input of the first comparator; an integrating capacitor coupled to the output of the transconductance amplifier and the first input of the first comparator; a first switch coupled to the integration capacitor, the first switch configured to discharge the integration capacitor when the power transistor is turned off; a zero-crossing detection circuit having an input coupled to the current path of the power transistor and the inductor, wherein the zero-crossing detection circuit is configured to generate a freewheeling signal based on demagnetization of the inductor; a first current generator configured to generate a first current, the first current generator being coupled to a first capacitor at a first node; a first resistor coupled between the first node and a reference power supply terminal; a second switch coupled in series with the first resistor and configured to be controlled based on the freewheeling signal; a second current generator configured to generate a second current based on the voltage at the first node; a third switch coupled between the second current generator and the second input of the transconductance amplifier; as well as A fourth switch is coupled between the third switch and the reference power terminal.

24. The switching converter of claim 23, further comprising: a one-shot circuit having an input configured to receive the first signal and an output configured to control the third switch; as well as A delay circuit is configured to control the fourth switch based on the output of the one-shot circuit.

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