A dual-mode voltage regulated MRAM memory cell based on ferroelectric / ferromagnetic material coupling and a regulating method and a preparation method thereof

Abstract

The application relates to a dual-mode voltage regulation MRAM storage unit based on ferroelectric / ferromagnetic material coupling and a regulation method thereof. A voltage regulation unit applies a pressure voltage between a free layer and a bottom electrode in a tunnel junction. The ferroelectric layer is regulated by applying the voltage, so that the ferroelectric layer can be switched between a non-breakdown state and a breakdown state. When the ferroelectric layer is in the non-breakdown state, the reversible change of the magnetic anisotropy of the free layer is affected. When the ferroelectric layer is in the breakdown state, the permanent magnetic moment of the free layer is increased, so that the non-volatile change of the magnetic anisotropy of the free layer is affected.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a dual-mode voltage-controlled MRAM memory cell based on ferroelectric / ferromagnetic material coupling, as well as its control and fabrication methods. Background Technology

[0002] Magnetic random access memory (MARM) stores data by changing the magnetization direction of the free magnetic layer relative to the pinned layer, forming different magnetoresistive states corresponding to parallel and antiparallel states. MARM has advantages such as high-speed read and write, high integration density, low power consumption, and near-infinite erase and write cycles, and is therefore considered one of the candidates for next-generation memory devices.

[0003] The magnetic tunnel junction (MTJ) is the core of an MRAM memory cell. The magnetic moment direction of the upper layer is pinned to a fixed direction by a pinning layer, called the pinned layer. The material chosen for this pinning layer is one that has a strong exchange bias with the pinning layer; CoFeB is a suitable material. The magnetic moment direction of the lower layer can freely flip under external excitation; this is called the free layer. It is generally made of soft ferromagnetic materials with relatively low coercivity, such as CoFeB, with a thickness of 1nm to 1.5nm to ensure perpendicular magnetic anisotropy. An isolation layer, a non-magnetic thin film typically made of MgO, is also included between the pinned and free layers. When the magnetic moment directions of the pinned and free layers are parallel, the MMT exhibits its lowest resistance; conversely, when they are parallel to each other, it exhibits its highest resistance. When the magnetic moments of the pinned and free layers are in other states, the resistance of the MMT falls between the lowest and highest resistance. As Moore's Law continues to advance, the feature size of integrated circuits is constantly shrinking. For MRAM memory, the size of its core memory cell has shrunk from 100nm to 30nm, and in the research community, it has even been reduced to below 10nm. However, maintaining the stability of data storage in such a small size has always been a research hotspot in both industry and academia.

[0004] Currently, several solutions have been proposed internationally. For example, the memory cells can be made cylindrical to maintain their magnetism using in-plane magnetic anisotropy; or more insulating / magnetic layer interfaces can be added to the memory cell structure to maintain their magnetism through interfacial magnetic anisotropy; or the magnetism of the memory cell can be dynamically controlled by applying voltage to the memory cell to regulate the interfacial magnetic anisotropy of CoFeB / MgO. While these methods have played a role, they have increased the complexity of the integration process and affected other electrical characteristics of the memory cell. Furthermore, the traditional voltage regulation effect is volatile, requiring a continuous voltage supply to maintain the magnetism of the memory cell. All of these methods are detrimental to the continuous miniaturization of MRAM. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a dual-mode non-volatile voltage-controlled MRAM memory cell based on ferroelectric / ferromagnetic material coupling, along with its control and fabrication methods.

[0006] The present invention adopts the following technical solution: a dual-mode voltage-controlled MRAM memory cell based on ferroelectric / ferromagnetic material coupling, comprising, from bottom to top: a substrate, a bottom electrode layer, a ferroelectric layer, a magnetic tunnel junction, and a pinning layer; and further comprising a voltage control unit; wherein, the pinning layer is an antiferromagnetic structure layer with magnetic anisotropy in the vertical plane;

[0007] A magnetic tunnel junction, from bottom to top, consists of: a free layer, an isolation layer, and a pinned layer. The pinned layer pins the magnetic moment of the pinned layer in a fixed direction.

[0008] The ferroelectric layer, through voltage modulation, applies an electric field that influences the direction of the magnetic moment of the free layer;

[0009] The voltage regulation unit applies a voltage between the free layer and the bottom electrode layer in the tunnel junction. By applying the voltage, the ferroelectric layer is regulated, allowing it to switch between a non-breakdown state and a breakdown state. When the ferroelectric layer is in the non-breakdown state, the magnetic anisotropy of the free layer undergoes a reversible change. When the ferroelectric layer is in the breakdown state, the permanent magnetic moment of the free layer increases, causing a non-volatile change in the magnetic anisotropy of the free layer.

[0010] A method for regulating a MARM memory cell as described above involves a voltage regulation unit applying a voltage between the free layer and the bottom electrode layer in the tunnel junction. When a non-breakdown voltage is applied, the magnetic anisotropy of the ferroelectric layer affects the free layer and undergoes a reversible change. When a breakdown voltage is applied, the permanent magnetic moment of the free layer increases, causing a non-volatile change in the magnetic anisotropy of the free layer.

[0011] A method for fabricating a memory cell as described above, characterized by comprising the following steps:

[0012] A bottom electrode layer and a ferroelectric layer are sequentially grown on the substrate;

[0013] A magnetic tunnel junction and a top electrode layer are grown sequentially on the ferroelectric layer; the magnetic tunnel junction includes, from bottom to top, a free layer, an isolation layer and a pinned layer, and the pinned layer pins the magnetic moment of the pinned layer in a fixed direction.

[0014] The magnetic tunnel junction is etched in a cylindrical shape from top to bottom until the free layer is exposed. Electrodes are set on the free layer and the bottom electrode layer to apply voltage V1, and electrodes are set on the free layer and the top electrode layer to apply voltage V2.

[0015] This application modulates the ferroelectric layer by applying voltage, enabling the ferroelectric layer to switch between a non-breakdown state and a breakdown state. When the ferroelectric layer is in the non-breakdown state, the magnetic anisotropy of the free layer undergoes a reversible change. When the ferroelectric layer is in the breakdown state, the permanent magnetic moment of the free layer increases, causing a non-volatile change in the magnetic anisotropy of the free layer. Attached Figure Description

[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0017] Figure 1 In the middle (a)-(c), the substrate preparation, magnetron sputtering of TiN, and ALD deposition of HfZrO are respectively.

[0018] Figure 2 In the middle (d)-(f), MTJ was grown by magnetron sputtering, annealed, and TiN hard mask was deposited by PVD, respectively;

[0019] Figure 3 In the middle (g)-(i), DUV exposure, etching of TiN hard mask, and MTJ first etching are respectively;

[0020] Figure 4 (j)-(l) represent PECVD growth of SiN, second DUV exposure and etching, and third exposure and etching, respectively;

[0021] Figure 5 The holes are formed by PECVD growth of TEOS, CMP, and DUV exposure, respectively.

[0022] Figure 6 In the middle (p)-(q), respectively, the MARM device is controlled by dual modes of PIE etching to form electrode holes, metal filling and patterning. Detailed Implementation

[0023] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0024] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0025] In the context of this invention, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0026] This embodiment provides a method for fabricating high-performance MRAM memory cells based on ferroelectric / ferromagnetic material coupling. Combined with... Figure 1-6 The specific fabrication process for the MRAM memory cell is as follows:

[0027] First, see Figure 1 (a) The natural oxide layer on the silicon wafer surface is removed using a standard cleaning process with buffered oxide etchant (BOE).

[0028] Figure 1 (b) A bottom electrode layer 102 is first grown on the substrate 101 using a magnetron sputtering process. In this embodiment, the bottom electrode layer 102 may be made of TiN and has a thickness of 10 nm.

[0029] Figure 1 (c) Using deionized water, Hf(NCH3C2H5)4 and Zr(NCH3CH5)4 as precursors, a metal oxide Hf with ferroelectric polarization characteristics is grown on the bottom electrode layer 102 by atomic layer deposition (ALD). 0.5 Zr 0.5 O2 (HfZrO) has standard ferroelectric properties and is a ferroelectric layer 103 with a thickness of 10 nm. In this embodiment, the metal oxide 103 with ferroelectric polarization properties is HfZrO.

[0030] See Figure 2 (d) A transition layer 104 is deposited on the ferroelectric layer 103 by magnetron sputtering. In this embodiment, tungsten W is used, with a thickness of 0-0.6 nm. Its main function is to serve as a transition layer between the ferroelectric layer 103 and the free layer in the magnetic tunnel junction, so that the free layer exhibits perpendicular magnetic anisotropy.

[0031] Next, in transition layer 104, the core-magnetic tunnel junction of the MRAM memory cell is deposited using magnetron sputtering, followed by the deposition of free layer 105-1. In one embodiment, free layer 105-1 is made of Co. 20 Fe 60 B 20 (CoFeB), with a thickness of 1 nm, can freely flip under external excitation; then, an isolation layer 105-2 is deposited, in one embodiment the isolation layer 105-2 is made of MgO, with a thickness ranging from 2 nm; finally, a pinned layer 105-3 is deposited, in one embodiment the pinned layer 105-3 is made of Co. 20 Fe 60 B 20 A (CoFeB) layer with a thickness of 1 nm is formed, and its magnetic moment direction is pinned to a fixed direction by an artificial antiferromagnetic structure. Then, a pinning layer 106 is grown above the pinned layer 105-3 by magnetron sputtering. In this embodiment, an artificial antiferromagnetic structure layer is used as the pinning layer 106. The artificial antiferromagnetic structure layer 106 has a structure consisting of (Co / Pt)n layer 106-1, Ru layer 106-2, and (Co / Pt)m layer 106-3 from bottom to top, where the Co layer is 0.3 nm thick, the Pt layer is 0.8 nm thick, and the Ru layer 106-2 is 0.5 nm thick, where n=3 and m=4.

[0032] like Figure 2 As shown in (e), the prepared thin film sample was placed in an N2 environment of 700 Torr and subjected to rapid annealing at 400 °C for 30 s to induce the formation of ferroelectric phase in HfZrO in ferroelectric layer 103 and the formation of perpendicular magnetic anisotropy in free layer 105-1.

[0033] The (Co / Pt)n / Ru / (Co / Pt)m 106 forms an artificial antiferromagnetic structure with perpendicular magnetic anisotropy. Its function is to pin the magnetic moment of CoFeB, which is the pinned layer 105-3, in a fixed direction through interface coupling. The tunnel junction composed of CoFeB / MgO / CoFeB, which is the free layer 105-1 / isolation layer 105-2 / pinned layer 105-3, is the core of the memory cell. When the magnetic moments of the two CoFeB layers are parallel, the tunnel junction exhibits a low resistance state; otherwise, it exhibits a high resistance state.

[0034] See Figure 2 (f) After annealing, the thin film sample is grown with a top electrode layer 107 with a thickness of 100 nm by PVD. In this embodiment, the top electrode layer 107 is a TiN layer.

[0035] Figure 3(g) To combine with DUV lithography, a cylinder 108 with a diameter of 180 nm is formed by exposure on the top electrode layer 107. Then, an ICP etching system is used for etching. First, the top electrode layer 107 is etched to transfer the photoresist pattern 108 onto the top electrode layer 107. Cl2 gas is generally used as the main etching gas. See [link to relevant documentation]. Figure 3 (h). Subsequently, using the top electrode layer 107 as a hard mask, Ar gas was used to etch the (Co / Pt)m layer 106-3, Ru layer 106-2, (Co / Pt)n layer 106-1, pinned layer 105-3, and isolation layer 105-2. By observing the OES signal in real time, the etching stopped at the surface of the free layer 105-1 or the transition layer 104. In this example, the etching stopped at the free layer 105-1, as shown below. Figure 3 As shown in (i).

[0036] Figure 4 (j) A SiN layer 109 with a thickness of 30 nm was grown on the surface of the thin film sample using PECVD. The SiN layer 109 covered the surface of the etched exposed free layer 115-1, the etched (Co / Pt)m layer 106-3, Ru layer 106-2, (Co / Pt)n layer 106-1, the pinned layer 105-3, the surface of the isolation layer 105-2, and the top surface of the etched (Co / Pt)m layer 106-3. The wafer was cleaned using ANJI.

[0037] Using DUV lithography, a 300nm diameter cylinder was used as a mask to overlay the etched structure. An ICP etching system was employed, with Ar as the primary etching gas, to etch SiN109, the free layer 105-1, the transition layer 104, and both sides of the ferroelectric layer 103, forming a structure as shown below. Figure 4 The platform structure shown in (k) is then used again with DUV lithography and etching processes. A cylinder with a diameter of 500 nm is used as a mask to overlay the etched structure, and the two sides of the bottom electrode layer 102 are etched to form the structure shown in (k). Figure 4 The platform structure shown in (l).

[0038] Then, a TEOS layer 110 was deposited on the thin film sample using PECVD with tetraethyl orthosilicate (TEOS) as the source. The TEOS layer 110 encapsulates the thin film sample and has a thickness of 300 nm, providing better step coverage for the thin film sample and isolating the subsequent metal electrode wiring from each other. Therefore, it provides an insulating protective layer. (See [link to relevant documentation]). Figure 5 (m).

[0039] Next, as Figure 5As shown in (n), the TEOS layer 110 and SiN layer 109 on the top of the device are chemically and mechanically polished by CMP process, so that the TEOS layer 110 and SiN layer 109 are flush with the upper surface of the (Co / Pt)m layer 106-3.

[0040] A photoresist layer 111 is applied to the upper surface of the device, and three through-holes 112 are formed on the photoresist layer 111 using a DUV exposure process. See [link to documentation]. Figure 5 (o). Using RIE etching technology, firstly... Figure 5 (o) The photoresist mask is used to etch the TEOS layer 110, forming three vias that reach the upper surface of the bottom electrode layer 102 and the upper surfaces of both sides of the free layer 105, respectively. Then, the photoresist layer 111 is etched to expose the top electrode 107. (See [reference]). Figure 6 (p).

[0041] Then, through a deposition process, the three vias are filled with metal to form three electrodes 113-1, 113-2, and 113-4 connecting the bottom electrode layer 102 and the free layer 105, respectively. Electrode 113-3 is formed on the upper surface of the (Co / Pt)m layer 116-3, ultimately forming the following... Figure 6 (q) is a dual-mode voltage-controlled MRAM memory cell based on ferroelectric / ferromagnetic material coupling.

[0042] like Figure 6 As shown in (q). A voltage V1 is applied between electrodes 113-1 and 113-2, that is, a voltage V1 is applied between the bottom electrode layer 102 and the free layer 105-1. A voltage V2 is applied between electrodes 113-3 and 113-4, that is, a voltage V2 is applied between the (Co / Pt)m layer 106-3 and the free layer 105-1.

[0043] Voltage V1 regulates the properties of ferroelectric materials, altering the characteristics of MRAM memory cells. Depending on the set voltage amplitude, dual-mode regulation—both ordinary and permanent voltage regulation—can be achieved; while voltage V2 is used to test the characteristics of the MTJ.

[0044] In the ordinary voltage regulation mode: a voltage is applied to the HfZrO layer of the ferroelectric layer 103 through the TiN layer of the bottom electrode 102 and the CoFeB layer of the free layer 105-1. The voltage range is generally controlled between -3V and 3V, which is less than the breakdown voltage of the HfZrO layer of the ferroelectric layer 103. Under this voltage, the ferroelectric polarization of the HfZrO layer of the ferroelectric layer 103 can undergo a non-volatile reversal, i.e., it exhibits ferroelectricity. The ferroelectric polarization and the magnetization of the free layer interact through the magnetoelectric coupling effect, causing a reversible change in the magnetic anisotropy of the free layer. The principle is as follows: when the polarization intensity direction is downward, electrons accumulate at the interface between the ferroelectric layer 103HfZrO layer and the free layer 105-1 CoFeB layer, which leads to a decrease in the interfacial magnetic anisotropy coefficient of the free layer 105-1 CoFeB layer, thereby reducing the magnetic anisotropy; conversely, the magnetic anisotropy increases. This modulation method has no effect on other physical characteristics of the free layer 105-1 CoFeB layer.

[0045] Under this effect, the overall behavior of the memory cell is as follows: when a positive voltage is applied, the coercivity of the memory cell decreases, meaning the dynamic switching current decreases and data retention stability decreases; conversely, the dynamic switching current increases and data retention stability increases. Therefore, this is a regulation method where intrinsic parameters are mutually constrained, and different voltages can be configured according to different application requirements.

[0046] Breakdown voltage mode: A voltage is applied to the ferroelectric layer 103 through the TiN layer of the bottom electrode layer 102 and the CoFeB layer of the free layer 105-1. The applied voltage exceeds the breakdown voltage of the HfZrO layer of the ferroelectric layer 103. In this breakdown mode, regardless of the direction of the applied voltage, when the HfZrO layer of the ferroelectric layer 103 is broken down, the potential barrier of the oxygen vacancies inside it is lowered under the action of the electric field, and the vacancy ions escape from the bound state. At this time, the oxygen ion concentration in the free layer 105-1 is different from that in the ferroelectric layer 103. Under the action of the chemical potential, the oxygen ions migrate into the free layer 105-1 and react with the boron ions (B) in the CoFeB layer of the free layer 105-1 to generate stable BOx, thereby releasing more CoFe in the "magnetically dead layer". This makes the saturation magnetic moment of the CoFeB layer of the free layer 105-1 permanently increase, with a relative change of up to 60%. Under this effect, the increase in the saturation magnetic moment of the CoFeB layer in the free layer 105-1 leads to an increase in its magnetic anisotropy, spin polarization, and tunneling magnetoresistance ratio. This will improve the data retention stability of the memory cell while keeping the dynamic flip-flop current variation small and increasing the read window of the memory cell.

[0047] Compared to ordinary voltage regulation mechanisms, the breakdown voltage mode can improve the stability of data storage in memory cells without affecting other electrical characteristics, and may even improve some of them. It will be one of the potential solutions to overcome the performance degradation caused by the miniaturization of MRAM memory cells in the future.

[0048] Figure 2 The MARM memory cell of the present invention is shown in the figure. The top of the device is a pinning layer 106. The pinning layer 106 adopts an artificial antiferromagnetic structure with vertical magnetic anisotropy. In one embodiment, the pinning layer is composed of a (Co / Pt)n / Ru / (Co / Pt)m structure from bottom to top. Its function is to pin the magnetic moment of the pinned layer 105-3 in the magnetic tunnel junction in a fixed direction through the interface coupling effect. The pinning layer is usually selected as a material structure with a strong exchange bias effect with the pinned layer.

[0049] The core of the device is the magnetic tunnel junction (MTJ) of the MARM memory cell. In this embodiment, a MTJ composed of CoFeB / MgO / CoFeB is used. When the magnetic moments of the two CoFeB layers are parallel, the tunnel junction exhibits a low resistance state; conversely, it exhibits a high resistance state. When the magnetic moments of the two CoFeB layers are in other states, the resistance of the MTJ is between the lowest and highest resistance. The thickness of CoFeB is set to 1nm~1.5nm to ensure that it exhibits perpendicular magnetic anisotropy. The magnetic moment direction of the upper CoFeB layer is pinned to a fixed direction by an artificial antiferromagnetic structure, which is called the pinned layer 105-3. It can also have a self-pinning structure and can be formed by a material or structure with high coercivity. The magnetic moment direction of the lower CoFeB layer can be freely flipped under external excitation, which is called the free layer 105-3. The spacer layer 105-2 can include a non-magnetically conductive material or a non-magnetically insulating material. When the spacer layer 105-2 is formed of a non-magnetically conductive material, its thickness is preferably not greater than the mean free path of the spin electrons of that material. When the spacer layer 105-2 is formed of a non-magnetic insulating material, it is also often referred to as a barrier layer. Electrons can pass through this barrier layer through the tunneling effect, thereby flowing between the pinned layer 105-3 and the free layer 105-1.

[0050] The lower part of the device is a ferroelectric layer 103, which can be formed of insulating or semiconductor ferroelectric materials. In this embodiment, HfZrO is used to form the ferroelectric layer. HfZrO has standard ferroelectric properties, and the direction of its electric dipole moment changes due to the external electric field, affecting the perpendicular magnetic moment direction of CoFeB in the magnetic tunnel junction. Between the ferroelectric layer 103 and the free layer 105-1, there is a transition layer 104, W, with a thickness of less than 1 nm. Its main function is to serve as a transition layer between the ferroelectric layer 103 and the free layer 105-1, thereby making the free layer 105-1 exhibit perpendicular magnetic anisotropy.

[0051] Below the ferroelectric layer 103 is the bottom electrode 102 of the memory cell. In this embodiment, TiN is used as the bottom electrode of the MRAM. An electrode is led out between CoFeB and TiN for voltage regulation of the ferroelectric material properties, thereby changing the characteristics of the MRAM memory cell. Depending on the set voltage amplitude, dual-mode regulation, including ordinary voltage regulation and permanent voltage regulation, can be achieved.

[0052] Because ferroelectric materials have polarization retention properties, different voltages are applied to the bottom electrodes 102 and 36 on the ferroelectric layer 103 to regulate the polarization of the ferroelectric layer 103.

[0053] In the ordinary voltage regulation mode: a voltage is applied to the HfZrO layer of the ferroelectric layer 103 through the TiN layer of the bottom electrode 102 and the CoFeB layer of the free layer 105-1. The voltage range is generally controlled between -3V and 3V, which is less than the breakdown voltage of HfZrO. Under this voltage, the ferroelectric polarization of HfZrO can undergo a non-volatile reversal, i.e., it exhibits ferroelectricity. The ferroelectric polarization and the magnetization of the free layer interact through magnetoelectric coupling, causing a reversible change in the magnetic anisotropy of the free layer. The principle is as follows: when the polarization direction is downward, electrons accumulate at the interface between the ferroelectric layer 103 and the free layer 105-1, resulting in a decrease in the interfacial magnetic anisotropy coefficient of the free layer 105-1, thereby reducing the magnetic anisotropy; conversely, the magnetic anisotropy increases. This regulation method has no effect on other physical characteristics of the free layer 105-1.

[0054] Under this effect, the memory cell as a whole exhibits the following behavior: when a positive voltage is applied, the coercivity of the memory cell decreases, meaning the dynamic switching current decreases and data retention stability decreases; conversely, when a negative voltage is applied, the dynamic switching current increases and data retention stability increases. Therefore, this is a control method where intrinsic parameters are mutually constrained, and different voltages can be configured according to different application requirements.

[0055] Breakdown voltage mode: A voltage exceeding the breakdown voltage of the HfZrO layer in the ferroelectric layer 103 is applied through the TiN layer of the bottom electrode 102 and the CoFeB layer of the free layer 105-. In this breakdown mode, regardless of the direction of the applied voltage, when the HfZrO layer breaks down, the oxygen vacancies inside it experience a lower potential barrier under the influence of the electric field, allowing vacancy ions to escape from their bound state. At this point, the oxygen ion concentrations in the free layer 105-1CoFeB and the HfZrO layer differ. Under the influence of the chemical potential, oxygen ions migrate into CoFeB and react with boron ions (B) to generate stable BOx, thus releasing more CoFe in the "magnetically dead layer." This permanently increases the saturation magnetic moment of the free layer, with a relative change of up to 60%. Under this effect, the increase in the saturation magnetic moment of the free layer leads to an increase in its magnetic anisotropy, spin polarization, and tunneling magnetoresistance ratio. This will improve the stability of data retention in the storage unit while keeping the dynamic flip-flop current variation small and increasing the read window of the storage unit.

[0056] Compared to ordinary voltage regulation mechanisms, the breakdown voltage mode, with its increased free-layer saturation magnetic moment, leads to increased magnetic anisotropy, spin polarization, and tunneling magnetoresistance. This can improve the stability of data storage in memory cells without affecting other electrical characteristics, and may even improve some of them. It is one of the potential solutions to overcome the performance degradation caused by the miniaturization of MRAM memory cells in the future.

[0057] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0058] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A dual-mode voltage-regulated MRAM memory cell based on ferroelectric / ferromagnetic material coupling, comprising, from bottom to top: a substrate, a bottom electrode layer, a ferroelectric layer, a magnetic tunnel junction, and a pinning layer; and a voltage-regulating unit; wherein the pinning layer is an anti-ferromagnetic structure layer with in-plane magnetic anisotropy; the magnetic tunnel junction is CoFeB / MgO / CoFeB, comprising, from bottom to top: a free layer, a spacer layer, and a pinned layer, wherein the pinned layer pins the magnetic moment of the pinned layer in a fixed direction; the ferroelectric layer is HfZrO, and the ferroelectric layer exerts an electric field on the free layer by voltage regulation to affect the magnetic moment direction of the free layer; the voltage-regulating unit applies a voltage between the free layer and the bottom electrode layer in the tunnel junction, and regulates the ferroelectric layer by applying a voltage, so that the ferroelectric layer can switch between an unbroken state and a broken state; when the ferroelectric layer is in the unbroken state, the magnetic anisotropy of the free layer is reversibly changed; when the ferroelectric layer is in the broken state, the permanent magnetic moment of the free layer is increased, so that the magnetic anisotropy of the free layer is non-volatilely changed. A transition layer is arranged between the ferroelectric layer and the free layer, and has a thickness of 0.5 nm. The anti-ferromagnetic structure layer is (Co / Pt)n / Ru / (Co / Pt)m. The bottom electrode layer is made of TiN. The voltage-regulating unit applies a voltage between the free layer and the bottom electrode layer in the tunnel junction, and when a non-breaking voltage is applied, the magnetic anisotropy of the free layer is reversibly changed; and when a breaking voltage is applied, the permanent magnetic moment of the free layer is increased, so that the magnetic anisotropy of the free layer is non-volatilely changed. The method comprises the following steps: growing the bottom electrode layer and the ferroelectric layer on the substrate; 2. The dual-mode voltage-regulated MRAM memory cell of claim 1, wherein: growing the magnetic tunnel junction and a top electrode layer on the ferroelectric layer, wherein the magnetic tunnel junction comprises, from bottom to top: the free layer, the spacer layer, and the pinned layer, and the pinned layer pins the magnetic moment of the pinned layer in a fixed direction; 3. The dual-mode voltage-regulated MRAM memory cell of claim 1, wherein: etching the magnetic tunnel junction in a cylindrical shape from top to bottom until the upper surface of the free layer is exposed 4. The dual-mode voltage-regulated MRAM memory cell of claim 1, wherein: applying a voltage V1 between the free layer and the bottom electrode layer, and applying a voltage V2 between the free layer and the top electrode layer.

5. The method of claim 1-4, wherein the method is a method of voltage regulation of a dual-mode voltage regulated MRAM memory cell, wherein the method comprises: ​ 6. A method of fabricating a dual-mode voltage-regulated MRAM memory cell as claimed in any one of claims 1-4, characterized by: ​ ​ ​ ​ ​

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