Row drive signal enhancement circuit, shift register unit and display panel

Abstract

Disclosed are a row drive signal enhancement circuit, a shift register unit and a display panel, belonging to the field of display technology. The row drive signal enhancement circuit comprises a first control unit (110), a second control unit (120), a first output unit (130) and a second output unit (140). The first control unit (110) is used to output a first power supply voltage (V1) to a first node (A) or a second node (B) under the control of a first control terminal (IN1) and a second control terminal (IN2); the second control unit (120) is used to respond to the first power supply voltage (V1) on the first node (A) and output a second power supply voltage (V2) to the second node (B), and is used to respond to the first power supply voltage (V1) on the second node (B) and output the second power supply voltage (V2) to the first node (A); the first output unit (110) is used to output one of the first power supply voltage (V1) and the second power supply voltage (V2) to the first output terminal (OUT1) under the control of the first node (A); the second output unit (120) is used to output the other of the first power supply voltage (V1) and the second power supply voltage (V2) to the second output terminal (OUT2) under the control of the second node (B). The row drive signal enhancement circuit can enhance the driving capability of the row drive signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a row drive signal enhancement circuit, a shift register unit and a display panel. Background Art

[0002] In a display panel, a scanning signal can be loaded to a pixel driving circuit through a gate lead; due to the load and impedance on the gate lead, there is often a certain delay and voltage loss when the scanning signal reaches the pixel driving circuit. In silicon-based OLED (organic light-emitting diode) displays, due to the large pixel resolution, the delay and voltage drop loss of the scanning signal on the gate lead are large, which will cause different data voltages written by different pixel driving circuits, thereby reducing the display uniformity of silicon-based OLED displays.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a row drive signal enhancement circuit, a shift register unit and a display panel.

[0005] According to one aspect of the present disclosure, a row drive signal enhancement circuit is provided, comprising:

[0006] A control unit having a first control terminal and a second control terminal, configured to input a first power supply voltage to one of the first node and the second node and input a second power supply voltage to the other node under the control of the first control terminal and the second control terminal;

[0007] a first output unit, connected to the first node and a first output terminal, and configured to output one of the first power supply voltage and the second power supply voltage to the first output terminal under the control of the first node;

[0008] A second output unit is connected to the second node and the second output terminal, and is used for outputting the other of the first power supply voltage and the second power supply voltage to the second output terminal under the control of the second node.

[0009] According to one embodiment of the present disclosure, the control unit includes:

[0010] A first control unit having the first control end and the second control end, and configured to output the first power supply voltage to the first node or the second node under the control of the first control end and the second control end;

[0011] A second control unit is connected to the first node and the second node, and is used to output the second power supply voltage to the second node in response to the first power supply voltage loaded on the first node, and is used to output the second power supply voltage to the first node in response to the first power supply voltage loaded on the second node.

[0012] According to an embodiment of the present disclosure, the second control unit has at least four transistors.

[0013] According to an embodiment of the present disclosure, the first control unit includes:

[0014] a first transistor having a first end for loading the first power supply voltage, a second end connected to the first node, and a control end serving as the first control end; the first transistor is used to output the first power supply voltage to the first node under the control of the control end of the first transistor;

[0015] a second transistor having a first end for loading the first power supply voltage, a second end connected to the second node, and a control end serving as the second control end; the second transistor is used to output the first power supply voltage to the second node under the control of the control end of the second transistor;

[0016] The first transistor and the second transistor are of the same type.

[0017] According to an embodiment of the present disclosure, the second control unit includes:

[0018] a third transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second node; the third transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node;

[0019] a fourth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second node; the fourth transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node;

[0020] a fifth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first node; the fifth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node;

[0021] a sixth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first node; the sixth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node;

[0022] The third to sixth transistors are of the same type.

[0023] According to an embodiment of the present disclosure, the first output unit includes:

[0024] A seventh transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal serving as the first output terminal;

[0025] An eighth transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal connected to the first output terminal;

[0026] a ninth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal;

[0027] a tenth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal;

[0028] The second output unit comprises:

[0029] an eleventh transistor having a control terminal connected to the second node, a first terminal for applying the second power supply voltage, and a second terminal serving as the second output terminal;

[0030] a twelfth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second output terminal;

[0031] a thirteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal;

[0032] a fourteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal;

[0033] Among them, any one of the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor is used to be turned on in response to one of the first power supply voltage and the second power supply voltage loaded on its control terminal, and any one of the ninth transistor to the twelfth transistor is used to be turned on in response to the other of the first power supply voltage and the second power supply voltage loaded on its control terminal.

[0034] According to another aspect of the present disclosure, there is provided a shift register unit, comprising a shift register, an inverter and the above-mentioned row drive signal enhancement circuit;

[0035] The shift register is used to output an initial scanning signal to the input end of the inverter and the first control end of the row drive signal enhancement circuit; the output end of the inverter is connected to the second control end of the row drive signal enhancement circuit.

[0036] According to another aspect of the present disclosure, a display panel is provided, comprising the above-mentioned shift register unit.

[0037] According to another aspect of the present disclosure, a display panel is provided, wherein the display panel comprises a driving backplane and a display layer stacked on the driving backplane; the driving backplane comprises a semiconductor substrate, a gate insulating layer, a gate layer, an insulating dielectric layer and a metal wiring layer stacked in sequence; the display panel comprises a display area and a peripheral area surrounding the display area, and a plurality of row drive signal enhancement areas are arranged in the peripheral area;

[0038] In any of the row drive signal enhancement areas, the drive backplane is provided with a row drive signal enhancement circuit including a first transistor to a fourteenth transistor; wherein the first transistor and the second transistor are of the same type; the seventh transistor, the eighth transistor, the thirteenth transistor and the fourteenth transistor are of the same type; the ninth transistor to the twelfth transistor are of the same type and are opposite to the type of the seventh transistor; the third transistor to the sixth transistor are of the same type; the semiconductor substrate is formed with active areas of each transistor, and the active area of ​​any transistor includes a channel area, a source and a drain on both sides of the channel area; the gate layer is formed with gates of each transistor, and the gate insulating layer isolates the gate and the channel area of ​​any transistor; the insulating dielectric layer covers the gate layer;

[0039] In one of the row drive signal enhancement areas, the metal wiring layer is provided with a connecting lead, a first power lead, a second power lead, a first control lead, a second control lead, a first output lead, and a second output lead; the connecting lead is electrically connected to the source, drain, and gate of each transistor through a conductive column located in the insulating dielectric layer; wherein the connecting lead electrically connects the gate of the first transistor to the first control lead, and electrically connects the gate of the second transistor to the second control lead, and electrically connects the source of the first transistor, the source of the second transistor, the source of the seventh transistor, the source of the eighth transistor, the source of the thirteenth transistor, and the source of the fourteenth transistor to the first power lead, and electrically connects the third transistor to the sixth transistor The source of the transistor and the source of the ninth to twelfth transistors are electrically connected to the second power lead, and the drains of the seventh to tenth transistors are electrically connected to the first output lead, and the drains of the eleventh to fourteenth transistors are electrically connected to the second output lead, and the drain of the first transistor, the drain of the fifth transistor, the drain of the sixth transistor, the gate of the third transistor, the gate of the fourth transistor, and the gates of the seventh to tenth transistors are electrically connected to each other, and the drain of the second transistor, the drain of the third transistor, the drain of the fourth transistor, the gate of the fifth transistor, the gate of the sixth transistor, and the gates of the eleventh to fourteenth transistors are electrically connected to each other.

[0040] According to an embodiment of the present disclosure, the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor are all N-type transistors, and the third to sixth transistors and the ninth to twelfth transistors are all P-type transistors.

[0041] According to an embodiment of the present disclosure, any one of the row drive signal enhancement regions includes a P-type substrate region and an N-type substrate region, the P-type substrate region is located on one side of a first direction of the N-type substrate region, and the first direction is a direction away from the display region; the N-type transistor is formed in the P-type substrate region, and the P-type transistor is formed in the N-type substrate region.

[0042] According to an embodiment of the present disclosure, the N-type substrate region includes an N-type auxiliary doping region, and includes a first active region and a second active region respectively surrounded by the N-type auxiliary doping region; the second active region is located on one side of the first direction of the first active region;

[0043] The first active area includes a first sub-active area and a second sub-active area sequentially arranged along the first direction; the ninth transistor and the eleventh transistor are located in the first sub-active area, and the tenth transistor and the twelfth transistor are located in the second sub-active area;

[0044] The second active region includes a third sub-active region and a fourth sub-active region arranged in sequence along a second direction; the second direction is perpendicular to the first direction and parallel to the plane where the semiconductor substrate is located; the fifth transistor and the sixth transistor are located in the third sub-active region, and the third transistor and the fourth transistor are located in the fourth sub-active region.

[0045] According to an embodiment of the present disclosure, the P-type substrate region includes a P-type auxiliary doping region, a third active region and a fourth active region; the fourth active region is located on one side of the third active region in the first direction;

[0046] The third active region is surrounded by the P-type auxiliary doping region and includes a fifth sub-active region and a sixth sub-active region sequentially arranged along the first direction; the seventh transistor and the thirteenth transistor are located in the fifth sub-active region, and the eighth transistor and the fourteenth transistor are located in the sixth sub-active region;

[0047] The fourth active region includes a seventh sub-active region and an eighth sub-active region which are arranged in sequence along the second direction and are respectively surrounded by the P-type auxiliary doping region; the first transistor is located in the seventh sub-active region, and the second transistor is located in the eighth sub-active region.

[0048] According to an embodiment of the present disclosure, the insulating dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially stacked on the gate layer, and the metal wiring layer includes a first metal wiring layer located between the first dielectric layer and the second dielectric layer, a second metal wiring layer located between the second dielectric layer and the third dielectric layer, and a third metal wiring layer located on a surface of the third dielectric layer away from the semiconductor substrate;

[0049] The conductive pillars include a first conductive pillar penetrating the first dielectric layer, a second conductive pillar penetrating the second dielectric layer, and a third conductive pillar penetrating the third dielectric layer; the first metal wiring layer is connected to the semiconductor substrate and the gate layer through the first conductive pillars; the second metal wiring layer is connected to the first metal wiring layer through the second conductive pillars; the third metal wiring layer is connected to the second metal wiring layer through the third conductive pillars;

[0050] Wherein, the first metal wiring layer includes some connecting leads; the connecting leads located in the first metal wiring layer include the first connecting lead to the sixth connecting lead, and also include the gate connecting lines, source connecting lines and drain connecting lines corresponding to the first transistor to the fourteenth transistor respectively; the gate connecting line corresponding to any transistor is connected to the gate of the transistor; the source connecting line corresponding to any transistor is connected to the source of the transistor; and the drain connecting line corresponding to any transistor is connected to the drain of the transistor;

[0051] The source connection line corresponding to the ninth transistor and the source connection line corresponding to the eleventh transistor are connected to the first connection lead;

[0052] The source connection line corresponding to the tenth transistor includes a first sub-connection line and a second sub-connection line; the source connection line corresponding to the twelfth transistor includes a first sub-connection line and a second sub-connection line; the first sub-connection line of the source connection line corresponding to the tenth transistor, the first sub-connection line of the source connection line corresponding to the twelfth transistor, the source connection line corresponding to the fifth transistor, and the source connection line corresponding to the fourth transistor are connected to the second connection lead;

[0053] The drain connection line corresponding to the third transistor, the drain connection line corresponding to the fourth transistor, the gate connection line corresponding to the fifth transistor, and the gate connection line corresponding to the sixth transistor are connected to the third connection lead;

[0054] The drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the gate connection line corresponding to the third transistor, and the gate connection line corresponding to the fourth transistor are connected to the fourth connection lead;

[0055] The source connection line corresponding to the eighth transistor includes a first sub-connection line and a second sub-connection line; the source connection line corresponding to the fourteenth transistor includes a first sub-connection line and a second sub-connection line; the first sub-connection line of the source connection line corresponding to the eighth transistor, the first sub-connection line of the source connection line corresponding to the fourteenth transistor, the source connection line corresponding to the seventh transistor, the source connection line corresponding to the thirteenth transistor, the source connection line corresponding to the first transistor, and the source connection line corresponding to the second transistor are connected to the fifth connection lead;

[0056] The source connection line corresponding to the third transistor and the source connection line corresponding to the sixth transistor are connected to the sixth connection lead;

[0057] The second metal wiring layer includes a first control lead, a second control lead, a first output lead, a second output lead and some connecting leads; the connecting leads located in the second metal wiring layer include the seventh connecting lead to the fifteenth connecting lead;

[0058] The first connecting lead and the second connecting lead are connected to the seventh connecting lead, and the first connecting lead and the second connecting lead are connected to the eighth connecting lead;

[0059] The fifth connecting lead is connected to the ninth connecting lead and the tenth connecting lead;

[0060] The gate connection line corresponding to the ninth transistor, the gate connection line corresponding to the tenth transistor, the drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the gate connection line corresponding to the seventh transistor, the gate connection line corresponding to the eighth transistor, and the drain connection line corresponding to the first transistor are connected to the eleventh connection lead;

[0061] The gate connection line corresponding to the eleventh transistor, the gate connection line corresponding to the twelfth transistor, the drain connection line corresponding to the third transistor, the drain connection line corresponding to the fourth transistor, the gate connection line corresponding to the thirteenth transistor, the gate connection line corresponding to the fourteenth transistor, and the drain connection line corresponding to the second transistor are connected to the twelfth connection lead;

[0062] The first connection lead, the source connection line corresponding to the ninth transistor, the source connection line corresponding to the eleventh transistor, the second sub-connection line of the source connection line corresponding to the tenth transistor, the second sub-connection line of the source connection line corresponding to the twelfth transistor, the sixth connection lead and the thirteenth connection lead are connected;

[0063] The source connection line corresponding to the seventh transistor, the second sub-connection line of the source connection line corresponding to the eighth transistor, the source connection line corresponding to the thirteenth transistor, the second sub-connection line of the source connection line corresponding to the fourteenth transistor, the fifth connection lead and the fourteenth connection lead are connected;

[0064] The fifth connecting lead is connected to the fifteenth connecting lead;

[0065] The drain connection line corresponding to the seventh transistor, the drain connection line corresponding to the eighth transistor, the drain connection line corresponding to the ninth transistor, and the drain connection line corresponding to the tenth transistor are connected to the first output lead;

[0066] The drain connection line corresponding to the eleventh transistor, the drain connection line corresponding to the twelfth transistor, the drain connection line corresponding to the thirteenth transistor, and the drain connection line corresponding to the fourteenth transistor are connected to the second output lead;

[0067] The gate connection line corresponding to the first transistor is connected to the first control lead, and the gate connection line corresponding to the second transistor is connected to the second control lead;

[0068] The third metal wiring layer includes a first power lead for loading a first power supply voltage, and a second power lead for loading a second power supply voltage; the ninth connecting lead, the tenth connecting lead, the fourteenth connecting lead, and the fifteenth connecting lead are connected to the first power lead; the seventh connecting lead, the eighth connecting lead, and the thirteenth connecting lead are connected to the second power lead.

[0069] According to an embodiment of the present disclosure, in any of the row drive signal enhancement regions, source connection lines and drain connection lines corresponding to each transistor extend along the first direction, and gates of each transistor extend along the first direction.

[0070] According to an embodiment of the present disclosure, the first connecting lead includes a first sub-lead, a second sub-lead and a third sub-lead connected in sequence; the first sub-lead of the first connecting lead and the third sub-lead of the first connecting lead extend along the first direction and at least partially overlap with the N-type auxiliary doping region; the second sub-lead of the first connecting lead extends along the second direction and at least partially overlaps with the N-type auxiliary doping region; the first sub-lead of the first connecting lead, the second sub-lead of the first connecting lead and the third sub-lead of the first connecting lead are all connected to the N-type auxiliary doping region; the first sub-active region is located in a space surrounded by the first connecting lead;

[0071] The source connection line corresponding to the ninth transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the ninth transistor and extending along the first direction; the source connection line corresponding to the eleventh transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the eleventh transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the ninth transistor is connected to the first sub-lead of the first connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the eleventh transistor is connected to the third sub-lead of the first connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the ninth transistor and the second sub-connection line of the source connection line corresponding to the eleventh transistor are the same lead, and extend in the opposite direction of the first direction to be connected to the second sub-lead of the first connection lead;

[0072] The seventh connecting lead is connected to the first sub-lead of the first connecting lead; the eighth connecting lead is connected to the third sub-lead of the first connecting lead; and the thirteenth connecting lead is connected to the second sub-lead of the first connecting lead.

[0073] According to an embodiment of the present disclosure, the second connecting lead includes a first sub-lead, a third sub-lead and a fourth sub-lead connected in sequence, and includes a second sub-lead; wherein the first sub-lead of the second connecting lead and the fourth sub-lead of the second connecting lead both extend along the first direction and at least partially overlap with the N-type auxiliary doping region; the second sub-lead of the second connecting lead and the third sub-lead of the second connecting lead both extend along the second direction and at least partially overlap with the N-type auxiliary doping region; the first sub-lead to the fourth sub-lead of the second connecting lead are all connected to the N-type auxiliary doping region;

[0074] The second sub-active region is located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, and the fourth sub-lead of the second connecting lead, and the second active region is located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, the third sub-lead of the second connecting lead, and the fourth sub-lead of the second connecting lead;

[0075] The first sub-connection line of the source connection line corresponding to the tenth transistor extends along the first direction, and its side in the opposite direction of the first direction is connected to the first sub-lead of the second connection lead; the first sub-connection line of the source connection line corresponding to the twelfth transistor extends along the first direction, and its side in the first direction is connected to the fourth sub-lead of the second connection lead; the second sub-connection line of the source connection line corresponding to the tenth transistor and the second sub-connection line of the source connection line corresponding to the twelfth transistor are the same lead and extend along the first direction.

[0076] According to an embodiment of the present disclosure, the fifth connecting lead includes a first sub-lead, a second sub-lead, a third sub-lead and a fourth sub-lead connected in sequence, and includes a fifth sub-lead and a sixth sub-lead;

[0077] The first sub-lead, the third sub-lead and the sixth sub-lead of the fifth connecting lead all extend along the first direction and at least partially overlap with the P-type auxiliary doping region; the sixth sub-lead of the fifth connecting lead is located between the first sub-lead and the third sub-lead, and its two ends are respectively connected to the fifth sub-lead and the fourth sub-lead;

[0078] The second sub-lead, the fourth sub-lead, and the fifth sub-lead of the fifth connecting lead all extend in the second direction, and at least partially overlap with the P-type auxiliary doping region; the fifth sub-lead of the fifth connecting lead is located between the second sub-lead and the fourth sub-lead, and its two ends are respectively connected to the first sub-lead and the third sub-lead; the first sub-lead to the sixth sub-lead of the fifth connecting lead are all connected to the P-type auxiliary doping region;

[0079] The third active region is located in a space surrounded by the first sub-lead, the second sub-lead, the third sub-lead and the fifth sub-lead of the fifth connecting lead; the seventh sub-active region is located in a space surrounded by the first sub-lead, the fifth sub-lead, the sixth sub-lead and the fourth sub-lead of the fifth connecting lead; the eighth sub-active region is located in a space surrounded by the sixth sub-lead, the fifth sub-lead, the third sub-lead and the fourth sub-lead of the fifth connecting lead;

[0080] The source connection line corresponding to the seventh transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the seventh transistor and extending along the first direction; the source connection line corresponding to the thirteenth transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the thirteenth transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the seventh transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the thirteenth transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the seventh transistor and the second sub-connection line of the source connection line corresponding to the thirteenth transistor are the same lead, and extend along the first direction to be connected to the second sub-lead of the fifth connection lead;

[0081] The first sub-connection line of the source connection line corresponding to the eighth transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the fourteenth transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the eighth transistor and the second sub-connection line of the source connection line corresponding to the fourteenth transistor are the same lead;

[0082] The source connection line corresponding to the first transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the first transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the first transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the second sub-connection line of the source connection line corresponding to the first transistor is connected to the sixth sub-lead of the fifth connection lead on one side in the second direction;

[0083] The source connection line corresponding to the second transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the second transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the second transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the second transistor is connected to the sixth sub-lead of the fifth connection lead on one side in the opposite direction of the second direction.

[0084] According to an embodiment of the present disclosure, the third connecting lead, the fourth connecting lead and the sixth connecting lead are located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, the third sub-lead of the second connecting lead and the fourth sub-lead of the second connecting lead; wherein the third connecting lead and the fourth connecting lead extend along the second direction, and the sixth connecting lead extends along the first direction;

[0085] The second direction side of the source connection line corresponding to the sixth transistor is connected to the sixth connection lead, and the opposite direction side of the second direction of the source connection line corresponding to the third transistor is connected to the sixth connection lead;

[0086] The drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the sixth transistor are the same lead, and one end is connected to one end of the fourth connection lead; the gate connection line corresponding to the third transistor and the gate connection line corresponding to the fourth transistor are the same lead, and one end is connected to the other end of the fourth connection lead;

[0087] The drain connection line corresponding to the third transistor and the drain connection line corresponding to the fourth transistor are the same lead, and one end is connected to one end of the third connection lead; the gate connection line corresponding to the fifth transistor and the gate connection line corresponding to the sixth transistor are the same lead, and one end is connected to the other end of the third connection lead.

[0088] According to an embodiment of the present disclosure, the seventh connecting lead extends along the first direction and is connected to the first sub-lead of the first connecting lead and the first sub-lead of the second connecting lead;

[0089] The eighth connecting lead extends along the first direction and is connected to the third sub-lead of the first connecting lead and the fourth sub-lead of the second connecting lead;

[0090] The ninth connecting lead extends along the first direction and is electrically connected to the first sub-lead of the fifth connecting lead;

[0091] The tenth connecting lead extends along the first direction and is connected to the third sub-lead of the fifth connecting lead;

[0092] The drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the first transistor are located in the same straight line, and the orthographic projection of the extension axis on the semiconductor substrate coincides with the orthographic projection of the extension axis of the eleventh connection lead on the semiconductor substrate;

[0093] The drain connection line corresponding to the third transistor and the drain connection line corresponding to the second transistor are located in the same straight line, and the orthographic projections of the extension axes on the semiconductor substrate coincide with the orthographic projections of the extension axes of the twelfth connection lead on the semiconductor substrate;

[0094] The orthographic projection of the extension axis of the thirteenth connecting lead on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connecting line of the source connecting line corresponding to the ninth transistor on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connecting line of the source connecting line corresponding to the tenth transistor on the semiconductor substrate, and the orthographic projection of the extension axis of the sixth connecting lead on the semiconductor substrate coincide with each other;

[0095] The orthographic projection of the extension axis of the second sub-connection line of the source connection line corresponding to the seventh transistor on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connection line of the source connection line corresponding to the eighth transistor on the semiconductor substrate, the orthographic projection of the extension axis of the sixth sub-lead of the fifth connection lead on the semiconductor substrate, the orthographic projection of the extension axis of the fourteenth connection lead on the semiconductor substrate and the orthographic projection of the extension axis of the fifteenth connection lead on the semiconductor substrate coincide with each other.

[0096] According to an embodiment of the present disclosure, the first power lead covers the third active area and the fourth active area; the second power lead covers the first active area and the second active area.

[0097] According to an embodiment of the present disclosure, the display panel is further provided with a pixel driving circuit in the display area, and the pixel driving circuit includes a data writing unit, a storage capacitor and a driving transistor;

[0098] The data writing unit has a first control electrode and a second control electrode, the first control electrode of the data writing unit is connected to the first output lead, the second control electrode of the data writing unit is connected to the second output lead, the input end of the data writing unit is connected to the data line of the display panel, and the output end of the data writing unit is connected to the third node;

[0099] The first electrode plate of the storage capacitor is connected to the third node, and the second electrode plate of the storage capacitor is used to load the first driving voltage;

[0100] The control end of the driving transistor is connected to the third node, the output end of the driving transistor is connected to the light-emitting element of the display panel, and the input end of the driving transistor can be loaded with a second driving voltage.

[0101] According to an embodiment of the present disclosure, the first power lead is used to load the first driving voltage; and the second power lead is used to load the second driving voltage.

[0102] According to an embodiment of the present disclosure, the display panel is further provided with a plurality of shift registers and a plurality of inverters in a peripheral area, which are arranged one-to-one corresponding to each of the row drive signal enhancement circuits;

[0103] In the row drive signal enhancement circuit, the shift register and the inverter that correspond to each other, the output end of the shift register is connected to the input end of the inverter and the first control lead of the row drive signal enhancement circuit, and the output end of the inverter is connected to the second control lead of the row drive signal enhancement circuit.

[0104] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0106] Figure 1 The figure is a schematic diagram of the structure of a row drive signal enhancement circuit according to an embodiment of the present disclosure.

[0107] Figure 2 The figure is a schematic diagram of the structure of a row drive signal enhancement circuit according to an embodiment of the present disclosure.

[0108] Figure 3 The present invention is a timing diagram of signals loaded on two control terminals of a row drive signal enhancement circuit in one embodiment of the present invention.

[0109] Figure 4 It is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0110] Figure 5 The present invention is a schematic diagram of the positions of active regions and auxiliary doping regions of a semiconductor substrate in a row drive signal enhancement region in one embodiment of the present invention.

[0111] Figure 6 It is a schematic diagram of the structure of the gate layer in the row drive signal enhancement area in one embodiment of the present disclosure.

[0112] Figure 7This is a schematic diagram of a structure in which N-type doping is performed on a semiconductor substrate in a row drive signal enhancement region in one embodiment of the present disclosure; wherein the shaded area filled with lines is an area where N-type doping is performed.

[0113] Figure 8 The figure is a schematic diagram of the positions of the N-type doped region and each active region in the row drive signal enhancement region in one embodiment of the present disclosure.

[0114] Fig. 9 This is a schematic structural diagram of performing P-type doping on a semiconductor substrate in a row drive signal enhancement region in one embodiment of the present disclosure; the dot-filled shaded area is a P-type doped area.

[0115] Fig.10 The figure is a schematic diagram of the positions of the P-type doped area, the N-type doped area and each active area in the row drive signal enhancement area in one embodiment of the present disclosure.

[0116] Fig.11 It is a schematic structural diagram of a P-type doped region, an N-type doped region, a gate layer and each active region in a row drive signal enhancement region in one embodiment of the present disclosure.

[0117] Fig.12 It is a schematic structural diagram of each first conductive column in the first dielectric layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0118] Fig.13 This is a schematic structural diagram of a first metal wiring layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0119] Fig.14 It is a schematic structural diagram of a row drive signal enhancement region, a P-type doped region, an N-type doped region, each active region, a gate layer, a first conductive column and a first metal wiring layer in one embodiment of the present disclosure.

[0120] Fig.15 It is a schematic structural diagram of each second conductive pillar in the second dielectric layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0121] Fig.16 It is a schematic structural diagram of a row drive signal enhancement region, a P-type doped region, an N-type doped region, each active region, a gate layer, a first conductive column, a first metal wiring layer and a second conductive column in one embodiment of the present disclosure.

[0122] Fig.17 It is a schematic structural diagram of a second metal wiring layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0123] Fig.18 It is a schematic structural diagram of a first metal wiring layer, a second conductive pillar and a second metal wiring layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0124] Fig.19 It is a schematic structural diagram of each third conductive column in the third dielectric layer in the row drive signal enhancement area in one embodiment of the present disclosure.

[0125] Fig. 20 It is a schematic structural diagram of a third metal wiring layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0126] Fig.21 It is a schematic structural diagram of a second metal wiring layer, a third conductive column and a third metal wiring layer in a row drive signal enhancement area in one embodiment of the present disclosure.

[0127] Fig. 22 This is a schematic structural diagram of an embodiment of the present invention, in a row drive signal enhancement area, a P-type doped area, an N-type doped area, each active area, a gate layer, a first conductive column, a first metal wiring layer, a second conductive column, a second metal wiring layer, a third conductive column, and a third metal wiring layer.

[0128] Fig.23 In one embodiment of the present disclosure, the driving backplane is Fig. 22 Schematic diagram of the structure at the QQ' position.

[0129] Fig.24 It is a schematic structural diagram of a plurality of row driving signal enhancement regions arranged in sequence on a semiconductor substrate in one embodiment of the present disclosure.

[0130] Description of reference numerals:

[0131] 101, row drive signal enhancement circuit; 102, shift register; 103, inverter; 104, pixel drive circuit; CRL, control unit; 110, first control unit; 120, second control unit; 130, first output unit; 140, second output unit; 250, data writing unit; M01, first switch transistor; M02, second switch transistor; Cst, storage capacitor; M03, drive transistor; 310, semiconductor substrate; 320, gate insulating layer; 330, gate layer; 340, insulating dielectric layer; 341, first dielectric layer; 342, second dielectric layer; 343, third dielectric layer; 351, first conductive column; 352, second conductive column; 353, first conductive column; three conductive pillars; 360, metal wiring layer; 361, first metal wiring layer; 362, second metal wiring layer; 363, third metal wiring layer; 411, first power lead; 412, second power lead; 421, first control lead; 422, second control lead; 431, first output lead; 432, second output lead; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; M11, eleventh transistor; M12, twelfth transistor; M13, thirteenth transistor; M14, tenth Four transistors; V1, first power supply voltage; V2, second power supply voltage; A, first node; B, second node; C, third node; IN1, first control terminal; IN2, second control terminal; OUT1, first output terminal; OUT2, second output terminal; D, display area; E, peripheral area; F, row drive signal enhancement area; G, first direction; H, second direction; Act1, first active area; Act2, second active area; Act3, third active area; Act4, fourth active area; Act_sub1, first sub-active area; Act_sub2, second sub-active area; Act_sub3, third sub-active area; Act_sub4, fourth sub-active area; Act_sub5, fifth sub-active area Source region; Act_sub6, sixth sub-active region; Act_sub7, seventh sub-active region; Act_sub8, eighth sub-active region; F_Pdop, P-type substrate region; F_Pdummy, P-type auxiliary doping region; F_Psub1, first P-type doping sub-region; F_Psub2, second P-type doping sub-region; F_Psub3, third P-type doping sub-region; F_Psub4, fourth P-type doping sub-region; F_Psub5, fifth P-type doping sub-region; F_Psub6, sixth P-type doping sub-region; F_Psub7, seventh P-type doping sub-region; F_Psub8, eighth P-type doping sub-region; F_Ndop, N-type substrate region; F_Ndummy, N-type auxiliary doping region;F_Nsub1, a first N-type doping sub-region; F_Nsub2, a second N-type doping sub-region; F_Nsub3, a third N-type doping sub-region; F_Nsub4, a fourth N-type doping sub-region; F_Nsub5, a fifth N-type doping sub-region; F_Nsub6, a sixth N-type doping sub-region; F_Nsub7, a seventh N-type doping sub-region; M1S1, a first source of the first transistor; M1S2, a second source of the first transistor; M1D, a drain of the first transistor; M1G, a gate of the first transistor; M1G1, a first gate of the first transistor; M1G2, a second gate of the first transistor; M1SL1, a first sub-connection line of a source connection line corresponding to the first transistor; M1SL2, a drain of the first transistor a second sub-connection line of the source connection line corresponding to the first transistor; M1DL, a drain connection line corresponding to the first transistor; M1GL, a gate connection line corresponding to the first transistor; M2S1, a first source of the second transistor; M2S2, a second source of the second transistor; M2D, a drain of the second transistor; M2G, a gate of the second transistor; M2G1, a first gate of the second transistor; M2G2, a second gate of the second transistor; M2SL1, a first sub-connection line of the source connection line corresponding to the second transistor; M2SL2, a second sub-connection line of the source connection line corresponding to the second transistor; M2DL, a drain connection line corresponding to the second transistor; M2GL, a gate connection line corresponding to the second transistor; M3S, a second source of the third transistor; a drain electrode of the third transistor; M3D, a drain electrode of the third transistor; M3G, a gate electrode of the third transistor; M3SL, a source electrode connection line corresponding to the third transistor; M3DL, a drain electrode connection line corresponding to the third transistor; M3GL, a gate electrode connection line corresponding to the third transistor; M4S, a second source electrode of the fourth transistor; M4D, a drain electrode of the fourth transistor; M4G, a gate electrode of the fourth transistor; M4SL, a source electrode connection line corresponding to the fourth transistor; M4DL, a drain electrode connection line corresponding to the fourth transistor; M4GL, a gate electrode connection line corresponding to the fourth transistor; M5S, a second source electrode of the fifth transistor; M5D, a drain electrode of the fifth transistor; M5G, a gate electrode of the fifth transistor; M5SL, a source electrode connection line corresponding to the fifth transistor; M5DL, The drain connection line corresponding to the fifth transistor; M5GL, the gate connection line corresponding to the fifth transistor; M6S, the second source of the sixth transistor; M6D, the drain of the sixth transistor; M6G, the gate of the sixth transistor; M6SL, the source connection line corresponding to the sixth transistor; M6DL, the drain connection line corresponding to the sixth transistor; M6GL, the gate connection line corresponding to the sixth transistor; M7S1, the first source of the seventh transistor; M7S2, the second source of the seventh transistor; M7D, the drain of the seventh transistor; M7G, the gate of the seventh transistor; M7G1, the first gate of the seventh transistor; M7G2, the second gate of the seventh transistor; M7SL1, the first sub-connection line of the source connection line corresponding to the seventh transistor;M7SL2, the second sub-connection line of the source connection line corresponding to the seventh transistor; M7DL, the drain connection line corresponding to the seventh transistor; M7GL, the gate connection line corresponding to the seventh transistor; M8S1, the first source of the eighth transistor; M8S2, the second source of the eighth transistor; M8D, the drain of the eighth transistor; M8G, the gate of the eighth transistor; M8G1, the first gate of the eighth transistor; M8G2, the second gate of the eighth transistor; M8SL1, the first sub-connection line of the source connection line corresponding to the eighth transistor; M8SL2, the second sub-connection line of the source connection line corresponding to the eighth transistor; M8DL, the drain connection line corresponding to the eighth transistor; M8GL, the gate connection line corresponding to the eighth transistor line; M9S1, the first source of the ninth transistor; M9S2, the second source of the ninth transistor; M9D, the drain of the ninth transistor; M9G, the gate of the ninth transistor; M9G1, the first gate of the ninth transistor; M9G2, the second gate of the ninth transistor; M9SL1, the first sub-connection line of the source connection line corresponding to the ninth transistor; M9SL2, the second sub-connection line of the source connection line corresponding to the ninth transistor; M9DL, the drain connection line corresponding to the ninth transistor; M9GL, the gate connection line corresponding to the ninth transistor; M10S1, the first source of the tenth transistor; M10S2, the second source of the tenth transistor; M10D, the drain of the tenth transistor; M10G, the gate of the tenth transistor; M10G1, the first gate of the tenth transistor; M10G2, the second gate of the tenth transistor; M10SL1, the first sub-connection line of the source connection line corresponding to the tenth transistor; M10SL2, the second sub-connection line of the source connection line corresponding to the tenth transistor; M10DL, the drain connection line corresponding to the tenth transistor; M10GL, the gate connection line corresponding to the tenth transistor; M11S1, the first source of the eleventh transistor; M11S2, the second source of the eleventh transistor; M11D, the drain of the eleventh transistor; M11G, the gate of the eleventh transistor; M11G1, the first gate of the eleventh transistor; M11G2, the second gate of the eleventh transistor; M11SL1, the drain of the eleventh transistor M11SL2, a first sub-connection line of the source connection line corresponding to the eleventh transistor; M11DL, a drain connection line corresponding to the eleventh transistor; M11GL, a gate connection line corresponding to the eleventh transistor; M12S1, a first source of the twelfth transistor; M12S2, a second source of the twelfth transistor; M12D, a drain of the twelfth transistor; M12G, a gate of the twelfth transistor; M12G1, a first gate of the twelfth transistor; M12G2, a second gate of the twelfth transistor; M12SL1, a first sub-connection line of the source connection line corresponding to the twelfth transistor; M12SL2, a second sub-connection line of the source connection line corresponding to the twelfth transistor;M12DL, drain connection line corresponding to the twelfth transistor; M12GL, gate connection line corresponding to the twelfth transistor; M13S1, first source of the thirteenth transistor; M13S2, second source of the thirteenth transistor; M13D, drain of the thirteenth transistor; M13G, gate of the thirteenth transistor; M13G1, first gate of the thirteenth transistor; M13G2, second gate of the thirteenth transistor; M13SL1, first sub-connection line of the source connection line corresponding to the thirteenth transistor; M13SL2, second sub-connection line of the source connection line corresponding to the thirteenth transistor; M13DL, the drain of the thirteenth transistor; M13S2, second source of the thirteenth transistor; M13D, drain of the thirteenth transistor; M13G, gate of the thirteenth transistor; M13G1, first gate of the thirteenth transistor; M13G2, second gate of the thirteenth transistor; M13SL1, first sub-connection line of the source connection line corresponding to the thirteenth transistor; M13SL2, second sub-connection line of the source connection line corresponding to the thirteenth transistor; The drain connection line corresponding to the thirteenth transistor is M13GL; the gate connection line corresponding to the thirteenth transistor is M14S1; the first source of the fourteenth transistor is M14S2; the second source of the fourteenth transistor is M14D; the drain of the fourteenth transistor is M14G; the gate of the fourteenth transistor is M14G1; the first gate of the fourteenth transistor is M14G2; the second gate of the fourteenth transistor is M14SL1; the first sub-connection line of the source connection line corresponding to the fourteenth transistor is M14SL2; the second sub-connection line of the source connection line corresponding to the fourteenth transistor is M14DL; the drain connection line corresponding to the fourteenth transistor is M14GL, The gate connection line corresponding to the fourteenth transistor; L01, the first connection lead; L011, the first sub-lead of the first connection lead; L012, the second sub-lead of the first connection lead; L013, the third sub-lead of the first connection lead; L02, the second connection lead; L021, the first sub-lead of the second connection lead; L022, the second sub-lead of the second connection lead; L023, the third sub-lead of the second connection lead; L024, the fourth sub-lead of the second connection lead; L03, the third connection lead; L04, the fourth connection lead; L05, the fifth connection lead; L051, the first sub-lead of the fifth connection lead; L0 52, the second sub-lead of the fifth connecting lead; L053, the third sub-lead of the fifth connecting lead; L054, the fourth sub-lead of the fifth connecting lead; L055, the fifth sub-lead of the fifth connecting lead; L056, the sixth sub-lead of the fifth connecting lead; L07, the seventh connecting lead; L08, the eighth connecting lead; L09, the ninth connecting lead; L10, the tenth connecting lead; L11, the eleventh connecting lead; L12, the twelfth connecting lead; L13, the thirteenth connecting lead; L14, the fourteenth connecting lead; L15, the fifteenth connecting lead; L16, the sixteenth connecting lead; L17, the seventeenth connecting lead. ; DETAILED DESCRIPTION

[0132] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0133] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0134] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0135] In the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In the case of using transistors of opposite types or the case where the current direction changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in the present disclosure, the "source" and the "drain" can be interchanged. Structurally, a transistor can have a first end, a second end, and a control end, wherein the gate of the transistor can serve as the control end (or control electrode) of the transistor; one of the source and the drain of the transistor can serve as the first end of the transistor, and the other can serve as the second end of the transistor.

[0136] In the present disclosure, the "on" state of a transistor refers to a state in which the source and drain of the transistor are electrically connected. The "off" state of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected; it is understood that when the transistor is off, leakage current may still exist.

[0137] In the present disclosure, when two signals are described as anti-phase signals, it means that one of the signals is a high-level signal and the other signal is a low-level signal.

[0138] See also Figure 1 The present disclosure provides a row drive signal enhancement circuit, comprising:

[0139] The control unit CRL has a first control terminal IN1 and a second control terminal IN2, and is used to input a first power supply voltage V1 to one of the first node A and the second node B, and input a second power supply voltage V2 to the other node under the control of the first control terminal IN1 and the second control terminal IN2;

[0140] The first output unit 130 is connected to the first node A and the first output terminal OUT1, and is used to output one of the first power supply voltage V1 and the second power supply voltage V2 to the first output terminal OUT1 under the control of the first node A;

[0141] The second output unit 140 is connected to the second node B and the second output terminal OUT2 , and is used for outputting the other of the first power voltage V1 and the second power voltage V2 to the second output terminal OUT2 under the control of the second node B.

[0142] See also Figure 4, the row drive signal enhancement circuit 101 provided in the present disclosure can form a shift register unit with a shift register 102 and an inverter 103; wherein the shift register 102 is used to output an initial scan signal (i.e., a first initial scan signal) to the input end of the inverter 103 and the first control end IN1 of the row drive signal enhancement circuit 101; the output end of the inverter 103 is connected to the second control end IN2 of the row drive signal enhancement circuit 101, so as to generate a second initial scan signal inverted from the first initial scan signal according to the first initial scan signal. In this way, the shift register 102 and the inverter 103 can respectively input two inverted initial scan signals (the first initial scan signal and the second initial scan signal) to the two control ends (the first control end IN1 and the second control end IN2) of the control unit CRL of the row drive signal enhancement circuit 101. The row drive signal enhancement circuit 101 can make the first output unit 130 and the second output unit 140 output two different power supply voltages (first power supply voltage V1 and second power supply voltage V2) as the scan signal of the display panel according to the two inverted initial scan signals loaded on the first control terminal IN1 and the second control terminal IN2, that is, output the scan signal formed by the first power supply voltage V1 and the second power supply voltage V2. The scan signal formed by the two power supply voltages can replace the initial scan signal generated by the shift register 102 and the inverter 103 to control the data writing unit of the pixel drive circuit.

[0143] Therefore, the row drive signal enhancement circuit 101 provided by the present disclosure can convert an initial scanning signal with a weak driving capability into a scanning signal with a stronger driving capability formed by a power supply voltage, and can overcome the problem of large delay and voltage loss when the initial scanning signal reaches the pixel driving circuit, and can improve the display uniformity of the display panel, especially improve the display uniformity of a silicon-based OLED (organic light-emitting diode) display.

[0144] The structure, principle and effect of the row drive signal enhancement circuit 101 of the present disclosure will be further explained and illustrated below in conjunction with the accompanying drawings.

[0145] The row drive signal enhancement circuit 101 provided by the present disclosure is used to improve the row drive capability of the display panel, especially to improve the row drive capability of the silicon-based OLED display. The row drive signal enhancement circuit 101 can generate two scan signals according to the two initial scan signals of the display panel, and the scan voltages of the two scan signals are different power supply voltages. On the one hand, it has a smaller voltage drop during the transmission process on the scan lead, and on the other hand, it has a greater signal transmission capacity to meet the requirements of each load on the scan lead, and reduce the conduction delay of each data writing unit. Therefore, the scan signal generated by the row drive signal enhancement circuit 101 has a stronger driving capability.

[0146] Optionally, in the row drive signal enhancement circuit 101, the control unit CRL may include:

[0147] The first control unit 110 has a first control terminal IN1 and a second control terminal IN2, and is used to output a first power supply voltage V1 to the first node A or the second node B under the control of the first control terminal IN1 and the second control terminal IN2;

[0148] The second control unit 120 is connected to the first node A and the second node B, and is used to output the second power supply voltage V2 to the second node B in response to the first power supply voltage V1 loaded on the first node A, and is used to output the second power supply voltage V2 to the first node A in response to the first power supply voltage V1 loaded on the second node B.

[0149] Optionally, the first output unit 130 may further include a first input terminal and a second input terminal, the first input terminal of the first output unit 130 being loaded with the first power supply voltage V1, and the second input terminal of the first output unit 130 being loaded with the second power supply voltage V2. In other words, the first input terminal of the first output unit 130 is connected to a power supply providing the first power supply voltage V1 through a lead, and the second input terminal of the first output unit 130 is connected to a power supply providing the second power supply voltage V2 through a lead. In this way, the first output unit 130 can directly output any one of the loaded first power supply voltage V1 and the second power supply voltage V2 to the first output terminal OUT1, without generating the first power supply voltage V1 and the second power supply voltage V2 by a voltage regulation method, thereby ensuring that the signal output by the first output terminal OUT1 is not only the first power supply voltage V1 or the second power supply voltage V2 in voltage, but also ensuring that the scanning signal output by the first output terminal OUT1 has a stronger driving capability, which can meet the requirements of each load on each scanning lead.

[0150] Optionally, in the row drive signal enhancement circuit 101, the second output unit 140 may further include a first input terminal and a second input terminal, the first input terminal of the second output unit 140 is loaded with the first power supply voltage V1, and the second input terminal of the second output unit 140 is loaded with the second power supply voltage V2. In other words, the first input terminal of the second output unit 140 is connected to a power supply providing the first power supply voltage V1 through a lead, and the second input terminal of the second output unit 140 is connected to a power supply providing the second power supply voltage V2 through a lead. In this way, the second output unit 140 can directly output any one of the loaded first power supply voltage V1 and the second power supply voltage V2 to the second output terminal OUT2, without generating the first power supply voltage V1 and the second power supply voltage V2 by a voltage regulation method, thereby ensuring that the signal output by the second output terminal OUT2 is not only the first power supply voltage V1 or the second power supply voltage V2 in voltage, but also ensuring that the scanning signal output by the second output terminal OUT2 has a stronger driving capability, which can meet the requirements of each load on each scanning lead.

[0151] Optionally, the second control unit 120 has at least two groups of transistors, each group of transistors includes at least two transistors of the same type. That is, the second control unit 120 has at least four transistors. Among them, in a group of transistors, each transistor is connected in parallel, that is, the source electrodes of each transistor in the same group are electrically connected to each other, the drain electrodes are electrically connected to each other, and the gate electrodes are electrically connected to each other; in this way, the signal delay (RC delay) of each transistor can be reduced, the turn-on speed of each group of transistors can be increased, the driving capability of each group of transistors can be guaranteed, and the signal delay of the second control unit 120 can be reduced.

[0152] In the present disclosure, the type of transistor refers to whether the transistor is an N-type transistor or a P-type transistor. When two or more transistors are of the same type, it means that the two or more transistors are all N-type transistors or all P-type transistors.

[0153] Alternatively, see Figure 2 , the first control unit 110 may include:

[0154] The first transistor M1 has a first end for loading the first power supply voltage V1, a second end connected to the first node A, and a control end as the first control end IN1; the first transistor M1 is used to output the first power supply voltage V1 to the first node A under the control of the control end of the first transistor M1;

[0155] The second transistor M2 has a first end for loading the first power supply voltage V1, a second end connected to the second node B, and a control end as the second control end IN2; the second transistor M2 is used to output the first power supply voltage V1 to the second node B under the control of the control end of the second transistor M2;

[0156] The first transistor M1 and the second transistor M2 are both N-type transistors or both P-type transistors.

[0157] See also Figure 3 When the row drive signal enhancement circuit 101 of the present disclosure is working, the first control terminal IN1 and the second control terminal IN2 of the first control unit 110 are respectively loaded with the first initial scanning signal and the second initial scanning signal of the inverted phase. Therefore, the control terminals of the first transistor M1 and the second transistor M2 are respectively loaded with two initial scanning signals of the inverted phase. The first transistor M1 and the second transistor M2 are of the same type, for example, both are N-type transistors or both are P-type transistors, which not only facilitates the preparation of transistors, but also allows the first transistor M1 and the second transistor M2 to be selectively turned on, so that the first control unit 110 selectively outputs the first power supply voltage V1 to the first node A or the second node B.

[0158] In the following, the working process of the first control unit 110 is described by taking the example that the first transistor M1 and the second transistor M2 are both N-type transistors and the example that the first initial scanning signal output by the shift register unit is a high level signal.

[0159] Figure 3 is a timing diagram of two initial scan signals loaded on the first control terminal IN1 and the second control terminal IN2. Figure 3 , the first control terminal IN1 is loaded with a low-level base voltage in the T1 stage and the T3 stage, and is loaded with a high-level first initial scan signal in the T2 stage. The second control terminal IN2 is loaded with a high-level base voltage in the T1 stage and the T3 stage, and is loaded with a low-level second initial scan signal in the T2 stage. Therefore, the signals on the first control terminal IN1 and the second control terminal IN2 remain in opposite phases, and when one is at a high level, the other is at a low level.

[0160] In the T1 phase and the T3 phase, the first control terminal IN1 is loaded with a low level signal and the second control terminal IN2 is loaded with a high level signal, so that the second transistor M2 is turned on and the first transistor M1 is turned off, and the first control unit 110 outputs the first power supply voltage V1 to the second node B. In the T2 phase, the first control terminal IN1 is loaded with a high level signal and the second control terminal IN2 is loaded with a low level signal, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and the first control unit 110 outputs the first power supply voltage V1 to the first node A.

[0161] Alternatively, see Figure 2 , the second control unit 120 may include:

[0162] The third transistor M3 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second node B; the third transistor M3 is used to output the second power supply voltage V2 to the second node B under the control of the first power supply voltage V1 loaded on the first node A;

[0163] The fourth transistor M4 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second node B; the fourth transistor M4 is used to output the second power supply voltage V2 to the second node B under the control of the first power supply voltage V1 loaded on the first node A;

[0164] a fifth transistor M5 having a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first node A; the fifth transistor M5 is used to output the second power supply voltage V2 to the first node A under the control of the first power supply voltage V1 loaded on the second node B;

[0165] The sixth transistor M6 has a control end connected to the second node B, a first end for loading the second power supply voltage V2, and a second end connected to the first node A; the sixth transistor M6 is used to output the second power supply voltage V2 to the first node A under the control of the first power supply voltage V1 loaded on the second node B.

[0166] The third transistor M3 to the sixth transistor M6 are of the same type, and are all N-type transistors or all P-type transistors.

[0167] Further, the first power supply voltage V1 is lower than the second power supply voltage V2, and the third transistor M3 to the sixth transistor M6 are P-type transistors; or, the first power supply voltage V1 is higher than the second power supply voltage V2, and the third transistor M3 to the sixth transistor M6 are N-type transistors. In other words, when the control terminal of any one of the third transistor M3 to the sixth transistor M6 is loaded with the first power supply voltage V1, the transistor can be turned on; when the control terminal of any one of the third transistor M3 to the sixth transistor M6 is loaded with the second power supply voltage V2, the transistor can be turned off.

[0168] Below, the working process of the second control unit 120 is explained and described by taking the first power supply voltage V1 as being lower than the second power supply voltage V2 and the third transistor M3 to the sixth transistor M6 as P-type transistors as an example. When the first control unit 110 loads the first power supply voltage V1 to the first node A, the first control unit 110 does not load voltage to the second node B; under the control of the first node A, the third transistor M3 and the fourth transistor M4 are turned on and output the second power supply voltage V2 to the second node B. In this way, the first node A is loaded with the first power supply voltage V1, and the second node B is loaded with the second power supply voltage V2. Conversely, when the first control unit 110 loads the first power supply voltage V1 to the second node B, the first control unit 110 does not load voltage to the first node A; under the control of the second node B, the fifth transistor M5 and the sixth transistor M6 are turned on and output the second power supply voltage V2 to the first node A. In this way, the second node B is loaded with the first power supply voltage V1, and the first node A is loaded with the second power supply voltage V2. It can be seen that no matter what working state the first control unit 110 and the second control unit 120 are in, two different power supply voltages are respectively loaded on the first node A and the second node B, namely the first power supply voltage V1 and the second power supply voltage V2.

[0169] Similarly, when the first power supply voltage V1 is higher than the second power supply voltage V2 and the third transistor M3 to the sixth transistor M6 are N-type transistors, two different power supply voltages can also be loaded on the first node A and the second node B respectively, and the present disclosure will not elaborate on its principles and processes.

[0170] Alternatively, see Figure 2 , the first output unit 130 may include:

[0171] A seventh transistor M7, having a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal as a first output terminal OUT1;

[0172] An eighth transistor M8 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the first output terminal OUT1;

[0173] A ninth transistor M9, having a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1;

[0174] A tenth transistor M10 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1;

[0175] The second output unit 140 includes:

[0176] an eleventh transistor M11 having a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal as a second output terminal OUT2;

[0177] a twelfth transistor M12, having a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second output terminal OUT2;

[0178] The thirteenth transistor M13 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2;

[0179] A fourteenth transistor M14 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2;

[0180] Among them, any one of the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 is used to respond to one of the first power supply voltage V1 and the second power supply voltage V2 loaded on its control terminal and turn on, and any one of the ninth transistor M9 to the twelfth transistor M12 is used to respond to the other of the first power supply voltage V1 and the second power supply voltage V2 loaded on its control terminal and turn on.

[0181] In other words, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are of the same type; the ninth transistor M9 to the twelfth transistor M12 are of the same type; the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are of different types from the ninth transistor M9 to the twelfth transistor M12. Thus, two different power supply voltages (i.e., the first power supply voltage V1 and the second power supply voltage V2) are respectively loaded on the first node A and the second node B, and the first output unit 130 and the second output unit 140 respectively output two different power supply voltages (i.e., the first power supply voltage V1 and the second power supply voltage V2).

[0182] In this embodiment, the seventh transistor M7 and the eighth transistor M8 of the first output unit 130 are arranged in parallel, and the ninth transistor M9 and the tenth transistor M10 are arranged in parallel; this can increase the magnitude of the current output by the first output unit 130, thereby ensuring the driving capability of the first output unit 130, and can reduce the RC delay of the first output unit 130. Similarly, the eleventh transistor M11 and the twelfth transistor M12 of the second output unit 140 are arranged in parallel, and the thirteenth transistor M13 and the fourteenth transistor M14 are arranged in parallel; this can increase the magnitude of the current output by the second output unit 140, thereby ensuring the driving capability of the second output unit 140, and can reduce the RC delay of the second output unit 140.

[0183] Illustratively, in one embodiment of the present disclosure, the first power supply voltage V1 may be a low level signal, and the second power supply voltage V2 may be a high level signal; the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 may be N-type transistors, and the ninth transistor M9 to the twelfth transistor M12 may be P-type transistors.

[0184] When the first node A is loaded with the first power supply voltage V1, the seventh transistor M7 and the eighth transistor M8 are turned off, while the ninth transistor M9 and the tenth transistor M10 are turned on, and the first output unit 130 outputs the second power supply voltage V2 through the first output terminal OUT1. At this time, B is loaded with the second power supply voltage V2, the eleventh transistor M11 and the twelfth transistor M12 are turned off, while the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, and the second output unit 140 outputs the first power supply voltage V1 through the second output terminal OUT2.

[0185] Similarly, when the first node A is loaded with the second power supply voltage V2, the seventh transistor M7 and the eighth transistor M8 are turned on, while the ninth transistor M9 and the tenth transistor M10 are turned off, and the first output unit 130 outputs the first power supply voltage V1 through the first output terminal OUT1. At this time, B is loaded with the first power supply voltage V1, the eleventh transistor M11 and the twelfth transistor M12 are turned on, while the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, and the second output unit 140 outputs the second power supply voltage V2 through the second output terminal OUT2.

[0186] Optionally, the first transistor M1 to the fourteenth transistor M14 may be MOS (Metal Oxide Semiconductor) transistors.

[0187] A row drive signal enhancement circuit 101 and its working process are introduced below by way of example, so as to further explain and illustrate the principle, structure and effect of the row drive signal enhancement circuit 101 of the present disclosure.

[0188] See also Figure 2 The exemplary row driving signal enhancement circuit 101 includes a first control unit 110 , a second control unit 120 , a first output unit 130 , and a second output unit 140 .

[0189] The first control unit 110 includes a first transistor M1 and a second transistor M2, and both the first transistor M1 and the second transistor M2 are N-type transistors. The first transistor M1 has a first end for loading a first power supply voltage V1, a second end connected to a first node A, and a control end as a first control end IN1. The second transistor M2 has a first end for loading a first power supply voltage V1, a second end connected to a second node B, and a control end as a second control end IN2. The first control end IN1 and the second control end IN2 of the row drive signal enhancement circuit 101 can load two inverted initial scan signals, one of which is a high level signal and the other is a low level signal. The first transistor M1 and the second transistor M2 can be turned on in response to a high level signal loaded on their respective control ends, and can be turned off in response to a low level signal loaded on their respective control ends.

[0190] The second control unit 120 includes a third transistor M3 to a sixth transistor M6, and the third transistor M3 to the sixth transistor M6 are all P-type transistors. Among them, the third transistor M3 has a control end connected to the first node A, a first end for loading the second power supply voltage V2, and a second end connected to the second node B. The fourth transistor M4 has a control end connected to the first node A, a first end for loading the second power supply voltage V2, and a second end connected to the second node B. The fifth transistor M5 has a control end connected to the second node B, a first end for loading the second power supply voltage V2, and a second end connected to the first node A. The sixth transistor M6 has a control end connected to the second node B, a first end for loading the second power supply voltage V2, and a second end connected to the first node A. During the operation of the row drive signal enhancement circuit 101, one of the first node A and the second node B is loaded with the first power supply voltage V1, and the other is loaded with the second power supply voltage V2; wherein the first power supply voltage V1 can be a low level and the second power supply voltage V2 is a high level, so that the third transistor M3 to the sixth transistor M6 can be turned on in response to the first power supply voltage V1 loaded on their respective control terminals, and can be turned off in response to the second power supply voltage V2 loaded on their respective control terminals.

[0191] The first output unit 130 includes a seventh transistor M7 to a tenth transistor M10, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors, and the ninth transistor M9 and the tenth transistor M10 are P-type transistors. The seventh transistor M7 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal as the first output terminal OUT1. The eighth transistor M8 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the first output terminal OUT1. The ninth transistor M9 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1. The tenth transistor M10 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1.

[0192] The second output unit 140 includes an eleventh transistor M11 to a fourteenth transistor M14, and the eleventh transistor M11 and the twelfth transistor M12 are P-type transistors, and the thirteenth transistor M13 and the fourteenth transistor M14 are N-type transistors. The eleventh transistor M11 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal as the second output terminal OUT2. The twelfth transistor M12 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second output terminal OUT2. The thirteenth transistor M13 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2. The fourteenth transistor M14 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2.

[0193] In the exemplary row drive signal enhancement circuit 101, the first power supply voltage V1 is at a low level, and the second power supply voltage V2 is at a high level, and the first power supply voltage V1 and the second power supply voltage V2 are two inverted initial scan signals. When the control end of the N-type transistor is loaded with the first power supply voltage V1, the N-type transistor is turned off; when the control end of the N-type transistor is loaded with the second power supply voltage V2, the N-type transistor is turned on; when the control end of the P-type transistor is loaded with the first power supply voltage V1, the N-type transistor is turned on; when the control end of the P-type transistor is loaded with the second power supply voltage V2, the P-type transistor is turned off. In this way, under the control of the two inverted initial scan signals respectively loaded on the first control end IN1 and the second control end IN2, the first output end OUT1 and the second output end OUT2 respectively output two inverted scan signals.

[0194] See also Figure 3, in the T1 time period, the first control terminal IN1 is loaded with the first power supply voltage V1 and the second control terminal IN2 is loaded with the second power supply voltage V2, the first transistor M1 is turned off and the second transistor M2 is turned on, so that the first power supply voltage V1 is loaded to B through the second transistor M2. The fifth transistor M5 and the sixth transistor M6 are turned on in response to the first power supply voltage V1 loaded on B, so that the second power supply voltage V2 is loaded to A through the fifth transistor M5 and the sixth transistor M6. The third transistor M3 and the fourth transistor M4 are turned off in response to the second power supply voltage V2 loaded on A, so that the signal loaded on B is locked to the first power supply voltage V1. The seventh transistor M7 and the eighth transistor M8 are turned on in response to the second power supply voltage V2 loaded on A, and the ninth transistor M9 and the tenth transistor M10 are turned off in response to the second power supply voltage V2 loaded on A, so that the first power supply voltage V1 is loaded to the first output terminal OUT1 through the seventh transistor M7 and the eighth transistor M8; that is, the first output terminal OUT1 of the row drive signal enhancement circuit 101 outputs the first power supply voltage V1. The eleventh transistor M11 and the twelfth transistor M12 are turned on in response to the first power supply voltage V1 loaded on B, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned off in response to the first power supply voltage V1 loaded on B, so that the second power supply voltage V2 is loaded to the second output terminal OUT2 through the eleventh transistor M11 and the twelfth transistor M12; that is, the second output terminal OUT2 of the row drive signal enhancement circuit 101 outputs the second power supply voltage V2.

[0195] See also Figure 3, in the T2 time period, the first control terminal IN1 is loaded with the second power supply voltage V2 and the second control terminal IN2 is loaded with the first power supply voltage V1, the first transistor M1 is turned on and the second transistor M2 is turned off, so that the first power supply voltage V1 is loaded to A through the first transistor M1. The third transistor M3 and the fourth transistor M4 are turned on in response to the first power supply voltage V1 loaded on A, so that the second power supply voltage V2 is loaded to B through the third transistor M3 and the fourth transistor M4. The fifth transistor M5 and the sixth transistor M6 are turned off in response to the second power supply voltage V2 loaded on B, so that the signal loaded on A is locked to the first power supply voltage V1. The seventh transistor M7 and the eighth transistor M8 are turned off in response to the first power supply voltage V1 loaded on A, and the ninth transistor M9 and the tenth transistor M10 are turned on in response to the first power supply voltage V1 loaded on A, so that the second power supply voltage V2 is loaded to the first output terminal OUT1 through the ninth transistor M9 and the tenth transistor M10; that is, the first output terminal OUT1 of the row drive signal enhancement circuit 101 outputs the second power supply voltage V2. The eleventh transistor M11 and the twelfth transistor M12 are turned off in response to the second power supply voltage V2 loaded on B, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned on in response to the second power supply voltage V2 loaded on B, so that the first power supply voltage V1 is loaded to the second output terminal OUT2 through the thirteenth transistor M13 and the fourteenth transistor M14; that is, the second output terminal OUT2 of the row drive signal enhancement circuit 101 outputs the first power supply voltage V1.

[0196] Optionally, in some embodiments, one of the first power supply voltage V1 and the second power supply voltage V2 may be a ground voltage (GND), ie, a reference voltage of the display panel, and the other may be a voltage VDD applied to the source of the driving transistor by the pixel driving circuit during the light emitting phase.

[0197] The present disclosure also provides a shift register unit, see Figure 4, the shift register unit includes any one of the row drive signal enhancement circuits 101 described in the above row drive signal enhancement circuit 101 implementation mode, and includes a shift register 102 and an inverter 103. Among them, the shift register 102 is used to output the first initial scan signal to the input end of the inverter 103 and the first control end IN1 of the row drive signal enhancement circuit 101; the output end of the inverter 103 is connected to the second control end IN2 of the row drive signal enhancement circuit 101. The shift register unit can generate an initial scan signal (including an inverted first initial scan signal and a second initial scan signal), and then use the power supply voltage (including a first power supply voltage V1 and a second power supply voltage V2) to convert the initial scan signal into a scan signal; the scan voltage and the base voltage of the scan signal are different power supply voltages (respectively the first power supply voltage V1 and the second power supply voltage V2), thereby improving the driving ability of the scan signal and overcoming the defects of large delay and large voltage drop of the scan signal on the scan lead.

[0198] Since the shift register unit has any one of the row drive signal enhancement circuits 101 described in the above row drive signal enhancement circuit implementations, it has the same beneficial effects, which will not be described in detail in the present disclosure.

[0199] The present disclosure also provides a display panel, which includes any one of the shift register units described in the above shift register unit implementation. The display panel can be an OLED (organic light emitting diode) display panel, a liquid crystal display panel, a Micro LED (micro light emitting diode) display panel or other types of display panels, especially a silicon-based OLED display panel or a silicon-based liquid crystal display panel. Since the display panel has any one of the shift register units described in the above shift register unit implementation, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0200] The present disclosure also provides a display panel, which may include a driving backplane and a display layer stacked on the driving backplane.

[0201] See also Fig.23 The driving backplane includes a semiconductor substrate 310, a gate insulating layer 320, a gate layer 330, an insulating dielectric layer 340 and a metal wiring layer 360 which are stacked in sequence. Figure 4 , the display panel includes a display area D and a peripheral area E located at at least one side of the display area D; see Fig.24 , a plurality of row driving signal enhancement areas F are disposed in the peripheral area E. In one embodiment of the present disclosure, the peripheral area E surrounds the display area D.

[0202] Figure 5 FIG. 3 is a schematic diagram of the structure of the semiconductor substrate 310 in the row drive signal enhancement area F. Figure 5 In the figure, only the positions of the active regions and the positions of the N-type substrate region F_Ndop and the P-type substrate region F_Pdop of the row driving signal enhancement region F are shown.

[0203] In any row drive signal enhancement area F, the display panel is provided with a row drive signal enhancement circuit 101 including a first transistor M1 to a fourteenth transistor M14; wherein the first transistor M1 and the second transistor M2 are of the same type; the fifth transistor M5, the eighth transistor M8, the thirteenth transistor M13 and the fourteenth transistor M14 are of the same type; the ninth transistor M9 to the twelfth transistor M12 are of the same type and are opposite to the type of the fifth transistor M5; and the third transistor M3 to the sixth transistor M6 are of the same type.

[0204] The semiconductor substrate 310 forms the active region of each transistor, and the active region of any transistor includes a channel region, a source and a drain on both sides of the channel region; the gate layer 330 forms the gate of each transistor, and the gate insulating layer 320 isolates the gate and the channel region of any transistor. Fig.23 , the insulating dielectric layer 340 covers the gate layer 330 .

[0205] In one row driving signal enhancement region F, the metal wiring layer 360 is provided with a connection lead, a first power lead 411 , a second power lead 412 , a first control lead 421 , a second control lead 422 , a first output lead 431 and a second output lead 432 . The connecting lead is electrically connected to the source, drain and gate of each transistor through a conductive column located in the insulating dielectric layer 340; wherein the connecting lead electrically connects the gate M1G of the first transistor M1 to the first control lead 421, and electrically connects the gate M2G of the second transistor M2 to the second control lead 422, and electrically connects the source of the first transistor M1, the source of the second transistor M2, the source of the seventh transistor M7, the source of the eighth transistor M8, the source of the thirteenth transistor M13, and the source of the fourteenth transistor M14 to the first power lead 411, and electrically connects the sources of the third transistor M3 to the sixth transistor M6, and the sources of the ninth transistor M9 to the twelfth transistor M12 to the second power lead 412, and The drains of the seventh transistor M7 to the tenth transistor M10 are electrically connected to the first output lead 431, and the drains of the eleventh transistor M11 to the fourteenth transistor M14 are electrically connected to the second output lead 432, and the drain M1D of the first transistor M1, the drain of the fifth transistor M5, the drain of the sixth transistor M6, the gate of the third transistor M3, the gate of the fourth transistor M4, and the gates of the seventh transistor M7 to the tenth transistor M10 are electrically connected to each other, and the drain M2D of the second transistor M2, the drain of the third transistor M3, the drain of the fourth transistor M4, the gate of the fifth transistor M5, the gate of the sixth transistor M6, and the gates of the eleventh transistor M11 to the fourteenth transistor M14 are electrically connected to each other.

[0206] Thus, in the display panel of the present disclosure, the equivalent circuit of the row drive signal enhancement circuit 101 is as follows: Figure 2 The working process and effect of the row drive signal enhancement circuit 101 are described in detail in the above-mentioned row drive signal enhancement circuit 101 implementation, and will not be repeated here. The display panel is provided with a row drive signal enhancement circuit 101, so that the row drive capability of the display panel can be improved and the display uniformity of the display panel can be improved.

[0207] In the display panel provided by the present disclosure, the first power lead 411 may be loaded with a first power supply voltage V1, and the second power lead 412 may be loaded with a second power supply voltage V2. The first control lead 421 may serve as a first control terminal IN1 of the row drive signal enhancement circuit 101, and the second control lead 422 may serve as a second control terminal IN2 of the row drive signal enhancement circuit 101. The first output lead 431 may serve as a first output terminal OUT1 of the row drive signal enhancement circuit 101, and the second output lead 432 may serve as a second output terminal OUT2 of the row drive signal enhancement circuit 101.

[0208] In one embodiment of the present disclosure, the first transistor M1, the second transistor M2, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are N-type transistors; the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are P-type transistors. In this way, each transistor can be formed by using a CMOS (Complementary Metal Oxide Semiconductor) process, without introducing an additional process to increase the cost of the display panel.

[0209] Optionally, the semiconductor substrate 310 may be a silicon-based semiconductor substrate, and in particular, may be a single crystal silicon semiconductor substrate 310 .

[0210] Alternatively, see Figure 5 Any row driving signal enhancement area F includes a P-type substrate area F_Pdop and an N-type substrate area F_Ndop, the P-type substrate area F_Pdop is located on the first direction G side of the N-type substrate area F_Ndop, and the first direction G is a direction away from the display area D; the N-type transistor is formed in the P-type substrate area F_Pdop, and the P-type transistor is formed in the N-type substrate area F_Ndop.

[0211] In some embodiments, see Figure 5 , the N-type substrate region F_Ndop includes an N-type auxiliary doping region F_Ndummy, and includes a first active region Act1 and a second active region Act2 respectively surrounded by the N-type auxiliary doping region F_Ndummy; the second active region Act2 is located on one side of the first active region Act1 in the first direction G;

[0212] The first active region Act1 includes a first sub-active region Act_sub1 and a second sub-active region Act_sub2 sequentially arranged along the first direction G; the ninth transistor M9 and the eleventh transistor M11 are located in the first sub-active region Act_sub1, and the tenth transistor M10 and the twelfth transistor M12 are located in the second sub-active region Act_sub2;

[0213] The second active region Act2 includes a third sub-active region Act_sub3 and a fourth sub-active region Act_sub4 arranged in sequence along the second direction H; the second direction H is perpendicular to the first direction G and parallel to the plane where the semiconductor substrate 310 is located; the fifth transistor M5 and the sixth transistor M6 are located in the third sub-active region Act_sub3, and the third transistor M3 and the fourth transistor M4 are located in the fourth sub-active region Act_sub4.

[0214] In this way, the arrangement of the transistors can improve the compactness of the transistor arrangement, reduce the area occupied by the row drive signal enhancement circuit 101, reduce the length of the connecting wires, and reduce the power consumption of the row drive signal enhancement circuit 101. In addition, the N-type auxiliary doping region F_Ndummy can reduce the leakage of each transistor, further reducing the power consumption of the row drive signal enhancement circuit 101.

[0215] In one embodiment of the present disclosure, see Figure 5 The N-type auxiliary doping region F_Ndummy may include a first N-type doping sub-region F_Nsub1 to a seventh N-type doping sub-region F_Nsub7. The first N-type doping sub-region F_Nsub1, the third N-type doping sub-region F_Nsub3, the fifth N-type doping sub-region F_Nsub5 and the seventh N-type doping sub-region F_Nsub7 extend along the first direction G, and the second N-type doping sub-region F_Nsub2, the fourth N-type doping sub-region F_Nsub4 and the sixth N-type doping sub-region F_Nsub6 extend along the second direction H. The first N-type doping sub-region F_Nsub1, the second N-type doping sub-region F_Nsub2, the third N-type doping sub-region F_Nsub3 and the fourth N-type doping sub-region F_Nsub4 are connected in sequence to form a closed ring, and the first active region Act1 is located in the space surrounded by the first N-type doping sub-region F_Nsub1, the second N-type doping sub-region F_Nsub2, the third N-type doping sub-region F_Nsub3 and the fourth N-type doping sub-region F_Nsub4; the fourth N-type doping sub-region F_Nsub4, the fifth N-type doping sub-region F_Nsub5, the sixth N-type doping sub-region F_Nsub6 and the seventh N-type doping sub-region F_Nsub7 are connected in sequence to form a closed ring, and the second active region Act2 is located in the space surrounded by the fourth N-type doping sub-region F_Nsub4, the fifth N-type doping sub-region F_Nsub5, the sixth N-type doping sub-region F_Nsub6 and the seventh N-type doping sub-region F_Nsub7. The fifth N-type doping sub-region F_Nsub5 is located at one side of the first direction G of the first N-type doping sub-region F_Nsub1, and is located on the extension line of the first N-type doping sub-region F_Nsub1 along the first direction G. The seventh N-type doping sub-region F_Nsub7 is located at one side of the first direction G of the third N-type doping sub-region F_Nsub3, and is located on the extension line of the third N-type doping sub-region F_Nsub3 along the first direction G. The second N-type doping sub-region F_Nsub2, the fourth N-type doping sub-region F_Nsub4 and the sixth N-type doping sub-region F_Nsub6 are arranged in sequence along the first direction G.

[0216] Alternatively, see Figure 5, the size of the fifth N-type doping sub-region F_Nsub5 in the second direction H is smaller than the size of the first N-type doping sub-region F_Nsub1 in the second direction H, and the size of the seventh N-type doping sub-region F_Nsub7 in the second direction H is smaller than the size of the third N-type doping sub-region F_Nsub3 in the second direction H. In this way, the size of the second active region Act2 in the second direction H can be increased, thereby facilitating the arrangement of the third sub-active region Act_sub3 and the fourth sub-active region Act_sub4 arranged along the second direction H in the second active region Act2.

[0217] Optionally, the size of the first sub-active region Act_sub1 in the first direction G is the same as the size of the second sub-active region Act_sub2 in the first direction G; the size of the first sub-active region Act_sub1 in the second direction H is the same as the size of the second sub-active region Act_sub2 in the second direction H. In this way, the sizes of the ninth transistor M9 and the tenth transistor M10 are made the same, and the sizes of the eleventh transistor M11 and the twelfth transistor M12 are made the same.

[0218] Optionally, the size of the third sub-active region Act_sub3 in the first direction G is the same as the size of the fourth sub-active region Act_sub4 in the first direction G; the size of the third sub-active region Act_sub3 in the second direction H is the same as the size of the fourth sub-active region Act_sub4 in the second direction H. In this way, the sizes of the third transistor M3 to the sixth transistor M6 are made the same.

[0219] In one embodiment of the present disclosure, along the first direction G, the size of the first sub-active region Act_sub1 is 3 to 5 times the size of the third sub-active region Act_sub3, and the size of the second sub-active region Act_sub2 is 3 to 5 times the size of the third sub-active region Act_sub3. In this way, the channel region of the ninth transistor M9 to the twelfth transistor M12 can have a larger width, thereby improving the current output capability of the ninth transistor M9 to the twelfth transistor M12, thereby improving the driving capability of the row drive signal enhancement circuit 101. Accordingly, the third transistor M3 to the sixth transistor M6 can have a smaller size, especially a smaller channel region, which can improve the conduction speed or cut-off speed of the third transistor M3 to the sixth transistor M6, reduce the signal delay caused by the third transistor M3 to the sixth transistor M6, and thereby reduce the signal delay of the row drive signal enhancement circuit 101.

[0220] In some embodiments, see Figure 5, the P-type substrate region F_Pdop includes a P-type auxiliary doping region F_Pdummy, a third active region Act3 and a fourth active region Act4; the fourth active region Act4 is located on the first direction G side of the third active region Act3. The third active region Act3 is surrounded by the P-type auxiliary doping region F_Pdummy, and includes a fifth sub-active region Act_sub5 and a sixth sub-active region Act_sub6 arranged in sequence along the first direction G; the seventh transistor M7 and the thirteenth transistor M13 are located in the fifth sub-active region Act_sub5, and the eighth transistor M8 and the fourteenth transistor M14 are located in the sixth sub-active region Act_sub6. The fourth active region Act4 includes a seventh sub-active region Act_sub7 and an eighth sub-active region Act_sub8 arranged in sequence along the second direction H and respectively surrounded by the P-type auxiliary doping region F_Pdummy; the first transistor M1 is located in the seventh sub-active region Act_sub7, and the second transistor M2 is located in the eighth sub-active region Act_sub8.

[0221] In this way, the arrangement of the transistors can improve the compactness of the transistor arrangement, reduce the area occupied by the row drive signal enhancement circuit 101, reduce the length of the connecting wires, and reduce the power consumption of the row drive signal enhancement circuit 101. In addition, the P-type auxiliary doping region F_Pdummy can reduce the leakage of each transistor, further reducing the power consumption of the row drive signal enhancement circuit 101.

[0222] In one embodiment of the present disclosure, the P-type auxiliary doping region F_Pdummy may include a first P-type doping sub-region F_Psub1 to an eighth P-type doping sub-region F_Psub8. The first P-type doping sub-region F_Psub1, the third P-type doping sub-region F_Psub3, the fifth P-type doping sub-region F_Psub5, the seventh P-type doping sub-region F_Psub7 and the eighth P-type doping sub-region F_Psub8 extend along the first direction G, and the second P-type doping sub-region F_Psub2, the fourth P-type doping sub-region F_Psub4 and the sixth P-type doping sub-region F_Psub6 extend along the second direction H. See Figure 5The first P-type doped sub-region F_Psub1, the second P-type doped sub-region F_Psub2, the third P-type doped sub-region F_Psub3 and the fourth P-type doped sub-region F_Psub4 are connected in sequence to form a closed ring, and the third active region Act3 is located in the space surrounded by the first P-type doped sub-region F_Psub1, the second P-type doped sub-region F_Psub2, the third P-type doped sub-region F_Psub3 and the fourth P-type doped sub-region F_Psub4; the fifth P-type doped sub-region F_Psub5, the sixth P-type doped sub-region F_Psub6, the seventh P-type doped sub-region F_Psub7 and the fourth P-type doped sub-region F_Psub4 are connected in sequence to form a closed ring, and the fourth active region Act4 is located in the space surrounded by the fifth P-type doped sub-region F_Psub5, the sixth P-type doped sub-region F_Psub6, the seventh P-type doped sub-region F_Psub7 and the fourth P-type doped sub-region F_Psub4. The two ends of the eighth P-type doped sub-region F_Psub8 are respectively connected to the fourth P-type doped sub-region F_Psub4 and the sixth P-type doped sub-region F_Psub6, wherein the seventh sub-active region Act_sub7 is located in the space surrounded by the fifth P-type doped sub-region F_Psub5, the sixth P-type doped sub-region F_Psub6, the eighth P-type doped sub-region F_Psub8 and the fourth P-type doped sub-region F_Psub4, and the eighth sub-active region Act_sub8 is located in the space surrounded by the eighth P-type doped sub-region F_Psub8, the sixth P-type doped sub-region F_Psub6, the seventh P-type doped sub-region F_Psub7 and the fourth P-type doped sub-region F_Psub4.

[0223] The fifth P-type doping sub-region F_Psub5 is located on one side of the first direction G of the first P-type doping sub-region F_Psub1, and is located on the extension line of the first P-type doping sub-region F_Psub1 along the first direction G. The seventh P-type doping sub-region F_Psub7 is located on one side of the first direction G of the third P-type doping sub-region F_Psub3, and is located on the extension line of the third P-type doping sub-region F_Psub3 along the first direction G. The second P-type doping sub-region F_Psub2, the fourth P-type doping sub-region F_Psub4 and the sixth P-type doping sub-region F_Psub6 are arranged in sequence along the first direction G, and the fifth P-type doping sub-region F_Psub5, the eighth P-type doping sub-region F_Psub8 and the seventh P-type doping sub-region F_Psub7 are arranged in sequence along the second direction H.

[0224] Alternatively, see Figure 5, the size of the fifth P-type doping sub-region F_Psub5 in the second direction H is smaller than the size of the first P-type doping sub-region F_Psub1 in the second direction H, and the size of the seventh P-type doping sub-region F_Psub7 in the second direction H is smaller than the size of the third P-type doping sub-region F_Psub3 in the second direction H. In this way, the size of the fourth active region Act4 in the second direction H can be increased, providing more space for setting the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8, and also providing space for setting the eighth P-type doping sub-region F_Psub8.

[0225] Optionally, the size of the fifth sub-active region Act_sub5 in the first direction G is the same as the size of the sixth sub-active region Act_sub6 in the first direction G; the size of the sixth sub-active region Act_sub6 in the second direction H is the same as the size of the fifth sub-active region Act_sub5 in the second direction H. This facilitates making the sizes of the seventh transistor M7 and the eighth transistor M8 the same, and facilitates making the sizes of the thirteenth transistor M13 and the fourteenth transistor M14 the same.

[0226] Optionally, the size of the seventh sub-active region Act_sub7 in the first direction G is the same as the size of the eighth sub-active region Act_sub8 in the first direction G; the size of the seventh sub-active region Act_sub7 in the second direction H is the same as the size of the eighth sub-active region Act_sub8 in the second direction H. This facilitates making the sizes of the first transistor M1 and the second transistor M2 the same.

[0227] In one embodiment of the present disclosure, along the first direction G, the size of the seventh sub-active region Act_sub7 is 1.5 to 2.5 times the size of the fifth sub-active region Act_sub5; the size of the seventh sub-active region Act_sub7 is the same as the size of the eighth sub-active region Act_sub8; the size of the fifth sub-active region Act_sub5 is the same as the size of the sixth sub-active region Act_sub6.

[0228] See also Figure 6 , Fig.11 and Fig.23 The gate layer 330 is formed with gates of the first transistor M1 to the fourteenth transistor M14, and the gate insulating layer 320 isolates the gate and the channel region of any transistor. Optionally, the gates of each transistor extend along the first direction G.

[0229] In one embodiment of the present disclosure, when forming each transistor, a CMOS process may be used for preparation. Exemplarily, each transistor of the row drive signal enhancement circuit 101 may be formed in the row drive signal enhancement region F by the following method.

[0230] See also Figure 5 and Fig.23 A P-type semiconductor substrate 310 may be provided first, and the P-type semiconductor substrate 310 has a first region and a second region in the row drive signal enhancement region F. The first region may be used as a P-type substrate region F_Pdop, which has a P well. N-type ions may be implanted in the second region so that the second region forms an N well, which is used as the N-type substrate region F_Ndop.

[0231] Then, see Figure 6 and Fig.23 , a gate insulating layer 320 (not shown in the figure) and a gate layer 330 can be formed, so that the gate insulating layer 320 and the gate layer 330 cover the channel region of each transistor and expose the source and drain of each transistor. The material of the gate insulating layer 320 can be an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the gate layer 330 can be polysilicon.

[0232] See also Figure 7 , Figure 8 and Fig.11 In the middle line filling part, N-type ion implantation can be performed on each active area of ​​the P-type substrate area F_Pdop and the N-type auxiliary doping area F_Ndummy of the N-type substrate area F_Ndop. In this way, the source and drain of each transistor in the P-type substrate area F_Pdop are transformed into N-type doping, and then each N-type transistor is formed in the P-type substrate area F_Pdop; the doping concentration of the N-type auxiliary doping area F_Ndummy is increased, which has a better anti-leakage effect.

[0233] See also Fig. 9 , Fig.10 and Fig.11 In the midpoint filling part, P-type ion implantation can be performed on each active area of ​​the N-type substrate area F_Ndop and the P-type auxiliary doping area F_Pdummy of the P-type substrate area F_Pdop. In this way, the source and drain of each transistor located in the N-type substrate area F_Ndop are transformed into P-type doping, and then each P-type transistor is formed in the N-type substrate area F_Ndop; the doping concentration of the P-type auxiliary doping area F_Pdummy is increased, which has a better anti-leakage effect.

[0234] According to the above preparation method, the portion of each active region overlapping with the gate can be used as the channel region of each transistor. During the process of N-type ion implantation or P-type ion implantation, the gate can block the ion implantation into the active region, thereby maintaining its semiconductor properties.

[0235] In one embodiment of the present disclosure, see Fig.11, the gate M1G of the first transistor M1 includes a first gate M1G1 and a second gate M1G2, the first gate M1G1 of the first transistor M1 and the second gate M1G2 of the first transistor M1 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion of the seventh sub-active region Act_sub7 that overlaps with the first gate M1G1 of the first transistor M1 and the second gate M1G2 of the first transistor M1 serves as the channel region of the first transistor M1. In other words, the channel region of the first transistor M1 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the first transistor M1 overlaps with the first gate M1G1 of the first transistor M1, and the second channel region of the first transistor M1 overlaps with the second gate M1G2 of the first transistor M1. The drain M1D of the first transistor M1 is located between the first channel region of the first transistor M1 and the second channel region of the first transistor M1, and the source M1S of the first transistor M1 is located on the side of the first channel region of the first transistor M1 away from the second channel region of the first transistor M1 and on the side of the second channel region of the first transistor M1 away from the first channel region of the first transistor M1. In other words, the source M1S of the first transistor M1 includes a first source M1S1 and a second source M1S2 arranged in parallel with each other, the first source M1S1 of the first transistor M1 is located on the side of the first channel region of the first transistor M1 away from the second channel region of the first transistor M1, and the second source M1S2 of the first transistor M1 is located on the side of the second channel region of the first transistor M1 away from the first channel region of the first transistor M1. In this way, the first source M1S1 of the first transistor M1, the first channel region of the first transistor M1, the drain M1D of the first transistor M1, the second channel region of the first transistor M1, and the second source M1S2 of the first transistor M1 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0236] In one embodiment of the present disclosure, see Fig.11, the gate M2G of the second transistor M2 includes a first gate M2G1 and a second gate M2G2, the second gate M2G2 of the second transistor M2 and the first gate M2G1 of the second transistor M2 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the eighth sub-active region Act_sub8 overlaps with the first gate M2G1 of the second transistor M2 and the second gate M2G2 of the second transistor M2 serves as the channel region of the second transistor M2. In other words, the channel region of the second transistor M2 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the second transistor M2 overlaps with the first gate M2G1 of the second transistor M2, and the second channel region of the second transistor M2 overlaps with the second gate M2G2 of the second transistor M2. The drain M2D of the second transistor M2 is located between the first channel region of the second transistor M2 and the second channel region of the second transistor M2, and the source M2S of the second transistor M2 is located on the side of the first channel region of the second transistor M2 away from the second channel region of the second transistor M2 and on the side of the second channel region of the second transistor M2 away from the first channel region of the second transistor M2. In other words, the source M2S of the second transistor M2 includes a first source M2S1 and a second source M2S2 arranged in parallel with each other, the first source M2S1 of the second transistor M2 is located on the side of the first channel region of the second transistor M2 away from the second channel region of the second transistor M2, and the second source M2S2 of the second transistor M2 is located on the side of the second channel region of the second transistor M2 away from the first channel region of the second transistor M2. In this way, the second source M2S2 of the second transistor M2, the second channel region of the second transistor M2, the drain M2D of the second transistor M2, the first channel region of the second transistor M2, and the first source M2S1 of the second transistor M2 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0237] In one embodiment of the present disclosure, the first source M1S1 of the first transistor M1, the first gate M1G1 of the first transistor M1, the drain M1D of the first transistor M1, the second gate M1G2 of the first transistor M1, the second source M1S2 of the first transistor M1, the second source M2S2 of the second transistor M2, the second gate M2G2 of the second transistor M2, the drain M2D of the second transistor M2, the first gate M2G1 of the second transistor M2, and the first source M2S1 of the second transistor M2 are sequentially arranged along the second direction H. In this way, the second transistor M2 is located on the second direction H side of the first transistor M1.

[0238] In one embodiment of the present disclosure, see Fig.11, the gate M5G of the fifth transistor M5, the gate M6G of the sixth transistor M6, the gate M3G of the third transistor M3, and the gate M4G of the fourth transistor M4 extend along the first direction G, and are sequentially arranged along the second direction H, wherein the gate M5G of the fifth transistor M5 and the gate M6G of the sixth transistor M6 overlap with the third sub-active region Act_sub3, and the gate M3G of the third transistor M3 and the gate M4G of the fourth transistor M4 overlap with the fourth sub-active region Act_sub4. In this way, the fifth transistor M5, the sixth transistor M6, the third transistor M3, and the fourth transistor M4 are sequentially arranged along the second direction H.

[0239] The portion where the fourth sub-active region Act_sub4 overlaps with the gate M3G of the third transistor M3 serves as the channel region of the third transistor M3. The source M3S of the third transistor M3 is located on the opposite side of the second direction H of the channel region of the third transistor M3, and the drain M3D of the third transistor M3 is located on the second direction H side of the channel region of the third transistor M3. In other words, the source M3S of the third transistor M3, the channel region of the third transistor M3, and the drain M3D of the third transistor M3 all extend along the first direction G and are arranged in sequence along the second direction H.

[0240] The portion where the fourth sub-active region Act_sub4 overlaps with the gate M4G of the fourth transistor M4 serves as the channel region of the fourth transistor M4. The source M4S of the fourth transistor M4 is located on the second direction H side of the channel region of the third transistor M4, and the drain M4D of the fourth transistor M4 is located on the opposite direction side of the second direction H of the channel region of the fourth transistor M4. In other words, the drain M4D of the fourth transistor M4, the channel region of the fourth transistor M4, and the source M4S of the fourth transistor M4 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0241] The portion where the third sub-active region Act_sub3 overlaps with the gate M5G of the fifth transistor M5 serves as the channel region of the fifth transistor M5. The source M5S of the fifth transistor M5 is located on the opposite side of the second direction H of the channel region of the fifth transistor M5, and the drain M5D of the fifth transistor M5 is located on the second direction H side of the channel region of the fifth transistor M5. In other words, the source M5S of the fifth transistor M5, the channel region of the fifth transistor M5, and the drain M5D of the fifth transistor M5 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0242] The portion where the third sub-active region Act_sub3 overlaps with the gate M6G of the sixth transistor M6 serves as the channel region of the sixth transistor M6. The source M6S of the sixth transistor M6 is located on one side of the second direction H of the channel region of the sixth transistor M6, and the drain M6D of the sixth transistor M6 is located on one side of the channel region of the sixth transistor M6 in the opposite direction of the second direction H. In other words, the drain M6D of the sixth transistor M6, the channel region of the sixth transistor M6, and the source M6S of the sixth transistor M6 all extend along the first direction G and are arranged in sequence along the second direction H.

[0243] Optionally, the drain M3D of the third transistor M3 and the drain M4D of the fourth transistor M4 overlap. In this way, the third transistor M3 and the fourth transistor M4 can share a drain, thereby simplifying the wiring arrangement of the row drive signal enhancement circuit 101, improving the compactness of the row drive signal enhancement circuit 101, and reducing the area occupied by the row drive signal enhancement circuit 101.

[0244] Optionally, the drain M5D of the fifth transistor M5 and the drain M6D of the sixth transistor M6 overlap. In this way, the fifth transistor M5 and the sixth transistor M6 can share a drain, thereby simplifying the wiring arrangement of the row drive signal enhancement circuit 101, improving the compactness of the row drive signal enhancement circuit 101, and reducing the area occupied by the row drive signal enhancement circuit 101.

[0245] In one embodiment of the present disclosure, see Fig.11, the gate M7G of the seventh transistor M7 includes a first gate M7G1 and a second gate M7G2, the first gate M7G1 of the seventh transistor M7 and the second gate M7G2 of the seventh transistor M7 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the fifth sub-active region Act_sub5 overlaps with the first gate M7G1 of the seventh transistor M7 and the second gate M7G2 of the seventh transistor M7 serves as the channel region of the seventh transistor M7. In other words, the channel region of the seventh transistor M7 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the seventh transistor M7 overlaps with the first gate M7G1 of the seventh transistor M7, and the second channel region of the seventh transistor M7 overlaps with the second gate M7G2 of the seventh transistor M7. The drain M7D of the seventh transistor M7 is located between the first channel region of the seventh transistor M7 and the second channel region of the seventh transistor M7, and the source M7S of the seventh transistor is located on the side of the first channel region of the seventh transistor M7 away from the second channel region of the seventh transistor M7 and on the side of the second channel region of the seventh transistor M7 away from the first channel region of the seventh transistor M7. In other words, the source M7S of the seventh transistor includes a first source M7S1 and a second source M7S2 arranged in parallel with each other, the first source M7S1 of the seventh transistor M7 is located on the side of the first channel region of the seventh transistor M7 away from the second channel region of the seventh transistor M7, and the second source M7S2 of the seventh transistor M7 is located on the side of the second channel region of the seventh transistor M7 away from the first channel region of the seventh transistor M7. In this way, the first source M7S1 of the seventh transistor M7, the first channel region of the seventh transistor M7, the drain M7D of the seventh transistor M7, the second channel region of the seventh transistor M7, and the second source M7S2 of the seventh transistor M7 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0246] In one embodiment of the present disclosure, see Fig.11, the gate M8G of the eighth transistor M8 includes a first gate M8G1 and a second gate M8G2, the first gate M8G1 of the eighth transistor M8 and the second gate M8G2 of the eighth transistor M8 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the sixth sub-active region Act_sub6 overlaps with the first gate M8G1 of the eighth transistor M8 and the second gate M8G2 of the eighth transistor M8 serves as the channel region of the eighth transistor M8. In other words, the channel region of the eighth transistor M8 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the eighth transistor M8 overlaps with the first gate M8G1 of the eighth transistor M8, and the second channel region of the eighth transistor M8 overlaps with the second gate M8G2 of the eighth transistor M8. The drain M8D of the eighth transistor M8 is located between the first channel region of the eighth transistor M8 and the second channel region of the eighth transistor M8, and the source M8S of the eighth transistor is located on the side of the first channel region of the eighth transistor M8 away from the second channel region of the eighth transistor M8 and on the side of the second channel region of the eighth transistor M8 away from the first channel region of the eighth transistor M8. In other words, the source M8S of the eighth transistor includes a first source M8S1 and a second source M8S2 arranged in parallel with each other, the first source M8S1 of the eighth transistor M8 is located on the side of the first channel region of the eighth transistor M8 away from the second channel region of the eighth transistor M8, and the second source M8S2 of the eighth transistor M8 is located on the side of the second channel region of the eighth transistor M8 away from the first channel region of the eighth transistor M8. In this way, the first source M8S1 of the eighth transistor M8, the first channel region of the eighth transistor M8, the drain M8D of the eighth transistor M8, the second channel region of the eighth transistor M8, and the second source M8S2 of the eighth transistor M8 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0247] In one embodiment of the present disclosure, the first source M8S1 of the eighth transistor M8 and the first source M7S1 of the seventh transistor M7 overlap in the first direction G, that is, the first source M8S1 of the eighth transistor M8 and the first source M7S1 of the seventh transistor M7 are arranged in a straight line along the first direction G. The second source M8S2 of the eighth transistor M8 and the second source M7S2 of the seventh transistor M7 overlap in the first direction G, that is, the second source M8S2 of the eighth transistor M8 and the second source M7S2 of the seventh transistor M7 are arranged in a straight line along the first direction G. The first gate M8G1 of the eighth transistor M8 and the first gate M7G1 of the seventh transistor M7 overlap in the first direction G, that is, the first gate M8G1 of the eighth transistor M8 and the first gate M7G1 of the seventh transistor M7 are arranged in a straight line along the first direction G. The second gate M8G2 of the eighth transistor M8 and the second gate M7G2 of the seventh transistor M7 overlap in the first direction G, that is, the second gate M8G2 of the eighth transistor M8 and the second gate M7G2 of the seventh transistor M7 are arranged in a straight line along the first direction G. The drain M8D of the eighth transistor M8 and the drain M7D of the seventh transistor M7 overlap in the first direction G, that is, the drain M8D of the eighth transistor M8 and the drain M7D of the seventh transistor M7 are arranged in a straight line along the first direction G. The first channel region of the eighth transistor M8 and the first channel region of the seventh transistor M7 overlap in the first direction G, that is, the first channel region of the eighth transistor M8 and the first channel region of the seventh transistor M7 are arranged in a straight line along the first direction G. The second channel region of the eighth transistor M8 and the second channel region of the seventh transistor M7 overlap in the first direction G, that is, the second channel region of the eighth transistor M8 and the second channel region of the seventh transistor M7 are arranged in a straight line along the first direction G. In this way, the eighth transistor M8 is located on the first direction G side of the seventh transistor M7.

[0248] In one embodiment of the present disclosure, see Fig.11, the gate M13G of the thirteenth transistor M13 includes a first gate M13G1 and a second gate M13G2, the second gate M13G2 of the thirteenth transistor M13 and the first gate M13G1 of the thirteenth transistor M13 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the fifth sub-active region Act_sub5 overlaps with the first gate M13G1 of the thirteenth transistor M13 and the second gate M13G2 of the thirteenth transistor M13 serves as the channel region of the thirteenth transistor M13. In other words, the channel region of the thirteenth transistor M13 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the thirteenth transistor M13 overlaps with the first gate M13G1 of the thirteenth transistor M13, and the second channel region of the thirteenth transistor M13 overlaps with the second gate M13G2 of the thirteenth transistor M13. The drain M13D of the thirteenth transistor M13 is located between the first channel region of the thirteenth transistor M13 and the second channel region of the thirteenth transistor M13, and the source M13S of the thirteenth transistor is located on a side of the first channel region of the thirteenth transistor M13 away from the second channel region of the thirteenth transistor M13 and on a side of the second channel region of the thirteenth transistor M13 away from the first channel region of the thirteenth transistor M13. In other words, the source M13S of the thirteenth transistor includes a first source M13S1 and a second source M13S2 arranged in parallel with each other, the first source M13S1 of the thirteenth transistor M13 is located on a side of the first channel region of the thirteenth transistor M13 away from the second channel region of the thirteenth transistor M13, and the second source M13S2 of the thirteenth transistor M13 is located on a side of the second channel region of the thirteenth transistor M13 away from the first channel region of the thirteenth transistor M13. Thus, the second source M13S2 of the thirteenth transistor M13, the second channel region of the thirteenth transistor M13, the drain M13D of the thirteenth transistor M13, the first channel region of the thirteenth transistor M13 and the first source M13S1 of the thirteenth transistor M13 all extend along the first direction G and are sequentially arranged along the second direction H.

[0249] In one embodiment of the present disclosure, see Fig.11, the gate M14G of the fourteenth transistor M14 includes a first gate M14G1 and a second gate M14G2, the second gate M14G2 of the fourteenth transistor M14 and the first gate M14G1 of the fourteenth transistor M14 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the sixth sub-active region Act_sub6 overlaps with the first gate M14G1 of the fourteenth transistor M14 and the second gate M14G2 of the fourteenth transistor M14 serves as the channel region of the fourteenth transistor M14. In other words, the channel region of the fourteenth transistor M14 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the fourteenth transistor M14 overlaps with the first gate M14G1 of the fourteenth transistor M14, and the second channel region of the fourteenth transistor M14 overlaps with the second gate M14G2 of the fourteenth transistor M14. The drain M14D of the fourteenth transistor M14 is located between the first channel region of the fourteenth transistor M14 and the second channel region of the fourteenth transistor M14, and the source M14S of the fourteenth transistor is located on a side of the first channel region of the fourteenth transistor M14 away from the second channel region of the fourteenth transistor M14 and on a side of the second channel region of the fourteenth transistor M14 away from the first channel region of the fourteenth transistor M14. In other words, the source M14S of the fourteenth transistor includes a first source M14S1 and a second source M14S2 arranged in parallel with each other, the first source M14S1 of the fourteenth transistor M14 is located on a side of the first channel region of the fourteenth transistor M14 away from the second channel region of the fourteenth transistor M14, and the second source M14S2 of the fourteenth transistor M14 is located on a side of the second channel region of the fourteenth transistor M14 away from the first channel region of the fourteenth transistor M14. Thus, the second source M14S2 of the fourteenth transistor M14, the second channel region of the fourteenth transistor M14, the drain M14D of the fourteenth transistor M14, the first channel region of the fourteenth transistor M14 and the first source M14S1 of the fourteenth transistor M14 all extend along the first direction G and are sequentially arranged along the second direction H.

[0250] In one embodiment of the present disclosure, the first source M14S1 of the fourteenth transistor M14 and the first source M13S1 of the thirteenth transistor M13 overlap in the first direction G, that is, the first source M14S1 of the fourteenth transistor M14 and the first source M13S1 of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The second source M14S2 of the fourteenth transistor M14 and the second source M13S2 of the thirteenth transistor M13 overlap in the first direction G, that is, the second source M14S2 of the fourteenth transistor M14 and the second source M13S2 of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The first gate M14G1 of the fourteenth transistor M14 and the first gate M13G1 of the thirteenth transistor M13 overlap in the first direction G, that is, the first gate M14G1 of the fourteenth transistor M14 and the first gate M13G1 of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The second gate M14G2 of the fourteenth transistor M14 and the second gate M13G2 of the thirteenth transistor M13 overlap in the first direction G, that is, the second gate M14G2 of the fourteenth transistor M14 and the second gate M13G2 of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The drain M14D of the fourteenth transistor M14 and the drain M13D of the thirteenth transistor M13 overlap in the first direction G, that is, the drain M14D of the fourteenth transistor M14 and the drain M13D of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The first channel region of the fourteenth transistor M14 and the first channel region of the thirteenth transistor M13 overlap in the first direction G, that is, the first channel region of the fourteenth transistor M14 and the first channel region of the thirteenth transistor M13 are arranged in a straight line along the first direction G. The second channel region of the fourteenth transistor M14 and the second channel region of the thirteenth transistor M13 overlap in the first direction G, that is, the second channel region of the fourteenth transistor M14 and the second channel region of the thirteenth transistor M13 are arranged in a straight line along the first direction G. In this way, the fourteenth transistor M14 is located on the first direction G side of the thirteenth transistor M13.

[0251] In one embodiment of the present disclosure, the first source M7S1 of the seventh transistor M7, the first gate M7G1 of the seventh transistor M7, the drain M7D of the seventh transistor M7, the second gate M7G2 of the seventh transistor M7, the second source M7S2 of the seventh transistor M7, the second source M13S2 of the thirteenth transistor M13, the second gate M13G2 of the thirteenth transistor M13, the drain M13D of the thirteenth transistor M13, the first gate M13G1 of the thirteenth transistor M13, and the first source M13S1 of the thirteenth transistor M13 are sequentially arranged along the second direction H. In this way, the thirteenth transistor M13 is located on one side of the seventh transistor M7 in the second direction H. Further, the second source M7S2 of the seventh transistor M7 and the second source M13S2 of the thirteenth transistor M13 overlap. In this way, the seventh transistor M7 and the thirteenth transistor M13 can share a source, thereby simplifying the wiring arrangement of the row driving signal enhancement circuit 101, improving the compactness of the row driving signal enhancement circuit 101, and reducing the area occupied by the row driving signal enhancement circuit 101.

[0252] In one embodiment of the present disclosure, the first source M8S1 of the eighth transistor M8, the first gate M8G1 of the eighth transistor M8, the drain M8D of the eighth transistor M8, the second gate M8G2 of the eighth transistor M8, the second source M8S2 of the eighth transistor M8, the second source M14S2 of the fourteenth transistor M14, the second gate M14G2 of the fourteenth transistor M14, the drain M14D of the fourteenth transistor M14, the first gate M14G1 of the fourteenth transistor M14, and the first source M14S1 of the fourteenth transistor M14 are sequentially arranged along the second direction H. In this way, the fourteenth transistor M14 is located on one side of the eighth transistor M8 in the second direction H. Further, the second source M8S2 of the eighth transistor M8 and the second source M14S2 of the fourteenth transistor M14 overlap. In this way, the eighth transistor M8 and the fourteenth transistor M14 can share a source, thereby simplifying the wiring arrangement of the row driving signal enhancement circuit 101, improving the compactness of the row driving signal enhancement circuit 101, and reducing the area occupied by the row driving signal enhancement circuit 101.

[0253] In one embodiment of the present disclosure, see Fig.11, the gate M9G of the ninth transistor M9 includes a first gate M9G1 and a second gate M9G2, the first gate M9G1 of the ninth transistor M9 and the second gate M9G2 of the ninth transistor M9 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the first sub-active region Act_sub1 overlaps with the first gate M9G1 of the ninth transistor M9 and the second gate M9G2 of the ninth transistor M9 serves as the channel region of the ninth transistor M9. In other words, the channel region of the ninth transistor M9 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the ninth transistor M9 overlaps with the first gate M9G1 of the ninth transistor M9, and the second channel region of the ninth transistor M9 overlaps with the second gate M9G2 of the ninth transistor M9. The drain M9D of the ninth transistor M9 is located between the first channel region of the ninth transistor M9 and the second channel region of the ninth transistor M9, and the source M9S of the ninth transistor is located on the side of the first channel region of the ninth transistor M9 away from the second channel region of the ninth transistor M9 and on the side of the second channel region of the ninth transistor M9 away from the first channel region of the ninth transistor M9. In other words, the source M9S of the ninth transistor includes a first source M9S1 and a second source M9S2 arranged in parallel with each other, the first source M9S1 of the ninth transistor M9 is located on the side of the first channel region of the ninth transistor M9 away from the second channel region of the ninth transistor M9, and the second source M9S2 of the ninth transistor M9 is located on the side of the second channel region of the ninth transistor M9 away from the first channel region of the ninth transistor M9. In this way, the first source M9S1 of the ninth transistor M9, the first channel region of the ninth transistor M9, the drain M9D of the ninth transistor M9, the second channel region of the ninth transistor M9, and the second source M9S2 of the ninth transistor M9 all extend along the first direction G, and are arranged in sequence along the second direction H.

[0254] In one embodiment of the present disclosure, see Fig.11, the gate M10G of the tenth transistor M10 includes a first gate M10G1 and a second gate M10G2, the first gate M10G1 of the tenth transistor M10 and the second gate M10G2 of the tenth transistor M10 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the second sub-active region Act_sub2 overlaps with the first gate M10G1 of the tenth transistor M10 and the second gate M10G2 of the tenth transistor M10 serves as the channel region of the tenth transistor M10. In other words, the channel region of the tenth transistor M10 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the tenth transistor M10 overlaps with the first gate M10G1 of the tenth transistor M10, and the second channel region of the tenth transistor M10 overlaps with the second gate M10G2 of the tenth transistor M10. The drain M10D of the tenth transistor M10 is located between the first channel region of the tenth transistor M10 and the second channel region of the tenth transistor M10, and the source M10S of the tenth transistor is located on a side of the first channel region of the tenth transistor M10 away from the second channel region of the tenth transistor M10 and on a side of the second channel region of the tenth transistor M10 away from the first channel region of the tenth transistor M10. In other words, the source M10S of the tenth transistor includes a first source M10S1 and a second source M10S2 arranged in parallel with each other, the first source M10S1 of the tenth transistor M10 is located on a side of the first channel region of the tenth transistor M10 away from the second channel region of the tenth transistor M10, and the second source M10S2 of the tenth transistor M10 is located on a side of the second channel region of the tenth transistor M10 away from the first channel region of the tenth transistor M10. Thus, the first source M10S1 of the tenth transistor M10, the first channel region of the tenth transistor M10, the drain M10D of the tenth transistor M10, the second channel region of the tenth transistor M10 and the second source M10S2 of the tenth transistor M10 all extend along the first direction G and are sequentially arranged along the second direction H.

[0255] In one embodiment of the present disclosure, the first source M10S1 of the tenth transistor M10 and the first source M9S1 of the ninth transistor M9 overlap in the first direction G, that is, the first source M10S1 of the tenth transistor M10 and the first source M9S1 of the ninth transistor M9 are arranged in a straight line along the first direction G. The second source M10S2 of the tenth transistor M10 and the second source M9S2 of the ninth transistor M9 overlap in the first direction G, that is, the second source M10S2 of the tenth transistor M10 and the second source M9S2 of the ninth transistor M9 are arranged in a straight line along the first direction G. The first gate M10G1 of the tenth transistor M10 and the first gate M9G1 of the ninth transistor M9 overlap in the first direction G, that is, the first gate M10G1 of the tenth transistor M10 and the first gate M9G1 of the ninth transistor M9 are arranged in a straight line along the first direction G. The second gate M10G2 of the tenth transistor M10 and the second gate M9G2 of the ninth transistor M9 overlap in the first direction G, that is, the second gate M10G2 of the tenth transistor M10 and the second gate M9G2 of the ninth transistor M9 are arranged in a straight line along the first direction G. The drain M10D of the tenth transistor M10 and the drain M9D of the ninth transistor M9 overlap in the first direction G, that is, the drain M10D of the tenth transistor M10 and the drain M9D of the ninth transistor M9 are arranged in a straight line along the first direction G. The first channel region of the tenth transistor M10 and the first channel region of the ninth transistor M9 overlap in the first direction G, that is, the first channel region of the tenth transistor M10 and the first channel region of the ninth transistor M9 are arranged in a straight line along the first direction G. The second channel region of the tenth transistor M10 and the second channel region of the ninth transistor M9 overlap in the first direction G, that is, the second channel region of the tenth transistor M10 and the second channel region of the ninth transistor M9 are arranged in a straight line along the first direction G. Thus, the tenth transistor M10 is located at one side of the first direction G of the ninth transistor M9.

[0256] In one embodiment of the present disclosure, see Fig.11, the gate M11G of the eleventh transistor M11 includes a first gate M11G1 and a second gate M11G2, the second gate M11G2 of the eleventh transistor M11 and the first gate M11G1 of the eleventh transistor M11 both extend along the first direction G and are arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the first sub-active region Act_sub1 overlaps with the first gate M11G1 of the eleventh transistor M11 and the second gate M11G2 of the eleventh transistor M11 serves as the channel region of the eleventh transistor M11. In other words, the channel region of the eleventh transistor M11 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the eleventh transistor M11 overlaps with the first gate M11G1 of the eleventh transistor M11, and the second channel region of the eleventh transistor M11 overlaps with the second gate M11G2 of the eleventh transistor M11. The drain M11D of the eleventh transistor M11 is located between the first channel region of the eleventh transistor M11 and the second channel region of the eleventh transistor M11, and the source M11S of the eleventh transistor is located on a side of the first channel region of the eleventh transistor M11 away from the second channel region of the eleventh transistor M11 and on a side of the second channel region of the eleventh transistor M11 away from the first channel region of the eleventh transistor M11. In other words, the source M11S of the eleventh transistor includes a first source M11S1 and a second source M11S2 arranged in parallel with each other, the first source M11S1 of the eleventh transistor M11 is located on a side of the first channel region of the eleventh transistor M11 away from the second channel region of the eleventh transistor M11, and the second source M11S2 of the eleventh transistor M11 is located on a side of the second channel region of the eleventh transistor M11 away from the first channel region of the eleventh transistor M11. Thus, the second source M11S2 of the eleventh transistor M11, the second channel region of the eleventh transistor M11, the drain M11D of the eleventh transistor M11, the first channel region of the eleventh transistor M11 and the first source M11S1 of the eleventh transistor M11 all extend along the first direction G and are sequentially arranged along the second direction H.

[0257] In one embodiment of the present disclosure, see Fig.11, the gate M12G of the twelfth transistor M12 includes a first gate M12G1 and a second gate M12G2, the second gate M12G2 of the twelfth transistor M12 and the first gate M12G1 of the twelfth transistor M12 are both extended along the first direction G and arranged in sequence along the second direction H, and the lengths of the two are the same. The portion where the second sub-active region Act_sub2 overlaps with the first gate M12G1 of the twelfth transistor M12 and the second gate M12G2 of the twelfth transistor M12 serves as the channel region of the twelfth transistor M12. In other words, the channel region of the twelfth transistor M12 has a first channel region and a second channel region that are arranged in parallel with each other, the first channel region of the twelfth transistor M12 overlaps with the first gate M12G1 of the twelfth transistor M12, and the second channel region of the twelfth transistor M12 overlaps with the second gate M12G2 of the twelfth transistor M12. The drain M12D of the twelfth transistor M12 is located between the first channel region of the twelfth transistor M12 and the second channel region of the twelfth transistor M12, and the source M12S of the twelfth transistor is located on a side of the first channel region of the twelfth transistor M12 away from the second channel region of the twelfth transistor M12 and on a side of the second channel region of the twelfth transistor M12 away from the first channel region of the twelfth transistor M12. In other words, the source M12S of the twelfth transistor includes a first source M12S1 and a second source M12S2 arranged in parallel with each other, the first source M12S1 of the twelfth transistor M12 is located on a side of the first channel region of the twelfth transistor M12 away from the second channel region of the twelfth transistor M12, and the second source M12S2 of the twelfth transistor M12 is located on a side of the second channel region of the twelfth transistor M12 away from the first channel region of the twelfth transistor M12. Thus, the second source M12S2 of the twelfth transistor M12, the second channel region of the twelfth transistor M12, the drain M12D of the twelfth transistor M12, the first channel region of the twelfth transistor M12 and the first source M12S1 of the twelfth transistor M12 all extend along the first direction G and are sequentially arranged along the second direction H.

[0258] In one embodiment of the present disclosure, the first source M12S1 of the twelfth transistor M12 and the first source M11S1 of the eleventh transistor M11 are overlapped in the first direction G, that is, the first source M12S1 of the twelfth transistor M12 and the first source M11S1 of the eleventh transistor M11 are arranged in a straight line along the first direction G. The second source M12S2 of the twelfth transistor M12 and the second source M11S2 of the eleventh transistor M11 are overlapped in the first direction G, that is, the second source M12S2 of the twelfth transistor M12 and the second source M11S2 of the eleventh transistor M11 are arranged in a straight line along the first direction G. The first gate M12G1 of the twelfth transistor M12 and the first gate M11G1 of the eleventh transistor M11 are overlapped in the first direction G, that is, the first gate M12G1 of the twelfth transistor M12 and the first gate M11G1 of the eleventh transistor M11 are arranged in a straight line along the first direction G. The second gate M12G2 of the twelfth transistor M12 and the second gate M11G2 of the eleventh transistor M11 are overlapped in the first direction G, that is, the second gate M12G2 of the twelfth transistor M12 and the second gate M11G2 of the eleventh transistor M11 are arranged in a straight line along the first direction G. The drain M12D of the twelfth transistor M12 and the drain M11D of the eleventh transistor M11 are overlapped in the first direction G, that is, the drain M12D of the twelfth transistor M12 and the drain M11D of the eleventh transistor M11 are arranged in a straight line along the first direction G. The first channel region of the twelfth transistor M12 and the first channel region of the eleventh transistor M11 are overlapped in the first direction G, that is, the first channel region of the twelfth transistor M12 and the first channel region of the eleventh transistor M11 are arranged in a straight line along the first direction G. The second channel region of the twelfth transistor M12 and the second channel region of the eleventh transistor M11 overlap in the first direction G, that is, the second channel region of the twelfth transistor M12 and the second channel region of the eleventh transistor M11 are arranged in a straight line along the first direction G. In this way, the twelfth transistor M12 is located on the first direction G side of the eleventh transistor M11.

[0259] In one embodiment of the present disclosure, the first source M9S1 of the ninth transistor M9, the first gate M9G1 of the ninth transistor M9, the drain M9D of the ninth transistor M9, the second gate M9G2 of the ninth transistor M9, the second source M9S2 of the ninth transistor M9, the second source M11S2 of the eleventh transistor M11, the second gate M11G2 of the eleventh transistor M11, the drain M11D of the eleventh transistor M11, the first gate M11G1 of the eleventh transistor M11, and the first source M11S1 of the eleventh transistor M11 are sequentially arranged along the second direction H. In this way, the eleventh transistor M11 is located on one side of the ninth transistor M9 in the second direction H. Further, the second source M9S2 of the ninth transistor M9 overlaps with the second source M11S2 of the eleventh transistor M11. In this way, the ninth transistor M9 and the eleventh transistor M11 can share a source, thereby simplifying the wiring arrangement of the row driving signal enhancement circuit 101 , improving the compactness of the row driving signal enhancement circuit 101 , and reducing the area occupied by the row driving signal enhancement circuit 101 .

[0260] In one embodiment of the present disclosure, the first source M10S1 of the tenth transistor M10, the first gate M10G1 of the tenth transistor M10, the drain M10D of the tenth transistor M10, the second gate M10G2 of the tenth transistor M10, the second source M10S2 of the tenth transistor M10, the second source M12S2 of the twelfth transistor M12, the second gate M12G2 of the twelfth transistor M12, the drain M12D of the twelfth transistor M12, the first gate M12G1 of the twelfth transistor M12, and the first source M12S1 of the twelfth transistor M12 are sequentially arranged along the second direction H. In this way, the twelfth transistor M12 is located on one side of the tenth transistor M10 in the second direction H. Further, the second source M10S2 of the tenth transistor M10 and the second source M12S2 of the twelfth transistor M12 overlap. In this way, the twelfth transistor M12 and the tenth transistor M10 can share a source, thereby simplifying the wiring arrangement of the row driving signal enhancement circuit 101, improving the compactness of the row driving signal enhancement circuit 101, and reducing the area occupied by the row driving signal enhancement circuit 101.

[0261] Alternatively, see Fig.23 The insulating dielectric layer 340 includes a first dielectric layer 341, a second dielectric layer 342 and a third dielectric layer 343 which are sequentially stacked on the gate layer 330, and the metal wiring layer 360 includes a first metal wiring layer 361 located between the first dielectric layer 341 and the second dielectric layer 342, a second metal wiring layer 362 located between the second dielectric layer 342 and the third dielectric layer 343, and a third metal wiring layer 363 located on the surface of the third dielectric layer 343 away from the semiconductor substrate 310.

[0262] The conductive pillars include a first conductive pillar 351 penetrating the first dielectric layer 341, a second conductive pillar 352 penetrating the second dielectric layer 342, and a third conductive pillar 353 penetrating the third dielectric layer 343; the first metal wiring layer 361 is connected to the semiconductor substrate 310 and the gate layer 330 through the first conductive pillar 351; the second metal wiring layer 362 is connected to the first metal wiring layer 361 through the second conductive pillar 352; and the third metal wiring layer 363 is connected to the second metal wiring layer 362 through the third conductive pillar 353.

[0263] Alternatively, see Fig.23 Each conductive pillar penetrates the corresponding dielectric layer in a direction perpendicular to the semiconductor substrate 310. Exemplarily, the first conductive pillar 351 penetrates the first dielectric layer 341 in a direction perpendicular to the semiconductor substrate 310 to connect with the semiconductor substrate 310 or the gate layer 330.

[0264] In one embodiment of the present disclosure, the orthographic projection of the first conductive pillar 351 on the semiconductor substrate 310 does not overlap with the orthographic projection of the second conductive pillar 352 on the semiconductor substrate 310 ; the orthographic projection of the second conductive pillar 352 on the semiconductor substrate 310 does not overlap with the orthographic projection of the third conductive pillar 353 on the semiconductor substrate 310 .

[0265] Optionally, each conductive pillar may be a metal pillar, for example, a tungsten pillar.

[0266] Alternatively, see Fig.13 The first metal wiring layer 361 includes some connection leads. The connection leads located in the first metal wiring layer 361 include the first connection lead L01 to the sixth connection lead L06, and also include the gate connection line, source connection line and drain connection line corresponding to the first transistor M1 to the fourteenth transistor M14. Figure 12 to Figure 14 , the gate connection line corresponding to any transistor is connected to the gate of the transistor through the first conductive column 351; the source connection line corresponding to any transistor is connected to the source of the transistor through the first conductive column 351; and the drain connection line corresponding to any transistor is connected to the drain of the transistor through the first conductive column 351.

[0267] The source connection line corresponding to the ninth transistor M9 and the source connection line corresponding to the eleventh transistor M11 are connected to the first connection lead L01. The source connection line corresponding to the tenth transistor M10 includes a first sub-connection line M10SL1 and a second sub-connection line M10SL2; the source connection line corresponding to the twelfth transistor M12 includes a first sub-connection line M12SL1 and a second sub-connection line M12SL2. The first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10, the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12, the source connection line M5SL corresponding to the fifth transistor M5, and the source connection line M4SL corresponding to the fourth transistor M4 are connected to the second connection lead L02.

[0268] The drain connection line M3DL corresponding to the third transistor M3, the drain connection line M4DL corresponding to the fourth transistor M4, the gate connection line M5GL corresponding to the fifth transistor M5, and the gate connection line M6GL corresponding to the sixth transistor M6 are connected to the third connection lead L03.

[0269] The drain connection line M5DL corresponding to the fifth transistor M5, the drain connection line M6DL corresponding to the sixth transistor M6, the gate connection line M3GL corresponding to the third transistor M3, and the gate connection line M4GL corresponding to the fourth transistor M4 are connected to the fourth connection lead L04.

[0270] The source connection line corresponding to the eighth transistor M8 includes a first sub-connection line M8SL1 and a second sub-connection line M8SL2; the source connection line corresponding to the fourteenth transistor M14 includes a first sub-connection line M14SL1 and a second sub-connection line M14SL2. The first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8, the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14, the source connection line corresponding to the seventh transistor M7, the source connection line corresponding to the thirteenth transistor M13, the source connection line corresponding to the first transistor M1, and the source connection line corresponding to the second transistor M2 are connected to the fifth connection lead L05.

[0271] The source connection line M3SL corresponding to the third transistor M3 and the source connection line M6SL corresponding to the sixth transistor M6 are connected to the sixth connection lead L06.

[0272] See also Fig.17 The second metal wiring layer 362 includes a first control lead 421, a second control lead 422, a first output lead 431, a second output lead 432 and some connection leads; the connection leads located in the second metal wiring layer 362 include the seventh connection lead L07 to the fifteenth connection lead L15. Figure 15 to Figure 18The second metal wiring layer 362 is connected to the first metal wiring layer 361 through the second conductive pillar 352 .

[0273] The first connection lead L01 and the second connection lead L02 are connected to the seventh connection lead L07, and the first connection lead L01 and the second connection lead L02 are connected to the eighth connection lead L08. The fifth connection lead L05 is connected to the ninth connection lead L09 and the tenth connection lead L10.

[0274] The gate connection line M9GL corresponding to the ninth transistor M9, the gate connection line M10GL corresponding to the tenth transistor M10, the drain connection line M5DL corresponding to the fifth transistor M5, the drain connection line M6DL corresponding to the sixth transistor M6, the gate connection line M7GL corresponding to the seventh transistor M7, the gate connection line M8GL corresponding to the eighth transistor M8, and the drain connection line M1DL corresponding to the first transistor M1 are connected to the eleventh connection lead L11.

[0275] The gate connection line M11GL corresponding to the eleventh transistor M11, the gate connection line M12GL corresponding to the twelfth transistor M12, the drain connection line M3DL corresponding to the third transistor M3, the drain connection line M4DL corresponding to the fourth transistor M4, the gate connection line M13GL corresponding to the thirteenth transistor M13, the gate connection line M14GL corresponding to the fourteenth transistor M14, and the drain connection line M2DL corresponding to the second transistor M2 are connected to the twelfth connection lead L12.

[0276] The first connecting lead L01, the second sub-connection line M9SL2 of the source connecting line corresponding to the ninth transistor M9, the second sub-connection line M10SL2 of the source connecting line corresponding to the tenth transistor M10, the second sub-connection line M11SL2 of the source connecting line corresponding to the eleventh transistor M11, the second sub-connection line M12SL2 of the source connecting line corresponding to the twelfth transistor M12, the sixth connecting lead L06, the second connecting lead L02 and the thirteenth connecting lead L13 are connected.

[0277] The second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7, the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8, the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13, the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14, the fifth connection lead L05 and the fourteenth connection lead L14 are connected.

[0278] The second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1, the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2, the fifth connection lead L05 and the fifteenth connection lead L15 are connected.

[0279] The drain connection line M7DL corresponding to the seventh transistor M7, the drain connection line M8DL corresponding to the eighth transistor M8, the drain connection line M9DL corresponding to the ninth transistor M9, and the drain connection line M10DL corresponding to the tenth transistor M10 are connected to the first output lead 431. The drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line M14DL corresponding to the fourteenth transistor M14 are connected to the second output lead 432.

[0280] See also Fig. 20 The third metal wiring layer 363 includes a first voltage lead 411 for applying a first voltage, and a second power supply lead 412 for applying a second power supply voltage V2. Figure 19 to Figure 22 The ninth connecting lead L09, the tenth connecting lead L10, the fourteenth connecting lead L14, and the fifteenth connecting lead L15 are connected to the first power lead 411 through the third conductive column; the seventh connecting lead L07, the eighth connecting lead L08, and the thirteenth connecting lead L13 are connected to the second power lead 412 through the third conductive column.

[0281] As such, in the display panel of the present disclosure, the metal wiring layer 360 electrically connects the transistors in the row drive signal enhancement region F, thereby forming a row drive signal enhancement circuit 101 in the row drive signal enhancement region F of the display panel.

[0282] In one embodiment of the present disclosure, see Fig.11 , the second source M7S2 of the seventh transistor M7 coincides with the second source M13S2 of the thirteenth transistor M13. Fig.13 The second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 overlaps with the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13 and is the same lead line.

[0283] In one embodiment of the present disclosure, see Fig.11 , the second source M8S2 of the eighth transistor M8 coincides with the second source M14S2 of the fourteenth transistor M14. Fig.13 The second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8 overlaps with the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 and is the same lead.

[0284] In one embodiment of the present disclosure, see Fig.11 , the second source M9S2 of the ninth transistor M9 coincides with the second source M11S2 of the eleventh transistor M11. Fig.13 The second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9 overlaps with the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11 and is the same lead line.

[0285] In one embodiment of the present disclosure, see Fig.11 , the second source M10S2 of the tenth transistor M10 coincides with the second source M12S2 of the twelfth transistor M12. Fig.13 The second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 overlaps with the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12 and is the same lead line.

[0286] In one embodiment of the present disclosure, see Fig.11 , the drain M5D of the fifth transistor M5 and the drain M6D of the sixth transistor M6 coincide with each other. Fig.13 The drain connection line M5DL corresponding to the fifth transistor M5 overlaps with the drain connection line M6DL corresponding to the sixth transistor M6 and is the same lead line.

[0287] In one embodiment of the present disclosure, see Fig.11 , the drain M3D of the third transistor M3 coincides with the drain M4D of the fourth transistor M4. Fig.13 The drain connection line M3DL corresponding to the third transistor M3 overlaps with the drain connection line M4DL corresponding to the fourth transistor M4 and is the same lead line.

[0288] Optionally, the source connection line corresponding to any one of the first transistor M1 to the fourteenth transistor M14 overlaps with the source of the transistor, and the extension direction of the two is consistent. In one embodiment of the present disclosure, the extension direction of the source connection line corresponding to any one of the first transistor M1 to the fourteenth transistor M14 is the first direction G. Further optionally, for any one of the transistors, the source connection lead corresponding to the transistor is connected to the source of the transistor through a plurality of first conductive pillars 351 arranged in sequence along the first direction G.

[0289] Optionally, the drain connection line corresponding to any one of the first transistor M1 to the fourteenth transistor M14 overlaps with the drain of the transistor, and the two extend in the same direction. In one embodiment of the present disclosure, the drain connection line corresponding to any one of the first transistor M1 to the fourteenth transistor M14 extends in the first direction G. Further optionally, for any one of the transistors, the drain connection lead corresponding to the transistor is connected to the drain of the transistor through two first conductive pillars 351 arranged along the first direction G.

[0290] Optionally, the drain connection lines corresponding to the respective transistors have the same width as the drain connection lines.

[0291] Optionally, the gate of any transistor among the first transistor M1 to the fourteenth transistor M14 extends along the first direction G; the gate connection line corresponding to any transistor extends along the second direction H, and is electrically connected to the end of the gate of the transistor through the first conductive column 351. Further, the gate connection line corresponding to any transistor does not overlap with the active area.

[0292] Optionally, the drain connection lines and gate connection lines corresponding to the respective transistors have the same width.

[0293] For example, see Fig.13 The gate connection line M1GL corresponding to the first transistor M1 is located on the first direction G side of the seventh sub-active area Act_sub7 and extends along the second direction H, and is connected to the first gate M1G1 of the first transistor M1 and the end of the second gate M1G2 of the first transistor M1 on the first direction G side.

[0294] The gate connection line M2GL corresponding to the second transistor M2 is located on the first direction G side of the eighth sub-active region Act_sub8 and extends along the second direction H, and is connected to the first gate M2G1 of the second transistor M2 and the second gate M2G2 of the second transistor M2 on the first direction G side.

[0295] The gate connection line M3GL corresponding to the third transistor M3 is located at one side of the first direction G of the fourth sub-active region Act_sub4 and extends along the second direction H, and is connected to an end of the gate M3G of the third transistor M3 at one side of the first direction G.

[0296] The gate connection line M4GL corresponding to the fourth transistor M4 is located at one side of the first direction G of the fourth sub-active region Act_sub4 and extends along the second direction H, and is connected to an end of the gate M4G of the fourth transistor M4 at one side of the first direction G.

[0297] The gate connection line M5GL corresponding to the fifth transistor M5 is located on the opposite side of the first direction G of the third sub-active region Act_sub3 and extends along the second direction H, and is connected to the end of the gate M5G of the fifth transistor M5 on the opposite side of the first direction G.

[0298] The gate connection line M6GL corresponding to the sixth transistor M6 is located on the opposite side of the first direction G of the third sub-active region Act_sub3 and extends along the second direction H, and is connected to the end of the gate M6G of the sixth transistor M6 on the opposite side of the first direction G.

[0299] The gate connection line M7GL corresponding to the seventh transistor M7 is located on the first direction G side of the fifth sub-active region Act_sub5 and extends along the second direction H, and is connected to the first gate M7G1 of the seventh transistor M7 and the second gate M7G2 of the seventh transistor M7 on the first direction G side.

[0300] The gate connection line M8GL corresponding to the eighth transistor M8 is located on the first direction G side of the sixth sub-active region Act_sub6 and extends along the second direction H, and is connected to the first gate M8G1 of the eighth transistor M8 and the second gate M8G2 of the eighth transistor M8 on the first direction G side.

[0301] The gate connection line M9GL corresponding to the ninth transistor M9 is located on the first direction G side of the first sub-active area Act_sub1 and extends along the second direction H, and is connected to the first gate M9G1 of the ninth transistor M9 and the second gate M9G2 of the ninth transistor M9 on the first direction G side.

[0302] The gate connection line M10GL corresponding to the tenth transistor M10 is located on the first direction G side of the second sub-active region Act_sub2 and extends along the second direction H, and is connected to the first gate M10G1 of the tenth transistor M10 and the second gate M10G2 of the tenth transistor M10 on the first direction G side.

[0303] The gate connection line M11GL corresponding to the eleventh transistor M11 is located on the first direction G side of the first sub-active area Act_sub1 and extends along the second direction H, and is connected to the first gate M11G1 of the eleventh transistor M11 and the second gate M11G2 of the eleventh transistor M11 on the first direction G side.

[0304] The gate connection line M12GL corresponding to the twelfth transistor M12 is located on the first direction G side of the second sub-active area Act_sub2 and extends along the second direction H, and is connected to the first gate M12G1 of the twelfth transistor M12 and the second gate M12G2 of the twelfth transistor M12 on the first direction G side.

[0305] The gate connection line M13GL corresponding to the thirteenth transistor M13 is located on the first direction G side of the fifth sub-active region Act_sub5 and extends along the second direction H, and is connected to the first gate M13G1 of the thirteenth transistor M13 and the second gate M13G2 of the thirteenth transistor M13 on the first direction G side.

[0306] The gate connection line M14GL corresponding to the fourteenth transistor M14 is located on the first direction G side of the sixth sub-active region Act_sub6 and extends along the second direction H, and is connected to the first gate M14G1 of the fourteenth transistor M14 and the second gate M14G2 of the fourteenth transistor M14 on the first direction G side.

[0307] In one embodiment of the present disclosure, see Fig.13 , the gate connection line M3GL corresponding to the third transistor M3 and the gate connection line M4GL corresponding to the fourth transistor M4 overlap and are the same lead. The drain connection line M5DL corresponding to the fifth transistor M5 and the drain connection line M6DL corresponding to the sixth transistor M6 overlap and are the same lead. Further, the fourth connection lead L04 extends along the second direction H and is consistent with the extension direction of the gate connection line M3GL corresponding to the third transistor M3 / the gate connection line M4GL corresponding to the fourth transistor M4, and is connected to the end of the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6 in the first direction G. In this way, the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6, the fourth connection lead L04, the gate connection line M3GL corresponding to the third transistor M3 / the gate connection line M4GL corresponding to the fourth transistor M4 are L-shaped leads arranged along the first direction G and the second direction H. Exemplarily, along the first direction G, the gate connection line M3GL corresponding to the third transistor M3 / the gate connection line M4GL corresponding to the fourth transistor M4 and the fourth connection lead L04 are located between the sixth N-type doped sub-region F_Nsub6 and the third sub-active region Act_sub3 and the fourth sub-active region Act_sub4, and extend along the second direction H. One end of the fourth connection lead L04 in the second direction H is connected to the gate connection line M3GL corresponding to the third transistor M3 / the gate connection line M4GL corresponding to the fourth transistor M4, and one end of the fourth connection lead L04 in the opposite direction of the second direction H is connected to the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6.

[0308] In one embodiment of the present disclosure, see Fig.13, the gate connection line M5GL corresponding to the fifth transistor M5 and the gate connection line M6GL corresponding to the sixth transistor M6 overlap and are the same lead. The drain connection line M3DL corresponding to the third transistor M3 and the drain connection line M4DL corresponding to the fourth transistor M4 overlap and are the same lead. Further, the third connection lead L03 extends along the second direction H and is consistent with the extension direction of the gate connection line M5GL corresponding to the fifth transistor M5, and is connected to the end of the drain connection line M3DL corresponding to the third transistor M3 on the opposite side of the first direction G. In this way, the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, the third connection lead L03, the gate connection line M5GL corresponding to the fifth transistor M5 / the gate connection line M6GL corresponding to the sixth transistor M6 are L-shaped leads arranged along the first direction G and the second direction H. Exemplarily, along the first direction G, the gate connection line M5GL corresponding to the fifth transistor M5 / the gate connection line M6GL corresponding to the sixth transistor M6 and the third connection lead L03 are located between the fourth N-type doped sub-region F_Nsub4 and the third sub-active region Act_sub3 and the fourth sub-active region Act_sub4, and extend along the second direction H. One end of the third connection lead L03 in the second direction H is connected to the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, and one end of the third connection lead L03 in the opposite direction of the second direction H is connected to the gate connection line M5GL corresponding to the fifth transistor M5 / the gate connection line M6GL corresponding to the sixth transistor M6.

[0309] In one embodiment of the present disclosure, a gate connection line M9GL corresponding to the ninth transistor M9, a gate connection line M10GL corresponding to the tenth transistor M10, and a gate connection line M7GL corresponding to the seventh transistor M7 are all provided with a switching line extending along the first direction G at one end in the opposite direction of the second direction H; a switching line of the gate connection line M9GL corresponding to the ninth transistor M9, a switching line of the gate connection line M10GL corresponding to the tenth transistor M10, a switching line of the gate connection line M7GL corresponding to the seventh transistor M7, a drain connection line M5DL corresponding to the fifth transistor M5 / sixth transistor The drain connection line M6DL corresponding to M6 and the drain connection line M1DL corresponding to the first transistor M1 are arranged in a straight line along the first direction G; the eleventh connection lead L11 is arranged in a straight line along the first direction G, and overlaps with the switching line of the gate connection line M9GL corresponding to the ninth transistor M9, the switching line of the gate connection line M10GL corresponding to the tenth transistor M10, the switching line of the gate connection line M7GL corresponding to the seventh transistor M7, the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6, and the drain connection line M1DL corresponding to the first transistor M1. The eleventh connection lead L11 is respectively connected to the switching line of the gate connection line M9GL corresponding to the ninth transistor M9, the switching line of the gate connection line M10GL corresponding to the tenth transistor M10, the switching line of the gate connection line M7GL corresponding to the seventh transistor M7, the gate connection line M8GL corresponding to the eighth transistor M8, the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6, and the drain connection line M1DL corresponding to the first transistor M1 through the second conductive column 352. Optionally, the eleventh connection lead L11 can also be provided with a switching line extending in the second direction H; the switching line of the eleventh connection lead L11 overlaps with the gate connection line M8GL corresponding to the eighth transistor M8, and is connected to the gate connection line M8GL corresponding to the eighth transistor M8 through the second conductive column 352. In this way, the gate connection line M8GL corresponding to the eighth transistor M8 does not need to be provided with a switching line, which can avoid the switching line of the gate connection line M8GL corresponding to the eighth transistor M8 occupying space in the first direction G, thereby reducing the area of ​​the row driving signal enhancement circuit 101 disclosed in the present invention.

[0310] In one embodiment of the present disclosure, a gate connection line M11GL corresponding to the eleventh transistor M11, a gate connection line M12GL corresponding to the twelfth transistor M12, and a gate connection line M13GL corresponding to the thirteenth transistor M13 are all provided with a switching line extending along the first direction G at one end of the second direction H, and the switching line of the gate connection line M11GL corresponding to the eleventh transistor M11, the switching line of the gate connection line M12GL corresponding to the twelfth transistor M12, the switching line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, and the drain connection line M2DL corresponding to the second transistor M2 are arranged in a straight line along the first direction G. The twelfth connection lead L12 is arranged in a straight line along the first direction G, and overlaps with the switching line of the gate connection line M11GL corresponding to the eleventh transistor M11, the switching line of the gate connection line M12GL corresponding to the twelfth transistor M12, the switching line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, and the drain connection line M2DL corresponding to the second transistor M2. The twelfth connection lead L12 is respectively connected to the switching line of the gate connection line M11GL corresponding to the eleventh transistor M11, the switching line of the gate connection line M12GL corresponding to the twelfth transistor M12, the switching line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the gate connection line M14GL corresponding to the fourteenth transistor M14, the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, and the drain connection line M2DL corresponding to the second transistor M2 through the second conductive column 352. Optionally, the twelfth connection lead L12 may also be provided with a switching line extending in the opposite direction to the second direction H; the switching line of the twelfth connection lead L12 overlaps with the gate connection line M14GL corresponding to the fourteenth transistor M14, and is connected to the gate connection line M14GL corresponding to the fourteenth transistor M14 through the second conductive column 352. In this way, the gate connection line M14GL corresponding to the fourteenth transistor M14 does not need to be provided with a switching line, which can avoid the switching line of the gate connection line M14GL corresponding to the fourteenth transistor M14 from occupying space in the first direction G, thereby reducing the area of ​​the row drive signal enhancement circuit 101 disclosed in the present invention.

[0311] In some embodiments, see Fig.13The first connecting lead L01 includes a first sub-lead L011, a second sub-lead L012 and a third sub-lead L013 which are connected in sequence; the first sub-lead L011 of the first connecting lead L01 and the third sub-lead L013 of the first connecting lead L01 extend along a first direction G and at least partially overlap with the N-type auxiliary doping area F_Ndummy; the second sub-lead L012 of the first connecting lead L01 extends along a second direction H and at least partially overlaps with the N-type auxiliary doping area F_Ndummy; the first sub active area Act_sub1 is located in a semi-open space surrounded by the first connecting lead L01.

[0312] Exemplarily, the first connecting lead L01 is located on the side opposite to the first direction G of the second connecting lead L02. Among them, the extension direction of the first sub-lead L011 of the first connecting lead L01 is consistent with the extension direction of the first N-type doped sub-region F_Nsub1, both are the first direction G and the two are at least partially overlapped. The extension direction of the second sub-lead L012 of the first connecting lead L01 is consistent with the extension direction of the second N-type doped sub-region F_Nsub2, both are the second direction H and the two are at least partially overlapped. The extension direction of the third sub-lead L013 of the first connecting lead L01 is consistent with the extension direction of the third N-type doped sub-region F_Nsub3, both are the second direction H and the two are at least partially overlapped. In this way, the first connecting lead L01 forms a U-shaped structure with an opening facing the first direction G, and the first sub-active region Act_sub1 is located in the space surrounded by the U-shaped structure.

[0313] In one embodiment of the present disclosure, the first sub-lead L011 of the first connecting lead L01, the second sub-lead L012 of the first connecting lead L01, and the third sub-lead L013 of the first connecting lead L01 are all connected to the N-type auxiliary doping region F_Ndummy. Specifically, the first sub-lead L011 of the first connecting lead L01 is connected to the first N-type doped sub-region F_Nsub1 through a plurality of first conductive pillars 351 sequentially arranged along the first direction G; the second sub-lead L012 of the first connecting lead L01 is connected to the second N-type doped sub-region F_Nsub2 through a plurality of first conductive pillars 351 sequentially arranged along the second direction H; the third sub-lead L013 of the first connecting lead L01 is connected to the third N-type doped sub-region F_Nsub3 through a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Optionally, the first sub-lead L011 of the first connection lead L01 is connected to the first N-type doped sub-region F_Nsub1 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Optionally, the third sub-lead L013 of the first connection lead L01 is connected to the third N-type doped sub-region F_Nsub3 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G.

[0314] In this way, the second power supply voltage V2 loaded on the first connecting lead L01 can be evenly loaded to the N-type auxiliary doping region F_Ndummy overlapping with the first connecting lead L01, thereby reducing the leakage of the ninth transistor M9 and the eleventh transistor M11. Furthermore, the orthographic projection of the first sub-lead L011 of the first connecting lead L01 on the semiconductor substrate 310 is located within the range of the first N-type doping sub-region F_Nsub1; the orthographic projection of the second sub-lead L012 of the first connecting lead L01 on the semiconductor substrate 310 is located within the range of the second N-type doping sub-region F_Nsub2; the orthographic projection of the third sub-lead L013 of the first connecting lead L01 on the semiconductor substrate 310 is located within the range of the third N-type doping sub-region F_Nsub3.

[0315] In one embodiment of the present disclosure, see Fig.13The first sub-lead L011 of the first connecting lead L01 and the first sub-connection line M9SL1 of the source connecting line corresponding to the ninth transistor M9 both extend along the first direction G; the local position of the first sub-lead L011 of the first connecting lead L01 can also extend along the second direction H to form a protrusion, and the protrusion of the first sub-lead L011 of the first connecting lead L01 extends along the second direction H to connect with the first sub-connection line M9SL1 of the source connecting line corresponding to the ninth transistor M9, so that the side of the first sub-connection line M9SL1 of the source connecting line corresponding to the ninth transistor M9 in the opposite direction of the second direction H is connected to the first sub-lead L011 of the first connecting lead L01. Further, one end of the protrusion of the first sub-lead L011 of the first connection lead L01 in the first direction G is flush with one end of the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9 in the first direction G, and one end of the protrusion of the first sub-lead L011 of the first connection lead L01 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9 in the opposite direction of the first direction G. In this way, the length of the protrusion of the first sub-lead L011 of the first connection lead L01 in the first direction G is the same as the length of the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9 in the first direction G. The setting of the protrusion of the first sub-lead L011 of the first connection lead L01 can make the first source M9S1LN of the ninth transistor M9 and the first sub-lead L011 of the first connection lead L01 an integrated structure.

[0316] In one embodiment of the present disclosure, see Fig.13The third sub-lead L013 of the first connecting lead L01 and the first sub-connection line M11SL1 of the source connecting line corresponding to the eleventh transistor M11 both extend along the first direction G; the local position of the third sub-lead L013 of the first connecting lead L01 can also extend in the opposite direction of the second direction H to form a protrusion, and the protrusion of the third sub-lead L013 of the first connecting lead L01 extends in the opposite direction of the second direction H to connect with the first sub-connection line M11SL1 of the source connecting line corresponding to the eleventh transistor M11, so that the side of the second direction H of the first sub-connection line M11SL1 of the source connecting line corresponding to the eleventh transistor M11 is connected to the third sub-lead L013 of the first connecting lead L01. Further, one end of the protrusion of the third sub-lead L013 of the first connection lead L01 in the first direction G is flush with one end of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 in the first direction G, and one end of the protrusion of the third sub-lead L013 of the first connection lead L01 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 in the opposite direction of the first direction G. In this way, the length of the protrusion of the third sub-lead L013 of the first connection lead L01 in the first direction G is the same as the length of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 in the first direction G. The setting of the protrusion of the third sub-lead L013 of the first connection lead L01 can make the first source M11S1LN of the eleventh transistor M11 and the third sub-lead L013 of the first connection lead L01 an integrated structure.

[0317] Alternatively, see Fig.13, the second connecting lead L02 includes a first sub-lead L021, a second sub-lead L022 and a fourth sub-lead L024 connected in sequence, and includes a third sub-lead L023. Among them, the first sub-lead L021 of the second connecting lead L02 and the fourth sub-lead L024 of the second connecting lead L02 are extended along the first direction G, and at least partially overlap with the P-type auxiliary doping area F_Pdummy; the second sub-lead L022 of the second connecting lead L02 and the third sub-lead L023 of the second connecting lead L02 are extended along the second direction H, and at least partially overlap with the P-type auxiliary doping area F_Pdummy; the second sub-active area Act_sub2 is located The second active layer Act2 is located in a space surrounded by the first sub-lead L021 of the second connecting lead L02, the second sub-lead L022 of the second connecting lead L02 and the fourth sub-lead L024 of the second connecting lead L02.

[0318] For example, see Fig.13 , the second connecting lead L02 is located on the first direction G side of the first connecting lead L01. Among them, the first sub-lead L021 of the second connecting lead L02 is consistent with the extension direction of the first sub-lead L011 of the first connecting lead L01 and is discontinuous with the first sub-lead L011 of the first connecting lead L01. The portion of the first sub-lead L021 of the second connecting lead L02 close to the end in the opposite direction of the first direction G can at least partially overlap with the first N-type doped sub-region F_Nsub1; the portion of the first sub-lead L021 of the second connecting lead L02 close to the end in the first direction G can at least partially overlap with the fifth N-type doped sub-region F_Nsub5. The size of the portion where the first sub-lead L021 of the second connecting lead L02 overlaps with the fifth N-type doped sub-region F_Nsub5 in the second direction H can be smaller than the size of the portion where the first sub-lead L021 of the second connecting lead L02 overlaps with the first N-type doped sub-region F_Nsub1 in the second direction H.

[0319] The fourth sub-lead L024 of the second connecting lead L02 extends in the same direction as the third sub-lead L013 of the first connecting lead L01 and is discontinuous with the third sub-lead L013 of the first connecting lead L01. The portion of the fourth sub-lead L024 of the second connecting lead L02 close to the end in the opposite direction of the first direction G may at least partially overlap with the third N-type doped sub-region F_Nsub3; the portion of the fourth sub-lead L024 of the second connecting lead L02 close to the end in the first direction G may at least partially overlap with the seventh N-type doped sub-region F_Nsub7. The size of the portion of the fourth sub-lead L024 of the second connecting lead L02 overlapping with the seventh N-type doped sub-region F_Nsub7 in the second direction H may be smaller than the size of the portion of the fourth sub-lead L024 of the second connecting lead L02 overlapping with the third N-type doped sub-region F_Nsub3 in the second direction H.

[0320] The second sub-lead L022 of the second connecting lead L02 extends along the second direction H, and its two ends are respectively connected to the first sub-lead L021 of the second connecting lead L02 and the fourth sub-lead L024 of the second connecting lead L02. The portion where the first sub-lead L021 of the second connecting lead L02 overlaps with the first N-type doped sub-region F_Nsub1, and the portion where the fourth sub-lead L024 of the second connecting lead L02 overlaps with the third N-type doped sub-region F_Nsub3 are both located on the side opposite to the first direction G of the second sub-lead L022 of the second connecting lead L02; the portion where the first sub-lead L021 of the second connecting lead L02 overlaps with the fifth N-type doped sub-region F_Nsub5, and the portion where the fourth sub-lead L024 of the second connecting lead L02 overlaps with the seventh N-type doped sub-region F_Nsub7 are both located on the side of the first direction G of the second sub-lead L022 of the second connecting lead L02. The second sub-lead L022 of the second connecting lead L02 at least partially overlaps with the fourth N-type doping sub-region F_Nsub4.

[0321] The third sub-lead L023 of the second connecting lead L02 extends along the second direction H, and its two ends are respectively connected to the first sub-lead L021 of the second connecting lead L02 and the fourth sub-lead L024 of the second connecting lead L02. Among them, the first sub-lead L021 of the second connecting lead L02, the fourth sub-lead L024 of the second connecting lead L02, and the second sub-lead L022 of the second connecting lead L02 are all located on the opposite side of the first direction G of the third sub-lead L023 of the second connecting lead L02. The third sub-lead L023 of the second connecting lead L02 may at least partially overlap with the sixth N-type doped sub-region F_Nsub6.

[0322] See also Fig.13The first sub-lead L021 of the second connecting lead L02, the second sub-lead L022 of the second connecting lead L02, and the fourth sub-lead L024 of the second connecting lead L02 surround a space whose opening faces the opposite direction of the first direction G, and the second sub-active area Act_sub2 may be located in the space. The first sub-lead L021 of the second connecting lead L02, the second sub-lead L022 of the second connecting lead L02, the fourth sub-lead L024 of the second connecting lead L02, and the third sub-lead L023 of the second connecting lead L02 surround a closed space, and the second active area Act2 may be located in the closed space.

[0323] In one embodiment of the present disclosure, the first sub-lead L021 of the second connecting lead L02, the second sub-lead L022 of the second connecting lead L02, the third sub-lead L023 of the second connecting lead L02, and the fourth sub-lead L024 of the second connecting lead L02 are all connected to the N-type auxiliary doping region F_Ndummy. Figure 12 to Figure 14 The first sub-lead L021 of the second connecting lead L02 is connected to the first N-type doped sub-region F_Nsub1 and the fifth N-type doped sub-region F_Nsub5 through a plurality of first conductive pillars 351 arranged sequentially along the first direction G, the second sub-lead L022 of the second connecting lead L02 is connected to the fourth N-type doped sub-region F_Nsub4 through a plurality of first conductive pillars 351 arranged sequentially along the second direction H, the third sub-lead L023 of the second connecting lead L02 is connected to the sixth N-type doped sub-region F_Nsub6 through a plurality of first conductive pillars 351 arranged sequentially along the second direction H, and the fourth sub-lead L024 of the second connecting lead L02 is connected to the third N-type doped sub-region F_Nsub3 and the seventh N-type doped sub-region F_Nsub7 through a plurality of first conductive pillars 351 arranged sequentially along the first direction G. Optionally, the first sub-lead L021 of the second connection lead L02 is connected to the first N-type doped sub-region F_Nsub1 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Optionally, the fourth sub-lead L024 of the second connection lead L02 is connected to the third N-type doped sub-region F_Nsub3 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G. In this way, the second power supply voltage V2 loaded on the second connection lead L02 can be uniformly loaded on the N-type auxiliary doped region F_Ndummy overlapping with the third connection lead L03, thereby reducing the leakage of the tenth transistor M10, the twelfth transistor M12, the fourth transistor M4, and the fifth transistor M5.

[0324] In one embodiment of the present disclosure, see Fig.13The first sub-lead L021 of the second connecting lead L02 and the first sub-connection line M10SL1 of the source connecting line corresponding to the tenth transistor M10 both extend along the first direction G; the local position of the first sub-lead L021 of the second connecting lead L02 can also extend along the second direction H to form a first protrusion, and the first protrusion of the first sub-lead L021 of the second connecting lead L02 extends along the second direction H to connect with the first sub-connection line M10SL1 of the source connecting line corresponding to the tenth transistor M10, so that the side of the first sub-connection line M10SL1 of the source connecting line corresponding to the tenth transistor M10 in the opposite direction of the second direction H is connected to the first sub-lead L021 of the second connecting lead L02. Further, one end of the first protrusion of the first sub-lead L021 of the second connection lead L02 in the first direction G is flush with one end of the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10 in the first direction G, and one end of the first protrusion of the first sub-lead L021 of the second connection lead L02 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10 in the opposite direction G. In this way, the length of the first protrusion of the first sub-lead L021 of the second connection lead L02 in the first direction G is the same as the length of the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10 in the first direction G. The setting of the first protrusion of the first sub-lead L021 of the second connection lead L02 can make the first source M10S1LN of the tenth transistor M10 and the first sub-lead L021 of the second connection lead L02 an integrated structure.

[0325] In one embodiment of the present disclosure, see Fig.13The fourth sub-lead L024 of the second connecting lead L02 and the first sub-connection line M12SL1 of the source connecting line corresponding to the twelfth transistor M12 both extend along the first direction G; the local position of the fourth sub-lead L024 of the second connecting lead L02 can also extend in the opposite direction of the second direction H to form a first protrusion, and the first protrusion of the fourth sub-lead L024 of the second connecting lead L02 extends in the opposite direction of the second direction H to connect with the first sub-connection line M12SL1 of the source connecting line corresponding to the twelfth transistor M12, so that the side of the second direction H of the first sub-connection line M12SL1 of the source connecting line corresponding to the twelfth transistor M12 is connected to the fourth sub-lead L024 of the second connecting lead L02. Further, one end of the first protrusion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is flush with one end of the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12 in the first direction G, and one end of the first protrusion of the fourth sub-lead L024 of the second connection lead L02 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12 in the opposite direction of the first direction G. In this way, the length of the first protrusion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is the same as the length of the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12 in the first direction G. The setting of the first protrusion of the fourth sub-lead L024 of the second connection lead L02 can make the first source M12S1LN of the twelfth transistor M12 and the fourth sub-lead L024 of the second connection lead L02 an integrated structure.

[0326] In some embodiments, see Fig.13 , a third connection lead L03, a fourth connection lead L04, a drain connection line M3DL corresponding to the third transistor M3 / a drain connection line M4DL corresponding to the fourth transistor M4, a gate connection line M3GL corresponding to the third transistor M3 / a gate connection line M4GL corresponding to the fourth transistor M4, a drain connection line M5DL corresponding to the fifth transistor M5 / a drain connection line M6DL corresponding to the sixth transistor M6, a gate connection line M5GL corresponding to the fifth transistor M5 / a gate connection line M6GL corresponding to the sixth transistor M6, The sixth connecting lead L06, the source connecting line M5SL corresponding to the fifth transistor M5, the source connecting line M6SL corresponding to the sixth transistor M6, the source connecting line M3SL corresponding to the third transistor M3 and the source connecting line M4SL corresponding to the fourth transistor M4 are all located in a closed space surrounded by the first sub-lead L021 of the second connecting lead L02, the second sub-lead L022 of the second connecting lead L02, the fourth sub-lead L024 of the second connecting lead L02 and the third sub-lead L023 of the second connecting lead L02.

[0327] Optionally, the width of the third connection lead L03 and the fourth connection lead L04 is the same as the width of the drain connection line corresponding to each transistor.

[0328] In one embodiment of the present disclosure, see Fig.13 The first sub-lead L021 of the second connecting lead L02 and the source connecting line M5SL corresponding to the fifth transistor M5 both extend along the first direction G; the local position of the first sub-lead L021 of the second connecting lead L02 can also extend along the second direction H to form a second protrusion, and the second protrusion of the first sub-lead L021 of the second connecting lead L02 extends along the second direction H to connect with the source connecting line M5SL corresponding to the fifth transistor M5, so that the side of the source connecting line M5SL corresponding to the fifth transistor M5 in the opposite direction of the second direction H is connected to the first sub-lead L021 of the second connecting lead L02. Further, one end of the second protrusion of the first sub-lead L021 of the second connection lead L02 in the first direction G is flush with one end of the source connection line M5SL corresponding to the fifth transistor M5 in the first direction G, and one end of the second protrusion of the first sub-lead L021 of the second connection lead L02 in the opposite direction of the first direction G is flush with one end of the source connection line M5SL corresponding to the fifth transistor M5 in the opposite direction of the first direction G. In this way, the length of the second protrusion of the first sub-lead L021 of the second connection lead L02 in the first direction G is the same as the length of the source connection line M5SL corresponding to the fifth transistor M5 in the first direction G. The setting of the second protrusion of the first sub-lead L021 of the second connection lead L02 can make the source connection line M5SL corresponding to the fifth transistor M5 and the first sub-lead L021 of the second connection lead L02 an integrated structure.

[0329] In one embodiment of the present disclosure, see Fig.13, the sixth connection lead L06 and the source connection line M6SL corresponding to the sixth transistor M6 both extend along the first direction G; at least a partial position of the sixth connection lead L06 can also extend in the opposite direction of the second direction H to form a first protrusion, and the first protrusion of the sixth connection lead L06 extends in the opposite direction of the second direction H to connect with the source connection line M6SL corresponding to the sixth transistor M6, so that the side of the second direction H of the source connection line M6SL corresponding to the sixth transistor M6 is connected to the sixth connection lead L06. Further, one end of the first protrusion of the sixth connection lead L06 in the first direction G is flush with one end of the source connection line M6SL corresponding to the sixth transistor M6 in the first direction G, and one end of the first protrusion of the sixth connection lead L06 in the opposite direction of the first direction G is flush with one end of the source connection line M6SL corresponding to the sixth transistor M6 in the opposite direction of the first direction G. In this way, the length of the first protrusion of the sixth connection lead L06 in the first direction G is the same as the length of the source connection line M6SL corresponding to the sixth transistor M6 in the first direction G. The first protruding portion of the sixth connection lead L06 can be arranged so that the source connection line M6SL corresponding to the sixth transistor M6 and the sixth connection lead L06 are integrated into one structure.

[0330] In one embodiment of the present disclosure, see Fig.13 , the sixth connection lead L06 and the source connection line M3SL corresponding to the third transistor M3 both extend along the first direction G; at least a partial position of the sixth connection lead L06 can also extend along the second direction H to form a second protrusion, and the second protrusion of the sixth connection lead L06 extends along the second direction H to connect with the source connection line M3SL corresponding to the third transistor M3, so that the side of the source connection line M3SL corresponding to the third transistor M3 in the opposite direction of the second direction H is connected to the sixth connection lead L06. Further, one end of the first direction G of the second protrusion of the sixth connection lead L06 is flush with one end of the first direction G of the source connection line M3SL corresponding to the third transistor M3, and one end of the second protrusion of the sixth connection lead L06 in the opposite direction of the first direction G is flush with one end of the source connection line M3SL corresponding to the third transistor M3 in the opposite direction of the first direction G. In this way, the length of the second protrusion of the sixth connection lead L06 in the first direction G is the same as the length of the source connection line M3SL corresponding to the third transistor M3 in the first direction G. The second protruding portion of the sixth connection lead L06 can be arranged so that the source connection line M3SL corresponding to the third transistor M3 and the sixth connection lead L06 are integrated into one structure.

[0331] Optionally, the width of the sixth connection lead L06 is greater than the width of the source connection line corresponding to each transistor.

[0332] Alternatively, see Fig.13The axis line of the sixth connection lead L06 along the first direction G coincides with the axis line of the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12 along the first direction G.

[0333] In one embodiment of the present disclosure, see Fig.13 The fourth sub-lead L024 of the second connecting lead L02 and the source connecting line M4SL corresponding to the fourth transistor M4 both extend along the first direction G; the local position of the fourth sub-lead L024 of the second connecting lead L02 can also extend in the opposite direction of the second direction H to form a second protrusion, and the second protrusion of the fourth sub-lead L024 of the second connecting lead L02 extends in the opposite direction of the second direction H to connect with the source connecting line M4SL corresponding to the fourth transistor M4, so that the side of the second direction H of the source connecting line M4SL corresponding to the fourth transistor M4 is connected to the fourth sub-lead L024 of the second connecting lead L02. Further, one end of the second protrusion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is flush with one end of the source connection line M4SL corresponding to the fourth transistor M4 in the first direction G, and one end of the second protrusion of the fourth sub-lead L024 of the second connection lead L02 in the opposite direction of the first direction G is flush with one end of the source connection line M4SL corresponding to the fourth transistor M4 in the opposite direction of the first direction G. In this way, the length of the second protrusion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is the same as the length of the source connection line M4SL corresponding to the fourth transistor M4 in the first direction G. The setting of the second protrusion of the fourth sub-lead L024 of the second connection lead L02 can make the source connection line M4SL corresponding to the fourth transistor M4 and the fourth sub-lead L024 of the second connection lead L02 an integrated structure.

[0334] In some embodiments, see Fig.15 The fifth connecting lead L05 includes a first sub-lead L051, a second sub-lead L052, a third sub-lead L053 and a fourth sub-lead L054 connected in sequence, and includes a fifth sub-lead L055 and a sixth sub-lead L056.

[0335] The first sub-lead L051 of the fifth connecting lead L05, the third sub-lead L053 of the fifth connecting lead L05, and the sixth sub-lead L056 of the fifth connecting lead L05 all extend along the first direction G, and all at least partially overlap with the P-type auxiliary doping region F_Pdummy.

[0336] The sixth sub-lead L056 of the fifth connecting lead L05 is located between the first sub-lead L051 of the fifth connecting lead L05 and the third sub-lead L053 of the fifth connecting lead L05, and its two ends are respectively connected to the fifth sub-lead L055 of the fifth connecting lead L05 and the fourth sub-lead L054 of the fifth connecting lead L05; the second sub-lead L052 of the fifth connecting lead L05, the fourth sub-lead L054 of the fifth connecting lead L05, and the fifth sub-lead L055 of the fifth connecting lead L05 all extend along the second direction H, and all at least partially overlap with the P-type auxiliary doping area F_Pdummy. The fifth sub-lead L055 of the fifth connecting lead L05 is located between the second sub-lead L052 of the fifth connecting lead L05 and the fourth sub-lead L054 of the fifth connecting lead L05, and its two ends are respectively connected to the first sub-lead L051 of the fifth connecting lead L05 and the third sub-lead L053 of the fifth connecting lead L05; the first sub-lead L051 to the sixth sub-lead L056 of the fifth connecting lead L05 are all connected to the P-type auxiliary doping area F_Pdummy. The third active area Act3 is located in the space surrounded by the first sub-lead L051 of the fifth connecting lead L05, the first sub-lead L052 of the fifth connecting lead L05, the third sub-lead L053 of the fifth connecting lead L05 and the fifth sub-lead L055 of the fifth connecting lead L05; the seventh sub-active area Act_sub7 is located in the space surrounded by the first sub-lead L051 of the fifth connecting lead L05, the first sub-lead L055 of the fifth connecting lead L05, the sixth sub-lead L056 of the fifth connecting lead L05 and the fourth sub-lead L054 of the fifth connecting lead L05; the eighth sub-active area Act_sub8 is located in the space surrounded by the sixth sub-lead L056 of the fifth connecting lead L05, the first sub-lead L055 of the fifth connecting lead L05, the third sub-lead L053 of the fifth connecting lead L05 and the fourth sub-lead L054 of the fifth connecting lead L05.

[0337] Further, see Fig.13The gate connection line M7GL corresponding to the seventh transistor M7 and the gate connection line M13GL corresponding to the thirteenth transistor M13 are located in a space surrounded by the first sub-lead L051 of the fifth connecting lead L05, the second sub-lead L052 of the fifth connecting lead L05, the third sub-lead L053 of the fifth connecting lead L05 and the fifth sub-lead L055 of the fifth connecting lead L05, and are located between the fifth sub-active area Act_sub5 and the sixth sub-active area Act_sub6. The gate connection line M8GL corresponding to the eighth transistor M8 and the gate connection line M14GL corresponding to the fourteenth transistor M14 are located in the space surrounded by the first sub-lead L051 of the fifth connecting lead L05, the second sub-lead L052 of the fifth connecting lead L05, the third sub-lead L053 of the fifth connecting lead L05 and the fifth sub-lead L055 of the fifth connecting lead L05, and are located between the sixth sub active area Act_sub6 and the fifth sub-lead L055 of the fifth connecting lead L05.

[0338] Further, see Fig.13 , the gate connection line M1GL corresponding to the first transistor M1 is located in a space surrounded by the first sub-lead L051 of the fifth connection lead L05, the fifth sub-lead L055 of the fifth connection lead L05, the sixth sub-lead L056 of the fifth connection lead L05 and the fourth sub-lead L054 of the fifth connection lead L05, and is located between the seventh sub-active area Act_sub7 and the fourth sub-lead L054 of the fifth connection lead L05. The gate connection line M2GL corresponding to the second transistor M2 is located in a space surrounded by the third sub-lead L053 of the fifth connection lead L05, the fifth sub-lead L055 of the fifth connection lead L05, the sixth sub-lead L056 of the fifth connection lead L05 and the fourth sub-lead L054 of the fifth connection lead L05, and is located between the eighth sub-active area Act_sub8 and the fourth sub-lead L054 of the fifth connection lead L05.

[0339] In one embodiment of the present disclosure, see Fig.13, the first sub-lead L051 of the fifth connecting lead L05 extends along the first direction G and is consistent with the extension direction of the first P-type doped sub-region F_Psub1 and the fifth P-type doped sub-region F_Psub5. The first sub-lead L051 of the fifth connecting lead L05 includes a first portion located on one side of the first direction G and a second portion located on the opposite side of the first direction G. The first portion of the first sub-lead L051 of the fifth connecting lead L05 overlaps with the fifth P-type doped sub-region F_Psub5 and is electrically connected through a plurality of first conductive pillars 351 sequentially arranged along the first direction G; the second portion of the first sub-lead L051 of the fifth connecting lead L05 overlaps with the first P-type doped sub-region F_Psub1 and is electrically connected through a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Further, see Fig.12 The second portion of the first sub-lead L051 of the fifth connection lead L05 is electrically connected to the first P-type doped sub-region F_Psub1 through two rows of first conductive pillars 351, and any row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Further, see Fig.13 The connection position between the first part and the second part of the first sub-lead L051 of the fifth connecting lead L05 is connected to an end of the fifth sub-lead L055 of the fifth connecting lead L05 in the opposite direction of the second direction H.

[0340] In one embodiment of the present disclosure, see Fig.13The second part of the first sub-lead L051 of the fifth connecting lead L05 and the first sub-connection line M7SL1 of the source connecting line corresponding to the seventh transistor M7 both extend along the first direction G; the local position of the second part of the first sub-lead L051 of the fifth connecting lead L05 can also extend along the second direction H to form a first protrusion, and the first protrusion of the first sub-lead L051 of the fifth connecting lead L05 extends along the second direction H to be connected to the first sub-connection line M7SL1 of the source connecting line corresponding to the seventh transistor M7, so that the side of the first sub-connection line M7SL1 of the source connecting line corresponding to the seventh transistor M7 in the opposite direction of the second direction H is connected to the second part of the first sub-lead L051 of the fifth connecting lead L05. Further, one end of the first protrusion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 in the first direction G, and one end of the first protrusion of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 in the opposite direction of the first direction G. In this way, the length of the first protrusion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is the same as the length of the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 in the first direction G. The setting of the first protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 and the second part of the first sub-lead L051 of the fifth connection lead L05 an integrated structure.

[0341] In one embodiment of the present disclosure, see Fig.13The second part of the first sub-lead L051 of the fifth connecting lead L05 and the first sub-connection line M8SL1 of the source connecting line corresponding to the eighth transistor M8 both extend along the first direction G; the local position of the second part of the first sub-lead L051 of the fifth connecting lead L05 can also extend along the second direction H to form a second protrusion, and the second protrusion of the first sub-lead L051 of the fifth connecting lead L05 extends along the second direction H to connect with the first sub-connection line M8SL1 of the source connecting line corresponding to the eighth transistor M8, so that the side of the first sub-connection line M8SL1 of the source connecting line corresponding to the eighth transistor M8 in the opposite direction of the second direction H is connected to the second part of the first sub-lead L051 of the fifth connecting lead L05. Further, one end of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 in the first direction G, and one end of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 in the opposite direction of the first direction G. In this way, the length of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is the same as the length of the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 in the first direction G. The setting of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 and the second part of the first sub-lead L051 of the fifth connection lead L05 an integrated structure.

[0342] In one embodiment of the present disclosure, see Fig.13, the first part of the first sub-lead L051 of the fifth connecting lead L05 and the first sub-connection line M1SL1 of the source connecting line corresponding to the first transistor M1 both extend along the first direction G; the local position of the first part of the first sub-lead L051 of the fifth connecting lead L05 can also extend along the second direction H to form a third protrusion, and the third protrusion of the first sub-lead L051 of the fifth connecting lead L05 extends along the second direction H to connect with the first sub-connection line M1SL1 of the source connecting line corresponding to the first transistor M1, so that the side of the first sub-connection line M1SL1 of the source connecting line corresponding to the first transistor M1 in the opposite direction of the second direction H is connected to the first part of the first sub-lead L051 of the fifth connecting lead L05. Further, one end of the third protrusion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1 in the first direction G, and one end of the third protrusion of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction of the first direction G is connected to the fifth sub-lead L055 of the fifth connection lead L05. In this way, the third protrusion of the first sub-lead L051 of the fifth connection lead L05 exceeds the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1 in the opposite direction of the first direction G. The setting of the third protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1 and the first part of the first sub-lead L051 of the fifth connection lead L05 an integrated structure.

[0343] In one embodiment of the present disclosure, see Fig.13 The second sub-lead L052 of the fifth connecting lead L05 extends along the second direction H and is consistent with the extending direction of the second P-type doped sub-region F_Psub2, and the two may overlap. The second sub-lead L052 of the fifth connecting lead L05 is electrically connected to the second P-type doped sub-region F_Psub2 through a plurality of first conductive pillars 351 sequentially arranged along the second direction H.

[0344] Optionally, the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 overlaps with the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13, and extends in the opposite direction of the first direction G to connect to the second sub-lead L052 of the fifth connection lead L05.

[0345] In one embodiment of the present disclosure, see Fig.13, the third sub-lead L053 of the fifth connecting lead L05 extends along the first direction G and is consistent with the extension direction of the third P-type doped sub-region F_Psub3 and the seventh P-type doped sub-region F_Psub7. The third sub-lead L053 of the fifth connecting lead L05 includes a first portion located on one side of the first direction G and a second portion located on the opposite side of the first direction G. The first portion of the third sub-lead L053 of the fifth connecting lead L05 overlaps with the seventh P-type doped sub-region F_Psub7 and is electrically connected through a plurality of first conductive pillars 351 sequentially arranged along the first direction G; the second portion of the third sub-lead L053 of the fifth connecting lead L05 overlaps with the third P-type doped sub-region F_Psub3 and is electrically connected through a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Further, the second portion of the third sub-lead L053 of the fifth connection lead L05 is electrically connected to the third P-type doped sub-region F_Psub3 through two rows of first conductive pillars 351, and any row of first conductive pillars 351 includes a plurality of first conductive pillars 351 sequentially arranged along the first direction G. Further, see Fig.13 The connection position between the first part and the second part of the third sub-lead L053 of the fifth connecting lead L05 is connected to one end of the fifth sub-lead L055 in the second direction H of the fifth connecting lead L05.

[0346] In one embodiment of the present disclosure, see Fig.13The second part of the third sub-lead L053 of the fifth connecting lead L05 and the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 both extend along the first direction G; the local position of the second part of the third sub-lead L053 of the fifth connecting lead L05 can also extend in the opposite direction of the second direction H to form a first protrusion, and the first protrusion of the third sub-lead L053 of the fifth connecting lead L05 extends in the opposite direction of the second direction H to connect with the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13, so that the side of the second direction H of the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 is connected to the second part of the third sub-lead L053 of the fifth connecting lead L05. Further, one end of the first protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 in the first direction G, and one end of the first protrusion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 in the opposite direction of the first direction G. In this way, the length of the first protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is the same as the length of the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 in the first direction G. The setting of the first protrusion of the third sub-lead L053 of the fifth connection lead L05 can make the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 and the second part of the third sub-lead L053 of the fifth connection lead L05 an integrated structure.

[0347] In one embodiment of the present disclosure, see Fig.13The second part of the third sub-lead L053 of the fifth connecting lead L05 and the first sub-connection line M14SL1 of the source connecting line corresponding to the fourteenth transistor M14 both extend along the first direction G; the local position of the second part of the third sub-lead L053 of the fifth connecting lead L05 can also extend in the opposite direction of the second direction H to form a second protrusion, and the second protrusion of the third sub-lead L053 of the fifth connecting lead L05 extends in the opposite direction of the second direction H to connect with the first sub-connection line M14SL1 of the source connecting line corresponding to the fourteenth transistor M14, so that the side of the second direction H of the first sub-connection line M14SL1 of the source connecting line corresponding to the fourteenth transistor M14 is connected to the second part of the third sub-lead L053 of the fifth connecting lead L05. Further, one end of the second protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 in the first direction G, and one end of the second protrusion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction of the first direction G is flush with one end of the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 in the opposite direction of the first direction G. In this way, the length of the second protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is the same as the length of the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 in the first direction G. The setting of the second protrusion of the third sub-lead L053 of the fifth connection lead L05 can make the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 and the second part of the third sub-lead L053 of the fifth connection lead L05 an integrated structure.

[0348] In one embodiment of the present disclosure, see Fig.13, the first part of the third sub-lead L053 of the fifth connecting lead L05 and the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 both extend along the first direction G; the local position of the first part of the third sub-lead L053 of the fifth connecting lead L05 can also extend in the opposite direction of the second direction H to form a third protrusion, and the third protrusion of the third sub-lead L053 of the fifth connecting lead L05 extends in the opposite direction of the second direction H to connect with the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2, so that the side of the second direction H of the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 is connected to the first part of the third sub-lead L053 of the fifth connecting lead L05. Further, one end of the third protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is flush with one end of the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 in the first direction G, and one end of the third protrusion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction of the first direction G is connected to the fifth sub-lead L055 of the fifth connection lead L05. In this way, the third protrusion of the third sub-lead L053 of the fifth connection lead L05 exceeds the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 in the opposite direction of the first direction G. The setting of the third protrusion of the third sub-lead L053 of the fifth connection lead L05 can make the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 and the first part of the third sub-lead L053 of the fifth connection lead L05 an integrated structure.

[0349] In one embodiment of the present disclosure, see Fig.13 , the fourth sub-lead L054 of the fifth connecting lead L05 extends along the second direction H, and is consistent with the extension direction of the sixth P-type doped sub-region F_Psub6, and the two may overlap. Among them, the fourth sub-lead L054 of the fifth connecting lead L05 is electrically connected to the sixth P-type doped sub-region F_Psub6 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H. Further, one end of the first direction G of the sixth sub-lead L056 of the fifth connecting lead L05 is connected to the middle position of the fourth sub-lead L054 of the fifth connecting lead L05. In this way, the areas of the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8 can be made substantially consistent.

[0350] In one embodiment of the present disclosure, see Fig.13, the fifth sub-lead L055 of the fifth connecting lead L05 extends along the second direction H, and is consistent with the extension direction of the fourth P-type doped sub-region F_Psub4, and the two may overlap. Among them, the fifth sub-lead L055 of the fifth connecting lead L05 is electrically connected to the fourth P-type doped sub-region F_Psub4 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H. Further, one end of the sixth sub-lead L056 of the fifth connecting lead L05 in the opposite direction of the first direction G is connected to the middle position of the fifth sub-lead L055 of the fifth connecting lead L05. In this way, the areas of the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8 can be made substantially consistent.

[0351] In one embodiment of the present disclosure, the sixth sub-lead L056 of the fifth connecting lead L05 extends along the first direction G, and is consistent with the extension direction of the eighth P-type doped sub-region F_Psub8, and the two may overlap. The sixth sub-lead L056 of the fifth connecting lead L05 is electrically connected to the eighth P-type doped sub-region F_Psub8 through a plurality of first conductive pillars 351 sequentially arranged along the first direction G.

[0352] In one embodiment of the present disclosure, see Fig.13 The sixth sub-lead L056 of the fifth connecting lead L05 and the second sub-connection line M1SL2 of the source connecting line corresponding to the first transistor M1 both extend along the first direction G; at least a partial position of the sixth sub-lead L056 of the fifth connecting lead L05 can also extend in the opposite direction of the second direction H to form a first protrusion, and the first protrusion of the sixth sub-lead L056 of the fifth connecting lead L05 extends in the opposite direction of the second direction H to be connected to the second sub-connection line M1SL2 of the source connecting line corresponding to the first transistor M1, so that the side of the second direction H of the second sub-connection line M1SL2 of the source connecting line corresponding to the first transistor M1 is connected to the sixth sub-lead L056 of the fifth connecting lead L05. Further, one end of the first protrusion of the sixth sub-lead L056 of the fifth connection lead L05 in the first direction G is flush with one end of the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1 in the first direction G, and one end of the first protrusion of the sixth sub-lead L056 of the fifth connection lead L05 in the opposite direction of the first direction G is connected to the fifth sub-lead L055 of the fifth connection lead L05. The setting of the first protrusion of the sixth sub-lead L056 of the fifth connection lead L05 can make the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1 and the sixth sub-lead L056 of the fifth connection lead L05 an integrated structure.

[0353] In one embodiment of the present disclosure, see Fig.13The sixth sub-lead L056 of the fifth connecting lead L05 and the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2 both extend along the first direction G; at least a partial position of the sixth sub-lead L056 of the fifth connecting lead L05 can also extend along the second direction H to form a second protrusion, and the second protrusion of the sixth sub-lead L056 of the fifth connecting lead L05 extends along the second direction H to be connected to the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2, so that the side of the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2 in the opposite direction of the second direction H is connected to the sixth sub-lead L056 of the fifth connecting lead L05. Further, one end of the second protrusion in the first direction G of the sixth sub-lead L056 of the fifth connection lead L05 is flush with one end of the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2 in the first direction G, and one end of the second protrusion in the opposite direction of the first direction G of the sixth sub-lead L056 of the fifth connection lead L05 is connected to the fifth sub-lead L055 of the fifth connection lead L05. The setting of the second protrusion of the sixth sub-lead L056 of the fifth connection lead L05 can make the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2 and the sixth sub-lead L056 of the fifth connection lead L05 an integrated structure.

[0354] Optionally, the width of the sixth sub-lead L056 of the fifth connecting lead L05 is greater than the width of the source connecting line corresponding to each transistor.

[0355] Alternatively, see Fig.13 The axis line of the sixth sub-lead L056 of the fifth connecting lead L05 along the first direction G coincides with the axis line of the second sub-connection line M8SL2 of the source connecting line corresponding to the eighth transistor M8 / the second sub-connection line M14SL2 of the source connecting line corresponding to the fourteenth transistor M14 along the first direction G.

[0356] Optionally, the axes along the first direction G of the drain connection line M9DL corresponding to the ninth transistor M9 , the drain connection line M10DL corresponding to the tenth transistor M10 , the drain connection line M7DL corresponding to the seventh transistor M7 , and the drain connection line M8DL corresponding to the eighth transistor M8 coincide.

[0357] Optionally, the axes along the first direction G of the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13 and the drain connection line M14DL corresponding to the fourteenth transistor M14 coincide.

[0358] Optionally, the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9 / the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11, the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12, the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 / the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13, the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8 / the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14, the sixth connection lead L06, and the sixth sub-lead L056 of the fifth connection lead L05 coincide with the axis along the first direction G.

[0359] Optionally, the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9, the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10, the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7, and the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 coincide with the axis along the first direction G.

[0360] Optionally, the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11, the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12, the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13, and the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 coincide with the axis along the first direction G.

[0361] See also Fig.17 The second metal wiring layer 362 may include a first control lead 421, a second control lead 422, a first output lead 431, a second output lead 432, and some connection leads. The connection leads located in the second metal wiring layer 362 may include seventh connection leads L07 to fifteenth connection leads L15.

[0362] The seventh connection lead L07 extends along the first direction G and overlaps with the first sub-lead L011 of the first connection lead L01 and the first sub-lead L021 of the second connection lead L02. Fig.13 , Fig.17 and Fig.18, the extension lines of the seventh connecting lead L07, the first sub-lead L011 of the first connecting lead L01, and the first sub-lead L021 of the second connecting lead L02 are basically overlapped. In this way, the seventh connecting lead L07 can be electrically connected to the first sub-lead L011 of the first connecting lead L01 through a plurality of second conductive pillars 352 arranged along the first direction G, and the seventh connecting lead L07 can be electrically connected to the first sub-lead L021 of the second connecting lead L02 through a plurality of second conductive pillars 352 arranged along the first direction G. Further, each second conductive pillar 352 connected to the seventh connecting lead L07 is arranged in a straight line along the first direction G. It can be understood that the second conductive pillar 352 may not be provided in the gap between the first sub-lead L011 of the first connecting lead L01 and the first sub-lead L021 of the second connecting lead L02.

[0363] Optionally, along the first direction G, one end of the seventh connecting lead L07 in the first direction G does not exceed one end of the first sub-lead L021 in the first direction G of the second connecting lead L02; along the opposite direction of the first direction G, one end of the seventh connecting lead L07 in the opposite direction of the first direction G exceeds one end in the opposite direction of the first direction G of the first sub-lead L011 of the first connecting lead L01.

[0364] The eighth connecting lead L08 extends along the first direction G, and overlaps with the third sub-lead L013 of the first connecting lead L01 and the fourth sub-lead L024 of the second connecting lead L02. The extension lines of the eighth connecting lead L08, the third sub-lead L013 of the first connecting lead L01, and the fourth sub-lead L024 of the second connecting lead L02 are substantially coincident. In this way, the eighth connecting lead L08 can be electrically connected to the third sub-lead L013 of the first connecting lead L01 through a plurality of second conductive pillars 352 arranged along the first direction G, and the eighth connecting lead L08 can be electrically connected to the fourth sub-lead L024 of the second connecting lead L02 through a plurality of second conductive pillars 352 arranged along the first direction G. Furthermore, each second conductive pillar 352 connected to the seventh connecting lead L07 is arranged in a straight line along the first direction G. It is understandable that the second conductive pillar 352 may not be provided in the gap between the third sub-lead L013 of the first connecting lead L01 and the fourth sub-lead L024 of the second connecting lead L02.

[0365] Optionally, along the first direction G, one end of the eighth connecting lead L08 in the first direction G does not exceed one end of the fourth sub-lead L024 in the first direction G of the second connecting lead L02; along the opposite direction of the first direction G, one end of the eighth connecting lead L08 in the opposite direction of the first direction G exceeds one end of the third sub-lead L013 in the opposite direction of the first direction G of the first connecting lead L01.

[0366] In one embodiment of the present disclosure, the second power supply voltage V2 may be loaded onto the seventh connection lead L07 and the eighth connection lead L08, and then the second power supply voltage V2 may be loaded onto the first connection lead L01 and the second connection lead L02.

[0367] See also Fig.13 , Fig.15 and Fig.17 , the ninth connection lead L09 extends along the first direction G and overlaps with the first sub-lead L051 of the fifth connection lead L05. The extension lines of the ninth connection lead L09 and the first sub-lead L051 of the fifth connection lead L05 are substantially coincident. In this way, the ninth connection lead L09 can be electrically connected to the first sub-lead L051 of the fifth connection lead L05 through the plurality of second conductive pillars 352 arranged along the first direction G.

[0368] Optionally, along the first direction G, one end of the ninth connection lead L09 in the first direction G does not exceed one end of the first sub-lead L051 of the fifth connection lead L05 in the first direction G; along the opposite direction of the first direction G, one end of the ninth connection lead L09 in the opposite direction of the first direction G exceeds one end of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction of the first direction G. Further, one end of the ninth connection lead L09 in the opposite direction of the first direction G is flush with one end of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction of the first direction G; along the first direction G, one end of the ninth connection lead L09 in the first direction G is flush with one end of the drain connection line M1DL corresponding to the first transistor M1 in the first direction G.

[0369] See also Fig.13 , Fig.15 and Fig.17 , the tenth connection lead L10 extends along the first direction G and overlaps with the third sub-lead L053 of the fifth connection lead L05. The extension lines of the tenth connection lead L10 and the third sub-lead L053 of the fifth connection lead L05 are substantially coincident. In this way, the tenth connection lead L10 can be electrically connected to the third sub-lead L053 of the fifth connection lead L05 through the plurality of second conductive pillars 352 arranged along the first direction G.

[0370] Optionally, along the first direction G, one end of the tenth connection lead L10 in the first direction G does not exceed one end of the third sub-lead L053 of the fifth connection lead L05 in the first direction G; along the opposite direction of the first direction G, one end of the tenth connection lead L10 in the opposite direction of the first direction G exceeds one end of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction of the first direction G. Further, one end of the tenth connection lead L10 in the opposite direction of the first direction G is flush with one end of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction of the first direction G; along the first direction G, one end of the tenth connection lead L10 in the first direction G is flush with one end of the drain connection line M2DL corresponding to the second transistor M2 in the first direction G.

[0371] In one embodiment of the present disclosure, the first power supply voltage V1 may be loaded onto the ninth connecting lead L09 and the tenth connecting lead L10 , and then the first power supply voltage V1 may be loaded onto the fifth connecting lead L05 .

[0372] Alternatively, see Fig.17 The seventh connection lead L07 and the ninth connection lead L09 are located on the same straight line, and the ninth connection lead L09 is located on the first direction G side of the seventh connection lead L07. The eighth connection lead L08 and the tenth connection lead L10 are located on the same straight line, and the tenth connection lead L10 is located on the first direction G side of the eighth connection lead L08.

[0373] Alternatively, see Fig.17 , the widths of the seventh connection lead L07, the eighth connection lead L08, the ninth connection lead L09 and the tenth connection lead L10 (i.e., the size in the second direction H) are the same and larger than the widths of the source connection lines corresponding to the respective transistors. In this way, the impedances of the seventh connection lead L07, the eighth connection lead L08, the ninth connection lead L09 and the tenth connection lead L10 can be reduced, thereby improving the driving capability of the row drive signal enhancement.

[0374] In some embodiments, see Fig.13 , Fig.15 and Fig.17, the eleventh connection lead L11 extends along the first direction G, overlaps with the switching line of the gate connection line M9GL corresponding to the ninth transistor M9, the switching line of the gate connection line M10GL corresponding to the tenth transistor M10, the switching line of the gate connection line M7GL corresponding to the seventh transistor M7, the drain connection line M5DL corresponding to the fifth transistor M5 / the drain connection line M6DL corresponding to the sixth transistor M6, and the drain connection line M1DL corresponding to the first transistor M1, and is connected through the second conductive column 352. Optionally, the eleventh connection lead L11 may also be provided with a switching line extending in the second direction H; the switching line of the eleventh connection lead L11 overlaps with the gate connection line M8GL corresponding to the eighth transistor M8, and is connected through the second conductive column 352.

[0375] Optionally, along the first direction G, one end of the drain connection line M1DL corresponding to the first transistor M1 is located on the first direction G side of one end of the first direction G of the eleventh connection lead L11, and one end of the eleventh connection lead L11 in the opposite direction of the first direction G is flush with one end of the gate connection line M9GL corresponding to the ninth transistor M9 in the opposite direction of the first direction G.

[0376] Optionally, the width of the eleventh connection lead L11 is the same as the width of the source connection line corresponding to each transistor.

[0377] In some embodiments, see Fig.13 , Fig.15 and Fig.17 , the twelfth connection lead L12 is arranged in a straight line along the first direction G, and overlaps with the switching line of the gate connection line M11GL corresponding to the eleventh transistor M11, the switching line of the gate connection line M12GL corresponding to the twelfth transistor M12, the switching line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the drain connection line M3DL corresponding to the third transistor M3 / the drain connection line M4DL corresponding to the fourth transistor M4, and the drain connection line M2DL corresponding to the second transistor M2, and is connected through the second conductive column 352. Optionally, the twelfth connection lead L12 may also be provided with a switching line extending in the opposite direction of the second direction H; the switching line of the twelfth connection lead L12 overlaps with the gate connection line M14GL corresponding to the fourteenth transistor M14, and is connected through the second conductive column 352.

[0378] Optionally, along the first direction G, one end of the drain connection line M2DL corresponding to the second transistor M2 is located on the first direction G side of one end of the first direction G of the twelfth connection lead L12, and one end of the twelfth connection lead L12 in the opposite direction of the first direction G is flush with one end of the gate connection line M11GL corresponding to the eleventh transistor M11 in the opposite direction of the first direction G.

[0379] Optionally, the width of the twelfth connection lead L12 is the same as the width of the source connection line corresponding to each transistor.

[0380] In some embodiments, see Fig.13 , Fig.15 and Fig.17 The thirteenth connecting lead L13 extends along the first direction G, and overlaps with the second sub-lead L012 of the first connecting lead L01, the second sub-connection line M9SL2 of the source connecting line corresponding to the ninth transistor M9 / the second sub-connection line M11SL2 of the source connecting line corresponding to the eleventh transistor M11, the second sub-connection line M10SL2 of the source connecting line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connecting line corresponding to the twelfth transistor M12, the second sub-lead L022 of the second connecting lead L02, the third connecting lead L03, the sixth connecting lead L06, the fourth connecting lead L04, and the third sub-lead L023 of the second connecting lead L02 in sequence. Among them, along the first direction G, one end of the thirteenth connecting lead L13 in the first direction G does not exceed the third sub-lead L023 of the second connecting lead L02, and one end of the thirteenth connecting lead L13 in the opposite direction of the first direction G does not exceed the second sub-lead L012 of the first connecting lead L01. Exemplarily, along the first direction G, one end of the thirteenth connecting lead L13 in the first direction G is flush with the side of the third sub-lead L023 of the second connecting lead L02 in the first direction G, and one end of the thirteenth connecting lead L13 in the opposite direction of the first direction G is flush with the side of the second sub-lead L012 of the first connecting lead L01 in the opposite direction of the first direction G.

[0381] Alternatively, see Fig.13 , Fig.15 and Fig.17The thirteenth connection lead L13 is electrically connected to the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9 / the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11, the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12, and the sixth connection lead L06 through the second conductive pillar 352. In this way, the thirteenth connection lead L13 can load the second power supply voltage V2 on the first connection lead L01 to the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12, and the sixth connection lead L06. Further, the thirteenth connecting lead L13 is electrically connected to the second sub-connection line M9SL2 of the source connecting line corresponding to the ninth transistor M9 / the second sub-connection line M11SL2 of the source connecting line corresponding to the eleventh transistor M11 through a plurality of second conductive pillars 352 arranged in sequence along the first direction G, the thirteenth connecting lead L13 is electrically connected to the second sub-connection line M10SL2 of the source connecting line corresponding to the tenth transistor M10 / the second sub-connection line M12SL2 of the source connecting line corresponding to the twelfth transistor M12 through a plurality of second conductive pillars 352 arranged in sequence along the first direction G, and the thirteenth connecting lead L13 is electrically connected to the sixth connecting lead L06 through a plurality of second conductive pillars 352 arranged in sequence along the first direction G. Furthermore, the thirteenth connecting lead L13 is electrically connected to the second sub-lead L012 of the first connecting lead L01 through a second conductive column 352, the thirteenth connecting lead L13 is electrically connected to the second sub-lead L022 of the second connecting lead L02 through a second conductive column 352, and the thirteenth connecting lead L13 is electrically connected to the third sub-lead L023 of the second connecting lead L02 through a second conductive column 352.

[0382] In one embodiment of the present disclosure, see Fig.13 , Fig.15 and Fig.17 The gate connection line M9GL corresponding to the ninth transistor M9 and the gate connection line M11GL corresponding to the eleventh transistor M11 are respectively located on both sides of the thirteenth connection lead L13 and do not overlap with the thirteenth connection lead L13; the gate connection line M10GL corresponding to the tenth transistor M10 and the gate connection line M12GL corresponding to the twelfth transistor M12 are respectively located on both sides of the thirteenth connection lead L13 and do not overlap with the thirteenth connection lead L13.

[0383] Optionally, the width of the thirteenth connection lead L13 is the same as the width of the source connection line corresponding to each transistor.

[0384] In some embodiments, see Fig.13 , Fig.15 and Fig.17 The fourteenth connection lead L14 and the fifteenth connection lead L15 are connected to each other and extend along the first direction G. The fifteenth connection lead L15 is located on one side of the fourteenth connection lead L14 in the first direction G. The axes of the fourteenth connection lead L14 and the fifteenth connection lead L15 along the first direction G coincide with each other.

[0385] The fourteenth connection lead L14 overlaps and is electrically connected to the second sub-lead L052 of the fifth connection lead L05, the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 / the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13, the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8 / the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 in sequence. Fig.15 The fourteenth connection lead L14 is electrically connected to the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 / the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13 through a plurality of second conductive pillars 352 sequentially arranged along the first direction G, and the fourteenth connection lead L14 is electrically connected to the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8 / the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 through a plurality of second conductive pillars 352 sequentially arranged along the first direction G. The fourteenth connection lead L14 and the second sub-lead L052 of the fifth connection lead L05 can be electrically connected through a second conductive pillar 352 or directly connected without the second conductive pillar 352. Of course, the second conductive column 352 directly connecting the fourteenth connecting lead L14 and the second sub-lead L052 of the fifth connecting lead L05 can also be located at the connection between the fourteenth connecting lead L14 and the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 / the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13.

[0386] Optionally, the width of the fourteenth connection lead L14 is the same as the width of the source connection line corresponding to each transistor.

[0387] The fifteenth connecting lead L15 overlaps with the sixth sub-lead L056 of the fifth connecting lead L05, and is electrically connected through the second conductive pillars 352. Exemplarily, the fifteenth connecting lead L15 is electrically connected to the sixth sub-lead L056 of the fifth connecting lead L05 through a plurality of second conductive pillars 352 arranged along the first direction G. Optionally, the sixth sub-lead L056 of the fifth connecting lead L05 has a first protrusion and a second protrusion, so that the local width of the sixth sub-lead L056 of the fifth connecting lead L05 is greater than the width of the fourteenth connecting lead L14. At this time, the width of the fifteenth connecting lead L15 can be the same as the maximum width of the sixth sub-lead L056 of the fifth connecting lead L05, and the fifteenth connecting lead L15 is electrically connected to the sixth sub-lead L056 of the fifth connecting lead L05 through two rows of second conductive pillars 352, and any row of second conductive pillars 352 includes a plurality of second conductive pillars 352 arranged along the first direction G. Furthermore, among the two rows of second conductive pillars 352 , one row of second conductive pillars 352 overlaps with the first protrusion of the fifteenth connection lead L15 , and the other row of second conductive pillars 352 overlaps with the second protrusion of the fifteenth connection lead L15 .

[0388] Optionally, one end of the fifteenth connection lead L15 in the opposite direction of the first direction G overlaps with the fifth sub-lead L055 of the fifth connection lead L05 , and is electrically connected to the fifth sub-lead L055 of the fifth connection lead L05 through the second conductive column 352 .

[0389] Optionally, one end of the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1 in the first direction G is located on the first direction G side of one end of the fifteenth connection lead L15 in the first direction G. Further, one end of the fifteenth connection lead L15 in the first direction G is flush with one end of the eleventh connection lead L11 and the twelfth connection lead L12 in the first direction G.

[0390] See also Fig.13 , Fig.15 and Fig.17The first output lead 431 extends along the first direction G, and is electrically connected to the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8 through the second conductive column 352. In one embodiment of the present disclosure, the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8 extend in a straight line along the first direction G and are located in the same straight line; the extension direction of the first output lead 431 coincides with the extension direction of the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8, and overlaps with the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8, and are respectively connected through a plurality of second conductive pillars 352 arranged along the first direction G; these second conductive pillars 352 can be located in the same straight line.

[0391] Alternatively, see Fig.13 , Fig.15 and Fig.17 , along the opposite direction of the first direction G, one end of the first output lead 431 in the opposite direction of the first direction G exceeds the second sub-lead L012 of the first connecting lead L01, so that the first output lead 431 serves as the second output terminal OUT2 of the row drive signal enhancement circuit 101, and outputs the first scanning signal to the display area D of the display panel.

[0392] Alternatively, see Fig.13 , Fig.15 and Fig.17The second output lead 432 extends along the first direction G and is electrically connected to the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line M14DL corresponding to the fourteenth transistor M14 through the second conductive column 352. In one embodiment of the present disclosure, the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13 and the drain connection line M14DL corresponding to the fourteenth transistor M14 extend in a straight line along the first direction G and are located in the same straight line; the extension direction of the second output lead 432 coincides with the extension direction of the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13 and the drain connection line M14DL corresponding to the fourteenth transistor M14, and are respectively connected through a plurality of second conductive columns 352 arranged along the first direction G, and these second conductive columns 352 can be located in the same straight line.

[0393] Optionally, along the opposite direction of the first direction G, one end of the second output lead 432 in the opposite direction of the first direction G exceeds the second sub-lead L012 of the first connecting lead L01, so that the second output lead 432 serves as the second output terminal OUT2 of the row drive signal enhancement circuit 101, and outputs the second scanning signal to the display area D of the display panel.

[0394] See also Fig.13 , Fig.15 and Fig.17 The first control lead 421 is located at the first direction G side of the drain connection line M1DL corresponding to the first transistor M1, and is electrically connected to the gate connection line M1GL corresponding to the first transistor M1 through the second conductive column 352. In this way, the first control lead 421 can serve as the first input terminal IN1 of the row drive signal enhancement circuit 101 to input the first initial scanning signal to the row drive signal enhancement circuit 101.

[0395] Optionally, the first control lead 421 extends along the first direction G, and one end of the first direction G is located on the first direction G side of the fourth sub-lead L054 of the fifth connecting lead L05 so that it can receive the first initial scanning signal. The end of the first control lead 421 in the opposite direction of the first direction G is flush with the gate connection line M1GL corresponding to the first transistor M1. Further, the end of the first control lead 421 in the opposite direction of the first direction G has a connecting portion, and the connecting portion of the first control lead 421 extends in the opposite direction of the second direction H and overlaps with the gate connection line M1GL corresponding to the first transistor M1, and is connected to the gate connection line M1GL corresponding to the first transistor M1 through the second conductive column 352. In this way, the conductive area between the first control lead 421 and the gate connection line M1GL corresponding to the first transistor M1 can be increased, thereby reducing the delay of the row drive signal enhancement circuit 101.

[0396] See also Fig.13 , Fig.15 and Fig.17 The second control lead 422 is located at the first direction G side of the drain connection line M2DL corresponding to the second transistor M2, and is electrically connected to the gate connection line M2GL corresponding to the second transistor M2 through the second conductive column 352. In this way, the second control lead 422 can serve as the second input terminal IN2 of the row drive signal enhancement circuit 101 to input the second initial scanning signal to the row drive signal enhancement circuit 101.

[0397] Optionally, the second control lead 422 extends along the first direction G, and one end of the first direction G is located on the first direction G side of the fourth sub-lead L054 of the fifth connecting lead L05 so that it can receive the second initial scanning signal. The end of the second control lead 422 in the opposite direction of the first direction G is flush with the gate connection line M2GL corresponding to the second transistor M2. Further, the end of the second control lead 422 in the opposite direction of the first direction G has a connecting portion, and the connecting portion of the second control lead 422 extends along the second direction H and overlaps with the gate connection line M2GL corresponding to the second transistor M2, and is connected to the gate connection line M2GL corresponding to the second transistor M2 through the second conductive column 352. In this way, the conductive area between the second control lead 422 and the gate connection line M2GL corresponding to the second transistor M2 can be increased, thereby reducing the delay of the row drive signal enhancement circuit 101.

[0398] It is understandable that other leads or conductive structures may be provided in the row drive signal enhancement area F, and these leads or conductive structures may not constitute the row drive signal enhancement circuit 101 but only pass through the row drive signal enhancement area F, or adjust the parasitic capacitance, parasitic resistance, etc. at different positions in the row drive signal enhancement circuit 101. For example, see Fig.13 , Fig.15 and Fig.17 , the second metal wiring layer 362 may also have a sixteenth connection lead L16 and a seventeenth connection lead L17, the sixteenth connection lead L16 and the seventeenth connection lead L17 extend along the first direction G and their extension axes coincide. The sixteenth connection lead L16 penetrates the N-type substrate area F_Ndop along the first direction G and is located between the eighth connection lead L08 and the twelfth connection lead L12. The seventeenth connection lead L17 penetrates the P-type substrate area F_Pdop along the first direction G and is located between the tenth connection lead L10 and the twelfth connection lead L12. In the row drive signal enhancement area F, the sixteenth connection lead L16 and the seventeenth connection lead L17 are not electrically connected to any second conductive pillar 352 and the third conductive pillar 353, so that the sixteenth connection lead L16 and the seventeenth connection lead L17 are located in the row drive signal enhancement area F but do not constitute a part of the row drive signal enhancement circuit 101.

[0399] See also Fig.17 , Fig.19 and Fig. 20 , the third metal wiring layer 363 may be provided with a first power lead 411 and a second power lead 412. The first power lead 411 overlaps with the ninth connection lead L09 and the tenth connection lead L10, and is electrically connected through the third conductive pillar 353. Further, the first power lead 411 overlaps with the fourteenth connection lead L14 and the fifteenth connection lead L15, and is electrically connected through the third conductive pillar 353. In one embodiment of the present disclosure, the first power lead 411 covers the third active area Act3 and the fourth active area Act4 to shield the interference of external signals to the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, the fourteenth transistor M14, the first transistor M1, and the second transistor M2.

[0400] For example, see Fig.19 , Fig. 20 and Fig.21 The first power lead 411 has two sides that are oppositely arranged and extend along the second direction H, wherein the side on the first direction G is flush with the first direction G end of the ninth connection lead L09, and the side on the opposite direction of the first direction G is flush with the opposite direction of the first direction G end of the ninth connection lead L09. In one embodiment of the present disclosure, see Fig.24The display panel includes a plurality of row signal driving enhancement regions F sequentially arranged along the second direction H, and a row signal driving enhancement circuit is disposed in any row signal driving enhancement region F. Each row signal driving enhancement circuit may share the same first power lead 411, which extends along the second direction H to cover the third active region Act3 and the fourth active region Act4 of each row signal driving enhancement region, and is electrically connected to the ninth connecting lead L09, the tenth connecting lead L10, the fourteenth connecting lead L14, and the fifteenth connecting lead L15 in each row signal driving enhancement region F through the third conductive column 353.

[0401] See also Fig.19 , Fig. 20 and Fig.21 , the second power lead 412 overlaps with the seventh connection lead L07 and the eighth connection lead L08, and is electrically connected through the third conductive pillar 353. Further, the second power lead 412 overlaps with the thirteenth connection lead L13, and is electrically connected through the third conductive pillar 353. In one embodiment of the present disclosure, the second power lead 412 covers the first active area Act1 and the second active area Act2 to shield the interference of external signals to the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6.

[0402] In one embodiment of the present disclosure, see Fig.24 The display panel includes a plurality of row signal driving enhancement regions F arranged in sequence along the second direction H, and a row signal driving enhancement circuit is disposed in any row signal driving enhancement region. Each row signal driving enhancement circuit may share the same second power lead 412, which extends along the second direction H to cover the first active region Act1 and the second active region Act2 of each row signal driving enhancement region, and is electrically connected to the seventh connection lead L07, the eighth connection lead L08, and the fourteenth connection lead L14 in each row signal driving enhancement region through the third conductive column 353.

[0403] In one embodiment of the present disclosure, the number of the second power leads 412 is two, and both of the second power leads 412 extend along the second direction H. The second power lead 412 on the side of the first direction G covers the second sub-active region Act_sub2 and the second active region Act2, and its edge on the side of the first direction G is on the side of the first direction G of the third sub-lead L023 of the second connecting lead L02, and its edge in the opposite direction of the first direction G is on the side of the opposite direction of the first direction G of the first sub-lead L021 of the second connecting lead L02. The second power lead 412 on the side of the opposite direction of the first direction G overlaps with the first sub-active region Act_sub1, and its edge on the side of the first direction G is flush with one end of the drain connecting line M9DL corresponding to the ninth transistor M9 in the first direction G, and its edge on the side of the opposite direction of the first direction G is flush with the edge of the second sub-lead L012 of the first connecting lead L01 in the opposite direction of the first direction G. The two second power leads 412 are both extended along the second direction H to sequentially penetrate a plurality of row signal driving enhancement regions F arranged in a straight line along the second direction H.

[0404] Optionally, two adjacent row signal driving enhancement circuits along the second direction H may share a portion of the metal wiring layer and a portion of the conductive pillars; correspondingly, two adjacent row signal driving enhancement regions along the second direction H may share a portion of the area.

[0405] For example, each row of signal driving enhancement regions F may be numbered in sequence along the second direction H, wherein the third N-type doping sub-region F_Nsub3 of the signal driving enhancement region of the previous row may be connected to the first N-type doping sub-region F_Nsub1 of the signal driving enhancement region of the next row to form an integrated structure and be axially symmetrically arranged, or the third N-type doping sub-region F_Nsub3 of the signal driving enhancement region of the previous row and the first N-type doping sub-region F_Nsub1 of the signal driving enhancement region of the next row may be considered to be the same N-type doping sub-region. Correspondingly, the seventh N-type doping sub-region F_Nsub7 of the signal driving enhancement region of the previous row may be connected to the fifth N-type doping sub-region F_Nsub5 of the signal driving enhancement region of the next row to form an integrated structure and be axially symmetrically arranged, or the seventh N-type doping sub-region F_Nsub7 of the signal driving enhancement region of the previous row and the fifth N-type doping sub-region F_Nsub5 of the signal driving enhancement region of the next row may be considered to be the same N-type doping sub-region. The third P-type doped sub-region F_Psub3 of the signal drive enhancement region of the previous row can be connected to the first P-type doped sub-region F_Psub1 of the signal drive enhancement region of the next row to form an integrated structure and be axially symmetrical, or the third P-type doped sub-region F_Psub3 of the signal drive enhancement region of the previous row and the first P-type doped sub-region F_Psub1 of the signal drive enhancement region of the next row can be considered to be the same P-type doped sub-region. The seventh P-type doped sub-region F_Psub7 of the signal drive enhancement region of the previous row can be connected to the fifth P-type doped sub-region F_Psub5 of the signal drive enhancement region of the next row to form an integrated structure and be axially symmetrical, or the seventh P-type doped sub-region F_Psub7 of the signal drive enhancement region of the previous row and the fifth P-type doped sub-region F_Psub5 of the signal drive enhancement region of the next row can be considered to be the same P-type doped sub-region.

[0406] For another example, each row of signal driving enhancement circuits may be numbered in sequence along the second direction H. Among them, the third sub-lead L013 of the first connecting lead L01 of the signal driving enhancement circuit of the previous row may be connected to the first sub-lead L011 of the first connecting lead L01 of the signal driving enhancement circuit of the next row to form an integrated structure and be axially symmetrically arranged, or the third sub-lead L013 of the first connecting lead L01 of the signal driving enhancement circuit of the previous row and the first sub-lead L011 of the first connecting lead L01 of the signal driving enhancement circuit of the next row may be considered to be the same sub-lead.

[0407] The fourth sub-lead L024 of the second connecting lead L02 of the signal driving enhancement circuit in the previous row can be connected to the first sub-lead L021 of the second connecting lead L02 of the signal drivi...

Claims

1. A row drive signal enhancement circuit, comprising: A control unit having a first control terminal and a second control terminal, configured to input a first power supply voltage to one of the first node and the second node and input a second power supply voltage to the other node under the control of the first control terminal and the second control terminal; a first output unit, connected to the first node and a first output terminal, and configured to output one of the first power supply voltage and the second power supply voltage to the first output terminal under the control of the first node; a second output unit, connected to the second node and the second output terminal, for outputting the other of the first power supply voltage and the second power supply voltage to the second output terminal under the control of the second node; The control unit comprises: A first control unit, having the first control end and the second control end, configured to output the first power supply voltage to the first node or the second node under the control of the first control end and the second control end; a second control unit connected to the first node and the second node, configured to output the second power supply voltage to the second node in response to the first power supply voltage loaded on the first node, and to output the second power supply voltage to the first node in response to the first power supply voltage loaded on the second node; The first control unit comprises: a first transistor having a first end for loading the first power supply voltage, a second end connected to the first node, and a control end serving as the first control end; the first transistor is used to output the first power supply voltage to the first node under the control of the control end of the first transistor; a second transistor having a first end for loading the first power supply voltage, a second end connected to the second node, and a control end serving as the second control end; the second transistor is used to output the first power supply voltage to the second node under the control of the control end of the second transistor; The first transistor and the second transistor are of the same type; The second control unit comprises: a third transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second node; the third transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node; a fourth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second node; the fourth transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node; a fifth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first node; the fifth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node; a sixth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first node; the sixth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node; The third to sixth transistors are of the same type.

2. The row drive signal enhancement circuit according to claim 1, wherein: The first output unit comprises: A seventh transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal serving as the first output terminal; An eighth transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal connected to the first output terminal; a ninth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal; a tenth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal; The second output unit comprises: an eleventh transistor having a control terminal connected to the second node, a first terminal for applying the second power supply voltage, and a second terminal serving as the second output terminal; a twelfth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second output terminal; a thirteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal; a fourteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal; Among them, any one of the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor is used to be turned on in response to one of the first power supply voltage and the second power supply voltage loaded on its control terminal, and any one of the ninth transistor to the twelfth transistor is used to be turned on in response to the other of the first power supply voltage and the second power supply voltage loaded on its control terminal.

3. A shift register unit, comprising a shift register, an inverter and the row drive signal enhancement circuit according to any one of claims 1 to 2; in, The shift register is used to output an initial scanning signal to the input end of the inverter and the first control end of the row drive signal enhancement circuit; the output end of the inverter is connected to the second control end of the row drive signal enhancement circuit.

4. A display panel comprising the shift register unit according to claim 3.

5. A display panel, wherein: The display panel comprises a driving backplane and a display layer stacked on the driving backplane; the driving backplane comprises a semiconductor substrate, a gate insulating layer, a gate layer, an insulating dielectric layer and a metal wiring layer stacked in sequence; the display panel comprises a display area and a peripheral area surrounding the display area, and a plurality of row driving signal enhancement areas are arranged in the peripheral area; In any of the row drive signal enhancement areas, the drive backplane is provided with a row drive signal enhancement circuit including a first transistor to a fourteenth transistor; wherein the first transistor and the second transistor are of the same type; the seventh transistor, the eighth transistor, the thirteenth transistor and the fourteenth transistor are of the same type; the ninth transistor to the twelfth transistor are of the same type and are opposite to the type of the seventh transistor; the third transistor to the sixth transistor are of the same type; the semiconductor substrate is formed with active areas of each transistor, and the active area of ​​any transistor includes a channel area, a source and a drain on both sides of the channel area; the gate layer is formed with gates of each transistor, and the gate insulating layer isolates the gate and the channel area of ​​any transistor; the insulating dielectric layer covers the gate layer; In one of the row drive signal enhancement areas, the metal wiring layer is provided with a connecting lead, a first power lead, a second power lead, a first control lead, a second control lead, a first output lead, and a second output lead; the connecting lead is electrically connected to the source, drain, and gate of each transistor through a conductive column located in the insulating dielectric layer; wherein the connecting lead electrically connects the gate of the first transistor to the first control lead, and electrically connects the gate of the second transistor to the second control lead, and electrically connects the source of the first transistor, the source of the second transistor, the source of the seventh transistor, the source of the eighth transistor, the source of the thirteenth transistor, and the source of the fourteenth transistor to the first power lead, and electrically connects the third transistor to the sixth transistor The source of the transistor and the source of the ninth to twelfth transistors are electrically connected to the second power lead, and the drains of the seventh to tenth transistors are electrically connected to the first output lead, and the drains of the eleventh to fourteenth transistors are electrically connected to the second output lead, and the drain of the first transistor, the drain of the fifth transistor, the drain of the sixth transistor, the gate of the third transistor, the gate of the fourth transistor, and the gates of the seventh to tenth transistors are electrically connected to each other, and the drain of the second transistor, the drain of the third transistor, the drain of the fourth transistor, the gate of the fifth transistor, the gate of the sixth transistor, and the gates of the eleventh to fourteenth transistors are electrically connected to each other.

6. The display panel according to claim 5, wherein: The first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor are all N-type transistors, and the third to sixth transistors and the ninth to twelfth transistors are all P-type transistors.

7. The display panel according to claim 6, wherein: Any one of the row drive signal enhancement regions includes a P-type substrate region and an N-type substrate region, the P-type substrate region is located on one side of a first direction of the N-type substrate region, the first direction being a direction away from the display region; the N-type transistor is formed in the P-type substrate region, and the P-type transistor is formed in the N-type substrate region.

8. The display panel according to claim 7, wherein: The N-type substrate region includes an N-type auxiliary doping region, and includes a first active region and a second active region respectively surrounded by the N-type auxiliary doping region; the second active region is located on one side of the first active region in the first direction; The first active area includes a first sub-active area and a second sub-active area sequentially arranged along the first direction; the ninth transistor and the eleventh transistor are located in the first sub-active area, and the tenth transistor and the twelfth transistor are located in the second sub-active area; The second active region includes a third sub-active region and a fourth sub-active region arranged in sequence along a second direction; the second direction is perpendicular to the first direction and parallel to the plane where the semiconductor substrate is located; the fifth transistor and the sixth transistor are located in the third sub-active region, and the third transistor and the fourth transistor are located in the fourth sub-active region.

9. The display panel according to claim 8, wherein: The P-type substrate region includes a P-type auxiliary doping region, a third active region and a fourth active region; the fourth active region is located on one side of the third active region in the first direction; The third active region is surrounded by the P-type auxiliary doping region and includes a fifth sub-active region and a sixth sub-active region sequentially arranged along the first direction; the seventh transistor and the thirteenth transistor are located in the fifth sub-active region, and the eighth transistor and the fourteenth transistor are located in the sixth sub-active region; The fourth active region includes a seventh sub-active region and an eighth sub-active region which are arranged in sequence along the second direction and are respectively surrounded by the P-type auxiliary doping region; the first transistor is located in the seventh sub-active region, and the second transistor is located in the eighth sub-active region.

10. The display panel according to claim 9, wherein: The insulating dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially stacked on the gate layer, and the metal wiring layer comprises a first metal wiring layer located between the first dielectric layer and the second dielectric layer, a second metal wiring layer located between the second dielectric layer and the third dielectric layer, and a third metal wiring layer located on a surface of the third dielectric layer away from the semiconductor substrate; The conductive pillars include a first conductive pillar penetrating the first dielectric layer, a second conductive pillar penetrating the second dielectric layer, and a third conductive pillar penetrating the third dielectric layer; the first metal wiring layer is connected to the semiconductor substrate and the gate layer through the first conductive pillars; the second metal wiring layer is connected to the first metal wiring layer through the second conductive pillars; the third metal wiring layer is connected to the second metal wiring layer through the third conductive pillars; Wherein, the first metal wiring layer includes some connecting leads; the connecting leads located in the first metal wiring layer include the first connecting lead to the sixth connecting lead, and also include the gate connecting lines, source connecting lines and drain connecting lines corresponding to the first transistor to the fourteenth transistor respectively; the gate connecting line corresponding to any transistor is connected to the gate of the transistor; the source connecting line corresponding to any transistor is connected to the source of the transistor; and the drain connecting line corresponding to any transistor is connected to the drain of the transistor; The source connection line corresponding to the ninth transistor and the source connection line corresponding to the eleventh transistor are connected to the first connection lead; The source connection line corresponding to the tenth transistor includes a first sub-connection line and a second sub-connection line; the source connection line corresponding to the twelfth transistor includes a first sub-connection line and a second sub-connection line; the first sub-connection line of the source connection line corresponding to the tenth transistor, the first sub-connection line of the source connection line corresponding to the twelfth transistor, the source connection line corresponding to the fifth transistor, and the source connection line corresponding to the fourth transistor are connected to the second connection lead; The drain connection line corresponding to the third transistor, the drain connection line corresponding to the fourth transistor, the gate connection line corresponding to the fifth transistor, and the gate connection line corresponding to the sixth transistor are connected to the third connection lead; The drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the gate connection line corresponding to the third transistor, and the gate connection line corresponding to the fourth transistor are connected to the fourth connection lead; The source connection line corresponding to the eighth transistor includes a first sub-connection line and a second sub-connection line; the source connection line corresponding to the fourteenth transistor includes a first sub-connection line and a second sub-connection line; the first sub-connection line of the source connection line corresponding to the eighth transistor, the first sub-connection line of the source connection line corresponding to the fourteenth transistor, the source connection line corresponding to the seventh transistor, the source connection line corresponding to the thirteenth transistor, the source connection line corresponding to the first transistor, and the source connection line corresponding to the second transistor are connected to the fifth connection lead; The source connection line corresponding to the third transistor and the source connection line corresponding to the sixth transistor are connected to the sixth connection lead; The second metal wiring layer includes a first control lead, a second control lead, a first output lead, a second output lead and some connecting leads; the connecting leads located in the second metal wiring layer include the seventh connecting lead to the fifteenth connecting lead; The first connecting lead and the second connecting lead are connected to the seventh connecting lead, and the first connecting lead and the second connecting lead are connected to the eighth connecting lead; The fifth connecting lead is connected to the ninth connecting lead and the tenth connecting lead; The gate connection line corresponding to the ninth transistor, the gate connection line corresponding to the tenth transistor, the drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the gate connection line corresponding to the seventh transistor, the gate connection line corresponding to the eighth transistor, and the drain connection line corresponding to the first transistor are connected to the eleventh connection lead; The gate connection line corresponding to the eleventh transistor, the gate connection line corresponding to the twelfth transistor, the drain connection line corresponding to the third transistor, the drain connection line corresponding to the fourth transistor, the gate connection line corresponding to the thirteenth transistor, the gate connection line corresponding to the fourteenth transistor, and the drain connection line corresponding to the second transistor are connected to the twelfth connection lead; The first connection lead, the source connection line corresponding to the ninth transistor, the source connection line corresponding to the eleventh transistor, the second sub-connection line of the source connection line corresponding to the tenth transistor, the second sub-connection line of the source connection line corresponding to the twelfth transistor, the sixth connection lead and the thirteenth connection lead are connected; The source connection line corresponding to the seventh transistor, the second sub-connection line of the source connection line corresponding to the eighth transistor, the source connection line corresponding to the thirteenth transistor, the second sub-connection line of the source connection line corresponding to the fourteenth transistor, the fifth connection lead and the fourteenth connection lead are connected; The fifth connecting lead is connected to the fifteenth connecting lead; The drain connection line corresponding to the seventh transistor, the drain connection line corresponding to the eighth transistor, the drain connection line corresponding to the ninth transistor, and the drain connection line corresponding to the tenth transistor are connected to the first output lead; The drain connection line corresponding to the eleventh transistor, the drain connection line corresponding to the twelfth transistor, the drain connection line corresponding to the thirteenth transistor, and the drain connection line corresponding to the fourteenth transistor are connected to the second output lead; The gate connection line corresponding to the first transistor is connected to the first control lead, and the gate connection line corresponding to the second transistor is connected to the second control lead; The third metal wiring layer includes a first power lead for loading a first power supply voltage, and a second power lead for loading a second power supply voltage; the ninth connecting lead, the tenth connecting lead, the fourteenth connecting lead, and the fifteenth connecting lead are connected to the first power lead; the seventh connecting lead, the eighth connecting lead, and the thirteenth connecting lead are connected to the second power lead.

11. The display panel according to claim 10, wherein: In any of the row drive signal enhancement regions, source connection lines and drain connection lines corresponding to each transistor extend along the first direction, and gates of each transistor extend along the first direction.

12. The display panel according to claim 11, wherein: The first connecting lead comprises a first sub-lead, a second sub-lead and a third sub-lead which are connected in sequence; the first sub-lead of the first connecting lead and the third sub-lead of the first connecting lead extend along the first direction and overlap at least partially with the N-type auxiliary doping region; the second sub-lead of the first connecting lead extends along the second direction and overlaps at least partially with the N-type auxiliary doping region; the first sub-lead of the first connecting lead, the second sub-lead of the first connecting lead and the third sub-lead of the first connecting lead are all connected to the N-type auxiliary doping region; the first sub-active region is located in a space surrounded by the first connecting lead; The source connection line corresponding to the ninth transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the ninth transistor and extending along the first direction; the source connection line corresponding to the eleventh transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the eleventh transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the ninth transistor is connected to the first sub-lead of the first connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the eleventh transistor is connected to the third sub-lead of the first connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the ninth transistor and the second sub-connection line of the source connection line corresponding to the eleventh transistor are the same lead, and extend in the opposite direction of the first direction to be connected to the second sub-lead of the first connection lead; The seventh connecting lead is connected to the first sub-lead of the first connecting lead; the eighth connecting lead is connected to the third sub-lead of the first connecting lead; and the thirteenth connecting lead is connected to the second sub-lead of the first connecting lead.

13. The display panel according to claim 12, wherein: The second connecting lead includes a first sub-lead, a third sub-lead and a fourth sub-lead connected in sequence, and includes a second sub-lead; wherein the first sub-lead of the second connecting lead and the fourth sub-lead of the second connecting lead both extend along the first direction and at least partially overlap with the N-type auxiliary doping region; the second sub-lead of the second connecting lead and the third sub-lead of the second connecting lead both extend along the second direction and at least partially overlap with the N-type auxiliary doping region; the first sub-lead to the fourth sub-lead of the second connecting lead are all connected to the N-type auxiliary doping region; The second sub-active region is located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, and the fourth sub-lead of the second connecting lead, and the second active region is located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, the third sub-lead of the second connecting lead, and the fourth sub-lead of the second connecting lead; The first sub-connection line of the source connection line corresponding to the tenth transistor extends along the first direction, and its side in the opposite direction of the first direction is connected to the first sub-lead of the second connection lead; the first sub-connection line of the source connection line corresponding to the twelfth transistor extends along the first direction, and its side in the first direction is connected to the fourth sub-lead of the second connection lead; the second sub-connection line of the source connection line corresponding to the tenth transistor and the second sub-connection line of the source connection line corresponding to the twelfth transistor are the same lead and extend along the first direction.

14. The display panel according to claim 13, wherein: The fifth connecting lead includes a first sub-lead, a second sub-lead, a third sub-lead and a fourth sub-lead connected in sequence, and includes a fifth sub-lead and a sixth sub-lead; The first sub-lead, the third sub-lead and the sixth sub-lead of the fifth connecting lead all extend along the first direction and at least partially overlap with the P-type auxiliary doping region; the sixth sub-lead of the fifth connecting lead is located between the first sub-lead and the third sub-lead, and its two ends are respectively connected to the fifth sub-lead and the fourth sub-lead; The second sub-lead, the fourth sub-lead, and the fifth sub-lead of the fifth connecting lead all extend in the second direction, and at least partially overlap with the P-type auxiliary doping region; the fifth sub-lead of the fifth connecting lead is located between the second sub-lead and the fourth sub-lead, and its two ends are respectively connected to the first sub-lead and the third sub-lead; the first sub-lead to the sixth sub-lead of the fifth connecting lead are all connected to the P-type auxiliary doping region; The third active region is located in a space surrounded by the first sub-lead, the second sub-lead, the third sub-lead and the fifth sub-lead of the fifth connecting lead; the seventh sub-active region is located in a space surrounded by the first sub-lead, the fifth sub-lead, the sixth sub-lead and the fourth sub-lead of the fifth connecting lead; the eighth sub-active region is located in a space surrounded by the sixth sub-lead, the fifth sub-lead, the third sub-lead and the fourth sub-lead of the fifth connecting lead; The source connection line corresponding to the seventh transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the seventh transistor and extending along the first direction; the source connection line corresponding to the thirteenth transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the thirteenth transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the seventh transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the thirteenth transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the seventh transistor and the second sub-connection line of the source connection line corresponding to the thirteenth transistor are the same lead, and extend along the first direction to be connected to the second sub-lead of the fifth connection lead; The first sub-connection line of the source connection line corresponding to the eighth transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the first sub-connection line of the source connection line corresponding to the fourteenth transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the eighth transistor and the second sub-connection line of the source connection line corresponding to the fourteenth transistor are the same lead; The source connection line corresponding to the first transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the first transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the first transistor is connected to the first sub-lead of the fifth connection lead on one side in the opposite direction of the second direction; the second sub-connection line of the source connection line corresponding to the first transistor is connected to the sixth sub-lead of the fifth connection lead on one side in the second direction; The source connection line corresponding to the second transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the second transistor and extending along the first direction; the first sub-connection line of the source connection line corresponding to the second transistor is connected to the third sub-lead of the fifth connection lead on one side in the second direction; the second sub-connection line of the source connection line corresponding to the second transistor is connected to the sixth sub-lead of the fifth connection lead on one side in the opposite direction of the second direction.

15. The display panel according to claim 14, wherein: The third connecting lead, the fourth connecting lead and the sixth connecting lead are located in a space surrounded by the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, the third sub-lead of the second connecting lead and the fourth sub-lead of the second connecting lead; wherein the third connecting lead and the fourth connecting lead extend along the second direction, and the sixth connecting lead extends along the first direction; The second direction side of the source connection line corresponding to the sixth transistor is connected to the sixth connection lead, and the opposite direction side of the second direction of the source connection line corresponding to the third transistor is connected to the sixth connection lead; The drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the sixth transistor are the same lead, and one end is connected to one end of the fourth connection lead; the gate connection line corresponding to the third transistor and the gate connection line corresponding to the fourth transistor are the same lead, and one end is connected to the other end of the fourth connection lead; The drain connection line corresponding to the third transistor and the drain connection line corresponding to the fourth transistor are the same lead, and one end is connected to one end of the third connection lead; the gate connection line corresponding to the fifth transistor and the gate connection line corresponding to the sixth transistor are the same lead, and one end is connected to the other end of the third connection lead.

16. The display panel according to claim 15, wherein: The seventh connecting lead extends along the first direction and is connected to the first sub-lead of the first connecting lead and the first sub-lead of the second connecting lead; The eighth connecting lead extends along the first direction and is connected to the third sub-lead of the first connecting lead and the fourth sub-lead of the second connecting lead; The ninth connecting lead extends along the first direction and is electrically connected to the first sub-lead of the fifth connecting lead; The tenth connecting lead extends along the first direction and is connected to the third sub-lead of the fifth connecting lead; The drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the first transistor are located in the same straight line, and the orthographic projection of the extension axis on the semiconductor substrate coincides with the orthographic projection of the extension axis of the eleventh connection lead on the semiconductor substrate; The drain connection line corresponding to the third transistor and the drain connection line corresponding to the second transistor are located in the same straight line, and the orthographic projections of the extension axes on the semiconductor substrate coincide with the orthographic projections of the extension axes of the twelfth connection lead on the semiconductor substrate; The orthographic projection of the extension axis of the thirteenth connecting lead on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connecting line of the source connecting line corresponding to the ninth transistor on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connecting line of the source connecting line corresponding to the tenth transistor on the semiconductor substrate, and the orthographic projection of the extension axis of the sixth connecting lead on the semiconductor substrate coincide with each other; The orthographic projection of the extension axis of the second sub-connection line of the source connection line corresponding to the seventh transistor on the semiconductor substrate, the orthographic projection of the extension axis of the second sub-connection line of the source connection line corresponding to the eighth transistor on the semiconductor substrate, the orthographic projection of the extension axis of the sixth sub-lead of the fifth connection lead on the semiconductor substrate, the orthographic projection of the extension axis of the fourteenth connection lead on the semiconductor substrate and the orthographic projection of the extension axis of the fifteenth connection lead on the semiconductor substrate coincide with each other.

17. The display panel according to claim 10, wherein: The first power lead covers the third active area and the fourth active area; the second power lead covers the first active area and the second active area.

18. The display panel according to claim 5, wherein: The display panel is further provided with a pixel driving circuit in the display area, and the pixel driving circuit includes a data writing unit, a storage capacitor and a driving transistor; The data writing unit has a first control electrode and a second control electrode, the first control electrode of the data writing unit is connected to the first output lead, the second control electrode of the data writing unit is connected to the second output lead, the input end of the data writing unit is connected to the data line of the display panel, and the output end of the data writing unit is connected to the third node; The first electrode plate of the storage capacitor is connected to the third node, and the second electrode plate of the storage capacitor is used to load the first driving voltage; The control end of the driving transistor is connected to the third node, the output end of the driving transistor is connected to the light-emitting element of the display panel, and the input end of the driving transistor can be loaded with a second driving voltage.

19. The display panel according to claim 18, wherein: The first power lead is used to load the first driving voltage; the second power lead is used to load the second driving voltage.

20. The display panel according to claim 5, wherein: The display panel is further provided with a plurality of shift registers and a plurality of inverters in a peripheral area, which are arranged one-to-one corresponding to each of the row drive signal enhancement circuits; In the row drive signal enhancement circuit, the shift register and the inverter that correspond to each other, the output end of the shift register is connected to the input end of the inverter and the first control lead of the row drive signal enhancement circuit, and the output end of the inverter is connected to the second control lead of the row drive signal enhancement circuit.

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