Reference signal time of arrival estimation method, apparatus and chip

Abstract

A method, apparatus, and chip for estimating the time of arrival (TOA) of a reference signal are disclosed to improve the positioning accuracy of wireless communication devices with limited supported bandwidth. In this application, a first wireless communication device transmits a first reference signal in a first frequency band and a second reference signal in a second frequency band. The transmission times of the first and second reference signals are different. The center frequencies of the first and second frequency bands are different. The first and second reference signals are substantially synchronized in phase, and can be used together to estimate the TOA. This application requires that the radio frequency channel of the wireless communication device only needs to support the transmission of signals in both the first and second frequency bands, and that the estimation accuracy of the TOA is high, thereby improving the positioning accuracy of wireless communication devices with limited supported bandwidth.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus and chip for estimating the time of arrival of a reference signal. Background Technology

[0002] Signal arrival time estimation (TOA) is one of the key technologies in cellular positioning. For example, a first wireless communication device can send a reference signal to multiple other second wireless communication devices so that these devices can measure the arrival time of the received reference signal and thus locate the first wireless communication device. In practical applications, the TOA is usually used to determine the arrival time of the reference signal.

[0003] The accuracy of the time of arrival of the reference signal determines the positioning accuracy of the first wireless communication device. The accuracy of the time of arrival of the reference signal is limited by the effective bandwidth of the reference signal. The wider the bandwidth of the reference signal transmitted by the first wireless communication device, the higher the positioning accuracy of the first wireless communication device.

[0004] Therefore, improving the positioning accuracy of wireless communication devices with limited supported bandwidth has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a reference signal arrival time estimation method, apparatus, and chip to improve the positioning accuracy of wireless communication devices with limited bandwidth.

[0006] It should be understood that in the solutions provided in this application, the wireless communication device can be a wireless communication equipment, or a component within a wireless communication equipment, such as a system-on-a-chip (SoC) or communication chip, or other integrated circuit products. The wireless communication equipment can be a computer device that supports wireless communication functions.

[0007] Specifically, wireless communication devices can be terminals such as smartphones or wireless access network devices such as base stations. A system-on-a-chip (SoC) is also called a system-on-chip (SoC) or simply a SoC chip. Communication chips may include baseband processing chips and radio frequency (RF) processing chips. The baseband processing chip is sometimes called a modem or baseband chip. The RF processing chip is sometimes called an RF transceiver or RF chip. In physical implementation, some or all of the communication chips may be integrated within the SoC chip. For example, the baseband processing chip may be integrated into the SoC chip, while the RF processing chip may not be integrated with the SoC chip.

[0008] In a first aspect, this application provides a method for estimating the time of arrival of a reference signal, which can be executed by a first wireless communication device. The method includes: the first wireless communication device transmitting a first reference signal in a first frequency band and transmitting a second reference signal in a second frequency band. The transmission times of the first reference signal and the second reference signal are different, and the center frequencies of the first and second frequency bands are different; the first and second reference signals are substantially synchronized in phase, and the first and second reference signals can be used to jointly estimate the time of arrival of the reference signal.

[0009] Since the arrival time of the reference signal is estimated by jointly using the first reference signal and the second reference signal, compared with the scheme that only uses the first reference signal of the first frequency band to estimate the arrival time of the reference signal, the reference signal used to estimate the arrival time of the reference signal in this application occupies a larger frequency domain range, thereby improving the estimation accuracy of the arrival time of the reference signal.

[0010] Compared to the scheme that estimates the arrival time of reference signal by transmitting a reference signal occupying a third frequency band (the third frequency band includes the first and second frequency bands, and when there is a frequency band between the first and second frequency bands, the third frequency band also includes the frequency band between the first and second frequency bands), the estimation accuracy of the reference signal arrival time in this application is comparable. However, this application allows the radio frequency channel of the wireless communication device to only have the ability to support transmitting signals of the first and second frequency bands, without requiring it to support transmitting signals of the third frequency band. Therefore, this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.

[0011] Secondly, this application provides a method for estimating the arrival time of a reference signal, which can be executed by a first wireless communication device. The method includes: the first wireless communication device sequentially transmitting a first reference signal and a second reference signal in a frequency-hopping manner, wherein the first reference signal and the second reference signal have different frequency ranges but are substantially synchronized in phase, and the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal.

[0012] Since the arrival time of the reference signal is estimated by jointly using the first reference signal and the second reference signal, compared with the scheme that only uses the first reference signal of the first frequency band to estimate the arrival time of the reference signal, the reference signal used to estimate the arrival time of the reference signal in this application occupies a larger frequency domain range, thereby improving the estimation accuracy of the arrival time of the reference signal.

[0013] Compared to the scheme that estimates the arrival time of reference signal by transmitting a reference signal occupying a third frequency band (the third frequency band includes the first and second frequency bands, and when there is a frequency band between the first and second frequency bands, the third frequency band also includes the frequency band between the first and second frequency bands), the estimation accuracy of the reference signal arrival time in this application is comparable. However, this application allows the radio frequency channel of the wireless communication device to only have the ability to support transmitting signals of the first and second frequency bands, without requiring it to support transmitting signals of the third frequency band. Therefore, this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.

[0014] In one possible implementation of the first or second aspect, the reference signal arrival time can be used to estimate the location of the wireless communication device. Because the estimation accuracy of the reference arrival time is improved, the accuracy of the location of the wireless communication device estimated based on that reference arrival time is also improved.

[0015] In one possible implementation of the first or second aspect, there is an interval frequency band between the first frequency band and the second frequency band. When there is an interval frequency band between the first and second frequency bands, compared to a scheme that estimates the time of arrival of a reference signal by transmitting a reference signal in a third frequency band, this application can reduce the amount of signal transmitted by the wireless communication device, thereby reducing the power consumption of the wireless communication device.

[0016] In one possible implementation of the first or second aspect, the first wireless communication device may further generate a first local oscillator signal via a first phase-locked loop (PLL), the center frequency of which is the same as the center frequency of the first reference signal. The first wireless communication device may also generate a second local oscillator signal via a second PLL, the center frequency of which is the same as the center frequency of the second reference signal. Compared to the scheme of generating two local oscillator signals via only one PLL, generating two local oscillator signals via two PLLs does not involve the process of PLL unlocking and relocking, thereby avoiding phase jitter introduced by PLL unlocking and relocking, and thus laying the foundation for substantial phase synchronization of the first and second reference signals.

[0017] In one possible implementation of the first or second aspect, the first wireless communication device transmits a first reference signal in a first frequency band, including: transmitting the first reference signal in the first frequency band based on a first local oscillator signal. The first wireless communication device transmits a second reference signal in a second frequency band, including: transmitting the second reference signal in the second frequency band based on a second local oscillator signal. Thus, reference signals can be transmitted in desired frequency bands by modulating the reference signal onto local oscillator signals of different frequencies.

[0018] In one possible implementation of the first or second aspect, the input of the mixer of the first wireless communication device is selectively connected to a first phase-locked loop (PLL), and the input of the mixer is selectively connected to a second PLL. Thus, when a first reference signal needs to be transmitted, the mixer can be connected to the first PLL to provide a first local oscillator signal for the first radio frequency channel. When a second reference signal needs to be transmitted, the mixer can be connected to the second PLL to provide a second local oscillator signal for the first radio frequency channel.

[0019] In one possible implementation of the first or second aspect, the first phase-locked loop and the second phase-locked loop use the same reference clock signal. Thus, the local oscillator signals output by the two phase-locked loops can be phase-adjusted based on the same reference clock signal, thereby laying the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, for substantial phase synchronization of the first and second reference signals.

[0020] In one possible implementation of the first or second aspect, the first wireless communication device may further output a first synchronization signal to the first phase-locked loop (PLL) and the second PLL, respectively. The phase difference between the first local oscillator signal and the reference clock signal output by the first PLL is adjusted according to the first synchronization signal. The phase difference between the second local oscillator signal and the reference clock signal output by the second PLL is adjusted according to the first synchronization signal. Since the phase difference between the two PLLs and the reference clock signal is adjusted according to the same first synchronization signal, the initial phase difference between the first and second local oscillator signals can be adjusted to 0, thereby laying the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, laying the foundation for substantial phase synchronization of the first and second reference signals.

[0021] To provide flexibility, in one possible implementation of the first or second aspect, the frequency divider can be located either outside or inside the phase-locked loop (PLL). If the frequency divider is located outside the PLL, the first PLL includes a first oscillator, a first frequency divider, and a first feedback frequency divider. The output of the first oscillator is connected to both the first frequency divider and the first feedback frequency divider. The second PLL includes a second oscillator, a second frequency divider, and a second feedback frequency divider. The output of the second oscillator is connected to both the second frequency divider and the second feedback frequency divider.

[0022] In a phase-locked loop (PLL) where the frequency divider can be located inside the loop, the first PLL includes a first frequency divider and a first feedback frequency divider; the input of the first feedback frequency divider is connected to the output of the first frequency divider. The second PLL includes a second frequency divider and a second feedback frequency divider; the input of the second feedback frequency divider is connected to the output of the second frequency divider.

[0023] Since the first feedback divider divides the signal output from the first divider and feeds it back to the first phase-locked loop (PLL) to adjust the phase difference between the first local oscillator signal and the reference clock signal, and the second feedback divider divides the signal output from the second divider and feeds it back to the second PLL to adjust the phase difference between the second local oscillator signal and the reference clock signal, the phase jitter caused by the randomness of the start clock edges of the first and second dividers can be reduced.

[0024] In one possible implementation of the first or second aspect, the first wireless communication device adjusts the phase difference between a first local oscillator signal output by a first phase-locked loop and a reference clock signal based on a first synchronization signal, comprising: determining a first effective edge of the reference clock signal based on the first synchronization signal, and adjusting the phase difference between the first local oscillator signal and the reference clock signal based on the first effective edge. The first wireless communication device adjusts the phase difference between a second local oscillator signal output by a second phase-locked loop and a reference clock signal based on the first synchronization signal, comprising: determining a first effective edge based on the first synchronization signal, and adjusting the phase difference between the second local oscillator signal and the reference clock signal based on the first effective edge.

[0025] Since the same first effective edge of the reference signal specified by the first synchronization signal is used as the reference for phase adjustment of the two phase-locked loops, the phase difference between the initial phases of the first local oscillator signal and the second local oscillator signal can be adjusted to 0, thereby laying the foundation for the substantial phase synchronization of the first local oscillator signal and the second local oscillator signal, and subsequently laying the foundation for the substantial phase synchronization of the first reference signal and the second reference signal.

[0026] In one possible implementation of the first or second aspect, the first wireless communication device adjusts the phase difference between a first local oscillator signal output by a first phase-locked loop (PLL) and a reference clock signal based on a first synchronization signal, comprising: determining a first effective edge of the reference clock signal based on the first synchronization signal, and adjusting the phase difference between the first local oscillator signal and the reference clock signal based on the signal obtained by dividing the first local oscillator signal output by the first frequency divider of the first PLL using the first effective edge as a reference. The first wireless communication device adjusts the phase difference between a second local oscillator signal output by a second phase-locked loop (PLL) and a reference clock signal based on the first synchronization signal, comprising: determining a first effective edge based on the first synchronization signal, and adjusting the phase difference between the second local oscillator signal and the reference clock signal based on the signal obtained by dividing the second local oscillator signal output by the second frequency divider of the second PLL using the second feedback frequency divider of the second PLL using the first effective edge as a reference.

[0027] Since the first feedback divider divides the signal output from the first divider and feeds it back to the first phase-locked loop (PLL) to adjust the phase difference between the first local oscillator signal and the reference clock signal, and the second feedback divider divides the signal output from the second divider and feeds it back to the second PLL to adjust the phase difference between the second local oscillator signal and the reference clock signal, the phase jitter caused by the randomness of the start clock edges of the first and second dividers can be reduced.

[0028] In one possible implementation of the first or second aspect, the phase difference between the first local oscillator signal and the reference clock signal is equal to the phase difference between the second local oscillator signal and the reference clock signal. The phase difference between the first local oscillator signal and the reference clock signal can be 0 or a preset value. This lays the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, for substantial phase synchronization of the first and second reference signals.

[0029] In one possible implementation of the first or second aspect, the first wireless communication device may further transmit a second synchronization signal to the first phase-locked loop and the second phase-locked loop, respectively. The signal input to the first frequency divider of the first phase-locked loop is frequency-divided according to the second synchronization signal. The signal input to the second frequency divider of the second phase-locked loop is frequency-divided according to the second synchronization signal.

[0030] Since the frequency dividers of the two phase-locked loops are both based on the same second synchronization signal, the phase jitter between the first reference signal and the second reference signal caused by the randomness of the start clock edge of the two frequency dividers can be reduced.

[0031] In one possible implementation of the first or second aspect, the first and second frequency dividers have the same division ratio. This lays the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, for substantial phase synchronization of the first and second reference signals.

[0032] In one possible implementation of the first or second aspect, the first wireless communication device may further send a second synchronization signal to the first frequency divider and the second frequency divider, respectively. Based on the second synchronization signal, a first rising edge of the signal output by the first oscillator is determined as the starting clock edge for frequency division. Based on the second synchronization signal, a second rising edge of the signal output by the second oscillator is determined as the starting clock edge for frequency division. The phase difference between the first and second rising edges is equal to the phase difference between the signals output by the first and second oscillators.

[0033] Since the start clock edge of the two frequency dividers is determined based on the second synchronization signal, the phase jitter caused by the randomness of the start clock edge of the first and second frequency dividers can be reduced, which in turn lays the foundation for the substantial phase synchronization of the first and second local oscillator signals, and consequently lays the foundation for the substantial phase synchronization of the first and second reference signals.

[0034] In one possible implementation of the first or second aspect, the phase difference between the first local oscillator signal and the reference clock signal is less than the phase difference between the second local oscillator signal and the reference clock signal, which is less than a preset phase difference threshold. Thus, the phases of the first reference signal and the second reference signal can be approximately synchronized.

[0035] In one possible implementation of the first or second aspect, the phase difference between the first local oscillator signal and the reference clock signal is equal to the phase difference between the second local oscillator signal and the reference clock signal, which is equal to the phase difference between the signal output by the first oscillator of the first phase-locked loop and the signal output by the second oscillator of the second phase-locked loop. Thus, the phases of the first reference signal and the second reference signal can be approximately synchronized, and their phase difference is relatively small, within the error range, which satisfies the requirement of using the first and second reference signals to jointly estimate the arrival time of the reference signal.

[0036] In one possible implementation of the first or second aspect, the first wireless communication device may further output a third synchronization signal to a third phase-locked loop. A third local oscillator signal is generated, and the phase difference between the third local oscillator signal and a reference clock signal is adjusted according to the third synchronization signal; the center frequency of the third local oscillator signal is the same as the center frequency of the first reference signal. A fourth local oscillator signal is generated, and the phase difference between the fourth local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the fourth local oscillator signal is the same as the center frequency of the second reference signal. Wherein, the frequency of the third synchronization signal is the common divisor of the frequencies of the center frequencies of the third and fourth local oscillator signals.

[0037] Since the phase difference between the third local oscillator signal and the reference signal is adjusted based on the third synchronization signal, the phase jitter introduced by the relocking of the third phase-locked loop after it loses lock and then relocks can be reduced by adjusting the phase difference between the fourth local oscillator signal and the reference signal based on the third synchronization signal.

[0038] In one possible implementation of the first or second aspect, the first wireless communication device may further adjust the phase difference between the third local oscillator signal and the reference clock signal based on the third synchronization signal and the signal obtained by dividing the third local oscillator signal output by the third frequency divider of the third phase-locked loop (PLL) using the third feedback frequency divider. Similarly, the phase difference between the fourth local oscillator signal and the reference clock signal may be adjusted based on the third synchronization signal and the signal obtained by dividing the fourth local oscillator signal output by the third frequency divider of the third PLL using the third feedback frequency divider.

[0039] The third feedback frequency divider divides the signal output from the third frequency divider and feeds it back to the third phase-locked loop (PLL), adjusting the phase difference between the output signals (the third and fourth local oscillator signals) and the reference clock signal. Therefore, it can mitigate the phase jitter caused by the randomness of the starting clock edge during the two locking processes of the PLL.

[0040] In one possible implementation of the first or second aspect, the phase-adjusted third local oscillator signal is phase-synchronized with the reference clock signal, and the phase-adjusted fourth local oscillator signal is phase-synchronized with the reference clock signal. This lays the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, for substantial phase synchronization of the first and second reference signals.

[0041] In one possible implementation of the first or second aspect, the phase difference between the phase-adjusted third local oscillator signal and the third synchronization signal is equal to the phase difference between the phase-adjusted fourth local oscillator signal and the third synchronization signal. This lays the foundation for substantial phase synchronization of the first and second local oscillator signals, and consequently, for substantial phase synchronization of the first and second reference signals.

[0042] In one possible implementation of the first or second aspect, the third synchronization signal is phase-synchronized with the reference clock signal. The phase-adjusted third local oscillator signal is phase-synchronized with the third synchronization signal. The phase-adjusted fourth local oscillator signal is phase-synchronized with the third synchronization signal. This allows the first and second local oscillator signals to be substantially phase-synchronized, and the first and second reference signals to be substantially phase-synchronized.

[0043] In one possible implementation of the first or second aspect, the first wireless communication device may further input a third synchronization signal to the third phase-locked loop (PLL) while the PLL is locked. When the PLL is unlocked, inputting the third synchronization signal to the PLL ceases. This reduces the amount of third synchronization signal input to the PLL, thereby saving power consumption of the wireless communication device.

[0044] In one possible implementation of the first or second aspect, the third phase-locked loop (PLL) includes a third frequency divider and a third feedback frequency divider, with the input of the third feedback frequency divider connected to its output. Since the third feedback frequency divider divides the signal output from the third frequency divider and feeds it back to the third PLL, it adjusts the phase difference between the output signals (the third local oscillator signal and the fourth local oscillator signal) and the reference clock signal. Therefore, it can mitigate the phase jitter caused by the randomness of the starting clock edge during the two locking processes of the PLL.

[0045] In one possible implementation of the first or second aspect, before transmitting a first reference signal in a first frequency band and a second reference signal in a second frequency band, the first wireless communication device further includes: entering sleep mode. Upon the arrival of a wake-up time, it is woken up. During the wake-up period, the first and second reference signals are transmitted. Afterward, it enters sleep mode again. This can save power consumption of the wireless communication device.

[0046] In one possible implementation of the first or second aspect, before transmitting a first reference signal in a first frequency band and a second reference signal in a second frequency band, the method further includes: receiving configuration information, the configuration information including time-domain resource information for transmitting signals in an idle / inactive state; receiving an RRC connection release message; entering sleep mode; and waking up when a wake-up time arrives based on the time-domain resource information. Thus, the wake-up time can be determined based on the time-domain resource information configured for the first wireless communication device.

[0047] Thirdly, this application provides a method for estimating the time of arrival of a reference signal, which can be executed by a second wireless communication device. The method includes: the second wireless communication device receiving a first reference signal, the first reference signal being a signal in a first frequency band; receiving a second reference signal, the second reference signal being a signal in a second frequency band; wherein the transmission time of the first reference signal is different from the transmission time of the second reference signal, and the center frequency of the first frequency band is different from the center frequency of the second frequency band; wherein the first reference signal and the second reference signal are substantially synchronized in phase; and estimating the time of arrival of the reference signal based on the first reference signal and the second reference signal jointly.

[0048] Compared to the scheme that estimates the arrival time of reference signal by transmitting a reference signal occupying a third frequency band (the third frequency band includes the first and second frequency bands, and when there is a frequency band between the first and second frequency bands, the third frequency band also includes the frequency band between the first and second frequency bands), the estimation accuracy of the reference signal arrival time in this application is comparable. However, this application allows the radio frequency channel of the wireless communication device to only have the ability to support transmitting signals of the first and second frequency bands, without requiring it to support transmitting signals of the third frequency band. Therefore, this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.

[0049] Fourthly, this application provides a reference signal arrival time estimation method, which can be executed by a second wireless communication device. The method includes: the second wireless communication device receiving a first reference signal, wherein the first reference signal is a signal in a first frequency band;

[0050] Receive a second reference signal; the second reference signal is a signal in a second frequency band; wherein the first reference signal and the second reference signal are transmitted by frequency hopping, and the first reference signal and the second reference signal have different frequency ranges but are substantially synchronized in phase;

[0051] The arrival time of the reference signal is estimated by jointly estimating the first reference signal and the second reference signal.

[0052] Compared to the scheme that estimates the arrival time of reference signal by transmitting a reference signal occupying a third frequency band (the third frequency band includes the first and second frequency bands, and when there is a frequency band between the first and second frequency bands, the third frequency band also includes the frequency band between the first and second frequency bands), the estimation accuracy of the reference signal arrival time in this application is comparable. However, this application allows the radio frequency channel of the wireless communication device to only have the ability to support transmitting signals of the first and second frequency bands, without requiring it to support transmitting signals of the third frequency band. Therefore, this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.

[0053] In one possible implementation of the third or fourth aspect, the reference signal arrival time can be used to estimate the location of the wireless communication device. Since the estimation accuracy of the reference arrival time is improved, the accuracy of the location of the wireless communication device estimated based on that reference arrival time is also improved.

[0054] In one possible implementation of the third or fourth aspect, the second wireless communication device can superimpose the first reference signal and the second reference signal in the time domain to obtain a third reference signal. The arrival time of the reference signal is then estimated based on the third reference signal. Thus, a scheme for jointly estimating the arrival time of the reference signal based on the first and second reference signals can be provided.

[0055] In one possible implementation of the third or fourth aspect, the second wireless communication device may sample the signal corresponding to the received first reference signal according to the sampling rate corresponding to the bandwidth of the third frequency band to obtain the first reference signal. The second reference signal may also be obtained by sampling the signal corresponding to the received second reference signal according to the sampling rate corresponding to the bandwidth of the third frequency band. The third frequency band includes the first frequency band, the second frequency band, and a frequency band spaced between the first and second frequency bands.

[0056] Since a wider frequency band allows for a higher sampling rate, the first and second reference signals can be obtained based on a higher sampling rate, thereby improving the estimation accuracy of the reference signal arrival time.

[0057] Fifthly, a wireless communication device is provided, including a communication unit and a processing unit to perform the first aspect described above. This includes any one of the second, third, and fourth aspects, or any embodiment of any one of them. The communication unit is used to perform functions related to transmitting and receiving. Optionally, the communication unit includes a receiving unit and a transmitting unit. In one design, the wireless communication device is a communication chip, the processing unit can be one or more processors or processor cores, and the communication unit can be the input / output circuitry or port of the communication chip.

[0058] In another design, the communication unit can be a transmitter and a receiver, or the communication unit can be a transmitter and a receiver.

[0059] Optionally, the wireless communication device may further include modules that can be used to perform any of the embodiments of the communication methods described in the first aspect above.

[0060] A sixth aspect provides a wireless communication device including a processor and a memory. Optionally, it also includes a transceiver. The memory is used to store computer programs or instructions, and the processor is used to retrieve and execute the computer programs or instructions from the memory. When the processor executes the computer programs or instructions in the memory, the wireless communication device causes it to perform any one or any embodiment of the first, second, third, and fourth aspects described above.

[0061] Optionally, there may be one or more processors and one or more memories.

[0062] Optionally, the memory can be integrated with the processor, or the memory can be set up separately from the processor.

[0063] Optionally, the transceiver may include a transmitter and a receiver.

[0064] A seventh aspect provides a wireless communication device including a processor. The processor is coupled to a memory and can be used to execute any one or any embodiment of the first, second, third, and fourth aspects. Optionally, the wireless communication device further includes a memory. Optionally, the wireless communication device further includes a communication interface, and the processor is coupled to the communication interface.

[0065] In one implementation, when the wireless communication device is a first wireless communication device, the communication interface can be a transceiver or an input / output interface. Optionally, the transceiver can be a transceiver circuit. Optionally, the input / output interface can be an input / output circuit.

[0066] In another implementation, when the wireless communication device is a chip or chip system, the communication interface can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip or chip system. The processor can also be manifested as a processing circuit or logic circuit.

[0067] Eighthly, a system is provided, comprising the aforementioned wireless communication device and the second wireless communication device.

[0068] Ninthly, a computer program product is provided, comprising: a computer program (also referred to as code or instructions), which, when executed, causes a computer to perform any one of the first, second, third, and fourth aspects or any one of the embodiments described above.

[0069] In a tenth aspect, a computer-readable storage medium is provided, which stores a computer program (also referred to as code or instructions) that, when executed on a computer, causes the computer to perform any one or any embodiment of the first, second, third, and fourth aspects described above.

[0070] Eleventhly, a chip system is provided, which may include a processor. The processor is coupled to a memory and can be used to execute any one or any embodiment of the first, second, third, and fourth aspects described above. Optionally, the chip system further includes a memory. The memory is used to store a computer program (also referred to as code or instructions). The processor is used to call and run the computer program from the memory, causing a device on which the chip system is installed to execute any one or any embodiment of the first, second, third, and fourth aspects.

[0071] In a twelfth aspect, a processing apparatus is provided, comprising: an interface circuit and a processing circuit. The interface circuit may include an input circuit and an output circuit. The processing circuit is configured to receive signals through the input circuit and transmit signals through the output circuit, thereby enabling any one or any embodiment of the first, second, third, and fourth aspects to be implemented.

[0072] In specific implementation, the aforementioned processing device can be a chip, the input circuit can be an input pin, the output circuit can be an output pin, and the processing circuit can be a transistor, gate circuit, flip-flop, and various logic circuits, etc. The input signal received by the input circuit can be received and input by, for example, but not limited to, a receiver, and the signal output by the output circuit can be, for example, but not limited to, output to a transmitter and transmitted by the transmitter. Furthermore, the input circuit and the output circuit can be the same circuit, which is used as the input circuit and output circuit at different times. This application does not limit the specific implementation method of the processor and various circuits.

[0073] In one implementation, the wireless communication device is a first wireless communication device, which can be a terminal such as a smartphone or a wireless access network device such as a base station. The interface circuit can be a radio frequency processing chip in the first wireless communication device, and the processing circuit can be a baseband processing chip in the first wireless communication device.

[0074] In another implementation, the wireless communication device can be a component of the first wireless communication device, such as an integrated circuit product like a system-on-a-chip (SoC) or a communication chip. The interface circuit can be an input / output interface, interface circuit, output circuit, input circuit, pins, or related circuits on the chip or chip system. The processing circuit can be the logic circuit on the chip. Attached Figure Description

[0075] Figure 1 This application provides a schematic diagram of the structure of a wireless communication system according to an embodiment of the present application.

[0076] Figure 2 This is a schematic diagram of the structure of a wireless communication device provided in an embodiment of this application;

[0077] Figure 3a A schematic diagram illustrating a location estimation method for a wireless communication device provided in an embodiment of this application;

[0078] Figure 3b A schematic diagram illustrating phase synchronization of 10MHz and 20MHz clock signals provided for an embodiment of this application;

[0079] Figure 3c A schematic diagram illustrating the phase synchronization of 20MHz and 30MHz clock signals provided in an embodiment of this application;

[0080] Figure 4 This application provides a schematic flowchart of a method for estimating the arrival time of a reference signal.

[0081] Figure 5 For the above Figure 4A flowchart illustrating the method for the first wireless communication device in S401 to transmit a first reference signal and a second reference signal;

[0082] Figure 6 This is a schematic diagram illustrating an example of a first wireless communication device transmitting a first reference signal and a second reference signal, as provided in an embodiment of this application.

[0083] Figure 7 This is a schematic diagram of the structure of the first wireless communication device provided in an embodiment of this application;

[0084] Figure 8a An embodiment provided in this application Figure 7 A schematic diagram of the structure of phase-locked loop 75 and phase-locked loop 76 in the diagram;

[0085] Figure 8b for Figure 8a A schematic diagram of the reference clock signal, lock signal, and first synchronization signal;

[0086] Figure 8c for Figure 8a A schematic diagram showing the frequency of the signal output by the phase-locked loop 75, the phase difference detected by the phase detector 751, and the synchronization signal output by the first synchronization module;

[0087] Figure 9a An embodiment provided in this application Figure 7 A schematic diagram of the structure of phase-locked loop 75 and phase-locked loop 76 in the diagram;

[0088] Figure 9b for Figure 9a A schematic diagram of a reference clock signal, a lock signal, a second synchronization signal, a signal output by oscillator 754, a signal output by oscillator 764, a signal output by frequency divider 756, and a signal output by frequency divider 766.

[0089] Figure 10 An embodiment provided in this application Figure 7 A schematic diagram of the structure of phase-locked loop 75 and phase-locked loop 76 in the diagram;

[0090] Figure 11 This is a schematic diagram of another first wireless communication device provided in an embodiment of this application;

[0091] Figure 12a As a kind Figure 11 Schematic diagram of the structure of the intermediate phase-locked loop 81;

[0092] Figure 12b for Figure 12a A schematic diagram of the reference clock signal, the locking signal of the phase-locked loop 81, the signal output by the third synchronization module, and the signal output by the phase-locked loop 81;

[0093] Figure 13 As a kind Figure 11 Another structural schematic diagram of the central phase-locked loop 81;

[0094] Figure 14 for Figure 4 One possible implementation of S402;

[0095] Figure 15 A schematic diagram of a simulation environment provided for an embodiment of this application;

[0096] Figure 16 This is a schematic diagram of another wireless communication device provided in an embodiment of this application;

[0097] Figure 17 This is a schematic diagram of another wireless communication device provided in an embodiment of this application;

[0098] Figure 18 This is a schematic diagram of another wireless communication device provided in an embodiment of this application. Detailed Implementation

[0099] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0100] The technical solutions provided in this application are primarily applicable to wireless communication systems. These systems can comply with the wireless communication standards of the Third Generation Partnership Project (3GPP). For example, the solutions provided in this application can be applied to fourth-generation (4G) communication systems, such as Long Term Evolution (LTE) systems, fifth-generation (5G) communication systems, such as 5G New Radio (NR) systems, or various future communication systems, such as sixth-generation (6G) systems. The technical solutions provided in this application can also comply with other wireless communication standards, such as the Institute of Electrical and Electronics Engineers (IEEE) 802 series (e.g., 802.11, 802.15, or 802.20) wireless communication standards. The methods provided in this application can also be applied to Bluetooth systems, WiFi systems, LoRa systems, or vehicle-to-everything (V2X) systems. Furthermore, the methods provided in this application can be applied to satellite communication systems, where the satellite communication system can be integrated with the aforementioned communication systems.

[0101] The devices in the communication system to which this application's embodiments apply can be divided into: devices that provide wireless network services and devices that use wireless network services.

[0102] Equipment providing wireless network services refers to those devices that make up a wireless communication network, often simply called network equipment or network element. Network equipment typically belongs to operators or infrastructure providers and is operated or maintained by these vendors. Network equipment, including access network (AN) equipment such as base stations (e.g., access points), can refer to devices in the access network that communicate with wireless terminal devices over the air interface via one or more cells. Base stations can be used to convert received air frames to and from Internet Protocol (IP) packets, acting as routers between terminal devices and the rest of the access network, which may include IP networks. An RSU can be a fixed infrastructure entity supporting V2X applications and can exchange messages with other entities supporting V2X applications. Network equipment can also coordinate the management of air interface attributes. For example, network equipment may include evolved base stations (NodeBs, eNBs, or e-NodeBs) in LTE systems or Long Term Evolution-Advanced (LTE-A), or it may include fifth-generation mobile communication technologies (the 5G). th The next-generation node B (gNB) in a new radio (NR) system (5G) or a centralized unit (CU) and a distributed unit (DU) in a cloud radio access network (Cloud RAN) system are not limited to this embodiment.

[0103] Devices using wireless network services may be simply referred to as terminal devices. Terminal devices include those that provide voice and / or data connectivity to users, such as handheld devices with wireless connectivity or processing devices connected to a wireless modem. The terminal device can communicate with the core network via a radio access network (RAN) and exchange voice and / or data with the RAN. The terminal equipment may include user equipment (UE), wireless terminal equipment, mobile terminal equipment, device-to-device (D2D) terminal equipment, V2X terminal equipment, machine-to-machine / machine-type communications (M2M / MTC) terminal equipment, Internet of Things (IoT) terminal equipment, subscriber unit, subscriber station, mobile station, remote station, access point (AP), remote terminal equipment, access terminal equipment, user terminal equipment, user agent, or user device, etc. For example, it may include mobile phones (or "cellular" phones), computers with mobile terminal equipment, portable, pocket-sized, handheld, or computer-embedded mobile devices, etc. Examples include personal communication service (PCS) phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, and personal digital assistants (PDAs). It also includes limited devices, such as those with low power consumption, limited storage capacity, or limited computing power. Examples include information sensing devices such as barcode scanners, radio frequency identification (RFID), sensors, global positioning systems (GPS), and laser scanners.

[0104] The following section will use the device that provides the wireless network service as the base station and the device that uses the wireless network service as the terminal device. Figure 1 This is a schematic diagram of a wireless communication system provided in an embodiment of this application. Figure 1 As shown, a wireless communication system includes terminal equipment and a base station. Depending on the transmission direction, the transmission link from the terminal equipment to the base station is denoted as the uplink (UL), and the transmission link from the base station to the terminal equipment is denoted as the downlink (DL). Similarly, data transmission in the uplink can be abbreviated as uplink data transmission or uplink transmission, and data transmission in the downlink can be abbreviated as downlink data transmission or downlink transmission.

[0105] In this wireless communication system, a base station can provide communication coverage to a specific geographical area through integrated or external antenna devices. One or more terminal devices located within the communication coverage area of ​​the base station can access the base station. A base station can manage one or more cells. Each cell has an identification, also known as a cell identity (cell ID). From a radio resource perspective, a cell is a combination of downlink radio resources and paired uplink radio resources (optional).

[0106] Terminal devices and base stations should be aware of the predefined configuration of the wireless communication system, including the radio access technology (RAT) supported by the system and the system-specified wireless resource configuration, such as the basic configuration of radio frequency bands and carriers. A carrier is a frequency range specified by the system. This frequency range can be determined by the center frequency (denoted as the carrier frequency) and the carrier bandwidth. These predefined system configurations can be part of the standard protocol of the wireless communication system, or determined through interaction between the terminal device and the base station. The content of the relevant standard protocol may be pre-stored in the memory of the terminal device and the base station, or embodied in the hardware circuitry or software code of the terminal device and the base station.

[0107] In this wireless communication system, the terminal equipment and the base station support one or more of the same Radio Access Platforms (RATs), such as 5G NR, 4G LTE, or the RAT of future evolution systems. Specifically, the terminal equipment and the base station use the same air interface parameters, coding schemes, and modulation schemes, and communicate with each other based on the wireless resources specified by the system.

[0108] Based on the above, Figure 2 This is a schematic diagram of a wireless communication device provided in an embodiment of this application. The wireless communication device can be a terminal device as described in the embodiments of this application, for example... Figure 1The terminal device in the application. The wireless communication device can also be a network device as described in this application embodiment, for example, it can... Figure 1 Base stations in the region.

[0109] In one possible implementation, the wireless communication device may include a processing circuit and an interface circuit. The interface circuit may include an input circuit and an output circuit. The processing circuit is used to receive signals through the input circuit and transmit signals through the output circuit, such that the following... Figure 4 and Figure 5 The relevant methods are implemented. For example, when the wireless communication device is a terminal device, the processing circuit can execute S401, S503, S504, and S506 through the control interface circuit. As another example, when the wireless communication device is a network device, the processing circuit can execute S402, S502, and S505 through the control interface circuit. The first synchronization module, second synchronization module, and third synchronization module mentioned later in this application embodiment can all be modules within the processing circuit.

[0110] In one implementation, the interface circuit can also be a radio frequency processing chip in a wireless communication device, and the processing circuit can be a baseband processing chip in a wireless communication device.

[0111] In another implementation, the wireless communication device can be a component of a wireless communication equipment, such as a system-on-a-chip (SoC) or communication chip, or other integrated circuit products. The interface circuit can be an input / output interface, interface circuit, output circuit, input circuit, pins, or related circuits on the chip or chip system. The processing circuit can be the logic circuit on the chip.

[0112] In another implementation, the processing circuit in this embodiment may further be a processor or a module or unit within a processor, and the interface circuit may further be a radio frequency (RF) channel or a component within an RF channel. The processor controls the RF channel, enabling the following... Figure 4 and Figure 5 The relevant methods were implemented.

[0113] like Figure 2 As shown, the wireless communication device may include multiple components, such as: an application subsystem, memory, mass storage, a baseband subsystem, a radio frequency integrated circuit (RFIC), a radio frequency frontend (RFFE) device, and an antenna (ANT). These components may be coupled via various interconnect buses or other electrical connections.

[0114] Figure 2The application subsystem in the middle can be set in Figure 2 The processor 110, or a module within the processor 110.

[0115] Figure 2 In this code, ANT_1 represents the first antenna, ANT_N represents the Nth antenna, and N is a positive integer greater than 1. Tx represents the transmit path, and Rx represents the receive path; different numbers represent different paths. Each path can represent a signal processing channel. FBRx represents the feedback receive path, PRx represents the main receive path, and DRx represents the diversity receive path. HB represents high frequency, and LB represents low frequency; these refer to the relative high and low frequencies. BB represents baseband. It should be understood that... Figure 2 The labels and components shown are for illustrative purposes only and represent one possible implementation. Other implementations are also included in this application. For example, the communication device may include more or fewer paths and more or fewer components.

[0116] The application subsystem can serve as the main control system or main computing system of the communication device, running the main operating system and applications, managing the hardware and software resources of the entire communication device, and providing a user interface. Furthermore, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem).

[0117] The application subsystem may include one or more processors. Multiple processors may be multiple processors of the same type, or a combination of processors of various types. In this application, the processor may be a general-purpose processor or a processor designed for a specific domain. For example, the processor may be a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller (MCU). The processor may also be a graphics processing unit (GPU), an image signal processor (ISP), an audio signal processor (ASP), and an AI processor specifically designed for artificial intelligence (AI) applications. AI processors include, but are not limited to, neural network processing units (NPUs), tensor processing units (TPUs), and processors referred to as AI engines.

[0118] Figure 2In a radio frequency (RF) subsystem, RF integrated circuits (including RFIC 1 and one or more optional RFIC 2) and RF front-end devices together constitute the RF subsystem. Depending on the signal reception or transmission path, the RF subsystem can also be divided into an RF receive path and an RF transmit path. The RF receive path receives RF signals via an antenna, processes these signals (e.g., amplification, filtering, and down-conversion) to obtain a baseband signal, and then transmits it to the baseband subsystem. The RF transmit path receives baseband signals from the baseband subsystem, processes these baseband signals (e.g., up-conversion, amplification, and filtering) to obtain an RF signal, and finally radiates this RF signal into space via an antenna. RF integrated circuits can be referred to as RF processing chips or RF chips.

[0119] Specifically, an RF subsystem may include electronic components such as antenna switches, antenna tuners, low-noise amplifiers (LNAs), power amplifiers (PAs), mixers, local oscillators (LOs), and filters. These components can be integrated into one or more chips as needed. RF integrated circuits can be called RF processing chips or RF chips. RF front-end devices can also be standalone chips. RF chips are sometimes also referred to as receivers, transmitters, transceivers, or transceivers. With technological advancements, antennas can sometimes be considered part of the RF subsystem and integrated into the RF subsystem chip. Antennas, RF front-end devices, and RF chips can all be manufactured and sold separately. Of course, the RF subsystem can also employ different devices or different integration methods based on power consumption and performance requirements. For example, some components belonging to the RF front-end can be integrated into the RF chip, or even the antenna and RF front-end devices can be integrated into the RF chip, which can also be called an RF antenna module or antenna module.

[0120] Similar to the radio frequency (RF) subsystem, which primarily handles RF signal processing, the baseband subsystem, as its name suggests, primarily processes baseband signals. The baseband subsystem can extract useful information or data bits from the baseband signal, or convert information or data bits into baseband signals to be transmitted. These information or data bits can represent user data such as voice, text, and video, or control information. For example, the baseband subsystem can perform signal processing operations such as modulation and demodulation, encoding and decoding. The baseband signal processing operations are not entirely the same for different wireless access technologies, such as 5G NR and 4G LTE.

[0121] Furthermore, since radio frequency signals are typically analog signals, and the baseband subsystem primarily processes digital signals, the communication device also requires an analog-to-digital converter (ADC). In this embodiment, the ADC can be located in either the baseband subsystem or the radio frequency subsystem. The ADC includes an analog-to-digital converter (ADC) that converts analog signals to digital signals, and a digital-to-analog converter (DAC) that converts digital signals to analog signals.

[0122] Similar to the application subsystem, the baseband subsystem may also include one or more processors. Furthermore, the baseband subsystem may include one or more hardware accelerators (HACs). Hardware accelerators can be used to perform sub-functions with higher processing overhead, such as data packet assembly and parsing, and data packet encryption and decryption. These sub-functions can also be implemented using general-purpose processors, but due to performance or cost considerations, using hardware accelerators may be more suitable. In specific implementations, hardware accelerators are primarily implemented using application-specific integrated circuits (ASICs). Of course, hardware accelerators can also include one or more relatively simple processors, such as MCUs.

[0123] In this embodiment, the baseband subsystem and the radio frequency (RF) subsystem together constitute the communication subsystem, providing wireless communication functionality for the communication device. Typically, the baseband subsystem manages the hardware and software resources of the communication subsystem and can configure the operating parameters of the RF subsystem. The processor of the baseband subsystem can run a sub-operating system of the communication subsystem, which is often an embedded operating system or a real-time operating system, such as VxWorks or Qualcomm's QuRT system.

[0124] A baseband subsystem can be integrated into one or more chips, which may be called a baseband processing chip or baseband chip. Alternatively, the baseband subsystem can exist as a standalone chip, which may be called a modem or modem chip. Baseband subsystems can be manufactured and sold as modem chips. Modem chips are sometimes also referred to as baseband processors or mobile processors. Furthermore, baseband subsystems can be further integrated into larger chips, manufactured and sold as larger chip units. This larger chip may be called a system-on-a-chip (SoC), or simply a SoC chip. The software components of the baseband subsystem can be built into the chip's hardware components before the chip leaves the factory, or imported into the chip's hardware components from other non-volatile memory after the chip leaves the factory, or these software components can be downloaded and updated online via a network.

[0125] In addition, the communication device also includes a memory, for example Figure 2 The system includes main memory and large-capacity storage. Additionally, application subsystems and baseband subsystems may each include one or more caches. In specific implementations, memory can be divided into volatile memory and non-volatile memory (NVM). Volatile memory refers to memory whose data is lost when the power supply is interrupted. Currently, volatile memory is mainly random access memory (RAM), including static random access memory (SRAM) and dynamic random access memory (DRAM). Non-volatile memory refers to memory whose data is not lost even when the power supply is interrupted. Common non-volatile memories include read-only memory (ROM), optical discs, hard disks, and various memories based on flash memory technology. Generally speaking, main memory and cache can use volatile memory, while large-capacity storage can use non-volatile memory, such as flash memory.

[0126] Before introducing the solutions provided in this application, the nouns and terms involved in the embodiments of this application will be introduced first.

[0127] (1) TOA-based positioning method.

[0128] The solution provided in this application embodiment is applicable to the positioning of a first wireless communication device. The first wireless communication device can be a terminal device or a network device. In this application embodiment, the first wireless communication device used for positioning is a terminal device as an example for introduction.

[0129] 5G NR defines several positioning methods based on TOA estimation, such as Observed Time Difference of Arrival (OTDOA), Multi-RTT (round trip time), Downlink Time Difference of Arrival (DL-TDOA), and Uplink Time Difference of Arrival (UL-TDOA). Positioning methods based on TOA estimation use estimated TOA values ​​for location determination.

[0130] Figure 3a An exemplary illustration shows a schematic diagram of a positioning method provided in an embodiment of this application, such as... Figure 3a As shown, the terminal device can communicate with different network devices (such as...) Figure 3a Base stations 301, 302, and 303 transmit uplink reference signals, and different network devices measure the Time of Arrival (TOA) of the uplink reference signals. The network devices report the TOA to the positioning server. The positioning server can calculate the Time Difference of Arrival (OTDOA) based on the TOA information between multiple network devices and the terminal device, and obtain the location information of the terminal device based on the known location information of the network devices. For example... Figure 3a As shown, the positioning server knows the location information of base stations 301, 302, and 303, and also knows the TOA information between each network device and the terminal device. Therefore, by decoding... Figure 3a The hyperbolic equation in the equation can be used to obtain the location information of the terminal device. In another possible implementation, the terminal device can also have positioning capabilities; for example, the terminal device can request location information and determine its own location. Specifically, the terminal device requests location information from network devices. Multiple network devices send downlink positioning reference signals (PRS) to the terminal device. Based on the downlink PRS, the terminal device measures the Time of Arrival (TOA) of each of the network devices. The terminal device can then determine its own location based on the known locations of the network devices, or it can report the TOA information of each network device to a positioning server. The positioning server calculates the Time of Arrival (TDOA) based on the TOA information between the terminal device and the multiple network devices, and obtains the terminal device's location information based on the known location information of the network devices.

[0131] In this embodiment of the application, the positioning server may be, for example, the location management function (LMF) in the NR system. For example, in one possible positioning architecture, the Access and Mobility Management Function (AMF) receives service requests for terminal devices initiated by other network elements in the network. The AMF sends a positioning request for the terminal device to the LMF. The LMF receives the positioning request from the AMF, initiates the positioning of the terminal device, and determines the positioning information of the terminal device.

[0132] The positioning method provided in this application can be applied to various industries and businesses to locate people and objects, obtain location information of personnel and materials, and then carry out further application development based on the location information. For example, the positioning method provided in this application can be applied to industry application scenarios, such as intelligent manufacturing, warehousing physics, power energy, public security, procuratorate, and judicial systems, for example, to locate objects. In such scenarios, the terminal device that needs to be located can be materials and / or equipment that are fixed or integrated with positioning tags.

[0133] For example, the positioning method provided in this application embodiment can be applied to consumer application scenarios, such as museum exhibitions, smart supermarkets, and transportation hubs. It can be used to locate people in order to provide services such as indoor navigation and tour guides. In such scenarios, the terminal device requiring positioning can be a mobile phone or similar device.

[0134] (2) Phase synchronization.

[0135] When two signals have different frequencies, and the two frequencies are integer multiples of each other, then phase synchronization of the two signals means that the rising edge of the two signals is aligned with the rising edge of the signal with the lowest frequency. Figure 3b The diagram above exemplifies a phase synchronization of 10 MHz and 20 MHz signals provided in an embodiment of this application. Figure 3b As shown, the rising edge of the 20MHz signal is aligned with the rising edge of the 10MHz signal.

[0136] When two signals have different frequencies and the two frequencies are not integer multiples of each other, the phase synchronization of the two signals means that the rising edge of the clock of the two signals is aligned with the rising edge of the signal with the greatest common divisor frequency, which is a signal independent of the two signals. Figure 3c The diagram above illustrates a schematic representation of signal phase synchronization at 20MHz, 30MHz, and 40MHz according to an embodiment of this application. Figure 3cAs shown, the greatest common divisor of 20MHz, 30MHz, and 40MHz is 10MHz. Therefore, the rising edges of the 20MHz, 30MHz, and 40MHz signals are all aligned to the rising edge of the 10MHz signal. For another example, the greatest common divisor of 12.288MHz and 30.72MHz is 6.144MHz. Therefore, the rising edges of the 12.288MHz and 30.72MHz signals are all aligned to the rising edge of the 6.144MHz signal.

[0137] In this embodiment, the two signals can also be referred to as two clock signals. The two signals being phase-synchronized in this embodiment can also be referred to as having continuous phases.

[0138] Based on the above, Figure 4 An exemplary illustration shows a flowchart of a method for estimating the arrival time of a reference signal according to an embodiment of this application. Figure 4 The provided scheme can be used to determine the arrival time of the reference signal mentioned above. As follows, the execution entity of this method can be a first wireless communication device and a second wireless communication device. The first wireless communication device is a transmitting wireless communication device, and the second wireless communication device is a receiving wireless communication device. The first wireless communication device can be either a terminal device or a network device, and the second wireless communication device can be either a terminal device or a network device. When the first wireless communication device is a terminal device, the second wireless communication device can be a network device. When the first wireless communication device is a network device, the second wireless communication device can be a terminal device.

[0139] For ease of explanation, the following content will use the first wireless communication device as the terminal device and the second communication device as the network device as an example. Figure 4 As shown, the method includes:

[0140] S401, the first wireless communication device transmits a first reference signal in a first frequency band and a second reference signal in a second frequency band via a first radio frequency channel. The first and second reference signals are substantially synchronized in phase, and can be used to jointly estimate the arrival time of the reference signal.

[0141] Correspondingly, the second wireless communication device receives the first reference signal and the second wireless communication device receives the second reference signal.

[0142] In S401, the transmission time of the first reference signal is different from that of the second reference signal. The center frequency of the first frequency band is different from that of the second frequency band. In one possible implementation, the difference between the center frequency of the first frequency band and the center frequency of the second frequency band can be understood as the difference in the frequency ranges of the first and second reference signals. The frequency ranges of the first and second reference signals may partially overlap; they may also not overlap at all, with an interval frequency band between the frequency ranges of the first and second reference signals.

[0143] In one possible implementation, S401 can be replaced by: the first wireless communication device sequentially transmitting a first reference signal and a second reference signal in a frequency-hopping manner. Frequency hopping can refer to the carrier frequency changing within a certain frequency band. The first and second reference signals transmitted via frequency hopping can have the following characteristics: the transmission time of the first reference signal is different from that of the second reference signal, and the frequency ranges of the first and second reference signals are different.

[0144] In this embodiment, "substantially" in the phase synchronization of the first reference signal and the second reference signal can be understood as "substantially". The phase synchronization of the first reference signal and the second reference signal can include two cases:

[0145] In the first case, the first reference signal and the second reference signal are in phase synchronization.

[0146] In the second case, the first and second reference signals are approximately synchronized, meaning there is a small phase difference between them, which can also be understood as a phase difference less than a phase difference threshold. A possible implementation is described later, in which the phase difference between the first and second reference signals is the phase difference between the signals output by the oscillators of the two phase-locked loops.

[0147] The two situations mentioned above will be discussed in detail later, and will not be elaborated on here.

[0148] In this embodiment of the application, the first reference signal and the second reference signal can be reference signals used for positioning, such as downlink PRS or uplink sounding reference signal (SRS).

[0149] S402, the second wireless communication device estimates the arrival time of the reference signal based on the first reference signal and the second reference signal.

[0150] In this embodiment of the application, "joint estimation" can also be understood as "joint estimation", which means combining the first reference signal and the second reference signal to jointly determine the arrival time of the reference signal.

[0151] The arrival time of the reference signal can be used to estimate the location of the first wireless communication device. The specific scheme is as described above. Figure 3a As shown, the positioning server can estimate the location of the first wireless communication device by combining the arrival time of a reference signal transmitted by the first wireless communication device estimated by multiple wireless communication devices. Each wireless communication device can estimate the arrival time of the reference signal based on a first reference signal and a second reference signal jointly.

[0152] In S401, the first wireless communication device can also transmit multiple signals to the second wireless communication device on multiple frequency bands, and these multiple frequency bands can correspond one-to-one with the multiple signals. Correspondingly, in S402, the second wireless communication device can receive multiple signals and superimpose the received multiple signals in the time domain to determine the third reference signal. Multiple signals can refer to two or more signals. For example, multiple frequency bands can be three frequency bands, including a first frequency band, a second frequency band, and a fourth frequency band. The transmitting end transmits a first reference signal on the first frequency band, a second reference signal on the second frequency band, and a third reference signal on the fourth frequency band. The receiving end receives the first reference signal on the first frequency band, the second reference signal on the second frequency band, and the third reference signal on the fourth frequency band, and superimposes the first, second, and third reference signals in the time domain to obtain the third reference signal. For ease of explanation in this embodiment, the example given is that the multiple signals transmitted by the first wireless communication device to the second wireless communication device include the first and second reference signals.

[0153] Since the arrival time of the reference signal is estimated by jointly using the first reference signal and the second reference signal, compared with the scheme that only uses the first reference signal of the first frequency band to estimate the arrival time of the reference signal, the reference signal used to estimate the arrival time of the reference signal in this application occupies a larger frequency domain range, thereby improving the estimation accuracy of the arrival time of the reference signal.

[0154] Compared to the scheme that estimates the arrival time of reference signal by transmitting a reference signal occupying a third frequency band (the third frequency band includes the first and second frequency bands, and when there is a frequency band between the first and second frequency bands, the third frequency band also includes the frequency band between the first and second frequency bands), the estimation accuracy of the reference signal arrival time in this application is comparable. However, this application allows the radio frequency channel of the wireless communication device to only have the ability to support transmitting signals of the first and second frequency bands, without requiring it to support the ability to transmit signals of the third frequency band. Therefore, this application can improve the positioning accuracy of terminal devices with weak transmission capabilities.

[0155] Furthermore, when there are intervals between the first and second frequency bands, compared to the scheme of estimating the time of arrival of the reference signal by transmitting a reference signal of a third frequency band, this application can reduce the amount of signal transmitted by the wireless communication device, thereby reducing the power consumption of the wireless communication device.

[0156] To further improve the positioning accuracy of the first wireless communication device, an interval frequency band can be included between the first and second frequency bands. Since the estimation accuracy of the reference signal arrival time between the first and second wireless communication devices is positively correlated with the interval frequency band between the first and second frequency bands, a wider interval frequency band between the first and second frequency bands results in higher estimation accuracy of the reference signal arrival time, and consequently, more accurate positioning of the first wireless communication device. Of course, the first and second frequency bands can also have overlapping frequency domain resources, or the first and second frequency bands can be a continuous frequency band.

[0157] To save power consumption of the first wireless communication device, the following example uses the first wireless communication device as the terminal device and the second wireless communication device as the network device. Figure 5 The above is illustrated by example. Figure 4 A flowchart illustrating the method for the first wireless communication device in S401 to transmit the first reference signal and the second reference signal is shown below. Figure 5 As shown, the method includes:

[0158] S501, terminal equipment accesses network equipment.

[0159] When a terminal device first connects to a network device, it can authenticate and open an account with the authentication server to complete two-way authentication between the terminal device and the network device. It can also perform encryption and integrity protection. Both the terminal device and the network device can generate non-access stratum (NAS) encryption keys and integrity protection keys. The signals used for positioning later (positioning signals may include the aforementioned first reference signal and second reference signal) can be transmitted using NAS encryption.

[0160] S502, the network device sends configuration information to the terminal device. The configuration information includes information on the time domain resources allocated by the network device for transmitting signals in the idle / inactive state to the terminal device, and sends an RRC connection release message to the terminal device.

[0161] The temporal resource information in the configuration information can also be information on the temporal resources allocated by the network device to the terminal device for transmitting positioning signals in the idle / inactive state. The positioning signals can include the aforementioned first reference signal and second reference signal.

[0162] The time-domain resource defines the wake-up cycle of a terminal device after it enters sleep mode, i.e., how often it wakes up, such as every 6 seconds. After configuring this message, the network device can release the terminal device's RRC connection via the RRC connection release message.

[0163] S503, the terminal device enters sleep mode.

[0164] In S503, it can also be said that the terminal device enters deep sleep. In deep sleep, the terminal device enters a low-power state in order to save the terminal device's power.

[0165] S504: The terminal device wakes up when the wake-up time corresponding to a wake-up cycle arrives, based on the time domain resources configured in the network device.

[0166] S505, the terminal device receives a synchronization signal block (SSB) from the network device.

[0167] Once awakened, the terminal device can synchronize its time with the network device via the S505 terminal device to eliminate clock drift during sleep.

[0168] S506, the terminal device sends a first reference signal, and the terminal device sends a second reference signal.

[0169] After time synchronization, the terminal device can send the first reference signal and the second reference signal through S506. After sending, it can execute the above-mentioned S503 to re-enter sleep mode in order to save power consumption.

[0170] Regarding the aforementioned S401 and S506, Figure 6 The present application provides a specific example of a scheme for a first wireless communication device to transmit a first reference signal and a second reference signal, as exemplified in its embodiments. Figure 6 As shown:

[0171] First, the first wireless communication device generates an SRS signal of length corresponding to a bandwidth of 100MHz. This can also be understood as the first wireless communication device generating an SRS signal of bandwidth of 100MHz in the time domain.

[0172] Secondly, the first wireless communication device divides the SRS signal into 5 segments, with each segment corresponding to a 20MHz bandwidth.

[0173] Third, the first wireless communication device selects a first reference signal and a second reference signal from the five SRS signals. For example, the first wireless communication device can select the first SRS signal from the five segments as the first reference signal and the last SRS signal from the five segments as the second reference signal.

[0174] The above is just an example; two 20MHz bandwidth SRS signals can also be generated separately.

[0175] Fourth, at the first moment, the first wireless communication device transmits a first reference signal centered on carrier frequency f1. After being transmitted over the air interface, the first reference signal successively reaches three or more nearby second wireless communication devices. One beam of the first wireless communication device (e.g., Sub6G band) can cover multiple nearby second wireless communication devices. Therefore, when the first wireless communication device transmits once, three or more nearby second wireless communication devices can receive the SRS signal.

[0176] After transmitting the first reference signal, the first wireless communication device hops to (f1+80MHz) at a second time and transmits the second reference signal with the hopped carrier as the center. After being transmitted over the air interface, the second reference signal also arrives at three or more nearby second wireless communication devices.

[0177] The first and second moments can be separated by one or more time-domain symbol periods. To further improve the positioning accuracy of the first wireless communication device, the time interval between the first reference signal and the second reference signal can be as short as possible. For example, the first moment of transmitting the first reference signal and the second moment of transmitting the second reference signal can be separated by one time-domain symbol period.

[0178] This example demonstrates that to achieve higher positioning accuracy, the first wireless communication device can generate a higher bandwidth SRS signal at once, such as (2+N)*20MHz (e.g., 400MHz), and transmit it multiple times (e.g., twice). The frequency domain interval between the two frequency hopping sessions can be n*20MHz (n can be flexibly configured according to actual positioning accuracy requirements), and the frequency domains can be non-overlapping. This allows for the construction of a (2+N)*20MHz high bandwidth reference signal by transmitting small bandwidth reference signals multiple times. Since the TOA estimation accuracy is positively correlated with the reference signal bandwidth, the wider the bandwidth of the constructed signal, the higher the TOA accuracy estimated by the second wireless communication device based on the first and second reference signals received from the first wireless communication device. Consequently, the determined transmission delay is more accurate, leading to more accurate positioning of the first wireless communication device.

[0179] In one possible implementation, the phases of the first reference signal and the second reference signal in this application embodiment are substantially synchronized. Substantial phase synchronization of the first reference signal and the second reference signal in this application embodiment means that the phases of the first reference signal and the second reference signal are synchronized (phase difference is 0) or approximately synchronized (phase difference is less than a preset phase difference threshold). The specific forms of the phase difference between the first reference signal and the second reference signal will be illustrated in the following description.

[0180] In order to make the phases of the first reference signal and the second reference signal transmitted by the first wireless communication device through the first radio frequency channel substantially synchronized, Figure 7 The diagram above exemplarily illustrates the structure of the first wireless communication device provided in an embodiment of this application. Figure 7 The proposed scheme can achieve phase synchronization between the first reference signal and the second reference signal. In this embodiment, the first wireless communication device may include other radio frequency channels besides the first radio frequency channel, such as a radio frequency receiving channel or other radio frequency transmitting channels, etc., and no limitation is imposed in this embodiment.

[0181] Figure 7 The first radio frequency channel is connected to the antenna 70 and is used to process the baseband signal from the baseband subsystem 71 (such as upconversion, amplification and filtering) to obtain the radio frequency signal, and finally radiate the radio frequency signal into space through the antenna.

[0182] like Figure 7 As shown, the first radio frequency channel may include a DAC 72, a low-pass filter (LPF) 73, a mixer 74 (mixer 74 may also be called an uplink mixer), a variable gain amplifier 77, a PA 78, and a band-pass filter (BPF) 79.

[0183] It is important to note that Figure 7 The first radio frequency channel shown may further include a phase-locked loop (PLL) 75 and a phase-locked loop 76. The PLL 75 may be referred to as the first PLL. The PLL 75 may be selectively connected to the mixer 74. The PLL 75 can be used to generate a first local oscillator signal, the center frequency of which is the same as the center frequency of the first reference signal.

[0184] Phase-locked loop 76 can be referred to as the second phase-locked loop. Phase-locked loop 76 can be selectively connected to mixer 74. Phase-locked loop 76 can be used to generate a second local oscillator signal, the center frequency of which is the same as the center frequency of the second reference signal.

[0185] In S401 or S506 above, the first wireless communication device can connect the phase-locked loop 75 to the mixer 74 and disconnect the phase-locked loop 76 from the mixer 74 when it is necessary to send the first reference signal. In this way, the mixer 74 can receive the first local oscillator signal from the phase-locked loop 75, and then the first wireless communication device can send the first reference signal in the first frequency band according to the first local oscillator signal.

[0186] In S401 or S506 above, the first wireless communication device can connect the phase-locked loop 76 to the mixer 74 and disconnect the phase-locked loop 75 from the mixer 74 when it is necessary to send the second reference signal. In this way, the mixer 74 can receive the second local oscillator signal from the phase-locked loop 76, and then the first wireless communication device can send the second reference signal in the second frequency band according to the second local oscillator signal.

[0187] like Figure 7 As shown in the embodiments of this application, the first radio frequency channel can be capable of operating in multiple frequency bands. When the operating frequency band of the first radio frequency channel changes, one or more operating parameters of the radio frequency transmission channel need to be adjusted to change the operating frequency band of the first radio frequency channel. For example, when the operating frequency band of the first radio frequency channel changes between the first frequency band and the second frequency band, the parameters of at least one of the devices such as DAC72, low-pass filter 73, and band-pass filter 79 can be adjusted to achieve the purpose of adjusting the operating frequency band of the first radio frequency channel.

[0188] It should be noted that, Figure 7 The devices included in the first radio frequency channel shown are merely examples. In practical applications, in addition to the mixer 74, phase-locked loop 76, and phase-locked loop 75 included in the first radio frequency channel, more devices can be added to the first radio frequency receiving channel, or one or more devices shown in the figure can be deleted. It should be noted that, in the embodiments of this application... Figure 7 Phase-locked loop 76 can use the phase-locked loop of the first radio frequency channel, while phase-locked loop 75 can use phase-locked loops of other radio frequency channels, such as the phase-locked loop of the radio frequency receiving channel. This phase-locked loop can be time-division multiplexed, used for the data receiving process in the data receiving time slot and for the data transmitting process in the data transmitting time slot.

[0189] In the embodiments of this application, Figure 7 In this embodiment, phase-locked loop 75 and phase-locked loop 76 share the same reference clock signal. Figure 7Phase-locked loops 75 and 76 can share the same first synchronization module. This first synchronization module provides the same synchronization signal to both phase-locked loops 75 and 76, which can be referred to as the first synchronization signal to distinguish it from other synchronization signals. Both phase-locked loops 75 and 76 can adjust the phase difference between their respective output signals and the reference clock signal based on the first synchronization signal, thereby synchronizing the phases of their output signals. This can also be understood as phase-locked loops 75 and 76 determining the same effective edge (which can be a rising edge or a falling edge) of the reference clock signal as the first effective edge, and both adjusting the phase difference between their respective output signals and the reference signal based on this first effective edge. Furthermore, phase-locked loop 75 can be used to adjust the phase difference between the first local oscillator signal and the reference clock signal to a preset first phase difference, which can be 0 or a preset value. Phase-locked loop 76 can be used to adjust the phase difference between the second local oscillator signal and the reference clock signal to the preset first phase difference.

[0190] Figure 8a An exemplary embodiment of this application provides a method Figure 7 The structural schematic diagrams of phase-locked loops 75 and 76 are shown below. Figure 8a As shown, phase-locked loop 75 and phase-locked loop 76 share the same reference clock signal and can also share the same first synchronization module. Phase-locked loop 75 is used to generate a first local oscillator signal with a center frequency of a first frequency point. Phase-locked loop 76 is used to generate a second local oscillator signal with a center frequency of a second frequency point. The first center frequency point is the center frequency point of a first frequency band, and the second center frequency point is the center frequency point of a second frequency band.

[0191] like Figure 8a As shown, the phase-locked loop 75 includes a phase detector 751, a charge pump 752, a low-pass filter 753, an oscillator 754, and a frequency divider 756 connected in sequence. It also includes a frequency divider 755.

[0192] Phase detector 751 is used to receive the reference clock signal and the signal output by frequency divider 755, detect the phase relationship between the two, and generate an output signal that indicates the phase difference between the reference clock signal and the signal output by frequency divider 755.

[0193] The charge pump 752 is used to convert the phase difference output by the phase detector 751 into a level, which is then processed by a low-pass filter and input to the oscillator 754 to control the frequency of the oscillation signal output by the oscillator 754.

[0194] The low-pass filter 753, also known as a digital loop filter (DLF), is used to filter the received signal in order to output a frequency control signal for controlling the oscillator 754.

[0195] Oscillator 754 can be a voltage-controlled oscillator (VCO) used to receive a frequency control signal from low-pass filter 753 and output an oscillation signal under the control of the signal.

[0196] Frequency divider 756 receives the oscillation signal from oscillator 754 and divides the oscillation signal to obtain the first local oscillator signal. Frequency divider 756 can be used with... Figure 7 The frequency divider 74 is selectively connected. When the frequency divider 756 and the mixer 74 are connected, the mixer 74 can receive the first local oscillator signal from the frequency divider 756. When the frequency divider 756 and the mixer 74 are disconnected, the mixer 74 cannot receive the first local oscillator signal from the frequency divider 756. The frequency divider 756 can also be referred to as the first frequency divider.

[0197] Frequency divider 755 receives the first local oscillator signal output from frequency divider 756, performs frequency division processing on the first local oscillator signal, and inputs the frequency-divided signal to the input terminal of phase detector 751. Since frequency divider 755 is located in the feedback loop, it can also be called a feedback frequency divider. Frequency divider 755 can also be called a first feedback frequency divider.

[0198] The phase control module 757 is used to adjust the division ratio of the frequency divider 755. The phase control module 757 of this application can adjust the phase difference between the first local oscillator signal and the reference clock signal by adjusting the division ratio of the frequency divider 755.

[0199] It should be noted that, in Figure 8a In the illustrated scheme, the input terminal of the phase control module 757, in addition to receiving the reference clock signal and the output signal of the phase detector 751, also receives a signal from the first synchronization module. These three signals are then combined to adjust the division ratio of the frequency divider 755. Furthermore, it should be noted that both frequency dividers 756 and 766 are located within the phase-locked loop (PLL), therefore, their division ratios do not need to be the same, and can be different. When their division ratios are the same, the phase adjustment time of each of the PLLs 75 and 76 can be shortened.

[0200] like Figure 8aAs shown, the phase-locked loop 76 includes a phase detector 761, a charge pump 762, a low-pass filter 763, an oscillator 764, and a frequency divider 766 connected in sequence. It also includes a frequency divider 765.

[0201] Phase detector 761 is used to receive the reference clock signal and the signal output by frequency divider 765, detect the phase relationship between the two, and generate an output signal that indicates the phase difference between the reference clock signal and the signal output by frequency divider 765.

[0202] The charge pump 762 is used to convert the phase difference output by the phase detector 761 into a level, which is then processed by a low-pass filter and input to the oscillator 764 to control the frequency of the oscillation signal output by the oscillator 764.

[0203] The low-pass filter 763, also known as a digital loop filter (DLF), is used to filter the received signal in order to output a frequency control signal for controlling the oscillator 764.

[0204] Oscillator 764 can be a voltage-controlled oscillator (VCO) used to receive a frequency control signal from low-pass filter 763 and output an oscillation signal under the control of the signal.

[0205] Frequency divider 766 receives the oscillation signal from oscillator 764 and divides the oscillation signal to obtain the second local oscillator signal. Frequency divider 766 can be used with... Figure 7 The frequency divider 74 is selectively connected. When the frequency divider 766 and the mixer 74 are connected, the mixer 74 can receive the second local oscillator signal from the frequency divider 766. When the frequency divider 766 and the mixer 74 are disconnected, the mixer 74 cannot receive the second local oscillator signal from the frequency divider 766. The frequency divider 756 and the frequency divider 766 can be connected via a switch. Figure 7 The connection of mixer 74 in the middle. Frequency divider 766 can also be called second frequency divider.

[0206] Frequency divider 765 receives the second local oscillator signal output from frequency divider 766, performs frequency division on the second local oscillator signal, and inputs the frequency-divided signal to the input terminal of phase detector 761. Since frequency divider 765 is located in the feedback loop, it can also be called a feedback frequency divider. Frequency divider 765 can also be called a second feedback frequency divider.

[0207] The phase control module 767 is used to adjust the division ratio of the frequency divider 765. The phase control module 767 of this application can adjust the phase difference between the second local oscillator signal and the reference clock signal by adjusting the division ratio of the frequency divider 765.

[0208] It should be noted that, in Figure 8a In the scheme shown, the input terminal of the phase control module 767 is used to receive the reference clock signal and the output signal of the phase detector 761, as well as the signal from the first synchronization module, and to adjust the division ratio of the frequency divider 765 by combining the three signals.

[0209] like Figure 8a As shown, the first synchronization module can be connected to both the phase control module 757 and the phase control module 767. The first synchronization module can be used to send first synchronization signals to both the first and second phase control modules. In one possible implementation, when the phase-locked loop 75 is locked, it outputs a signal indicating that the phase-locked loop 75 is locked to the first synchronization module. Similarly, when the phase-locked loop 76 is locked, it outputs a signal indicating that the phase-locked loop 76 is locked to the first synchronization module. The first synchronization module can send the first synchronization signal after both the first and second phase-locked loops are locked.

[0210] It should be noted that, in the embodiments of this application, phase-locked loop (PLL) locking refers to the frequency synchronization between the local oscillator signal output by the PLL and the input reference clock signal, and the two can maintain a relatively fixed phase difference. For example, PLL 75 locking means that the first local oscillator signal output by PLL 75 and the reference clock signal maintain a relatively fixed phase difference (which can be expressed as...). Phase-locked loop 76 locking refers to maintaining a fixed phase difference between the second local oscillator signal output by phase-locked loop 76 and the reference clock signal (for example, it can be expressed as...). ). and The implementation details may be the same or different, and this application does not impose any limitations. In this application embodiment, after both phase-locked loop 75 and phase-locked loop 76 are locked, the phase between the local oscillator signals output by the two phase-locked loops and the reference clock signal is adjusted again to synchronize the phase of the first local oscillator signal and the second local oscillator signal.

[0211] The following is combined with Figure 8b A detailed introduction will be provided. Figure 8b An example is shown Figure 8a A schematic diagram of the reference clock signal, lock signal, and first synchronization signal is shown below. Figure 8bAs shown, the first synchronization module receives a reference clock signal. After receiving the lock signals from phase-locked loop 75 and phase-locked loop 76, the first synchronization module can select the falling edge of the next reference clock signal as the rising edge of the first synchronization signal. It should be noted that after receiving the lock signals from phase-locked loop 75 and phase-locked loop 76, the first synchronization module can delay for several reference clock signal periods before selecting the falling edge of the next reference clock signal as the rising edge of the first synchronization signal. Since the phase difference between the phase-locked loop output signal and the reference clock signal tends to stabilize after the phase-locked loop is locked, delaying for several reference clock signal periods can further stabilize the phase difference between the phase-locked loop output signal and the reference clock signal.

[0212] Furthermore, after the first synchronization module selects a falling edge of the reference clock signal as the rising edge of the first synchronization signal, the phase control module 757 and the phase control module 767, based on the rising edge of the signal output by the first synchronization module, both select the first (or a preset second, third, etc.) rising edge of the reference clock signal after that rising edge as the first valid edge. Then, the phase-locked loop 75 begins to adjust the phase of the first local oscillator signal and the reference clock signal based on the selected first valid edge, until the phase between the first local oscillator signal and the reference clock signal is adjusted to a preset first phase difference.

[0213] Specifically, after the phase control module 757 acquires the rising edge of the signal output by the first synchronization module, it detects the phase difference based on the phase detector 751. By controlling the division ratio of the frequency divider 755 within several cycles of the reference clock signal, it changes the output frequency of the oscillator 754 within those cycles, thereby changing the output integral phase and adjusting the phase difference. This achieves phase synchronization between the first and second local oscillator signals. This process can be repeated after each power-on of the phase-locked loop.

[0214] Similarly, the phase-locked loop 76 begins phase adjustment of the second local oscillator signal and the reference clock signal based on the selected first effective edge, until the phase between the second local oscillator signal and the reference clock signal is adjusted to a preset first phase difference. The preset first phase difference can be 0 or a preset value. The process by which the phase control module 767 adjusts the division ratio of the frequency divider 765 in the phase-locked loop 76 according to the signal output by the first synchronization module can be found in the content of the phase control module 757 described above, and will not be repeated here.

[0215] pass Figure 8bIt can be seen that after the phase-locked loop 75 and phase-locked loop 76 are locked, they both select the first effective edge of the reference clock signal as the reference for phase adjustment based on the first synchronization signal. Since the phase difference between the first local oscillator signal and the reference clock signal is the preset first phase difference after phase adjustment, and the phase difference between the second local oscillator signal and the reference clock signal is also the preset first phase difference, the first local oscillator signal and the second local oscillator signal are phase synchronized.

[0216] Figure 8c An example is shown Figure 8a A schematic diagram showing the frequency of the signal output by the phase-locked loop 75, the phase difference detected by the phase detector 75l, and the synchronization signal output by the first synchronization module, as shown below. Figure 8c As shown, the frequency of the signal output by the phase-locked loop 75 gradually increases, approaching the frequency of the first center frequency of the first local oscillator signal. Figure 8c As shown, the phase difference between the first local oscillator signal and the reference clock signal output by the phase-locked loop (PLL) tends to stabilize. When the phase difference between the first local oscillator signal and the reference clock signal tends to stabilize, the PLL 75 can be said to be in a locked state, or the PLL 75 is locked. When the PLL receives the first synchronization signal output from the first synchronization module, the PLL 75 begins to adjust the phase difference between the first local oscillator signal and the reference clock signal based on the first effective edge of the reference clock signal determined by the first synchronization signal.

[0217] It is important to note that, in Figure 8a In the provided solution, frequency divider 756 is located inside the phase-locked loop 75, meaning the input of frequency divider 755 is connected to the output of frequency divider 756. Frequency divider 766 is located inside the phase-locked loop 76, meaning the input of frequency divider 765 is connected to the output of frequency divider 766. Therefore, when the phases of their respective phase-locked loops are adjusted by phase control modules 757 and 767, random phase jitter between frequency dividers 756 and 766 can be eliminated.

[0218] Compared to a scheme that uses only one phase-locked loop (PLL) to provide the mixer with the first and second local oscillator signals sequentially, using only one PLL results in a process of locking, unlocking, and relocking because the PLL needs to switch between the first and second center frequencies. The two locking cycles of a single PLL introduce uncertain phase jitter. Figure 7 and Figure 8a The proposed solution uses two phase-locked loops to provide two local oscillator signals, which avoids the phase-locked loop relocking process and thus eliminates the uncertain phase jitter introduced by phase-locked loop relocking.

[0219] On the other hand, since the center frequency of the local oscillator signal received by the first RF channel can be switched by switching two phase-locked loops, compared with the scheme that uses only one phase-locked loop to provide the first local oscillator signal and the second local oscillator signal to the mixer sequentially, Figure 7 and Figure 8a The process of switching from receiving the first local oscillator signal to receiving the second local oscillator signal in the first radio frequency channel can be shortened, for example, the process can be shortened to 1 symbol period. This can shorten the time interval between the transmission time of the first reference signal and the transmission time of the second reference signal, thereby further improving the positioning accuracy. Furthermore, since the time interval between transmitting the first reference signal and transmitting the second reference signal is shortened, the working time of the wireless communication device can be reduced, its sleep time can be increased, and power consumption can be reduced.

[0220] To explain Figure 7 and Figure 8a The beneficial effects of the proposed solution are demonstrated below through a simulation example. This can be seen by combining the following formulas (1) and (2):

[0221]

[0222]

[0223] In the above formulas (1) and (2), N represents the division factor (also called the division ratio) of the frequency divider of the phase-locked loop (such as frequency divider 755 and frequency divider 765).

[0224] int represents the integer part of the frequency division coefficient of the frequency divider;

[0225] This represents the fractional part of the division coefficient of the frequency divider; where frac is the numerator and MOD is the denominator.

[0226] T refclk It indicates the duration of a cycle.

[0227] As can be seen from the above formulas (1) and (2), MOD can determine the minimum phase difference between the output signal of the phase-locked loop and the reference clock signal. Figure 8aTaking the phase-locked loop 75 as an example, if the reference clock signal is 38.4MHz, the signal output by the frequency divider 755 is related to the denominator MOD of the fraction. The phase of the signal output by the frequency divider 755 can cover one cycle, and the phase step is (duration of one cycle / MOD). It should be noted that the phase deviation between two signals can be identified by angle, or by the interval between the rising edges of two signals (such as two clock signals). Therefore, in the above formula (2), it can also be said that the phase of the signal output by the frequency divider 755 can cover 360°, and the phase step is (360° / MOD).

[0228] Taking a 24-bit MOD value in phase-locked loop 75 as an example, the minimum allowed phase difference between the output signal of phase-locked loop 75 and the reference clock signal is 0.005 ps. For instance, if MOD is greater than 2604, by controlling the phase difference between the first local oscillator signal output by phase-locked loop 75 and the reference clock signal, and by controlling the phase difference between the second local oscillator signal and the reference clock signal through phase-locked loop 76, the phase difference between the first and second local oscillator signals can be controlled within 10 picoseconds (ps). To achieve an even smaller phase deviation, the MOD value can be increased through the configuration register.

[0229] In practical applications, within the 1.5GHz frequency band below 6GHz, the bandwidths of N41, N77, N78, and N79 are greater than 100MHz, making them suitable for high-precision positioning (high bandwidth). Table 1 provides illustrative examples of several possible simulation results. Using the values ​​in the first row of Table 1 as an example, the positioning signal bandwidth (including the total bandwidth of the first and second frequency bands, as well as the bandwidth of the frequency bands between the first and second frequency bands) is 100MHz. The maximum allowable phase difference (also known as phase jitter) between the first and second reference signals is 277.7ps. As can be seen from Table 1, N41, N77, N78, and N79 all meet the requirements. The 277.7ps phase difference requirement for 100MHz positioning is calculated using the following formula: (duration of one cycle) * 10° / 360° = (1 / 100MHz) * 10 / 360 = 277.7ps.

[0230] Table 1. Simulation Results

[0231]

[0232] Simulation results from several examples in Table 1 show that when the phase difference between the first and second reference signals is less than 10 degrees, they are close to coherent. When MOD > 2604, controlling the phase difference between the first and second reference signals to within 4 ps can meet the phase deviation requirement for positioning with a bandwidth of less than 100 MHz (the phase deviation requirement for positioning with a bandwidth of 100 MHz is 277.7 ps). The bandwidth requirements for other positioning signals are similar and will not be elaborated further.

[0233] Figure 9a An exemplary embodiment of this application provides a method Figure 7 The schematic diagram of phase-locked loop 75 and phase-locked loop 76 is shown. Figure 9a In the provided scheme, the phases of the first reference signal and the second reference signal are approximately synchronized. The phase difference between the first reference signal and the second reference signal is equal to the phase difference between the signals output by oscillator 754 and oscillator 764. The phase difference between the first reference signal and the second reference signal can also be understood as the phase difference between the first local oscillator signal and the second local oscillator signal. It should be noted that... Figure 9a and Figure 8a The difference is: Figure 9a The intermediate frequency divider 756 is located outside the loop of the phase-locked loop 75, that is... Figure 9a The input terminal of frequency divider 755 is connected to the output terminal of oscillator 754, not the output terminal of frequency divider 756. Frequency divider 756 is located outside the loop of phase-locked loop 76, that is... Figure 9a The input terminal of the frequency divider 765 is connected to the output terminal of the oscillator 764, not the output terminal of the frequency divider 766. Furthermore... Figure 9a The first synchronization module has been removed. A second synchronization module has been added. Figure 9a For other components, please refer to Figure 8a The relevant descriptions in [the document] will not be repeated here. It should be added that, in [the document]... Figure 8a A second synchronization module can also be added. The functions of the second synchronization module are as follows: Figure 9a The second synchronization module in it has the same function and purpose.

[0234] It is important to note that Figure 9a Phase-locked loop 75 and phase-locked loop 76 still share the same reference clock signal. However, frequency dividers 756 and 766 introduce random phase errors, for the following reasons:

[0235] A frequency divider with a division ratio of N can essentially be understood as a counter. The counter accumulates the rising edges (cycles) of the input clock signal. When the counter reaches N-1, it outputs the first rising edge of the divided clock signal. However, the first clock edge at which a frequency divider begins counting is uncertain; it may start counting at the first rising edge of the received clock signal or at the second rising edge. Based on this, frequency divider 756 may start counting at the first rising edge of the received signal, while frequency divider 766 may start counting at the second or third rising edge of the received signal. This uncertainty leads to a random phase error between the first and second local oscillator signals.

[0236] To resolve the random phase error introduced by frequency divider 756 and frequency divider 766 Figure 9a In this configuration, a second synchronization module can be provided for frequency dividers 756 and 766 to provide a second synchronization signal, enabling frequency dividers 7546 and 766 to perform frequency division based on the same second synchronization signal. The division ratios of frequency dividers 756 and 766 can be the same, thus ensuring that the phase difference between the first local oscillator signal and the second local oscillator signal is equal to the phase difference between the signals output by oscillators 754 and 764.

[0237] Figure 9a In the provided scheme, adjusting the division ratio of the frequency divider 755 via the phase control module 757 allows the signal output from the oscillator 754 to maintain a relatively fixed phase difference with the reference clock signal. When this phase difference is maintained, the phase-locked loop 75 is considered to be in a locked state. Similarly, adjusting the division ratio of the frequency divider 765 via the phase control module 767 allows the signal output from the oscillator 764 to maintain a relatively fixed phase difference with the reference clock signal. When this phase difference is maintained, the phase-locked loop 76 is considered to be in a locked state. When both phase-locked loops 75 and 76 are locked, a phase difference exists between the signals output from the oscillators 754 and 764; this phase difference can be called the initial phase difference.

[0238] Furthermore, since the phase difference between oscillators 754 and 764 is less than one of the minimum clock cycles in the signals output by oscillators 754 and 764, when the phase difference between the first local oscillator signal and the second local oscillator signal is the same as the phase difference between oscillators 754 and 764, the phase change requirements of bandwidths such as 100M / 200M / 300M / 400M can be met.

[0239] The following is combined with Figure 9b A detailed introduction will be provided. Figure 9b An example is shown Figure 9a A schematic diagram of a reference clock signal, a lock signal, a second synchronization signal, signals output by oscillator 754, signals output by oscillator 764, signals output by frequency divider 756, and signals output by frequency divider 766 is shown below. Figure 9b As shown, the second synchronization module receives a reference clock signal. After receiving the lock signals from phase-locked loop 75 and phase-locked loop 76, the second synchronization module can select the falling edge of the next reference clock signal as the rising edge of the second synchronization signal. It should be noted that after receiving the lock signals from phase-locked loop 75 and phase-locked loop 76, the second synchronization module can delay for several reference clock signal periods before selecting the falling edge of the next reference clock signal as the rising edge of the second synchronization signal. Since the phase difference between the phase-locked loop output signal and the reference clock signal tends to stabilize after the phase-locked loop is locked, delaying for several reference clock signal periods can further stabilize the phase difference between the phase-locked loop output signal and the reference clock signal.

[0240] Furthermore, after the second synchronization module selects a falling edge of the reference clock signal as the rising edge of the second synchronization signal, the frequency divider 756 uses the rising edge of the signal output by the received second synchronization module as a reference and selects the first rising edge of the signal output by the oscillator 754 after receiving the rising edge of the second synchronization signal as the starting rising edge for frequency division.

[0241] Similarly, the frequency divider 766 uses the rising edge of the signal output by the received second synchronization module as a reference, and selects the first rising edge of the signal output by the oscillator 764 after the rising edge of the received second synchronization signal as the starting rising edge for frequency division.

[0242] In this way, it can be ensured that the phase difference between the selected starting rising edges of frequency divider 756 and frequency divider 766 is the same as the phase difference between oscillator 754 and oscillator 764 (e.g., ...). Figure 9b (The initial phase difference shown). Figure 9b Both frequency divider 756 and frequency divider 766 use the first rising edge of the received signal after receiving the second synchronization signal as the starting rising edge. Alternatively, both frequency divider 756 and frequency divider 766 can use the second (or third, fourth, etc.) rising edge of the received signal after receiving the second synchronization signal as the starting rising edge, as long as the frequency divider 756 and frequency divider 766 do not introduce a new phase deviation between the first local oscillator signal and the second local oscillator signal due to the selection of the starting rising edge position.

[0243] The following is illustrated in Tables 2 and 3. Figure 9a The simulation results of the proposed scheme are shown in Table 2. Figure 9aThe table below illustrates the simulation results for the maximum phase difference between the first and second local oscillator signals. Taking the values ​​in the first row as an example, the bandwidth of frequency band N41 is 2496MHz-2690MHz, with a total bandwidth of 194MHz. Using phase-locked loop 75 as an example, assuming the frequency divider 756 is a 4-fold divider (a common division ratio in the Sub-6GHz band), the center frequency of oscillator 754 is four times the center frequency of the first local oscillator signal. The center frequency of the first local oscillator signal is 2593MHz (the center frequency of the 2496MHz-2690MHz band), and the center frequency of oscillator 754 is 10.372GHz (four times the center frequency of the first local oscillator signal). The maximum phase difference between the first and second local oscillator signals is one cycle of the clock signal output by oscillator 754, which is 96.4ps. The contents of the other rows are similar and will not be repeated here.

[0244] Table 2 is... Figure 9a A schematic table illustrating the simulation results of the maximum phase difference between the first and second local oscillator signals.

[0245]

[0246] Table 3 illustrates several possible simulation results. Using the values ​​in the first row of Table 3 as an example, the positioning signal bandwidth (including the total bandwidth of the first and second frequency bands, and the bandwidth of the frequency bands between the first and second frequency bands) is 100 MHz. The maximum allowed phase difference between the first and second reference signals is 277.7 ps. N41, N77, N78, and N79 all meet the requirements. It should be noted that with a 400 MHz bandwidth, the frequency hopping bandwidth in the N78 band can be reduced, providing more assurance for meeting the phase requirements.

[0247] Table 3. Simulation Results

[0248]

[0249]

[0250] Figure 10 An exemplary embodiment of this application provides a method Figure 7 The schematic diagram of phase-locked loop 75 and phase-locked loop 76 is shown. Figure 10 The provided scheme can synchronize the phase between the first and second reference signals. It should be noted that... Figure 10 and Figure 9a The difference is that a first synchronization module has been added, which is connected to the phase control module 757 and the phase control module 767.

[0251] in, Figure 10 The first synchronization module and Figure 8a The first synchronization module in both modules has the same function, so it will not be described again here. The difference is that the phase control module 757 changes the phase difference between the signal output by the oscillator 754 and the reference clock signal by adjusting the division ratio of the frequency divider 755, while the phase control module 767 changes the phase difference between the signal output by the oscillator 764 and the reference clock signal by adjusting the division ratio of the frequency divider 765.

[0252] like Figure 10 As shown, after receiving the first synchronization signal from the first synchronization module, phase control module 757 and phase control module 767 each select the first (or a preset second, third, etc.) rising edge of the reference clock signal following the rising edge of the first synchronization signal as the initial phase, using the selected initial phase as a reference. Then, phase-locked loop 75 begins to adjust the phase of the signal output by oscillator 754 and the reference clock signal based on the selected initial phase, until the phase between the signal output by oscillator 754 and the reference clock signal is adjusted to a preset first phase difference.

[0253] Similarly, the phase-locked loop 76 begins to adjust the phase of the signal output by the oscillator 764 and the reference clock signal based on the selected initial phase, until the phase between the signal output by the oscillator 764 and the reference clock signal is adjusted to a preset first phase difference.

[0254] Since both phase control module 757 and phase control module 767 select the same position of the reference clock signal as the initial phase according to the first synchronization signal, and since the phase difference between the signal output by oscillator 754 and the reference clock signal after phase adjustment is the preset first phase difference, and the phase difference between the signal output by oscillator 764 and the reference clock signal is also the preset first phase difference, the signals output by oscillator 754 and the signals output by oscillator 764 are phase synchronized.

[0255] And because Figure 10 A second synchronization module is provided for frequency dividers 7546 and 766 to provide a second synchronization signal for them, so that frequency dividers 7546 and 766 perform frequency division based on the same second synchronization signal, thereby making the phase difference between the first local oscillator signal and the second local oscillator signal the phase difference between oscillators 754 and 764. Based on the phase synchronization of the signals output by oscillators 754 and 764, the first local oscillator signal and the second local oscillator signal are phase synchronized.

[0256] Figure 11 An exemplary schematic diagram of another first wireless communication device provided in an embodiment of this application is shown. Figure 11 The proposed scheme can synchronize the phase between the first reference signal and the second reference signal. Figure 11 and Figure 7 The difference is that, Figure 11 The circuit includes only one phase-locked loop (PLL) 81. PLL 81, which can be referred to as the third PLL, is coupled to mixer 74 and is used to generate a third local oscillator (LO) signal during the transmission of the first reference signal and a fourth LO signal during the transmission of the second reference signal. The center frequency of the third LO signal is the same as that of the first reference signal; the center frequency of the fourth LO signal is the same as that of the second reference signal. In other words, PLL 81 first outputs the third LO signal, then switches its frequency to output the fourth LO signal. Alternatively, PLL 81 can be understood as first locking, then outputting the third LO signal, then unlocking, then locking again, and finally outputting the fourth LO signal. To synchronize the phases of the first and second reference signals, in this embodiment, the third and fourth LO signals can be synchronized.

[0257] Figure 12a An example is shown. Figure 11 A schematic diagram of the structure of the intermediate phase-locked loop 81 is shown below. Figure 12a As shown, the phase-locked loop 81 includes a phase detector 811, a charge pump 812, a low-pass filter 813, an oscillator 814, and a frequency divider 816 connected in sequence. It also includes a frequency divider 815. Frequency divider 816 can be referred to as the third frequency divider, and frequency divider 815 can be referred to as the third feedback frequency divider. The functions of the related components can be found in the preceding description. Figure 8a The relevant content will not be repeated here.

[0258] Figure 12a The schematic diagram of the first wireless communication device also includes a third synchronization signal module. The output of the third synchronization signal module is connected to the third phase control module and is used for the third synchronization signal. The third synchronization signal can be output periodically. During the process of the third phase-locked loop outputting the third local oscillator signal: after the third phase-locked loop is locked, the third phase control module determines the second effective edge of the reference signal based on the received third synchronization signal, and adjusts the phase difference between the third local oscillator signal output by the third phase-locked loop and the reference clock signal to a preset second phase difference based on the second effective edge.

[0259] During the process of the third phase-locked loop outputting the fourth local oscillator signal: after the third phase-locked loop is locked, the third phase control module determines the third effective edge according to the received third synchronization signal, and adjusts the phase difference between the fourth local oscillator signal output by the third phase-locked loop and the reference clock signal to the preset second phase difference based on the third effective edge.

[0260] Figure 12b An example is shown Figure 12aA schematic diagram of the reference clock signal, the locking signal of the phase-locked loop 81, the signal output by the third synchronization module, and the signal output by the phase-locked loop 81 is shown below. Figure 12b As shown, the third synchronization module periodically outputs a third synchronization signal. The frequency of the third synchronization signal is the common divisor of the center frequency of the third local oscillator signal and the center frequency of the fourth local oscillator signal. In another possible implementation, the frequency of the third synchronization signal can be the common divisor of the frequency of the reference clock signal, the center frequency of the third local oscillator signal, and the center frequency of the fourth local oscillator signal.

[0261] After the phase-locked loop 81 locks for the first time, the rising edge of the first reference clock signal received after the phase control module 817 receives the first third synchronization signal is determined as the second valid edge. Then, based on this second valid edge, the phase difference between the third local oscillator signal output by the phase-locked loop 81 and the reference clock signal is adjusted to a preset second phase difference. The second phase difference can be 0 or a preset value. When the second phase difference is 0, it can be said that the phase-locked loop 81, based on the second valid edge, adjusts the phase difference between the third local oscillator signal output by the phase-locked loop 81 and the reference clock signal to 0, thereby achieving phase synchronization between the third local oscillator signal and the reference clock signal.

[0262] After the first wireless communication device finishes transmitting the first reference signal through the first radio frequency channel, the phase-locked loop (PLL) is in a unlocked state and then locks for the second time. After the PLL 81 locks for the second time, the rising edge of the first reference clock signal received after the phase control module 817 receives the first third synchronization signal is determined as the third valid edge. Then, based on the third valid edge, the phase difference between the fourth local oscillator signal output by the PLL 81 and the reference clock signal is adjusted to a preset second phase difference. The second phase difference can be 0 or a preset value. Figure 12b The diagram illustrates the second phase difference as 0. When the second phase difference is 0, it can be said that the phase-locked loop 81, using the third effective edge as a reference, adjusts the phase difference between the fourth local oscillator signal output by the phase-locked loop 81 and the reference clock signal to 0, thereby achieving phase synchronization between the fourth local oscillator signal and the reference clock signal. For details on how the phase control module 817 adjusts the phase difference between the signal output by the phase-locked loop 81 and the reference clock signal, please refer to the aforementioned... Figure 8a The relevant description of the phase control module 757 will not be repeated here.

[0263] It should be noted that, Figure 12b For illustrative purposes only, in practical applications, the duration of the first lock of the phase-locked loop 81 may include the period of the reference clock signal or multiple periods of the third synchronization signal. One period of the third synchronization signal may include multiple periods of the reference clock signal.

[0264] Because the third synchronization module periodically provides a third synchronization signal to the phase control module 817, although the third and fourth local oscillator signals are output by the phase-locked loop 81 after two separate locking cycles, the phase-locked loop 81 synchronizes the phases of the third local oscillator signal and the reference clock signal, and the fourth local oscillator signal and the reference clock signal, based on the third synchronization signal after each locking. Furthermore, since the frequency of the third synchronization signal is the common divisor of the center frequencies of the third and fourth local oscillator signals, and given that the two signals can be synchronized to the frequency of the greatest common divisor of their frequencies, the third and fourth local oscillator signals are phase-synchronized.

[0265] In another possible implementation, the phase difference between the phase-adjusted third local oscillator signal and the third synchronization signal is equal to the phase difference between the phase-adjusted fourth local oscillator signal and the third synchronization signal. The third synchronization signal is phase-synchronized with the reference clock signal. Furthermore, since the frequency of the third synchronization signal is the common divisor of the center frequencies of the third and fourth local oscillator signals, and since it has been explained that two signals can be synchronized to the frequency of the greatest common divisor of their frequencies, the phase-adjusted third local oscillator signal can be phase-synchronized with the third synchronization signal. The phase-adjusted fourth local oscillator signal is also phase-synchronized with the third synchronization signal.

[0266] Figure 13 An example is shown. Figure 11 Another structural schematic diagram of the intermediate phase-locked loop 81, compared to Figure 12a The difference is that, Figure 13 A fourth synchronization module is added between the third synchronization module and the phase control module. After detecting that the third phase-locked loop is locked, the fourth synchronization module transmits the received third synchronization signal from the third synchronization module to the third phase control module. After detecting that the third phase-locked loop is unlocked, the fourth synchronization module stops transmitting the received third synchronization signal from the third synchronization module to the third phase control module. This saves power consumption.

[0267] It is important to note that, in Figure 12a and Figure 13 In the provided solution, the frequency divider 816 is located inside the phase-locked loop 81, that is, the input terminal of the frequency divider 815 is connected to the output terminal of the frequency divider 816. Therefore, when the phase of the phase-locked loop 81 is adjusted by the phase control module 817 based on the periodically sent third synchronization signal after two phase locks, the random phase jitter caused by the frequency divider 816 during the two locks can be eliminated.

[0268] Figure 14An example is shown above. Figure 4 One possible implementation of S402 is as follows: Figure 14 As shown, the second wireless communication device combines the two received signals in the time domain to obtain a third reference signal.

[0269] The following is combined with Figure 14 The solution for the second wireless communication device side is described, such as... Figure 14 As shown:

[0270] The first wireless communication device transmits a first reference signal at a first moment, and the first reference signal occupies a bandwidth of 20MHz. The second wireless communication device samples the received signal at a sampling rate corresponding to a bandwidth of 100MHz, and obtains y1(t) at a third moment (where y1(t) can be understood as the first reference signal received by the second wireless communication device).

[0271] The first wireless communication device transmits a second reference signal at a second time point, the second reference signal occupying a 20MHz bandwidth. The second wireless communication device samples the received signal at a sampling rate corresponding to a 100MHz bandwidth, and obtains y2(t) at a fourth time point (where y2(t) can be understood as the second reference signal received by the second wireless communication device).

[0272] The second wireless communication device superimposes the signals y1(t) and y2(t) obtained from the two trials in the time domain to obtain the third reference signal y(t), which can be written as: y(t) = y1(t) + y2(t).

[0273] The second wireless communication device locally generates a 100MHz bandwidth SRS sequence x(t). It can retain only the first 20MHz and last 20MHz of the SRS sequence x(t) with SRS signals, and set the middle 60MHz to 0. That is, it retains the SRS signals of the first and second frequency bands of the SRS sequence x(t), and sets the rest to 0.

[0274] Furthermore, the second wireless communication device performs cross-correlation calculations using the following formula (3):

[0275] R(τ)=∑ k y(t)x(t+τ) * ...Formula (3)

[0276] In formula (3), y(t) represents the signal superimposed on y1(t) and y2(t) in the time domain, and x(t) represents a 100MHz bandwidth SRS sequence x(t) locally generated by the second wireless communication device, wherein the signals of the other frequency bands in the SRS sequence x(t) other than the SRS signals of the first and second frequency bands can be set to 0. x(t+τ) represents the sequence after cyclically shifting x(t) by τ points, and * indicates taking the conjugate.

[0277] Since the SRS sequence uses a ZC sequence, it has good autocorrelation and low cross-correlation. When the two sequences are aligned, a spike will appear. The Time of Arrival (TOA) of the received signal is obtained by searching for the time corresponding to the spike. Because the frequency bandwidth of the signal used for positioning is larger, the time-domain pulse is narrower; and because the signal bandwidth used for positioning is higher, the second wireless communication device can use a higher sampling rate to sample the received signal. Therefore, when the second wireless communication device performs sequence correlation detection, it is easier to detect the first path of the SRS, resulting in a more accurate TOA and thus higher positioning accuracy for the first wireless communication device. In this embodiment, the positioning accuracy of the first wireless communication device obtained by only transmitting the first and second reference signals is comparable to the positioning accuracy obtained by transmitting the full bandwidth signal (including the first frequency band, the second frequency band, and the interval frequency band between the first and second frequency bands). In this embodiment, to further improve positioning accuracy, the MUSIC algorithm can be further used in the frequency domain for fine time delay estimation to obtain a high-precision TOA. The scheme provided in this embodiment can also be applied to carrier aggregation (CA) positioning. The phase-to-physical synchronization technology provided in this application embodiment can also be applied to the phase-to-physical synchronization of two carriers in 5G CA high-precision positioning.

[0278] In the process of estimating the TOA of the third reference signal, for example, a threshold can be set, and the delay corresponding to the first peak point that exceeds the threshold can be determined as the path delay of the first wireless communication device and the second wireless communication device.

[0279] TOA cor =arg(|R(τ)) peak | first >threshold×R max )......Formula (4)

[0280] In formula (4), R(τ) peak This represents the peak point of the correlation sequence R(τ) in formula (3);

[0281] TOA cor Indicates the path delay of the first wireless communication device and the second wireless communication device;

[0282] |R(τ) peak | first This represents the first peak point of the correlation sequence R(τ) in formula (3);

[0283] threshold represents the set threshold value;

[0284] R max This represents the highest peak point of the correlation sequence R(τ) in formula (3);

[0285] arg represents the function that evaluates the arguments to the function;

[0286] Formula (4) indicates that the delay corresponding to the first peak point greater than the threshold is the path delay from the first wireless communication device to the second wireless communication device, TOA. cor =τ Cor .

[0287] To further demonstrate the beneficial effects of this application, a simulation scenario is provided below. Considering that factories have high requirements for positioning accuracy, and that the larger the distance between base stations (which can be the aforementioned second wireless communication device), the lower the positioning accuracy, the InF-SH (indoor factory, sparse station spacing, 50m station spacing) scenario is used to simulate the positioning accuracy of the solution provided in the embodiments of this application.

[0288] Figure 15 A schematic diagram of a simulation environment provided by an embodiment of this application is illustrated, and Table 4 illustrates a schematic table of system parameters. The following is in conjunction with... Figure 15 Table 4 introduces the simulation parameters:

[0289] Number of base stations: 18 (7 of them will be selected for location services);

[0290] Factory dimensions: 300 meters long, 150 meters wide, and 10 meters high;

[0291] Base station height: 8 meters;

[0292] UE height: 1.5 meters;

[0293] Base station antenna configuration: (4, 4, 2, 1, 1);

[0294] UE antenna configuration: (1, 2, 2, 1, 1).

[0295] Table 4 provides an example of a schematic table of system parameters.

[0296]

[0297] Table 5. Simulation Results

[0298]

[0299]

[0300] For example, in simulation scenarios 3 and 6 in Table 5, simulation scenario 3 achieves a positioning accuracy of 0.035mCEP90%@LOS by constructing a 400MHz bandwidth through two frequency hopping transmissions. This is comparable to the positioning accuracy (0.018m) achieved by simulation scenario 6 by transmitting a complete 400MHz bandwidth signal. Both achieve centimeter-level positioning accuracy. However, in the embodiments of this application, the first wireless communication device only needs to transmit two narrow bandwidth signals, thereby improving the positioning accuracy of the low-performance wireless communication device and reducing the power consumption of the wireless communication device.

[0301] It is understood that, in order to achieve the functions in the above embodiments, the first wireless communication device and the second wireless communication device include hardware structures and / or software modules corresponding to each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0302] Figure 16 , Figure 17 and Figure 18 The diagram illustrates the possible structures of communication devices provided in embodiments of this application. These communication devices can be used to implement the functions of the first or second wireless communication device in the above method embodiments, and thus also achieve the beneficial effects of the above method embodiments. In the embodiments of this application, the communication device can be as follows: Figure 1 The first wireless communication device shown can also be as follows: Figure 1 The second wireless communication device shown can also be a module (such as a chip) applied to the first or second wireless communication device.

[0303] like Figure 16 As shown, the communication device 1300 includes a processing unit 1310 and a transceiver unit 1320. The communication device 1300 is used to implement the above-mentioned... Figure 4 or Figure 5 The method embodiments shown illustrate the functions of the first or second wireless communication device.

[0304] When the communication device 1300 is used to implement Figure 4 or Figure 5In the method embodiment shown, the function of the first wireless communication device is as follows: the processing unit 1310 is used, through the transceiver unit 1320, to transmit a first reference signal in a first frequency band and a second reference signal in a second frequency band. The transmission times of the first and second reference signals are different, and the center frequencies of the first and second frequency bands are different. The first and second reference signals are substantially synchronized in phase, and can be used to jointly estimate the arrival time of the reference signal.

[0305] When the communication device 1300 is used to implement Figure 4 or Figure 5 In the illustrated method embodiment, the function of the second wireless communication device is as follows: Processing unit 1310 is configured, through transceiver unit 1320, to: receive a first reference signal, where the first reference signal is a signal of a first frequency band; receive a second reference signal, where the second reference signal is a signal of a second frequency band. The transmission times of the first and second reference signals are different, and the center frequencies of the first and second frequency bands are different; the phases of the first and second reference signals are substantially synchronized. The arrival time of the reference signal is estimated jointly based on the first and second reference signals.

[0306] For a more detailed description of the processing unit 1310 and the transceiver unit 1320, please refer to [the relevant documentation]. Figure 4 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0307] like Figure 17 As shown, the communication device 1400 includes a processing circuit 1410 and an interface circuit 1420. The processing circuit 1410 and the interface circuit 1420 are coupled to each other. It is understood that the interface circuit 1420 can be a transceiver or an input / output interface. Optionally, the communication device 1400 may also include a memory for storing instructions executed by the processing circuit, or storing input data required for the processing circuit 1410 to execute instructions, or storing data generated after the processing circuit 1410 executes instructions.

[0308] When the communication device 1400 is used to implement Figure 4 or Figure 5 In the method shown, the processing circuit 1410 is used to implement the function of the processing unit 1310, and the interface circuit 1420 is used to implement the function of the transceiver unit 1320.

[0309] like Figure 18As shown, the communication device 1500 includes a processor 1510 and a communication interface 1520. The processor 1510 and the communication interface 1520 are coupled to each other. It is understood that the communication interface 1520 can be a transceiver or an input / output interface. Optionally, the communication device 1500 may also include a memory 1530 for storing instructions executed by the processor 1510, or storing input data required by the processor 1510 to execute instructions, or storing data generated after the processor 1510 executes instructions.

[0310] When the communication device 1500 is used to achieve Figure 4 or Figure 5 In the method shown, the processor 1510 is used to implement the functions of the processing unit 1310, and the communication interface 1520 is used to implement the functions of the transceiver unit 1320.

[0311] When the communication device 1500 is used to achieve Figure 4 or Figure 5 In the illustrated method embodiment, the first wireless communication device functions as follows: the processor 1510 performs the following via the communication interface 1520: transmitting a first reference signal in a first frequency band and transmitting a second reference signal in a second frequency band. The transmission times of the first and second reference signals are different, and the center frequencies of the first and second frequency bands are different. The first and second reference signals are substantially synchronized in phase, and can be used to jointly estimate the arrival time of the reference signal.

[0312] When the communication device 1500 is used to achieve Figure 4 or Figure 5 In the method embodiment shown, the function of the second wireless communication device is as follows: the processor 1510 is used to perform the following through the communication interface 1520: receiving a first reference signal, the first reference signal being a signal of a first frequency band; receiving a second reference signal; the second reference signal being a signal of a second frequency band; wherein the transmission time of the first reference signal is different from the transmission time of the second reference signal, and the center frequency of the first frequency band is different from the center frequency of the second frequency band; wherein the first reference signal and the second reference signal are substantially synchronized in phase; and estimating the arrival time of the reference signal based on the first reference signal and the second reference signal.

[0313] When the aforementioned communication device is a chip applied to a first wireless communication device, the first wireless communication device chip implements the functions of the first wireless communication device in the above method embodiments. The first wireless communication device chip receives information from other modules (such as radio frequency modules or antennas) in the first wireless communication device, the information being sent to the first wireless communication device by the second wireless communication device; or, the first wireless communication device chip sends information to other modules (such as radio frequency modules or antennas) in the first wireless communication device, the information being sent to the second wireless communication device by the first wireless communication device.

[0314] When the aforementioned communication device is a module applied to a second wireless communication device, the second wireless communication device module implements the functions of the second wireless communication device in the above method embodiments. The second wireless communication device module receives information from other modules (such as a radio frequency module or antenna) in the second wireless communication device, the information being sent from the first wireless communication device to the second wireless communication device; or, the second wireless communication device module sends information to other modules (such as a radio frequency module or antenna) in the second wireless communication device, the information being sent from the second wireless communication device to the first wireless communication device. Here, the second wireless communication device module can be the baseband chip of the second wireless communication device, or it can be a DU or other modules. The DU here can be a DU under an open radio access network (O-RAN) architecture.

[0315] It is understood that the processor in the embodiments of this application may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0316] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code or instructions, which, when executed on a computer, cause the computer to perform... Figure 4 and Figure 5 The method of any one of the embodiments shown.

[0317] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to perform... Figure 4 and Figure 5 The method of any one of the embodiments shown.

[0318] According to the method provided in the embodiments of this application, this application also provides a chip system, which may include a processor. The processor is coupled to a memory and can be used to execute... Figure 4 and Figure 5 The method of any one of the embodiments shown. Optionally, the chip system further includes a memory. The memory is used to store computer programs (also referred to as code or instructions). The processor is used to retrieve and run the computer programs from the memory, causing the device on which the chip system is installed to perform... Figure 4 and Figure 5 The method of any one of the embodiments shown.

[0319] According to the method provided in the embodiments of this application, this application also provides a system including the aforementioned first wireless communication device and one or more second wireless communication devices.

[0320] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Furthermore, the ASIC can reside in a first wireless communication device or a second wireless communication device. Alternatively, the processor and storage medium can exist as discrete components in the first or second wireless communication device.

[0321] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer programs or instructions. When a computer program or instruction is loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, a computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or non-volatile storage medium, or may include both types of storage media.

[0322] It should be noted that a portion of this patent application contains copyrighted material. The copyright holder retains all rights except for making copies of the contents of patent documents or records from the patent office.

[0323] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0324] In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates an "or" relationship between the preceding and following related objects; in the formulas of this application, the character " / " indicates a "division" relationship between the preceding and following related objects. "Including at least one of A, B, and C" can mean: including A; including B; including C; including A and B; including A and C; including B and C; including A, B, and C.

[0325] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. A wireless communication device, characterized in that, Includes processing circuitry and an interface circuit coupled to the processing circuitry, wherein the processing circuitry is configured to communicate via the interface circuitry: A first reference signal is transmitted in the first frequency band, and a second reference signal is transmitted in the second frequency band. Wherein, the transmission time of the first reference signal is different from that of the second reference signal, and the center frequency of the first frequency band is different from that of the second frequency band; wherein, the first reference signal and the second reference signal are substantially synchronized in phase, the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal, and the third reference signal obtained by superimposing the first reference signal and the second reference signal in the time domain is used to estimate the arrival time of the reference signal.

2. The wireless communication device as claimed in claim 1, characterized in that, It also includes a first phase-locked loop and a second phase-locked loop; The first phase-locked loop is used to generate a first local oscillator signal, the center frequency of which is the same as the center frequency of the first reference signal; The second phase-locked loop is used to generate a second local oscillator signal, the center frequency of which is the same as the center frequency of the second reference signal.

3. The wireless communication device as described in claim 2, characterized in that, The first phase-locked loop and the second phase-locked loop use the same reference clock signal.

4. The wireless communication device as described in claim 2 or 3, characterized in that, The processing circuit is also used to output a first synchronization signal to the first phase-locked loop and the second phase-locked loop respectively through the interface circuit; The first phase-locked loop is further configured to: adjust the phase difference between the first local oscillator signal and the reference clock signal according to the first synchronization signal; The second phase-locked loop is further configured to: adjust the phase difference between the second local oscillator signal and the reference clock signal according to the first synchronization signal.

5. The wireless communication device as described in claim 4, characterized in that, The first phase-locked loop is specifically used for: Based on the first synchronization signal, the first effective edge of the reference clock signal is determined, and the phase difference between the first local oscillator signal and the reference clock signal is adjusted with the first effective edge as a reference. The second phase-locked loop is specifically used for: Based on the first synchronization signal, the first effective edge is determined, and the phase difference between the second local oscillator signal and the reference clock signal is adjusted with the first effective edge as a reference.

6. The wireless communication device as claimed in claim 5, characterized in that, The first phase-locked loop is specifically used for: Based on the first synchronization signal, the first effective edge of the reference clock signal is determined, and based on the first effective edge, the phase difference between the first local oscillator signal and the reference clock signal is adjusted according to the signal after the first local oscillator signal output by the first frequency divider of the first phase-locked loop is divided according to the first feedback frequency divider of the first phase-locked loop. The second phase-locked loop is specifically used for: Based on the first synchronization signal, the first effective edge is determined, and based on the first effective edge, the phase difference between the second local oscillator signal and the reference clock signal is adjusted according to the signal after the second local oscillator signal output by the second frequency divider of the second phase-locked loop is divided according to the second feedback frequency divider of the second phase-locked loop.

7. The wireless communication device as described in claim 2 or 3, characterized in that, The phase difference between the first local oscillator signal and the reference clock signal is equal to the phase difference between the second local oscillator signal and the reference clock signal.

8. The wireless communication device as described in claim 2 or 3, characterized in that, The first phase-locked loop includes a first frequency divider and a first feedback frequency divider; the input terminal of the first feedback frequency divider is connected to the output terminal of the first frequency divider. The second phase-locked loop includes a second frequency divider and a second feedback frequency divider; the input of the second feedback frequency divider is connected to the output of the second frequency divider.

9. The wireless communication device as described in claim 2 or 3, characterized in that, The processing circuit is also used to send a second synchronization signal to the first phase-locked loop and the second phase-locked loop respectively through the interface circuit; The first phase-locked loop is also used to perform frequency division processing on the signal based on the second synchronization signal; The second phase-locked loop is also used to perform frequency division processing of the signal based on the second synchronization signal.

10. The wireless communication device as claimed in claim 1, characterized in that, It also includes a third phase-locked loop; The processing circuit is also used to output a third synchronization signal to the third phase-locked loop through the interface circuit; The third phase-locked loop is used for: A third local oscillator signal is generated, and the phase difference between the third local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the third local oscillator signal is the same as the center frequency of the first reference signal. A fourth local oscillator signal is generated, and the phase difference between the fourth local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the fourth local oscillator signal is the same as the center frequency of the second reference signal. The frequency of the third synchronization signal is the common divisor of the center frequency of the third local oscillator signal and the center frequency of the fourth local oscillator signal.

11. The wireless communication device according to any one of claims 1-3, characterized in that, The processing circuit is specifically used through the interface circuit: Fall asleep; Wake up when the wake-up time arrives; A first reference signal is transmitted in the first frequency band, and a second reference signal is transmitted in the second frequency band. I fell asleep again.

12. A wireless communication device, characterized in that, Includes processing circuitry and an interface circuit coupled to the processing circuitry, wherein the processing circuitry is configured to communicate via the interface circuitry: Receive a first reference signal, wherein the first reference signal is a signal of a first frequency band; Receive a second reference signal; the second reference signal is a signal of a second frequency band; wherein the transmission time of the first reference signal is different from the transmission time of the second reference signal, and the center frequency of the first frequency band is different from the center frequency of the second frequency band; wherein the first reference signal and the second reference signal are substantially synchronized in phase; The arrival time of the reference signal is estimated by jointly using the first reference signal and the second reference signal; Specifically, the processing circuit is used for: The first reference signal and the second reference signal are superimposed in the time domain to obtain the third reference signal; The arrival time of the reference signal is estimated based on the third reference signal.

13. A method for estimating the arrival time of a reference signal, characterized in that, include: A first reference signal is transmitted in the first frequency band, and a second reference signal is transmitted in the second frequency band. Wherein, the transmission time of the first reference signal is different from that of the second reference signal, and the center frequency of the first frequency band is different from that of the second frequency band; wherein, the first reference signal and the second reference signal are substantially synchronized in phase, the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal, and the third reference signal obtained by superimposing the first reference signal and the second reference signal in the time domain is used to estimate the arrival time of the reference signal.

14. The method as described in claim 13, characterized in that, The method further includes: A first local oscillator signal is generated by a first phase-locked loop, and the center frequency of the first local oscillator signal is the same as the center frequency of the first reference signal. A second local oscillator signal is generated by a second phase-locked loop, and the center frequency of the second local oscillator signal is the same as the center frequency of the second reference signal.

15. The method as described in claim 14, characterized in that, The first phase-locked loop and the second phase-locked loop use the same reference clock signal.

16. The method as described in claim 14 or 15, characterized in that, The method further includes: The first synchronization signal is output to the first phase-locked loop and the second phase-locked loop respectively; The phase difference between the first local oscillator signal and the reference clock signal output by the first phase-locked loop is adjusted according to the first synchronization signal; The phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal is adjusted according to the first synchronization signal.

17. The method as described in claim 16, characterized in that, The step of adjusting the phase difference between the first local oscillator signal and the reference clock signal output by the first phase-locked loop according to the first synchronization signal includes: Based on the first synchronization signal, the first effective edge of the reference clock signal is determined, and the phase difference between the first local oscillator signal and the reference clock signal is adjusted with the first effective edge as a reference. The step of adjusting the phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal according to the first synchronization signal includes: Based on the first synchronization signal, the first effective edge is determined, and the phase difference between the second local oscillator signal and the reference clock signal is adjusted with the first effective edge as a reference.

18. The method as described in claim 17, characterized in that, The step of adjusting the phase difference between the first local oscillator signal and the reference clock signal output by the first phase-locked loop according to the first synchronization signal includes: Based on the first synchronization signal, the first effective edge of the reference clock signal is determined, and based on the first effective edge, the phase difference between the first local oscillator signal and the reference clock signal is adjusted according to the signal after the first local oscillator signal output by the first frequency divider of the first phase-locked loop is divided according to the first feedback frequency divider of the first phase-locked loop. The step of adjusting the phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal according to the first synchronization signal includes: Based on the first synchronization signal, the first effective edge is determined, and based on the first effective edge, the phase difference between the second local oscillator signal and the reference clock signal is adjusted according to the signal after the second local oscillator signal output by the second frequency divider of the second phase-locked loop is divided according to the second feedback frequency divider of the second phase-locked loop.

19. The method according to any one of claims 14-15, characterized in that, The phase difference between the first local oscillator signal and the reference clock signal is equal to the phase difference between the second local oscillator signal and the reference clock signal.

20. The method according to any one of claims 14-15, characterized in that, The method further includes: Send a second synchronization signal to the first phase-locked loop and the second phase-locked loop respectively; The signal input to the first frequency divider of the first phase-locked loop is divided according to the second synchronization signal; The signal input to the second frequency divider of the second phase-locked loop is divided according to the second synchronization signal.

21. The method as described in claim 13, characterized in that, The method further includes: Output the third synchronization signal to the third phase-locked loop; A third local oscillator signal is generated, and the phase difference between the third local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the third local oscillator signal is the same as the center frequency of the first reference signal. A fourth local oscillator signal is generated, and the phase difference between the fourth local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the fourth local oscillator signal is the same as the center frequency of the second reference signal. The frequency of the third synchronization signal is the common divisor of the center frequency of the third local oscillator signal and the center frequency of the fourth local oscillator signal.

22. The method according to any one of claims 13-15, characterized in that, Before transmitting the first reference signal in the first frequency band and the second reference signal in the second frequency band, the method further includes: Fall asleep; Wake up when the wake-up time arrives; After transmitting the first reference signal in the first frequency band and the second reference signal in the second frequency band, the method further includes: I fell asleep again.

23. A method for estimating the arrival time of a reference signal, characterized in that, include: Receive a first reference signal, wherein the first reference signal is a signal of a first frequency band; Receive the second reference signal; The second reference signal is a signal in the second frequency band; wherein the transmission time of the first reference signal is different from that of the second reference signal, and the center frequency of the first frequency band is different from that of the second frequency band; wherein the first reference signal and the second reference signal are substantially synchronized in phase; The first reference signal and the second reference signal are superimposed in the time domain to obtain the third reference signal; The arrival time of the reference signal is estimated based on the third reference signal.

24. A communication device, characterized in that, The device includes a processor and a memory. The memory is used to store executable programs; The processor is configured to execute a computer-executable program in memory, such that the method of any one of claims 13-23 is performed.

25. A communication device, characterized in that, The device includes a processor and a communication interface. The communication interface is used for inputting and / or outputting information; The processor is configured to execute a computer-executable program such that the method of any one of claims 13-23 is performed.

26. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer-executable program, which, when invoked by a computer, causes the computer to perform the method as described in any one of claims 13-23.

27. A chip system, characterized in that, include: A communication interface used for inputting and / or outputting information; A processor for executing a computer-executable program, causing a device having the chip system mounted to perform the method as described in any one of claims 13-23.

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