An electronic paper display panel and display device

Abstract

This invention discloses an electronic paper display panel and a display device. The display panel includes: multiple data lines and multiple scan lines; and sub-pixels enclosed by the multiple data lines. The data lines are serpentine, with two data lines between adjacent columns of sub-pixels. Each pair of adjacent rows of sub-pixels is connected to a scan line, and within the same column, each pair of sub-pixels is not completely enclosed by two data lines. The two rows of sub-pixels are respectively connected to left and right data lines. The display panel provided by this invention, by setting the data lines in a serpentine pattern, with at least a portion of adjacent columns of sub-pixels having two data lines between them; each pair of adjacent rows of sub-pixels is connected to a scan line, and within the same column, each pair of sub-pixels is not completely enclosed by two data lines. The two rows of sub-pixels are respectively connected to left and right data lines. This reduces the intersection of signal lines on the bottom bezel of the electronic paper display panel, saves costs, facilitates the realization of a narrow bezel in the electronic paper display panel, and improves the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an electronic paper display panel and display device. Background Technology

[0002] An electronic paper display panel is a type of display panel that controls the brightness of light-emitting elements in subpixels to display images. When the element characteristics of the subpixels in an electronic paper display panel are not uniform, image retention can easily occur, thus affecting the quality of the displayed image.

[0003] The electronic paper display panel includes sub-pixels arranged in an array. The sub-pixels are connected to scan lines and data lines. The connection traces between the scan lines and data lines are located in the driver chip on the lower bezel of the display panel.

[0004] Existing electronic paper display panels have the problem of too many signal lines on the bottom bezel. The intersection of different signal lines causes mutual interference between signals on different lines, and also increases costs. Summary of the Invention

[0005] This invention provides an electronic paper display panel and a display device, which can reduce the intersection of signal lines on the bottom bezel of the electronic paper display panel, save costs, facilitate the realization of narrow bezels in the electronic paper display panel, and improve the display effect.

[0006] In a first aspect, embodiments of the present invention provide an electronic paper display panel, comprising: multiple data lines and multiple scan lines; and sub-pixels enclosed by the multiple data lines; wherein the data lines are serpentine, and two data lines are disposed between two adjacent columns of sub-pixels; each two adjacent rows of sub-pixels are connected by a scan line, and in the same column, each two rows of sub-pixels are non-closed by two data lines, and the two rows of sub-pixels are respectively connected to the left and right data lines.

[0007] Optionally, the data line includes a first trace segment and a second trace segment, which are spaced apart and connected sequentially; the first trace segment extends along a first direction, and the second trace segment extends along a second direction; the scan line extends along the second direction, and the first direction and the second direction intersect, wherein the first direction is the column direction and the second direction is the row direction; the first trace segment is located between two adjacent column sub-pixels, and the second trace segment is located between two adjacent row sub-pixels.

[0008] Optionally, in the same column, each pair of adjacent rows of subpixels is non-closed by the first trace segment of a data line, two second trace segments, and the first trace segment of another data line.

[0009] Optionally, the sub-pixel located in row 4k+1 and column 4j+1 is connected to the data line in column j+2; the sub-pixel located in row 4k+2 and column 4j+1 is connected to the data line in column j+3; the sub-pixel located in row 4k+3 and column 4j+2 is connected to the data line in column j+2; and the sub-pixel located in row 4k+4 and column 4j+2 is connected to the data line in column j+3, where k and j are both integers greater than or equal to zero.

[0010] Optionally, the subpixels in rows 2k+1 and 2k+2 are connected to the (k+1)th scan line.

[0011] Optionally, the data signals on the data lines connecting the subpixels in rows 2k+1 and 2k+2 can be turned off and on simultaneously.

[0012] Optionally, a sub-pixel includes a first transistor and a pixel electrode; the first and second electrodes of the first transistor are respectively connected to the corresponding data line and the pixel electrode, and the gate of the first transistor is connected to the corresponding scan line.

[0013] Optionally, a sub-pixel includes a second transistor, a third transistor, and a pixel electrode. The first electrode of the second transistor is connected to the corresponding data line, the second electrode of the second transistor is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the pixel electrode, and the gates of the second transistor and the third transistor are connected to the corresponding scan line.

[0014] Optionally, for two sub-pixels connected to the same scan line in the same column, the second electrode of the second transistor of the preceding sub-pixel is connected to the pixel electrode of the following sub-pixel.

[0015] Secondly, embodiments of the present invention also provide a display device, the display device including the display panel provided in the first aspect.

[0016] The display panel provided in this embodiment of the invention sets the data lines to a serpentine pattern, with two data lines between adjacent columns of sub-pixels; each pair of adjacent rows of sub-pixels is connected by a scan line, and in the same column, each pair of rows of sub-pixels is not enclosed by two data lines. The two rows of sub-pixels are respectively connected to the left and right data lines. This can reduce the crossing of signal lines on the bottom bezel of the electronic paper display panel, save costs, facilitate the realization of a narrow bezel in the electronic paper display panel, extend the charging time of sub-pixels, and improve the display effect of the display panel.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an electronic paper display panel in the prior art;

[0020] Figure 2 This is a schematic diagram of the structure of a sub-pixel of an electronic paper display panel provided by existing technology;

[0021] Figure 3 This is a schematic diagram of the sub-pixel structure of another type of electronic paper display panel provided by existing technology;

[0022] Figure 4 This is a schematic diagram of the structure of an electronic paper display panel provided in an embodiment of the present invention;

[0023] Figure 5 This is a partial structural schematic diagram of an electronic paper display panel provided in an embodiment of the present invention;

[0024] Figure 6 This is a partial structural schematic diagram of another electronic paper display panel provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the working timing of an electronic paper display panel provided in an embodiment of the present invention;

[0026] Figure 8 This is a charging simulation diagram of an electronic paper display panel provided in an embodiment of the present invention;

[0027] Figure 9 This is a partial structural schematic diagram of another electronic paper display panel provided in an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] As described in the background section, in existing technologies, electronic paper display panels typically include sub-pixels. The data signals and scan signals of the sub-pixels are usually provided by a driver chip located on the bottom bezel of the display panel. The sub-pixels are connected to the driver chip via connection traces for scan lines and data lines. The gold fingers of the driver chip are soldered onto a flexible printed circuit board (FPC). This results in an excessive number of signal lines on the bottom bezel, with different signal lines intersecting and causing mutual interference, as well as increased costs. The inventors have discovered that the reason for these problems is that currently, in electronic paper display panels, one row of sub-pixels connects to one scan line. This causes the connection traces for scan lines to intersect with the data lines during the bottom bezel design. When the bottom bezel clearance is insufficient, multiple metal layers are needed to bridge and transfer different signals, increasing manufacturing costs and hindering the achievement of narrow bezels in electronic paper display panels. Figure 1 This is a schematic diagram of the structure of an electronic paper display panel in the prior art, in which... Figure 1 The image only schematically illustrates a portion of the structure of the electronic paper display panel; see reference. Figure 1 Electronic paper display panels include multiple data lines (Data) and multiple scan lines (Scan). Data lines extend along the row direction (X), and scan lines extend along the column direction (Y). Each row of data lines (Data) connects to a row of sub-pixels. This causes the connection traces (Cline) between the data lines (Data) and scan lines (Scan) at the bottom bezel to intersect. When the distance at the bottom bezel is insufficient, multiple metal layers need to be added to bridge and transfer different signals, increasing costs. Furthermore, the intersection of different signal lines causes the signals on different signal lines to interfere with each other, affecting the accuracy of signal transmission and thus impacting the display effect.

[0031] Figure 2 This is a schematic diagram of the sub-pixel structure of an electronic paper display panel provided by existing technology, for reference. Figure 2One scan line (Scan) controls one row of sub-pixels, and one data line (Data) controls one column of sub-pixels. One row of sub-pixels includes a first thin-film transistor (MP1), a storage capacitor (Cst), and an electronic paper ink layer capacitor (Cfpl). The first terminal of the first thin-film transistor (MP1) is connected to the corresponding data line (Data), and the second terminal of the first thin-film transistor (MP1) is connected to one end of the storage capacitor (Cst) and one end of the electronic paper ink layer capacitor (Cfpl). The other ends of the storage capacitor (Cst) and the electronic paper ink layer capacitor (Cfpl) are connected to a common voltage. The gate of the first thin-film transistor (MP1) is connected to the scan line (Scan).

[0032] Figure 3 This is a schematic diagram of the sub-pixel structure of another electronic paper display panel provided by existing technology, for reference. Figure 3 Each row of subpixels is driven by two scan lines (Scan) and one data line (Data) controls two columns of subpixels. Each row of subpixels includes a second thin-film transistor (TFT) MP2, a third TFT MP3, a storage capacitor (Cst), and an electronic paper ink layer capacitor (Cfpl). The first terminal of the second TFT MP2 is connected to the corresponding data line (Data), and the second terminal of the second TFT MP2 is connected to one end of the storage capacitor (Cst) and one end of the electronic paper ink layer capacitor (Cfpl). The other ends of the storage capacitor (Cst) and the electronic paper ink layer capacitor (Cfpl) are connected to a common voltage. The gate of the second TFT MP2 is connected to the first scan line (Scan1). Similarly, the first terminal of the third TFT MP3 is connected to the corresponding data line (Data), and the second terminal of the third TFT MP3 is connected to one end of the storage capacitor (Cst) and one end of the electronic paper ink layer capacitor (Cfpl). The other ends of the storage capacitor (Cst) and the electronic paper ink layer capacitor (Cfpl) are connected to a common voltage. The gate of the third TFT MP3 is connected to the second scan line (Scan2).

[0033] To address the aforementioned issues, embodiments of the present invention provide a structure for an electronic paper display panel. Figure 4 This is a schematic diagram of the structure of an electronic paper display panel provided in an embodiment of the present invention. This embodiment is applicable to electronic paper displays.

[0034] like Figure 4 As shown, the electronic paper display panel includes multiple data lines 100 and multiple scan lines 200. The data lines 100 extend along the column direction Y, and the scan lines 200 extend along the row direction X. The data signals and scan signals of the sub-pixels are provided by a driver chip located on the lower bezel of the electronic paper display panel. The sub-pixels are connected to the driver chip through the connection traces of the scan lines and the connection traces of the data lines. The gold fingers of the driver chip are soldered onto a flexible circuit board (FPC). The ports connecting to the scan lines 200 are located on the left and right sides of the driver chip, and the ports connecting to the data lines 100 are located in the middle of the driver chip.

[0035] Figure 5 This is a partial structural schematic diagram of an electronic paper display panel provided in an embodiment of the present invention.

[0036] like Figure 4 and Figure 5 As shown, the electronic paper display panel 10 provided in this embodiment of the invention includes: multiple data lines 100 and multiple scan lines 200; and sub-pixels 300 enclosed by the multiple data lines 100; wherein, the data lines 100 are serpentine, and two data lines 100 are arranged between two adjacent columns of sub-pixels 300; each two adjacent rows of sub-pixels are connected by a scan line 200, and in the same column, each two rows of sub-pixels 300 are not enclosed by two data lines 100, and the two rows of sub-pixels 300 are respectively connected to the left and right data lines 100.

[0037] Data line 100 transmits data signals to sub-pixel 300, and scan line 200 transmits scan signals to sub-pixel 300. Sub-pixel 300 drives the light-emitting element to emit light according to the data signal and scan signal, thereby realizing image display. The electronic paper display panel 10 includes m rows and n columns of sub-pixels, where m is an even number.

[0038] In this embodiment of the invention, by setting the data lines in a serpentine pattern, two data lines 100 are set between two adjacent columns of sub-pixels; and within the same column, every two rows of sub-pixels 300 are not enclosed by the two data lines 100, and the two rows of sub-pixels 300 are respectively connected to the left and right data lines 100. The cooperative arrangement of the data lines 100 and the sub-pixels 300 allows the two rows of sub-pixels 300 to be driven by a single scan line 100, that is, the two rows of sub-pixels 300 are connected to the same scan line 200. In a specific example, Figure 5A partial schematic diagram of an electronic paper display panel is shown, using a 4x4 sub-pixel array on the electronic paper display panel 10 as an example. This 4x4 sub-pixel array is driven by 2 scan lines and 8 data lines, meaning one scan line controls two rows of sub-pixels 300. The first scan line, gate1, connects the first and second rows of sub-pixels 300, and the second scan line, gate2, connects the third and fourth rows of sub-pixels 300. The scan signal provided by the first scan line, gate1, controls the display of the first and second rows of sub-pixels 300, while the scan signal provided by the second scan line, gate2, controls the display of the third and fourth rows of sub-pixels 300. Therefore, the actual number of scan lines is half of the original. Taking an 800(G)*480(S) resolution display as an example, only 400 scan lines are needed in the design. The display of one column of sub-pixels 300 requires four data lines to drive it. Taking the display process of the second column of sub-pixels 300 as an example: the data voltage is input to the first row, second column of sub-pixels 300 through the fourth data line data4, the data voltage is input to the second row, second column of sub-pixels 300 through the fifth data line data5, the data voltage is input to the third row, second column of sub-pixels 300 through the second data line data2, and the data voltage is input to the fourth row, second column of sub-pixels 300 through the third data line data3.

[0039] When the refresh rate of the electronic paper display panel is 60Hz, the effective time of each frame is 1 / 60 = 16.7ms. In the prior art, one scan line corresponds to one row of sub-pixels 300, so the effective time of each row of sub-pixels 300 is (16.7 / m)ms. In contrast, the present invention uses one scan line to control two rows of sub-pixels 300, so the effective time of each row of sub-pixels 300 is ((16.7*2) / m)ms, which is twice as long as the prior art.

[0040] As can be seen, under the same scanning frequency, compared with the existing electronic paper display panel design, this embodiment realizes that one scan line controls two rows of sub-pixels 300 to perform dual-line driving scanning, so that there are always two rows of sub-pixels 300 in the charging state at any time. The charging time of each sub-pixel 300 is doubled, ensuring that the sub-pixels 300 have a sufficiently long charging time. This solution is particularly suitable for manufacturing large-size, high-resolution display devices.

[0041] refer to Figure 5In this embodiment of the invention, since a single scan line is used to drive two rows of sub-pixels on the same side for display, and the upper and lower rows of sub-pixels are charged simultaneously through corresponding data lines, the number of scan lines can be reduced by half compared to the prior art. For electronic paper display panels, the connection traces between the scan lines and the driver chip are routed through the left and right borders, which can better match the driver chip. Moreover, since the number of scan lines is reduced by half, the connection traces on the left and right borders are also reduced by half, which is beneficial for wiring and narrow bezel design.

[0042] Additionally, the bottom border design avoids crossovers between scan line connections and data lines, reducing layer transition issues between different signal layers, minimizing mask design costs, and lowering overall costs. (Reference) Figure 4 In the lower border area, there is no issue of crossover between the scan line connection trace (Cline) and the data line connection trace.

[0043] The electronic paper display panel provided in this embodiment of the invention sets the data lines in a serpentine pattern, with two data lines between adjacent columns of sub-pixels; each pair of adjacent rows of sub-pixels is connected by a scan line, and in the same column, each pair of rows of sub-pixels is not enclosed by two data lines. The two rows of sub-pixels are respectively connected to the left and right data lines. This can reduce the crossing of signal lines on the bottom bezel of the electronic paper display panel, save costs, facilitate the realization of a narrow bezel in the electronic paper display panel, improve the display effect, extend the charging time of sub-pixels, and improve the display effect of the display panel.

[0044] Figure 6 This is a partial structural schematic diagram of another electronic paper display panel provided in an embodiment of the present invention, as shown below. Figure 6 As shown, optionally, the data line 100 includes a first trace segment 101 and a second trace segment 102, the first trace segment 101 and the second trace segment 102 are spaced apart and connected sequentially; the first trace segment 101 extends along a first direction, and the second trace segment 102 extends along a second direction; the scan line 200 extends along the second direction, and the first direction and the second direction intersect, wherein the first direction is the column direction and the second direction is the row direction;

[0045] The first trace segment 101 is positioned between two adjacent columns of sub-pixels 300, and the second trace segment 102 is positioned between two adjacent rows of sub-pixels 300. In other words, every two sub-pixels 300 in the same column are enclosed by three trace segments of the data line 100. The data line 100 is arranged in a serpentine pattern, allowing it to drive multiple columns of sub-pixels 300 and charge two rows of simultaneously active sub-pixels 300. Charging refers to transmitting data voltage to the data line 100. After a sub-pixel 300 is activated (after the transistor connected to the corresponding data line 100 in the sub-pixel 300 is activated), the data voltage on the data line 100 is transmitted to the sub-pixel 300 and stored.

[0046] In the same column, each pair of adjacent sub-pixels 300 is non-closed by the first trace segment 101 of a data line 100, two second trace segments 102, and the first trace segment 101 of another data line 100.

[0047] Sub-pixel 300, located in row 4k+1 and column 4j+1, is connected to data line 100 in column j+2.

[0048] Sub-pixel 300, located in row 4k+2 and column 4j+1, is connected to data line 100 in column j+3;

[0049] Subpixel 300, located in row 4k+3 and column 4j+2, is connected to data line 100 in column j+2.

[0050] The sub-pixel 300 located in row 4k+4 and column 4j+2 is connected to the data line 100 in column j+3, where k and j are both integers greater than or equal to zero.

[0051] Subpixel 300, located in row 4k+1 and column 4j+3, is connected to data line 100 in column j+6;

[0052] Subpixel 300, located in row 4k+1 and column 4j+4, is connected to data line 100 in column j+8;

[0053] Subpixel 300, located in row 4k+2 and column 4j+3, is connected to data line 100 in column j+7;

[0054] Subpixel 300, located in row 4k+2 and column 4j+4, is connected to data line 100 in column j+9;

[0055] Sub-pixel 300, located in row 4k+3 and column 4j+3, is connected to data line 100 in column j+4;

[0056] Subpixel 300, located in row 4k+4 and column 4j+4, is connected to data line 100 in column j+5.

[0057] For example, when k=0 and j=0, the sub-pixel 300 located in the 1st row and 1st column is connected to the 2nd column data line, the sub-pixel 300 located in the 2nd row and 1st column is connected to the 3rd column data line, the sub-pixel 300 located in the 3rd row and 2nd column is connected to the 2nd column data line 100, the sub-pixel 300 located in the 4th row and 2nd column is connected to the 3rd column data line 100, the sub-pixel 300 located in the 1st row and 3rd column is connected to the 6th column data line, the sub-pixel 300 located in the 1st row and 4th column is connected to the 8th column data line, the sub-pixel 300 located in the 2nd row and 3rd column is connected to the 7th column data line, the sub-pixel 300 located in the 2nd row and 4th column is connected to the 9th column data line 100, the sub-pixel 300 located in the 3rd row and 3rd column is connected to the 4th column data line 100, and the sub-pixel 300 located in the 4th row and 4th column is decomposed into the 5th column data line 100.

[0058] Subpixels 300 in rows 2k+1 and 2k+2 are connected to scan line 200 (k+1). The data signals on data lines 100 connected to subpixels 300 in rows 2k+1 and 2k+2 are simultaneously turned off and on.

[0059] Sub-pixel 300 includes a first transistor TFT1 and a pixel electrode; the first and second electrodes of the first transistor TFT1 are respectively connected to the corresponding data line 100 and the pixel electrode, and the gate of the first transistor TFT2 is connected to the corresponding scan line. Specifically, the first electrode of the first transistor TFT1 is connected to the corresponding data line 100, the second electrode of the first transistor TFT1 is connected to the pixel electrode, and the gate of the first transistor TFT1 is connected to the corresponding scan line 200. The display panel 10 also includes a common electrode, and a storage capacitor and a parasitic capacitor are formed between the pixel electrode and the common electrode.

[0060] It should be noted that the transistor described above can be an N-type transistor or a P-type transistor; the first terminal of the transistor can be the source and the second terminal can be the drain, or the first terminal of the transistor can be the drain and the second terminal can be the source. This invention does not limit this.

[0061] Figure 7 This is a timing diagram illustrating the operation of an electronic paper display panel according to an embodiment of the present invention. This timing diagram is applicable to... Figure 6 The electronic paper display panel shown. Combined with... Figure 6 and Figure 7 The following explanation uses an example of an electronic paper display panel where the second column of sub-pixels displays an image and all transistors are N-type transistors. Exemplarily, the driving process of this electronic paper display panel includes multiple stages.

[0062] In the first stage (t01), the scan signal G1 on the first scan line (gate1) is high, and the scan signal G2 on the second scan line (gate2) is low. The first transistor TFT1 of the first and second row sub-pixels 300 is turned on, while the first transistor TFT1 of the third and fourth row sub-pixels 300 is turned off. The first and second row pixel electrodes begin charging, meaning the data voltage is written to the pixel electrodes. Since the data signal D4 on the fourth data line (data4) is low and the data signal D5 on the fifth data line (data5) is high, the sub-pixel in the first row, second column is displayed as white, and the sub-pixel in the second row, second column is displayed as black.

[0063] In the second stage t02, the scan signal G1 on the first scan line is low, and the scan signal G2 on the second scan line is high. The first transistor TFT1 of the first and second row sub-pixels 300 is turned off, while the first transistor TFT1 of the third and fourth row sub-pixels 300 is turned on. The third and fourth row pixel electrodes begin charging, i.e., the data voltage is written to the pixel electrodes. Since the data signal D2 on the second data line data2 is low and the data signal D3 on the third data line data3 is high, the sub-pixel 300 in the first row, second column is displayed as white, and the sub-pixel 300 in the fourth row, second column is displayed as black.

[0064] This invention enables a single scan line to control two rows of sub-pixels 300 for dual-line driving scanning. The data signals of the upper and lower rows of sub-pixels need to be turned off and on simultaneously. While the lower row of sub-pixels is charging, the upper row of sub-pixels can continue to charge, ensuring that there are always two rows of sub-pixels 300 in a charging state at any given time. The charging time of each sub-pixel 300 is doubled compared to the prior art, ensuring that the sub-pixels 300 have a sufficiently long charging time. This solution is particularly suitable for manufacturing large-size, high-resolution display devices.

[0065] Figure 8 This is a charging simulation diagram of an electronic paper display panel provided in an embodiment of the present invention. (Reference) Figure 8 The charging rate of the third frame of the electronic paper display panel in this embodiment of the invention can reach over 99%; the simulation diagram of the electronic paper display panel confirms that there is no difference in the charging rate of two rows of sub-pixels controlled by one scan line.

[0066] As one possible implementation method, Figure 9 This is a partial structural schematic diagram of another electronic paper display panel provided in an embodiment of the present invention. (See attached diagram.) Figure 9As shown, sub-pixel 300 includes a second transistor TFT2, a third transistor TFT3, and a pixel electrode. The first electrode of the second transistor TFT2 is connected to the corresponding data line 100, the second electrode of the second transistor TFT2 is connected to the first electrode of the third transistor TFT3, and the second electrode of the third transistor TFT3 is connected to the pixel electrode. The gates of the second transistor TFT2 and the third transistor TFT3 are connected to the same scan line 200. For two sub-pixels connected to the same scan line 200 in the same column, the second electrode of the second transistor TFT2 of the preceding sub-pixel is connected to the pixel electrode of the following sub-pixel. The second transistor TFT2 and the third transistor TFT3 are used to turn on or off in response to the scan signal on the scan line 200. The second electrode of the third transistor TFT3 of the m-th row sub-pixel 300 is connected to the pixel electrode of the n-th row sub-pixel 300, where n = m + 1, and m and n are both positive integers.

[0067] Since the second stage of the second transistor TFT2 of the m-th row sub-pixel 300 is connected to the pixel electrode of the n-th row sub-pixel 300, when the second transistor TFT2 of the m-th row sub-pixel 300 is turned on, it transmits data voltage to the m-th row pixel electrode and simultaneously transmits data voltage to the pixel electrode of the n-th row sub-pixel 300, pre-charging the pixel electrode of the n-th row, i.e., pre-charging the storage capacitor of the n-th row, which helps stabilize the voltage of the n-th row pixel electrode. Furthermore, during the off-state of the second transistor TFT2 and the third transistor TFT3 of the m-th row sub-pixel, the leakage current of the m-th row pixel electrode is compensated by the charge of the n-th row pixel electrode to stabilize the pixel electrode voltage. Specifically, the m-th row sub-pixel 300 is charged first (i.e., the process of writing data voltage to the pixel electrode), and the n-th row sub-pixel 300 is charged later. The sub-pixel 300 containing the pixel electrode of the n-th row sub-pixel 300 and the sub-pixel 300 containing the connected second transistor TFT2 of the m-th row can be located in the same column or different columns; both can achieve the effects of this embodiment of the invention, and this embodiment of the invention is not limited thereto.

[0068] Because the pixel electrode in the m-th row is pre-charged when it is being charged, the leakage current of the pixel electrode in the n-th row replenishes the charge of the pixel electrode in the n-th row when the second transistor TFT2 and the third transistor TFT3 of the m-th row sub-pixel 300 are turned off. The pre-charging of the n-th row pixel electrode during the charging of the m-th row sub-pixel 300 stabilizes its voltage. The replenishment of charge during leakage current in the m-th row pixel electrode further stabilizes the voltage of each individual pixel. By connecting the first electrode of the second transistor TFT2 in the m-th row to the pixel electrode in the n-th row, the leakage current path is increased, effectively reducing leakage current and improving the voltage retention rate of the pixel electrode, thereby enhancing the display effect of the display panel. In other words, for adjacent rows, charging the pixel electrode in the previous row can charge the pixel electrode (i.e., the storage capacitor) in the next row. This improves the voltage retention rate of the pixel electrode while saving wiring length, reducing wiring difficulty and signal interference, further enhancing the display effect of the display panel.

[0069] Based on the same inventive concept, embodiments of the present invention also provide a display device. This display device includes any of the electronic paper display panels provided in the above embodiments. This display device also possesses the beneficial effects of the display panels described in the above embodiments; similarities can be understood by referring to the explanation of the display panels above, and will not be repeated below.

[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An electronic paper display panel, characterized in that, include: Multiple data lines and multiple scan lines; and sub-pixels enclosed by the multiple data lines described; The data lines are serpentine, with two data lines between two adjacent columns of sub-pixels; each row of sub-pixels is connected to a scan line, and in the same column, each row of sub-pixels is not enclosed by two data lines, and the two rows of sub-pixels are respectively connected to the left and right data lines. The data line includes a first trace segment and a second trace segment, which are spaced apart and connected sequentially; the first trace segment extends along a first direction, and the second trace segment extends along a second direction; the scan line extends along the second direction, and the first direction and the second direction intersect, wherein the first direction is a column direction and the second direction is a row direction; The first trace segment is located between two adjacent columns of the sub-pixels, and the second trace segment is located between two adjacent rows of the sub-pixels.

2. The electronic paper display panel according to claim 1, characterized in that, In the same column, each pair of adjacent rows of sub-pixels are non-closed by a first trace segment of one data line, two second trace segments, and a first trace segment of another data line.

3. The electronic paper display panel according to claim 1, characterized in that, The sub-pixel located in row 4k+1 and column 4j+1 is connected to the data line in column j+2; The sub-pixel located in row 4k+2 and column 4j+1 is connected to the data line in column j+3; The sub-pixel located in row 4k+3 and column 4j+2 is connected to the data line in column j+2; The sub-pixel located in row 4k+4 and column 4j+2 is connected to the data line in column j+3, where k and j are both integers greater than or equal to zero.

4. The electronic paper display panel according to claim 3, characterized in that, The sub-pixels in rows 2k+1 and 2k+2 are connected to the (k+1)th scan line.

5. The electronic paper display panel according to claim 4, characterized in that, The data signals on the data lines connecting the sub-pixels in rows 2k+1 and 2k+2 are simultaneously turned off and on.

6. The electronic paper display panel according to any one of claims 1-5, characterized in that, The sub-pixel includes a first transistor and a pixel electrode; the first electrode and the second electrode of the first transistor are respectively connected to the corresponding data line and the pixel electrode, and the gate of the first transistor is connected to the corresponding scan line.

7. The electronic paper display panel according to any one of claims 1-5, characterized in that, The sub-pixel includes a second transistor, a third transistor, and a pixel electrode. The first electrode of the second transistor is connected to the corresponding data line, the second electrode of the second transistor is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the pixel electrode, and the gates of the second transistor and the third transistor are connected to the same scan line.

8. The electronic paper display panel according to claim 7, characterized in that, In two sub-pixels connected to the same scan line in the same column, the second electrode of the second transistor of the preceding sub-pixel is connected to the pixel electrode of the following sub-pixel.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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