A DLDO circuit using logic control to eliminate LCO oscillation

Abstract

The present invention relates to the technical field of dust collecting circuits, and discloses a DLDO circuit that uses logic control to eliminate LCO oscillation, including a fine adjustment circuit, a coarse adjustment circuit, a window comparator, a dynamic single limit comparator and a load circuit. The input end of the window comparator is connected to the circuit output voltage V OUT The output end of the window comparator is connected to the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected to the circuit output voltage V OUT The output end of the single limit comparator is connected to the input end of the fine adjustment circuit, and the fine adjustment circuit includes a stable state detection, a bidirectional shift register group and a small size PMOS array. The DLDO circuit that uses logic control to eliminate LCO oscillation adopts dynamic comparator technology, effectively avoids the unexpected flip of the comparator output signal, and reduces the power consumption of the comparator. By using the technology of combining the coarse adjustment circuit with the fine adjustment circuit, the transient response speed is improved while the output voltage error is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a DLDO circuit which uses logic control to eliminate LCO oscillation. Background Art

[0002] DLDO is the abbreviation of Digital Low dropout regulator, which is a digital low voltage dropout linear regulator. A digital low voltage dropout linear regulator is a circuit that uses digital logic to achieve low voltage difference conversion between input and output. The voltage difference refers to the minimum difference between the input voltage and the output voltage required to maintain the output voltage within 100mV of its rated value. Digital LDO has smaller power transistors, fewer stability issues and better process scalability than analog LDO, so it is used in mobile power systems.

[0003] However, compared with analog LDO, traditional digital LDO has the disadvantages of continuous LCO oscillation, large oscillation error, large static power consumption and slow transient response. Therefore, it is necessary to invent a DLDO circuit that can stabilize the output voltage, eliminate LCO oscillation, reduce power consumption and reduce stability error while improving transient response speed to solve the above problems. Summary of the invention

[0004] The object of the present invention is to provide a DLDO circuit which adopts logic control to eliminate LCO oscillation, so as to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a DLDO circuit that uses logic control to eliminate LCO oscillation, comprising a fine adjustment circuit, a coarse adjustment circuit, a window comparator, a dynamic single limit comparator and a load circuit, wherein the input end of the window comparator is connected to the circuit output voltage V OUT The output end of the window comparator is connected to the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected to the circuit output voltage V OUT The output end of the single limit comparator is connected to the input end of the fine adjustment circuit.

[0006] The fine adjustment circuit includes a stable state detection, a bidirectional shift register group and a small-size PMOS array. The input ends of the stable state detection, the bidirectional shift register group and the small-size PMOS array are connected to the input ends of the window comparator and the single-limit comparator. The output end of the stable state detection is connected to the input end of the bidirectional shift register, and the output end of the bidirectional shift register is connected to the input end of the small-size PMOS array.

[0007] The coarse adjustment circuit includes a coarse adjustment logic and a large-size PMOS array. The output end of the coarse adjustment logic is connected to the input end of the large-size PMOS array. The output end of the large-size PMOS array is connected to the output end of the small-size PMOS array as the output voltage V of the circuit. OUT .

[0008] Preferably, the single limit comparator outputs the voltage V OUT With reference voltage V REF By comparison, the direction FD signal is obtained to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit. OUT >V REF , FD=0 is obtained, which is used to control the bidirectional shift register group and the coarse adjustment logic module in the fine adjustment logic to adjust the PMOS tube to turn off the output voltage V OUT Approaching the reference voltage V REF , conversely, ensures the correct adjustment direction of the output voltage.

[0009] Preferably, the window comparator outputs a voltage V OUT With the window upper and lower limit voltage V REFH and V REFL By comparison, the window signal EN is obtained to control whether the bidirectional shift register group and the coarse adjustment logic in the fine adjustment logic are enabled or not; when the output voltage V OUT When outside the window, the coarse adjustment logic is enabled and the bidirectional shift register in the fine adjustment logic is disabled; when the output voltage V OUT When within the window, the bidirectional shift register in the fine adjustment logic is enabled and the bidirectional coarse adjustment logic is disabled, ensuring that the circuit can adaptively select the appropriate adjustment logic according to the state of the output voltage. The coarse adjustment circuit is combined with the fine adjustment circuit to improve the transient response speed while reducing the output voltage error.

[0010] Preferably, the dynamic single-limit comparator uses dynamic technology to perform voltage comparison. When the clock signal CLK is at a high level, the input node of the SR trigger is charged, and the SR trigger stabilizes the comparator output; when the clock signal CLK is at a low level, the side with a high input voltage discharges the input node of the SR trigger, and the SR trigger locks the comparator output. The window comparator is constructed using a dynamic single-limit comparator, and the use of dynamic technology effectively avoids unexpected flipping of the comparator output signal, while reducing the power consumption of the comparator.

[0011] Preferably, the stable state detection module uses a D flip-flop, a D flip-flop with asynchronous setting and an XOR gate to detect the stable state. Within the window range, if the direction signal FD flips and does not exceed the window, it is determined to be a stable state of the output voltage, which is used to disable the bidirectional shift register group in the fine-tuning logic, thereby achieving effective detection of the stable state of the output voltage, effectively eliminating the LCO oscillation of the output voltage, and reducing static power consumption.

[0012] Preferably, the bidirectional shift register uses a TG transmission gate, a NOT gate and an NMOS tube to achieve bidirectional selective shifting of the register.

[0013] Preferably, the bidirectional shift register group realizes that when FD=1, the register group shifts 1 to the right, i.e., turns on the PMOS tube; when FD=0, the register group shifts 0 to the left, i.e., turns off the PMOS tube. The bidirectional shift register group is a limited bit register connected to a small-size PMOS array, thereby realizing precise control of the output voltage and reducing the output error.

[0014] Compared with the prior art, the present invention provides a DLDO circuit that uses logic control to eliminate LCO oscillation, which has the following beneficial effects:

[0015] 1. The DLDO circuit that uses logic control to eliminate LCO oscillation adopts dynamic comparator technology, which effectively avoids the unexpected flipping of the comparator output signal, while reducing the power consumption of the comparator. By using the technology of combining coarse adjustment circuit with fine adjustment circuit, the transient response speed is improved while reducing the output voltage error.

[0016] 2. The DLDO circuit that uses logic control to eliminate LCO oscillation uses stable state detection module technology to determine the stable state STD of the output voltage and disable the bidirectional shift register group in the fine adjustment logic in time. The LCO oscillation of the output voltage is eliminated, the static power consumption is reduced, and the limited-bit bidirectional shift register group technology is used to access the small-size PMOS array to achieve precise and accurate adjustment of the output voltage and reduce the output error. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor:

[0018] Figure 1 The overall structure diagram of the DLDO circuit of the present invention;

[0019] Figure 2The circuit diagram of the dynamic single limit comparator of the present invention;

[0020] Figure 3 It is the structural diagram of the window comparator of the present invention;

[0021] Figure 4 This is a structural diagram of a stable state detection module of the present invention;

[0022] Figure 5 The bidirectional shift register circuit diagram of the present invention;

[0023] Figure 6 This is a structural diagram of the bidirectional shift register group of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] See also Figure 1-6 The present invention provides a technical solution: a DLDO circuit that uses logic control to eliminate LCO oscillation, including a fine adjustment circuit, a coarse adjustment circuit, a window comparator, a dynamic single limit comparator and a load circuit, the input end of the window comparator is connected to the circuit output voltage V OUT The output of the window comparator is connected to the input of the fine-tuning circuit, and the input of the single-limit comparator is connected to the circuit output voltage V OUT The output end of the single limit comparator is connected to the input end of the fine adjustment circuit.

[0027] The fine-tuning circuit includes a stable state detection, a bidirectional shift register group and a small-size PMOS array. The input ends of the stable state detection, the bidirectional shift register group and the small-size PMOS array are connected to the input ends of the window comparator and the single-limit comparator. The output end of the stable state detection is connected to the input end of the bidirectional shift register, and the output end of the bidirectional shift register is connected to the input end of the small-size PMOS array.

[0028] The coarse adjustment circuit includes a coarse adjustment logic and a large-size PMOS array. The output end of the coarse adjustment logic is connected to the input end of the large-size PMOS array. The output end of the large-size PMOS array is connected to the output end of the small-size PMOS array as the output voltage V of the circuit. OUT .

[0029] Furthermore, the single limit comparator outputs the voltage V OUT With reference voltage V REF By comparison, the direction FD signal is obtained to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit. OUT >V REF , FD=0 is obtained, which is used to control the bidirectional shift register group and the coarse adjustment logic module in the fine adjustment logic to adjust the PMOS tube to turn off the output voltage V OUT Approaching the reference voltage V REF , conversely, ensures the correct adjustment direction of the output voltage.

[0030] Furthermore, the window comparator outputs a voltage V OUT With the window upper and lower limit voltage V REFH and V REFL By comparison, the window signal EN is obtained to control whether the bidirectional shift register group and the coarse adjustment logic in the fine adjustment logic are enabled or not; when the output voltage V OUT When outside the window, the coarse adjustment logic is enabled and the bidirectional shift register in the fine adjustment logic is disabled; when the output voltage V OUT When within the window, the bidirectional shift register in the fine adjustment logic is enabled and the bidirectional coarse adjustment logic is disabled, ensuring that the circuit can adaptively select the appropriate adjustment logic according to the state of the output voltage. The coarse adjustment circuit is combined with the fine adjustment circuit to improve the transient response speed while reducing the output voltage error.

[0031] Furthermore, the dynamic single-limit comparator uses dynamic technology to perform voltage comparison. When the clock signal CLK is at a high level, the input node of the SR trigger is charged, and the SR trigger stabilizes the comparator output; when the clock signal CLK is at a low level, the side with a high input voltage discharges the input node of the SR trigger, and the SR trigger locks the comparator output. The window comparator is constructed using a dynamic single-limit comparator. The use of dynamic technology effectively avoids unexpected flipping of the comparator output signal and reduces the power consumption of the comparator.

[0032] Furthermore, the stable state detection module adopts a D flip-flop, a D flip-flop with asynchronous setting and an XOR gate to detect the stable state. Within the window range, if the direction signal FD flips and does not exceed the window, it is determined to be a stable state of the output voltage, which is used to disable the bidirectional shift register group in the fine-tuning logic, thereby realizing effective detection of the stable state of the output voltage, effectively eliminating the LCO oscillation of the output voltage, and reducing static power consumption.

[0033] Furthermore, the bidirectional shift register adopts a TG transmission gate, a NOT gate and an NMOS tube to realize bidirectional selection shifting of the register.

[0034] Furthermore, the bidirectional shift register group realizes that when FD=1, the register group shifts 1 to the right, that is, turns on the PMOS tube; when FD=0, the register group shifts 0 to the left, that is, turns off the PMOS tube. The bidirectional shift register group is a limited bit register and is connected to a small-size PMOS array, which realizes precise control of the output voltage and reduces the output error.

[0035] In actual operation, when the device is used, the voltage signal output by the PMOS array is input to the dynamic single-limit comparator and the window comparator. The dynamic single-limit comparator detects and judges the signal to control the adjustment direction of the circuit; the window comparator detects and judges the signal to control the circuit to enable coarse adjustment or fine adjustment.

[0036] When the coarse adjustment mode is enabled, the coarse adjustment control word is calculated by the coarse adjustment logic. When the fine adjustment mode is enabled, the fine adjustment control word is initialized first, and then the shift direction of the bidirectional shift register group is controlled by the FD signal. When the stable state detection module detects the stable state STD, the bidirectional shift register group is enabled to keep the output voltage stable.

[0037] The control word is output to the PMOS array to control the on or off of the PMOS array to adapt to changes in load current, stabilize the output voltage, and achieve regulation.

[0038] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A DLDO circuit that uses logic control to eliminate LCO oscillation, including a fine adjustment circuit, a coarse adjustment circuit, a window comparator, a dynamic single limit comparator and a load circuit, characterized in that: The input end of the window comparator is connected to the circuit output voltage VOUT, the output end of the window comparator is connected to the input end of the fine adjustment circuit, the input end of the single limit comparator is connected to the circuit output voltage VOUT, and the output end of the single limit comparator is connected to the input end of the fine adjustment circuit; The fine adjustment circuit includes a stable state detection, a bidirectional shift register group and a small-size PMOS array, the input ends of the stable state detection, the bidirectional shift register group and the small-size PMOS array are connected to the input ends of the window comparator and the single-limit comparator, the output end of the stable state detection is connected to the input end of the bidirectional shift register, and the output end of the bidirectional shift register is connected to the input end of the small-size PMOS array; The coarse adjustment circuit includes a coarse adjustment logic and a large-size PMOS array, the output end of the coarse adjustment logic is connected to the input end of the large-size PMOS array, and the output end of the large-size PMOS array is connected to the output end of the small-size PMOS array as the output voltage VOUT of the circuit; The output end of the small-size PMOS array in the fine adjustment circuit is connected in parallel with the output end of the large-size PMOS array in the coarse adjustment circuit and then connected in series with the load circuit; The dynamic single-limit comparator uses dynamic technology to perform voltage comparison. When the clock signal CLK is at a high level, the input node of the SR trigger is charged, and the SR trigger stabilizes the comparator output; when the clock signal CLK is at a low level, the side with a high input voltage discharges the input node of the SR trigger, and the SR trigger locks the comparator output. The window comparator is constructed using a dynamic single-limit comparator.

2. A DLDO circuit for eliminating LCO oscillation by logic control according to claim 1, characterized in that: The single-limit comparator compares the output voltage VOUT with the reference voltage VREF to obtain a direction FD signal, which is used to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit. When VOUT>VREF, FD=0 is obtained, which is used to control the bidirectional shift register group and the coarse adjustment logic module in the fine adjustment logic to adjust in the direction of turning off the PMOS tube, so that the output voltage VOUT approaches the reference voltage VREF. Otherwise, the correct adjustment direction of the output voltage is ensured.

3. The DLDO circuit for eliminating LCO oscillation by logic control according to claim 1, characterized in that: The window comparator compares the output voltage VOUT with the upper and lower limit voltages VREFH and VREFL of the window to obtain a window signal EN, which is used to control whether the bidirectional shift register group and the coarse adjustment logic in the fine adjustment logic are enabled or not; when the output voltage VOUT is outside the window, the coarse adjustment logic is enabled and the bidirectional shift register in the fine adjustment logic is disabled; when the output voltage VOUT is within the window, the bidirectional shift register in the fine adjustment logic is enabled and the bidirectional coarse adjustment logic is disabled.

4. The DLDO circuit for eliminating LCO oscillation by logic control according to claim 1, characterized in that: The stable state detection uses a D flip-flop, a D flip-flop with asynchronous setting and an XOR gate to detect the stable state. Within the window range, if the direction signal FD flips and does not exceed the window, it is determined to be the stable state of the output voltage, which is used to disable the bidirectional shift register group in the fine-tuning logic.

5. The DLDO circuit for eliminating LCO oscillation by logic control according to claim 1, characterized in that: The bidirectional shift register adopts a TG transmission gate, a NOT gate and an NMOS tube to realize bidirectional selection shift of the register.

6. The DLDO circuit for eliminating LCO oscillation by logic control according to claim 5, characterized in that: The bidirectional shift register group realizes that when FD=1, the register group shifts 1 rightward, that is, turns on the PMOS tube; when FD=0, the register group shifts 0 leftward, that is, turns off the PMOS tube. The bidirectional shift register group is a limited bit register and is connected to a small-size PMOS array.

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