Pre-staged instruction register for variable-length instruction set machines

Abstract

Methods and systems related to an improved processing architecture with pre-staged instructions are disclosed herein. The disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers, and logic circuits, wherein the set of instruction registers is configured to load a set of pre-staged instructions from the instruction memory using the bus, and the logic circuit is configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Description

Technical Field

[0001] The present invention relates to the field of computer processing architecture and instruction set, and more particularly to a pre-staged instruction register for a variable length instruction set machine. Background Art

[0002] A processing architecture includes functional units that must be provided with instructions and data in order to perform their functions. Instructions identify the operation and the data on which the operation will be performed. Operations are identified by the operation code of the processing architecture. The operation code is a bit string that represents the specific operation to be performed (for example, the operation code "001" tells the functional processing unit to add, while "002" tells the functional unit to subtract). There are many trade-offs associated with selecting and designing the various operation codes for functional processing units or processing architecture units. It takes energy and time to transmit instructions through the system. In addition, larger instruction sizes require larger buses, registers, and logic circuits, which increases the cost of the architecture. In general, including more and more specialized instructions can bring significant benefits because each instruction can do more, assuming the correct specialized instructions are selected, and fewer instructions need to be transmitted through the system. However, more specialized instructions require the creation of larger instruction libraries, as well as more or more complex functional processing units to process the instructions, which increases the cost of the architecture. Summary of the invention

[0003] Methods and systems related to the field of computer processing architectures and instruction sets are disclosed. The methods and systems disclosed herein include a processing architecture that can dynamically create large compound instructions that can be executed using the amount of power required to move a single instruction. The methods and systems disclosed herein include a processing architecture that can implement the functions of a variable length instruction set machine with a minimum size instruction bus. In a specific embodiment, a processor is provided that includes a set of instruction registers that load a set of pre-staged instructions from an instruction memory and, in response to receiving another instruction passed from the instruction memory, subsequently provide the pre-staged instructions to at least one functional processing unit.

[0004] Specific embodiments of the present invention provide significant benefits. Processors according to specific embodiments of the present invention can create many different compound instructions that can be executed repeatedly while using only the power and bus size associated with moving a single smaller component instruction. Thus, the architecture maintains the configurability of executing a variety of compound instructions without causing the instruction size to become too large or requiring excessive instructions to be transmitted over relatively long distances through the system to the functional processing units.

[0005] In general, while the benefits described in the preceding paragraph represent improvements in processing architecture, there are some applications where they are particularly relevant. For example, in a processor designed to operate on large data sets, where a series of operations will be performed multiple times by the processor as the processor works through the data sets, the series of operations can be pre-staged in registers and then repeatedly applied to different portions of the data in response to a single instruction transmitted only from an instruction memory. As another example, when the processor intends to perform multiple operations in parallel, the parallel groups of operations can be pre-staged in registers and then applied to different portions of the data in response to a single instruction transmitted only from memory. In a further example involving a combination of large data and parallel computing, a sequence of large numbers of parallel instructions will need to be repeatedly applied to different portions of the data, and the same approach can be used to compound the number of instructions that need to be transmitted from the instruction memory through the system.

[0006] In a specific embodiment of the present invention, a processor is provided. The processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers and a logic circuit. The set of instruction registers is configured to load a set of pre-stored instructions from the instruction memory using the bus. The logic circuit is configured to provide the set of pre-stored instructions from the set of instruction registers to at least one functional processing unit in response to receiving an instruction from the instruction memory.

[0007] In a specific embodiment of the present invention, a method is provided, wherein each step is performed by a processor. The method includes: storing instructions in an instruction memory, loading a set of pre-staged instructions from the instruction memory to a set of instruction registers using a bus, receiving instructions at a logic circuit, and providing the pre-staged instructions from the set of instruction registers to at least one functional processing unit in response to the received instructions and using the logic circuit.

[0008] In a specific embodiment of the present invention, a processor is provided. The processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers and a logic circuit. The processor also includes a device for loading a set of pre-stored instructions from the instruction memory into the set of instruction registers using the bus. The processor also includes a device for providing the set of pre-stored instructions from the set of instruction registers to at least one functional processing unit in response to receiving an instruction from the instruction memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram of a processor according to a specific embodiment of the invention disclosed herein is shown.

[0010] Figure 2 A block diagram illustrating execution areas of a processor according to specific embodiments of the invention disclosed herein.

[0011] Figure 3 A flow chart of a set of methods according to specific embodiments of the invention disclosed herein is shown.

[0012] Figure 4 Block diagrams and flow charts are presented to illustrate the operation of a portion of the logic circuitry according to specific embodiments of the invention disclosed herein.

[0013] Figure 5 A partial block diagram of a logic circuit and at least two functional processing units according to a specific embodiment of the present invention disclosed herein is shown.

[0014] Figure 6 A block diagram of a portion of a logic circuit designed to operate with a load-triggered instruction is shown in accordance with a specific embodiment of the invention disclosed herein. DETAILED DESCRIPTION

[0015] Methods and systems related to the field of computer processor architecture according to the above-mentioned invention content are disclosed in detail herein. The methods and systems disclosed in this section are non-limiting embodiments of the present invention, are used for explanation purposes only, and should not be used to limit the full scope of the present invention. It should be understood that the disclosed embodiments may or may not overlap with each other. Therefore, a portion of an embodiment or a specific embodiment thereof may or may not fall within the scope of another embodiment or a specific embodiment thereof, and vice versa. Different embodiments from different aspects may be combined or implemented separately. Many different combinations and sub-combinations of representative embodiments shown within the large framework of the present invention may be obvious to those skilled in the art, and those not explicitly shown or described should not be interpreted as being excluded.

[0016] Processor architecture refers to the design of various hardware elements required by a processor to perform calculations. A processor may include at least one memory and at least one functional processing unit, the functional processing unit being used to perform processor calculations. Calculations may be performed by executing instructions by the functional processing unit. The memory may include a single hardware element or separate hardware elements. The memory may store both the data on which the calculations will be performed ("operand data") and the instructions themselves ("instruction data" or "instructions"). A processor may be defined at least in part by the processor's instruction set, as the processor's hardware elements are designed to operate with the instruction set. For example, the processor's instruction bus may be designed to accommodate data elements having the instruction size of the instruction set, and the processor's functional processing unit may be designed to take specific actions when a register is loaded with a given operation code from the instruction set.

[0017] The processor disclosed herein can take various forms. The processor can be a processing core in a multi-core processor or a stand-alone processor. The processor can be implemented as a single-chip system, including a wafer-level single-chip system, a multi-chip single-package system, or in a multi-chip multi-package system, where the chip is generally connected to a common substrate, such as a printed circuit board (PCB), a socket or a silicon mesh. The processor can be part of a processor network. The network can be a network on chip (NoC). The processor according to the present invention can also be part of a network that includes chips on multiple substrates that are connected together through an advanced common substrate, such as in the case of multiple PCBs, each PCB has a set of chips, and multiple PCBs are fixed to a common base plate. The processor according to the present invention can also be implemented in a chiplet-based system. For example, in a specific embodiment of the present invention, one or more processors can be packaged or implemented by one or more network chipsets, such as connected by a socket.

[0018] The processor disclosed herein may include various elements. The processor may include at least one functional processing unit, a memory, and at least one bus. The processor disclosed herein may also include additional or more functionally special elements, such as a network interface unit, a controller, a serializer / deserializer, and a non-volatile memory that can modify configuration information. The functional processing unit of the processor may be used to perform component calculations required for the computing network to perform composite calculations. The computing network may include a router and a bus system on each processor, the bus system either only connecting adjacent processors to facilitate multi-hop communication, or also connecting remote processors to facilitate single-hop communication between these remote processors.

[0019] The memory of a processor can take various forms. The memory can be a random access volatile memory, such as a static random access memory (SRAM). The memory can store both instructions executed by the processor (instruction data) and data that these instructions will use as operands (operand data). The memory can be a cache memory of the processor or a main memory of the processor. The processor can include multiple memories, such as a cache memory and a main memory. The processor can have an instruction buffer memory and a separate data buffer memory. In an embodiment where the memory stores compiled instruction data, it can be referred to as the instruction memory of the processor.

[0020] Functional processing units can take various forms and be arranged on the processor in various ways. Functional processing units can be implemented in an execution region on the processor. The execution region can be a substantially continuous region on the processor substrate (e.g., a silicon substrate). In a specific embodiment of the present invention, the execution region is small enough that the time required to move data between any parts of the execution region is negligible relative to the clock cycle of the processor. In an alternative embodiment, the execution region may require several clock cycles to traverse (e.g., 3 clock cycles). However, specific embodiments of the present invention will obtain significant benefits, which are proportional to the cost associated with fetching instructions from memory and transferring them to the execution region. In these embodiments, the benefits of repeatedly executing pre-stored instructions will repeatedly save time and energy associated with fetching instructions from memory, regardless of the size of the execution region. The bus can be an instruction bus for the processor, which can route instructions directly from the instruction memory to the execution region. The functional processing units can be arranged completely in parallel or in a computational pipeline. If the processor is a processing core, the processing pipeline can be the main computational pipeline of the processing core. The functional processing unit can be any type of computing unit, including an arithmetic logic unit, a floating point unit, a rounding unit, a general math unit, a compression unit, a data type modification unit, a load unit, a storage unit, and other basic computing units or computing pipeline units. The task of the load unit can be to load data from the processor's cache memory, from the processor's main memory, or from a temporary storage area in the processor's execution area into the processor's computing pipeline. The task of the storage unit can be to store the data output by the functional processing unit in the processor's cache memory or the processor's main memory. Depending on the application for which the processor is designed, specialized functional processing units and functional processing unit groups can be selected. For example, the functional processing unit can form a graphics rendering pipeline or a systolic array for intensive linear algebra calculations.

[0021] In an embodiment, the processor includes a controller, which can take various forms. The processor disclosed herein may include a controller for coordinating the execution of operations within the processor and exchanging data (including instruction data and operand data) between the functional processing unit and the memory of the processor. As known in the art, the controller can handle many known actions, which are performed by a standard processor controller for managing the processor. For example, the controller can load instructions from the instruction memory to the execution area of ​​the processor. More specifically, the controller can load instructions into the instruction decoding logic of the processor execution area. If the processor is a processing core in a multi-core processor, the controller can be the core controller of the processor. In a specific embodiment, the controller can be a dedicated central processing unit (CPU) for performing the management of the processor.

[0022] In a specific embodiment of the present invention, the processor disclosed herein may include a set of instruction registers. The set of instruction registers may be located near the functional processing unit. The set of instruction registers may be in the execution area of ​​the processor. The set of instruction registers may be closer to the functional processing unit than the instruction memory. The set of instruction registers may be part of the processor instruction decoding logic circuit. The set of instruction registers is independent and distinct from the instruction memory of the processor, but can load instructions from the instruction memory. In a specific embodiment, the instruction memory can be implemented in the high-speed cache memory of the processor in the form of SRAM, and the set of instruction registers is usually an independent hardware unit in the form of a register or a latch logic circuit.

[0023] In a specific embodiment of the present invention, the group of instruction registers can be configured to load a group of pre-stored instructions using a bus. The instructions can be called pre-stored because they are pre-loaded into the group of instruction registers so that they can be quickly applied to at least one functional processing unit of the processor later. The group of instruction registers can load instructions from the instruction memory. The instruction register can be configured to load the group of pre-stored instructions in various ways. For example, the instruction decoding logic of the processor can identify a special operation code in a specific instruction loaded from the memory, which indicates that the net load of the specific instruction should be provided to the instruction register. Then, the processing of these special instructions by the instruction decoding logic may cause these instructions to be stored in the instruction register instead of causing the computing unit of the processing core to perform the operation immediately. In a specific embodiment of the present invention, the instruction decoding logic of the processor can also identify an address indicating which instruction register the net load instruction should be loaded into. These special instructions can be referred to as "configuration instructions" here, and the operation code is a "configuration" operation code identified by the instruction decoding logic.

[0024] In an embodiment, a processor includes a set of instruction registers configured to load a set of pre-staged instructions, and the processor can implement the functions of a variable length instruction set machine. Because the contents of the instruction set registers can load different instruction sets, the processor can effectively create new compound instructions from the combination of operation codes that the functional processing unit is designed to execute, for execution by the processor. These compound instructions can include different numbers of component instructions, so the length of the compound instructions is variable.

[0025] In a specific embodiment of the present invention, pre-storing instructions can provide significant benefits in reducing the size of the instruction bus, reducing the number of instructions that need to be transmitted on the instruction bus, or a combination of the two. Because the contents of the instruction set registers can be loaded with instruction sets that can be used multiple times, for example, in the case of large data sets or loop programs, the relevant instructions do not need to be repeatedly transferred from the instruction memory to the execution area of ​​the processor, while still achieving the same amount of computation. In addition, although there is an overhead in loading these registers, if the pre-stored instruction set is used multiple times, this overhead can be negligible relative to the savings brought about. This is particularly true in applications such as graphics rendering, training of machine learning applications, drawing inferences from artificial neural networks, and others.

[0026] In a specific embodiment of the present invention, in response to receiving an instruction from an instruction memory, a pre-stored instruction may be provided from the set of instruction registers to at least one functional processing unit. The instruction may include a specific operation code, which will be identified as a "trigger instruction." The instruction decoding logic of the processor may detect the "trigger" operation code in the instruction and, in response, initiate the provision of the pre-stored instruction to at least one functional processing unit. The instruction may be referred to as a trigger instruction because it triggers the provision of the pre-stored instruction to at least one functional processing unit. The instruction may also be referred to as a macroinstruction because the pre-stored instruction may be a set of component instructions that form an instruction composite program that is provided to at least one functional processing unit in sequence. In a specific embodiment of the present invention, reference is made to Figure 6 As described below, the trigger instruction may be identified by an operation code which will be executed by the functional processing unit but which will serve dual purpose as the trigger instruction.

[0027] In a specific embodiment of the present invention, the trigger instruction may include a payload having configuration information about the manner in which the pre-staging instruction is provided from the set of instruction registers to at least one functional processing unit and / or configuration information about how the at least one functional processing unit should execute the instruction. As an example of configuration information, the trigger instruction may include sequence information for identifying a sequence for applying the instruction in the instruction register to at least one functional processing unit. Accordingly, the content of the trigger instruction may be designed to identify the pre-staging instruction by the address of the pre-staging instruction in the instruction register and describe their sequence by the arrangement of these addresses. As another example of configuration information, the trigger instruction may include execution information, which specifies the location of specific operands of the instruction and where the result of the instruction execution is placed. In an embodiment in which at least one functional processing unit is associated with a set of staging registers, the execution information may identify an address in the staging register in which an intermediate or final result of executing the instruction is stored. The execution information may include additional specifications for how the pre-staging instruction should be executed, such as which specific functional unit the execution of the instruction should be assigned, the precision with which the instruction should be executed, the required data type of the instruction output, if the instruction should be suppressed in some other way, and a variety of other options.

[0028] Figure 1A block diagram of a processor 100 according to a specific embodiment of the invention disclosed herein is shown. The processor 100 includes an instruction memory 101, a functional processing unit 102, a bus 103, a set of instruction registers 104, and a logic circuit 105. The functional processing unit 102, the instruction register 104, and the logic circuit 105 are in an execution region 106 of the processor 100. The instruction memory 101 is separate from the execution region 106, but is capable of providing instructions to the execution region 106 via the bus 103. Since the bus 103 routes instructions from the instruction memory, the bus 103 can be referred to as the instruction bus of the processor 100. The instruction memory 101 stores instructions (e.g., instruction 107) for transmission to the execution region 106 via the bus 103, in an order determined by their location in the instruction memory 101. The instructions can be provided to the instruction memory 101 by an automatic compiler acting on higher-level instructions or directly by a human programmer. In a specific embodiment of the present invention, the processor 100 uses the instruction fetch command as a trigger for stepping through the program and fetching the next instruction from the instruction memory 101 to pass to the execution region 106. The functional processing unit 102 is drawn overlaid on the main computational data flow of the processor 100. The input of the data flow is the input data register 108 in the execution region 106, and the output of the data flow is the output data register 109 in the execution region 106. In a specific embodiment of the present invention, the data flow will include the computation pipeline of the processor 100, and the functional processing unit 102 is part of the processor 100. The input data register 108 and the output data register 109 can be temporary registers for data that will be stored more permanently in the processor's memory as operand data. In a specific embodiment of the present invention, the input data register 108 and the output data register 109 can be the same so that the output overlays the input. The memory for the operand data can be the same hardware element as the instruction memory 101, or it can be a different memory, such as the processor's cache memory or main memory.

[0029] The processor 100 may be defined at least in part by an instruction set of the processor 100. The instruction set may include all instructions that can be recognized by the functional processing units of the processor (e.g., functional processing unit 102). The width of the bus 103 is at least the same as the instruction size of the instruction set. For example, the instruction size may be 32 bits and the bus may be a 32-wire bus. In addition, the instruction register 104 may be designed to store pre-stored instructions having the instruction size of the instruction set. The processor 100 may have an instruction set, which includes a trigger instruction and a configuration instruction, the trigger instruction is used to trigger the provision of instructions from the instruction register to the functional processing unit, and the configuration instruction is used to control the initial storage of the pre-stored instructions in the instruction register.

[0030] In a specific embodiment of the present invention, the processor may include logic circuitry in the form of an instruction decoding logic circuitry that operates in conjunction with the functional processing unit of the processor to execute instructions. The instruction decoding logic circuitry may be defined at least in part by the instruction set of the processor. For example, the logic circuitry 105 may include an instruction decoding logic circuitry 110 that operates according to the instruction decoding logic circuitry of a standard processor to decode instructions provided on the bus 103 for execution by the functional processing unit 102. Thus, the functional processing unit 102 and the instruction decoding logic circuitry 110 may execute instructions, such as instructions 107 from the instruction memory 101, using operand data from the input data register 108 to output the operand data to the output data register 109. Furthermore, in addition to decoding instructions for execution according to the methods of a standard processor, the instruction decoding logic circuitry 110 may also include the functionality of identifying configuration and triggering instructions and processing them appropriately. The logic circuitry may use standard processes for identifying operation codes to identify the associated operation codes. The logic circuit may then be in a state of routing instruction data to the instruction register 104 (upon receiving a configuration instruction) or routing instruction data from the instruction register 104 to the functional processing unit 102 (upon receiving a trigger instruction).

[0031] In a specific embodiment of the present invention, the processor may include a device for loading a set of pre-stored instructions into a set of instruction registers using a bus. The instruction register may be configured to load a set of pre-stored instructions from an instruction memory using a bus. For example, the bus may be an instruction bus of the processor, such as bus 103, and the instruction register should be configured to be optionally connected to an instruction fetch line, which is coupled to bus 103 through a multiplexer or a crossbar latch, or the instruction register may be connected to logic circuit 105 so as to receive the instruction after the logic circuit has processed the instruction. The device for loading a set of pre-stored instructions into the set of instruction registers 104 using bus 103 may be an instruction decoding logic circuit 110. The instruction decoding logic circuit 110 may be designed to examine the instruction provided on bus 103, identify the instruction as a configuration instruction in response to an instruction fetch command, and take appropriate actions to load the pre-stored instruction into an instruction register (e.g., instruction register 104), such as routing the net load of the configuration instruction to a specific register. The instruction decoding logic circuit 110 may route the instruction to a specific register according to a fixed schedule (e.g., by a circular order of register addresses). Alternatively, the configuration instruction may include specific information about which instruction register the pre-staged instruction should be loaded into. As mentioned elsewhere, the configuration instruction may include other instruction data, such as what type of instruction the pre-staged instruction is, and other data associated with the pre-staged instruction, such as how the pre-staged instruction should be executed and what the operands of the instruction are. In a specific embodiment, the net load of the configuration instruction may be the pre-staged instruction itself or a large part of such an instruction. In a specific embodiment, the instruction decoding logic circuit 110 may change its state after detecting the configuration instruction and directly route it to the instruction register when receiving additional instructions instead of decoding it. In these embodiments, the configuration instruction may include a counter for counting the number of instructions that the decoding logic circuit 110 should route to the instruction register before restoring to its nominal state. Alternatively, a separate instruction to turn off the configuration mode may then return the instruction decoding logic 110 to its normal state, in which additional incoming instructions are processed normally. In an alternative or combination, the device for loading the set of instruction registers using a bus may include a controller, such as controller 113. The controller may be configured to load the set of pre-staged instructions from the instruction memory to the set of instruction registers using the bus. The process may override the operation of logic circuit 105 and use bus 114 to directly write to the address in instruction register 104 to pre-store the set of instructions. The controller may be a software accessible controller to facilitate debugging the operation of the instruction register. Controller 113 may also load instructions into instruction memory 101 via bus 115 to facilitate debugging configuration instructions. In embodiments where processor 100 is a processing core, controller 113 may be a core controller.

[0032] In a specific embodiment of the present invention, the processor may include means for providing a set of pre-stored instructions from a set of instruction registers to at least one functional processing unit in response to receiving instructions from an instruction memory. For example, the processor may include logic circuitry configured to provide the set of pre-stored instructions from the set of instruction registers to at least one functional processing unit in response to receiving instructions from the instruction memory. Figure 1 In the example of , the logic circuit 105 may include a pre-storage instruction transfer logic circuit 111 to facilitate providing the pre-storage instructions to the functional processing unit 102. In a specific embodiment of the present invention, the pre-storage instruction transfer logic circuit 111 may do so under the control of a controller (e.g., controller 113). In a specific embodiment of the present invention, the pre-storage instruction transfer logic circuit 111 may do so under the control of configurable information provided by the instruction decoding logic circuit 110. The instruction decoding logic circuit 110 may provide such configurable information of an operation code or a net load from a trigger instruction upon receiving such a trigger instruction on the bus 103. In either of these two types of embodiments, upon decoding the trigger instruction, the instruction decoding logic circuit may start the pre-storage instruction transfer logic circuit. In either of these two types of embodiments, the pre-storage instruction transfer logic circuit (e.g., the pre-storage instruction transfer logic circuit 111) may be designed to provide an instruction sequence from an instruction register to the functional processing unit, synchronized by an instruction fetch command sent by a controller of the processor (e.g., controller 113). The instruction fetch command may be a standard signal issued by a controller to synchronize the operation of the processor when executing its instructions.

[0033] Depending on the embodiment of the invention, the instructions in the instruction register may have the same size as the instruction size of the processor's instruction set, or may have a different size. For example, the pre-staged instructions may be passed to the logic circuit 105 in a first format that identifies them as intended to be stored in the instruction register 104, and may then be stored in the instruction register 104 in a second format. The second format may have fewer bits than the first format. When the instruction is first passed to the logic circuit 105, the operation code of the instruction may identify it as a configuration instruction, and when the instruction is stored in the instruction register 104, the header of the instruction may identify it as a mathematical operation or some other type of operation to be performed by the functional processing unit 102. As another example, the pre-staged instructions may be passed directly to the instruction register 104 without being modified by the controller 113 or the logic circuit 105.

[0034] A specific example of the functionality of processor 100 illustrates the benefits of certain embodiments of the present invention. Functional processing unit 102 may be a floating point unit for executing a program stored in instruction memory 101. The program may be a loop of four floating point unit operations that must be executed on a large data set. The data set may include billions of entries, so the loop needs to be run billions of times to process the entire data set. To perform this operation, a compiler may compile a set of instructions for instruction memory 101 that first instructs logic circuit 105 to pre-stage the four floating point unit operations of the loop into instruction register 104, and then instructs logic circuit 105 to apply these instructions to functional processing unit 102 in a repeating sequence. The initial loading of the instruction register may be achieved by passing four configuration instructions to logic circuit 105. Each repetition of the sequence may be achieved by passing a trigger instruction with a payload that identifies additional data for running the sequence. This example illustrates the benefits of the disclosed architecture. Because the number of instructions that must be transmitted over bus 103 is reduced by a factor of four. If the data set contains billions of cycles, this can represent a significant savings, and the overhead of sending the initial four configuration instructions can be negligible. This provides significant benefits, bus 103 can be kept small because the required instruction size is small (more complex instructions can be formed by sending configuration information, so each component instruction can be small), and because instruction transfers within the execution region consume less power than instruction transfers from instruction memory to the execution region. In addition, the trigger instruction can include sequence information to identify the order in which the four operations should be run. Therefore, this example illustrates the additional benefit that commonly used component instructions can be reconfigured into different composite instructions without having to send additional configuration instructions to reconfigure the instructions stored in instruction register 104.

[0035] Figure 2 A block diagram of an execution region of a processor according to a specific embodiment of the present invention disclosed herein is shown. Execution region 200 may be used to explain further embodiments of the present invention. In a specific embodiment of the present invention, the processor may include two or more functional processing units, and instructions from an instruction register may be fed to these functional processing units in parallel. Figure 1 Reference numbers in are again used to indicate previously described elements. Execution region 200 is distinguishable from execution region 106 because execution region 200 explicitly shows multiple functional processing units on the data flow path of the processor. Specifically, execution region 200 includes functional processing unit 201 and functional processing unit 202. Each functional unit in the present disclosure may require more than one clock cycle to execute an instruction, so instructions can be executed in a pipeline manner. In addition, multiple functional processing units can be arranged to perform pipeline operations on data. For example, Figure 2The functional units in can be arranged to obtain data from data register 108 and operate on the data using a systolic array paradigm, where the output of each functional unit (i.e., 201 and 102) is provided as the input of the next functional unit (i.e., 102 and 202, respectively). In addition, multiple functional units can be arranged to operate in a pipelined manner by writing and reading from a set of common registers (e.g., scratch register 203). For example, functional processing unit 201 can write output data to scratch register 203, which is then read as input data by functional processing unit 202. Figure 2 In a specific embodiment, the functional processing unit is configured to use any of the three pipeline concepts described above. In addition, the manner of executing the pipeline can be described in the execution information in the configuration or trigger instruction received on the bus 103. According to a specific embodiment of the present invention, the logic circuit 105 can provide instructions from the instruction register 104 to any functional processing unit in the pipeline. Since the execution area 200 includes a set of temporary registers 203, the functional processing units 102, 201, 202 can access the temporary registers 203, so the execution area 200 is further distinguished from the execution area 106. The temporary registers 203 can be a set of general registers available to the functional processing units.

[0036] In a system where the execution region includes multiple functional processing units, instructions from the instruction register can be routed to the correct functional processing unit in various ways. For example, in a specific embodiment, the instruction in the instruction register may include instruction data that identifies which functional processing unit the instruction is for (e.g., directly through a functional processing unit identifier or indirectly by including an operation code that can only be executed by a specific functional unit). As another example, the instruction decoding logic may store the instruction in a specific instruction register that is associated with a given functional processing unit. The instruction decoding logic may obtain the information required for the storage step from an analysis of the operation code of the instruction or from an analysis of the configuration data stored in the instruction payload.

[0037] In the processing architecture, the processing pipeline includes a set of temporary registers, and the specific addresses of the temporary registers to be used during the execution of a set of instructions in the instruction register can be specified by the configuration data in the trigger instruction. The execution area 200 includes a set of temporary registers 203 accessible to the functional unit. The temporary registers can store intermediate results from the functional processing unit, which may be required by other functional processing units in the pipeline outside the mainstream pipeline. In these embodiments, the trigger instruction for executing the instruction in the instruction register may include configuration information, and the logic circuit 105 may be configured to provide the set of pre-temporary instructions from the set of instruction registers 104 to the functional processing unit 102, 201, 202 together with the configuration information. The configuration information can be set at the address in the temporary register 203 for use by the set of pre-temporary instructions. In a specific embodiment, the instruction in the instruction register may be smaller than the instruction transmitted on the bus 103. For example, the instruction transmitted on the bus 103 may be a 32-bit instruction, and the instruction stored in the instruction register 104 may be a 28-bit instruction. In these embodiments, the configuration information from the trigger instruction may be large enough to provide 4 bits to each instruction in the set of instruction registers 104 so that they become full 32-bit instructions processed by the instruction decode logic 110. The configuration information may include additional information in alternative embodiments that will increase the size of the pre-staged instructions before they are executed by the functional processing unit.

[0038] Figure 3A flow chart 300 of a set of methods is shown, which is in accordance with a specific embodiment disclosed in the present invention. Flowchart 300 begins with step 301 of compiling instructions for a processor to perform a calculation. This step may result in the storage of a sequence of instructions in an instruction memory of the processor. Step 301 may be performed by a compiler that is part of the processor, or by an external compiler, where the instructions are pushed to the processor through a network for performing a composite calculation, where the processor is only a single processing node. In a specific embodiment, step 301 may also be performed by a human programmer operating a control system, where the human programmer directly specifies a sequence of instructions stored in the instruction memory. These instructions may be stored in a series of addresses that will be accessed in sequence by a program counter and synchronized by an instruction fetch command issued by a controller of the processor. Step 301 may include a step of increasing the parallelization of program execution. To this end, the compiler may search for loops in the program and form a set of pre-staged instructions and related configuration data for each operation in the loop. Step 301 may also include generating configuration and trigger instructions to be included in the instruction sequence. This step can be performed as part of a process of searching for a loop in a program, because the configuration instruction can pre-store instructions for executing the loop in an instruction register of the processor, and the trigger instruction can trigger an execution of the loop by triggering the pre-stored instructions to be provided from the instruction register to at least one functional processing unit of the processor.

[0039] Flowchart 300 continues with step 302 of storing instructions in an instruction memory. The instructions may be the instructions compiled in step 301, including trigger and configuration instructions. The instruction memory may be a local cache or main memory of the processor. For example, the instruction memory may be from Figure 1 The instruction memory 101. The instructions may be stored in the order in which they will be executed.

[0040] Flowchart 300 continues with step 303, where a set of pre-stored instructions are loaded from an instruction memory to a set of instruction registers using a bus. The bus may be an instruction bus of a processor. The instructions may be processed by logic circuits in the execution area of ​​the processor and routed to the instruction registers according to the above method. For example, instruction decode logic 110 may receive configuration instructions on bus 103 and switch to a mode in which additional instructions received on bus 103 are routed to instruction registers 104. Alternatively, a specific instruction received on bus 103 may identify itself as an instruction that should be routed to instruction registers 104 by instruction decode logic 110. This step may be performed synchronously with the instruction fetch command of the processor. This step may include actions taken by a controller of the processor and an instruction memory and logic circuits of the processor.

[0041] Flowchart 300 continues with step 304 of receiving an instruction. The instruction may be received at logic circuitry on the processor. The logic circuitry may be instruction decode logic circuitry of the processor. The instruction may be received according to a standard procedure for obtaining instructions to be executed by the processor. The instruction may be received on an instruction bus of the processor. Alternatively, the instruction may be passed from a controller of the processor on a bus used for debugging to the instruction decode logic of the processor, or otherwise override the normal manner in which the instruction is passed to the instruction decode logic of the processor. The instruction may be a trigger instruction that will initiate the transfer of a pre-staged instruction from an instruction register to at least one functional processing unit of the processor. The trigger instruction may also be an instruction that is itself executable by the functional processing unit, but also includes information indicating that the pre-staged instruction should be provided from the instruction register, such as a tag or other header information.

[0042] In a specific embodiment of the present invention, the received instruction will start providing instructions to the functional processing unit, such as the trigger instruction received in step 304, and may include configuration information about how the pre-stored instructions should be executed. The configuration information may include selection information, sequence information and / or execution information. The logic circuit of the processor may be configured to select a subset of a set of pre-stored instructions stored in the instruction register using the selection information. The logic circuit may also be configured to provide the subset of the set of pre-stored instructions to at least one functional processing unit in a specified sequence based on the sequence information. For example, the trigger instruction may include configuration information, which will use the selection information to select two from twelve pre-stored instructions, and may use the sequence information to specify that one of the instructions should be executed before the other instruction. In a specific embodiment of the present invention, the sequence information may be implicit in the arrangement of the selection information. For example, the trigger instruction may have a first register address followed by a second register address. Therefore, due to the storage order of the two addresses, the sequence and selection information are combined. The selection of the two register addresses will serve as the selection information, and the order of the two addresses in the net load will serve as the sequence information.

[0043] Flowchart 300 continues with step 305, in response to receiving the instruction and using the logic circuit, providing the pre-stored instruction from the set of instruction registers to at least one functional processing unit. The pre-stored instruction may be provided to the at least one functional processing unit using configuration information provided with the instruction. The instruction may be the trigger instruction mentioned above. This step may be performed by the logic circuit of the processor. For example, this step may be performed by the logic circuit 105 of the processor 100. As a more specific example, this step may be performed by the pre-stored instruction transfer logic circuit 111. The pre-stored instruction transfer logic circuit 111 may perform step 305 in response to a signal from the instruction decoding logic circuit 110 or in response to a signal from a controller (e.g., controller 113) of the processor.

[0044] Flowchart 300 includes a set of sub-steps of step 305 to describe a specific embodiment of performing step 305. Specifically, performing this step can be performed by a pre-staged instruction delivery logic circuit having a multiplexer and a shift register, wherein the shift register controls which register is accessed at a given time, and the multiplexer can deliver the contents of the register to at least one functional processing unit of the processor. The sub-steps include step 306 of using a logic circuit to load the shift register of the logic circuit with instruction sequence information from the instruction sequence information, step 307 of controlling the multiplexer with the sequence information from the shift register, and step 308 of providing the group of pre-staged instructions from the group of instruction registers to at least one functional processing unit through the multiplexer. Reference can be made to the following Figure 4 Describe the specific systems used to perform these substeps.

[0045] In a specific embodiment of the present invention, the processor includes a logic circuit having a shift register and a multiplexer for performing the provision of pre-staged instructions from the instruction register to the functional processing unit. The logic circuit can be used for the purpose of pre-staged instruction transfer logic circuit, for example, pre-staged instruction transfer logic circuit 111. The shift register can be coupled to the multiplexer control, and the multiplexer can be configured to provide the contents of various different instruction registers to a given functional processing unit based on the control input of the shift register. The various inputs of the multiplexer can be different instruction registers in a set of instruction registers. The input of the multiplexer can also include a direct link to the instruction bus, which will allow the pre-staged instruction transfer logic circuit to be bypassed. The input of the multiplexer can also have hard-coded instructions that are commonly accessed. In the case where such hard-coded instructions are required to be executed in any given composite instruction, embodiments of the present invention will further save time and energy because the hard-coded instructions do not need to be set in advance by configuration instructions.

[0046] Figure 4 Block diagrams and flow charts are shown to illustrate the operation of a portion of a logic circuit according to a specific embodiment of the present invention disclosed herein. The portion of the logic circuit 400 may include a multiplexer 401 and a shift register 402. The multiplexer 401 is coupled to the shift register 402. The portion of the logic circuit 400 may be a pre-staged instruction transfer logic circuit, such as the pre-staged instruction transfer logic circuit 111. The portion of the logic circuit 400 may be combined with an instruction decoding logic that identifies a trigger instruction as a means for providing a set of pre-staged instructions from a set of instruction registers to at least one functional processing unit in response to an instruction received from an instruction memory. Reference will be made to Figure 5As described above, multiple instantiations of the portion of the logic circuit 400 may be used in combination to provide instructions to multiple functional processing units in parallel. The portion of the logic circuit 400 may also perform steps 307 and 308 in the flowchart 300 and receive the sequence information loaded in step 306. In these embodiments, the instruction decoding circuit may perform step 306 and serve as a means for loading a set of pre-staged instructions into the set of instruction registers using the bus.

[0047] In a specific embodiment of the present invention, the net load of the configuration instruction will be used to load the instruction register, and the net load of the trigger instruction will be used to load the shift register. The shift register can load the address of a specific instruction register in the encoding space of the multiplexer to which it is connected. The shift register can load a series of such addresses so as to trigger the provision of pre-temporary instructions by the functional processing unit, and the pre-temporary instructions come from the instruction register associated with such addresses. The shift register can be configured to shift for various reasons as described below. Regardless of how the shift register shifts, when the value in the shift register circulates, the instruction register address sequence will be provided to the multiplexer, and the pre-temporary instructions at the associated instruction register address will be provided to the associated functional processing unit and executed. In this way, the logic circuit of the processor can be configured to load the sequence information from the instruction to the shift register, and to use the sequence information and the shift register to provide the pre-registered instructions from the group of instruction registers to at least one functional processing unit through the multiplexer. However, these steps can also have a variety of alternative methods.

[0048] In an alternative embodiment of the present invention, the net load of one or more configuration instructions will be used to load the instruction register and provide multiple groups of pre-storage inputs to the shift register, while the net load of the trigger instruction will be used to select which group of pre-storage inputs should be provided to the shift register. These methods are different from the methods described in the previous paragraph because the net load of the trigger instruction can be smaller because it will only select one group of pre-storage inputs to the shift register without encoding all groups of pre-storage inputs. Other than that, the method is similar to the method described in the previous paragraph. Upon receiving a trigger instruction that identifies a group of pre-storage inputs for the shift register, the group of pre-storage inputs can be loaded into the shift register. The pre-storage inputs can be the addresses of specific instruction registers in the encoding space of the multiplexer to which they are connected. The pre-storage inputs of the shift register can be a sequence of such addresses so that the pre-storage instructions are triggered by the functional processing unit to provide pre-storage instructions, and the pre-storage instructions are from the instruction register associated with such addresses.

[0049] Figure 4It includes a configuration instruction 410 and a trigger instruction 411. The logic circuit shown implements the function by first loading the pre-temporary instruction into the instruction register 104. For example, the net load 412 of the configuration instruction 410 can be loaded into the instruction register 413 and stored as a pre-temporary instruction. In this example, a separate instruction is previously loaded into the instruction register 104. Subsequently, the net load 415 of the trigger instruction 411 can be loaded into the shift register 402. The net load 415 can be the address of the register 414, followed by the address of the register 413 in the MUX401 encoding space, and can be loaded into the sequential register of the shift register 402. Alternatively, as described above, the net load 415 can identify a set of pre-temporary inputs of the shift register in the form of the address sequence mentioned in the previous paragraph. In this method, the set of pre-temporary inputs can be provided by the configuration instruction 410, and the configuration instruction 410 also has a shift register net load.

[0050] In a specific embodiment of the present invention, the trigger instruction may include sufficient configuration information to select and order a large number of pre-stored instructions for execution by one or more functional processing units of the processor. For example, if the encoding space of MUX401 is two bits and the net load 415 is a 24-bit net load, the net load 415 will be able to select and order 12 pre-stored instructions for execution by the functional processing unit 102. Therefore, the net load 415 of the trigger instruction 411 will be sequence and selection information (specifying that the instructions in the instruction registers 413, 414 should be executed in the order in which they should be executed). At this point, the circuit will be ready to provide the pre-stored instructions to the functional processing unit. Flowchart 420 provides sub-steps of the execution step 303 from flowchart 300, including a step 421 of receiving a processor instruction fetch command and a step 422 of shifting a shift register when receiving a processor instruction fetch command. These steps may involve a shift register (e.g., shift register 402), receiving a processor instruction fetch command on an input (e.g., input 403), and shifting the shift register accordingly. As a result, the contents of the next register of the shift register 402 will be provided to the control input of the multiplexer. For example, the shift register 402 may first output the address of the instruction register 414 to the MUX 401, which will cause the MUX to provide the instruction from the instruction register 414 to the functional processing unit 102, and then the address of the instruction register 413 may be output to the control input of the MUX 401 by shifting by receiving the signal on the input 403. Thus, the trigger instruction may create different compound instructions based on a set of pre-stored instructions by loading the shift register in different sequences. Although not provided in this example, different compound instructions may also be distinguished based on other configuration information from the trigger instruction, such as the address of the input, output, or intermediate register for use by the instruction during execution.

[0051] In specific embodiments of the present invention, the shift register described throughout this disclosure may be configured to shift in different ways. In specific embodiments, the shift register may shift once a set of designated dependencies are met. The designated dependencies may change over the course of the device's operation. The dependencies may be programmed by a higher-level controller or by control information sent in a configuration or trigger instruction. The set of dependencies may be programmed to an empty set, causing the shift register to continue to shift automatically without receiving additional external control signals. The shift register may be configured to shift without receiving another processor instruction, and may continue to loop through pre-staged instructions at the same speed as the functional processing unit is able to process these pre-staged instructions. As an example of a dependency, the shift register may be configured to shift upon receiving an instruction fetch command from a processor. The instruction fetch command may be in Figure 4 402. As another example of a dependency, the shift register may be configured to require another instruction to be received before shifting. As another example, the shift register may be configured to require another trigger instruction to be received before shifting. As another example, the shift register may be configured to shift once a response is received from the memory that the data has been successfully written therein. As another example, the shift register may be configured to shift in response to a combination of the above events. In a specific embodiment of the present invention, the shift register may be configured to exhibit any of these behaviors, and the shifting mode used may be set by the initial trigger instruction or the net load of the configuration instruction. For example, if instruction 413 should not be executed before receiving some other instruction, the shift register 402 may be configured to shift only when the instruction is received. However, if instruction 413 can be performed immediately after 414, the shift register 402 may also be configured to shift immediately.

[0052] Reference above Figure 4The described method can be extended to a processor having multiple functional processing units. The processor may include multiple pre-staged instruction delivery logic circuits for delivering the correct pre-staged instructions to the appropriate functional processing unit. In a single instruction multiple data (SIMD) implementation, the same instruction from an instruction register can be provided to multiple functional processing units at the same time. In a pipeline parallel computing implementation, additional multiplexers and shift registers can be used for each functional processing unit to provide different instructions to different functional processing units in parallel. The different functional processing units can be different types of functional processing units, or they can be the same type of functional processing units executing different instructions or the same instructions on data that has changed as it moves down the processing pipeline. The additional multiplexer and shift register groups can share a set of instruction registers, or they can each have their own set of instruction registers.

[0053] Figure 5 A block diagram of a portion of a logic circuit 500 having at least two functional processing units according to a specific embodiment of the invention disclosed herein is shown. The functional processing units 501 and 502 shown may be functional processing units that operate on different parts of a processor pipeline. Various ways of incorporating the functional processing units 501 and 502 into the data path of the processor may be similar to those described in reference to Figure 2 1, 201, and 202 in the same manner as described above. For example, functional processing units 501 and 502 can be connected to the same pipeline stage in the processor, can be arranged sequentially in a systolic array paradigm, and / or can be interconnected to a set of temporary registers to support multiple potential pipeline paths. Functional processing units 501 and 502 can be the same type of functional processing units, or different types of functional processing units. For example, a functional processing unit can include two different functional processing blocks selected from: a load block, a data type conversion block, an arithmetic logic unit block, a floating point math block, a rounding block, and a storage block, as well as any other type of specialized functional processing unit. Logic circuit 500 is capable of executing Figure 3 Another example of the circuit of step 305 in the embodiment adds at least one functional processing unit, including two functional processing units 501 and 502, and providing pre-stored instructions from the set of instruction registers in step 305 includes providing instructions to the two functional processing units 501 and 502 in parallel.

[0054] The operation of logic circuit 500 is similar to the operation of logic circuit 400, and similar principles can be applied to processing architectures having even more than two functional processing units operating in parallel. In addition, as described above, each functional processing unit in logic circuit 500 can be mirrored by one or more functional processing units in a SIMD architecture, wherein each mirrored functional processing unit receives the same instruction as the functional processing unit shown. Two or more functional processing units can be arranged in a parallel pipeline, or arranged in sequence in a single pipeline. Logic circuit 500 includes at least two multiplexers 503 and 504, and at least two multiplexers 503 and 504 are controlled by at least two shift registers 505 and 506 in a one-to-one correspondence. The logic circuit of the processor is configured to load configuration information from an instruction to at least two shift registers 505 and 506. In the illustrated embodiment, the instruction is a trigger instruction 540, which has two separate configuration information segments 511 and 512 provided to the shift registers 505 and 506, respectively. Configuration information 511 and 512 may be sequence information and include addresses of specific registers in instruction registers 507 and 508, respectively, in the address encoding space of multiplexers 503 and 504. The logic circuit for providing configuration information to the shift register may be instruction decoding logic of the processor.

[0055] In the illustrated embodiment, the logic circuit is configured to provide a set of pre-stored instructions to two functional processing units in parallel using sequence information and at least two shift registers. The set of pre-stored instructions from the set of instruction registers can be provided to at least one functional processing unit through at least two multiplexers. For example, shift register 505 can provide an address for register 509 in the encoding space of multiplexer 503 at the control input of multiplexer 503, and at the same time, shift register 506 can provide an address for register 510 in the encoding space of multiplexer 504 at the control input of multiplexer 504. As a result, multiplexer 503 will pass the instruction of register 509 to functional processing unit 501, and multiplexer 504 will pass the instruction of register 510 to functional processing unit 502. Registers 509 and 510 are not in the same part of their associated register group to illustrate the fact that multiple multiplexers can be connected to the same group of instruction registers. This approach may make sense when multiple functional processing units are designed to recognize the same operation code (for example, if functional processing unit 501 and functional processing unit 502 are the same type of functional processing unit). Logic circuit 500 can be designed to provide instructions to functional processing units 501 and 502 in parallel because shift registers 505 and 506 can both be controlled by common signal 513. For example, the common signal can be a processor instruction fetch command of a processor and cause the two shift registers to shift in parallel.

[0056] Based on Figure 5 In this method, the instruction register can be used in a similar way to the above reference Figure 4 The method described loads pre-staged instructions. Specialized instructions (such as configuration instructions) can be pre-issued from the instruction memory, and these instructions either load the registers themselves or include data for loading the registers. Figure 5 In the example of FIG. 5 , the trigger instruction 540 is preceded by a first configuration instruction 520 and a second configuration instruction 530. The trigger instruction 540 may be preceded by any number of instructions that will be used to load the instruction register. As shown, the configuration instruction 520 includes a first net load, which may be at least a portion of a pre-staged instruction for storage in the instruction register 509, and the configuration instruction 530 includes a second net load, which may be at least a portion of a second pre-staged instruction for storage in the instruction register 510. Figure 5 This is illustrative only, and in particular embodiments, a single configuration instruction may include the data necessary to load more than one instruction register.

[0057] In a specific embodiment of the present invention, the functional processing unit of the processor can be a functional block of different types. For example, the functional processing unit can be selected from a load block, a data type conversion block, an arithmetic logic unit block, a floating point math block, a rounding block and a storage block, as well as any other form of basic or specialized functional processing unit. In these embodiments, the processor can be configured to pass each instruction transmitted on the instruction issuing bus to the instruction decoding logic of the circuit, and push the operation code of the instruction to each functional processing unit, and only the functional processing unit designed to perform the relevant operation will operate. In an alternative embodiment, the instruction decoding logic will include logic for evaluating the operation code and route it separately to the appropriate functional unit based on the evaluation. Regardless of the method adopted, the instruction decoding logic can be configured to treat a specific instruction as a regular instruction executed by the functional processing unit and a trigger instruction as described elsewhere in this article.

[0058] In a specific embodiment of the present invention, as shown below Figure 6 As described, the trigger instruction can be identified by an operation code, which will be executed by the functional processing unit, but it will play a dual role as a trigger instruction. These instructions can be called operation trigger instructions. For example, if the operation is a load instruction, the instruction can be called a load trigger instruction. In this example, at least one functional processing unit can include a load block and at least one different functional block. The load trigger instruction can be a load instruction with dedicated space for additional configuration information (such as sequence information) to define how to execute pre-staged instructions stored in the instruction register and intended for different functional blocks.

[0059] Embodiments using operation trigger instructions may exhibit specific benefits. They will particularly benefit from methods that use a specific functional processing unit in each sequence or pipeline of instructions executed by a processor. The aforementioned load trigger instruction is an example of such an instruction, and when it is used in a processing architecture configured with a load functional processing unit, the load functional processing unit is used as the first step in executing an operation sequence using the available functional processing units. In these embodiments, the instruction for loading the functional processing unit may include an operation code that identifies the instruction as a load instruction, a net load required for the load functional processing unit operation (e.g., the address of the data to be loaded into the pipeline), and configuration information for the trigger instruction as described above.

[0060] Figure 6 A block diagram 600 is shown of a portion of a logic circuit according to a specific embodiment of the present invention, the logic circuit being designed to operate with a load trigger instruction. Block diagram 600 includes a pipeline of different functional processing units in the form of a load block 601, a math block 602, and a rounding block 603. The pipeline may also include other blocks such as those described herein. As shown, load block 601 is not associated with a logic circuit for providing pre-staged instructions. Instead, load block 601 receives a load instruction 611, which is part of a load trigger instruction 610. The path for the illustrated load block 601 to receive the load instruction 611 may involve standard instruction decoding logic circuitry. The load instruction 611 may provide an address from a main memory or a cache memory to the load block 601, from which operand data is loaded for operation by the rest of the pipeline. At the same time, the load trigger instruction 610 may include a math shift register net load 612 for passing to a shift register 620, and a circular shift register net load 613 for a shift register 630. As shown in FIG. Figure 5 As shown, the shift register net load can specify the address in the instruction register 622 in the address space of MUX621, and the address in the instruction register 632 in the address space of MUX631. The shift register net load may include configuration information for executing multiple instructions by each of the math block 602 and the loop block 603. Multiple instructions can be executed on multiple rounds of pipelined data through the pipeline, or multiple data elements can be executed in a single execution of the pipeline. This second type of instruction execution may involve temporary registers to store intermediate values ​​and multiple operations performed by each functional processing unit. In a specific embodiment of the present invention, the load trigger instruction 610 can specify instructions for each functional processing unit in the pipeline, otherwise the functional processing unit will require a separate instruction from the instruction memory, so that a single load trigger instruction (delivered synchronously with the processor's instruction fetch command) will enable the entire pipeline to run with maximum parallelism without waiting for other commands.

[0061] The processor according to the present disclosure may include at least one non-transitory computer-readable medium. At least one processor may include at least one computing node in a computing node network. The medium may include a cache memory on the processor. The medium may also include a shared memory that is not associated with a unique computational node. The medium may be a shared memory, a shared random access memory, or, for example, a DDR DRAM. The shared memory may be accessed through multiple channels. The non-transitory computer-readable medium may store data required to perform any method disclosed herein, instruction data disclosed herein, and / or operand data disclosed herein. The computer-readable medium may also store instructions that, when executed by the system, cause the system to perform the method disclosed herein. The concept of executing instructions is used herein to describe the operation of a device that performs any logic or data movement operation, even if the "instruction" is fully specified in hardware (e.g., an AND gate executes a "logical and" instruction). The term does not mean that the device is given the ability to be programmable.

[0062] A processor according to the present disclosure may include at least one logic circuit as described above. The logic circuit may include active and passive devices and operate at one or more logic levels. The logic circuit may use Boolean logic operations and may be a synchronous clock circuit or an asynchronous circuit. The logic circuit may include logic gates, flip-flops, latches, registers, and other basic circuit elements that are required to produce digital logic outputs for digital logic inputs. The logic circuit may be implemented directly in hardware, thereby performing a logical or operation by a physical collection of transistors that implement an or gate, and the storage of data elements involves the physical state of at least one flip-flop, delay line, or other physical storage element.

[0063] Although this specification has been described in detail for specific embodiments of the present invention, it should be understood that those skilled in the art, after obtaining an understanding of the foregoing, can easily conceive of changes, variations and equivalents to these embodiments. Any method disclosed herein can be performed by a processor in conjunction with a computer-readable medium, which stores instructions for methods combined with the above-mentioned other hardware elements. These and other modifications and variations of the present invention can be implemented by those skilled in the art without departing from the scope of the present invention, which is more specifically set forth in the appended claims.

Claims

1. A processor, comprising: Instruction memory; at least one functional processing unit; bus; a set of instruction registers configured to load a set of pre-staged instructions from the instruction memory using the bus, the set of pre-staged instructions being pre-loaded into the set of instruction registers for later accelerated application to the at least one functional processing unit; and logic circuitry configured to receive instructions from the instruction memory, detect a trigger operation code in the instruction, and in response provide a subset of the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit; The instructions include configuration information, and the configuration information is used to select multiple component instructions from the set of pre-stored instructions and sort the multiple component instructions. The subset formed by the multiple component instructions is of variable length, and the length of the subset depends on the configuration information.

2. The processor according to claim 1, further comprising: Core controller; wherein the processor is a processing core; and The core controller is configured to use the bus to load the set of pre-stored instructions from the instruction memory to the set of instruction registers.

3. The processor of claim 1 , wherein: The processor has an instruction set; The width of the bus is at least the same as the instruction size of the instruction set; Each of the pre-staged instructions in the set of pre-staged instructions has a size equal to the instruction size; and The instruction has a size equal to the instruction size.

4. The processor of claim 1, wherein: The logic circuitry includes instruction decoding logic circuitry; and The at least one functional processing unit and the instruction decode logic circuit execute instructions from the instruction memory.

5. The processor according to claim 1, wherein: The logic circuit comprises: shift register; and a multiplexer, the multiplexer being controllably coupled to the shift register; wherein the logic circuit is configured to load sequence information from the instruction into the shift register; wherein the sequence information is the configuration information; and The logic circuit is configured to use the sequence information and the shift register to provide the subset of the set of pre-stored instructions from the set of instruction registers to the at least one functional processing unit through the multiplexer.

6. The processor of claim 5, wherein: The shift register is configured to shift when a specified set of dependencies are satisfied.

7. The processor of claim 1, wherein: The instructions include selection information and sequence information; The logic circuit is configured to use the selection information to select a subset of the set of pre-staged instructions; The logic circuit is configured to provide the subset of the set of pre-staged instructions to the at least one functional processing unit based on the sequence information; and The selection information and the sequence information are the configuration information.

8. The processor of claim 1, wherein: The instructions include sequence information; The logic circuit is configured to provide a subset of the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit using the sequence information from the instructions; and The sequence information is the configuration information.

9. The processor of claim 1 , further comprising: a set of scratch registers accessible by the at least one functional processing unit; wherein the logic circuit is configured to provide the subset of the set of pre-stored instructions together with the configuration information from the set of instruction registers to the at least one functional processing unit; and The configuration information sets addresses in the set of temporary registers for use by a subset of the set of pre-temporarily stored instructions.

10. The processor of claim 1, wherein: The at least one functional processing unit comprises at least two functional processing units; and The logic circuit provides at least two pre-staged instructions from the set of pre-staged instructions to the at least two functional processing units in parallel.

11. The processor of claim 1, wherein: The logic circuit comprises: At least two multiplexers, wherein the at least two multiplexers are controlled by at least two shift registers in a one-to-one correspondence; wherein the logic circuit is configured to load sequence information from the instruction into the at least two shift registers; Wherein, the sequence information is the configuration information; wherein the at least one functional processing unit comprises at least two functional processing units; and The logic circuit is configured to provide a subset of the set of pre-stored instructions in parallel to the at least two functional processing units using the sequence information and the at least two shift registers.

12. The processor of claim 1, wherein: The logic circuit includes at least two multiplexers, and the at least two multiplexers are controlled by at least two shift registers in a one-to-one correspondence; The at least one functional processing unit includes at least two different functional blocks, the at least two different functional blocks are selected from: a load block, a data type conversion block, an arithmetic logic unit block, a floating point math block, a rounding block, and a storage block; The logic circuit is configured to load sequence information from the instruction into the at least two shift registers; The sequence information is the configuration information; and The logic circuit is configured to use the sequence information in the at least two shift registers to provide a subset of the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit through the at least two multiplexers.

13. The processor of claim 12, wherein: The at least two shift registers are configured to shift upon receiving a processor instruction fetch command; and The logic circuit is configured to provide a subset of the set of pre-staged instructions in parallel to the at least two different functional blocks using the at least two multiplexers and the sequence information.

14. The processor of claim 1, wherein: The at least one functional processing unit includes a loading block and at least one different functional block; and The instruction is a load instruction having dedicated space for additional sequence information to define how to execute the pre-staged instructions of the subset of the set of pre-staged instructions.

15. The processor of claim 1, wherein: The processor has a single instruction multiple data architecture; The at least one functional processing unit comprises at least two functional processing units; and The logic circuit is configured to synchronously provide pre-staged instructions from the set of pre-staged instructions to the at least two functional processing units.

16. A method for providing a variable length instruction set, wherein each step is performed by a processor, comprising: storing instructions in an instruction memory; loading a set of pre-staged instructions from the instruction memory to a set of instruction registers using a bus, the set of pre-staged instructions being pre-loaded into the set of instruction registers for later accelerated application to at least one functional processing unit; receiving instructions at a logic circuit; as well as The logic circuit detects a trigger operation code in the instruction and in response provides a subset of the set of pre-staged instructions from the set of instruction registers to at least one functional processing unit; The instructions include configuration information, and the configuration information is used to select multiple component instructions from the set of pre-stored instructions and sort the multiple component instructions. The subset formed by the multiple component instructions is of variable length, and the length of the subset depends on the configuration information.

17. The method for providing a variable length instruction set according to claim 16, further comprising: Using the logic circuit, loading sequence information from the instruction into a shift register of the logic circuit; wherein the sequence information is the configuration information; controlling a multiplexer using said sequence information from said shift register; and A subset of the set of pre-staged instructions is provided from the set of instruction registers to the at least one functional processing unit via the multiplexer.

18. The method for providing a variable length instruction set according to claim 17, further comprising: receiving a processor instruction fetch command; and The shift register is caused to shift upon receiving the processor instruction fetch command.

19. The method for providing a variable length instruction set according to claim 16, wherein: The at least one functional processing unit comprises at least two functional processing units; and Providing a subset of the set of pre-staged instructions from the set of instruction registers includes providing the instructions to the at least two functional processing units in parallel.

20. The method for providing a variable length instruction set according to claim 16, wherein: The at least one functional processing unit includes a loading block and at least one different functional block; and The instruction is a load instruction having dedicated space for additional sequence information to define how the pre-staged instruction is to be executed.

21. A processor, comprising: Instruction memory; at least one functional processing unit; bus; a set of instruction registers; means for loading a set of pre-staged instructions into the set of instruction registers using the bus, the set of pre-staged instructions being pre-loaded into the set of instruction registers for later accelerated application to the at least one functional processing unit; as well as means for receiving instructions from said instruction memory, detecting a trigger operation code in said instructions, and in response providing a subset of said set of pre-staged instructions from said set of instruction registers to said at least one functional processing unit; The instructions include configuration information, and the configuration information is used to select multiple component instructions from the set of pre-stored instructions and sort the multiple component instructions. The subset formed by the multiple component instructions is of variable length, and the length of the subset depends on the configuration information.

Images