Dual-channel serial bus switching system and method based on single-pole double-throw analog switch

Abstract

The present invention discloses a dual-channel serial bus switching system and method. The system includes a master device, a first single-pole double-throw analog switch, a second single-pole double-throw analog switch, a first serial bus, a second serial bus, and a slave device. When switching the first serial bus, the master device controls the two single-pole double-throw analog switches to switch simultaneously, causing the first single-pole double-throw analog switch to output the clock signal of the first serial bus to the slave device, and the second single-pole double-throw analog switch to output the data signal of the first serial bus to the slave device. When switching the second serial bus, the master device controls the two single-pole double-throw analog switches to switch simultaneously, causing the first single-pole double-throw analog switch to output the clock signal of the second serial bus to the slave device, and the second single-pole double-throw analog switch to output the data signal of the second serial bus to the slave device. The present invention can achieve serial bus switching without using a dedicated bus switching chip or designing logic driver code.

Description

Technical Field

[0001] The present invention relates to the field of bus technology, and in particular to a dual-channel serial bus switching system based on a single-pole double-throw analog switch and a method for implementing dual-channel serial bus switching by the dual-channel serial bus switching system. Background Art

[0002] With the development of modern electronic circuit systems, the functions they support have become increasingly diverse. With the advancement of integrated circuits, more and more electronic circuit systems have adopted modular designs, separating the functional modules from the management modules, which are connected via connectors. The ability to support a growing number of functions relies on the addition of sensors and special function components to the functional modules. These sensors and special function components are typically managed via a low-speed serial bus, which includes data and clock signal lines. The device that manages these sensors and special function components is called a master, while the sensors and special function components are called slaves.

[0003] When the master device supports two types of serial buses, the communication protocols followed by the two serial buses are different, and the connector has only one serial communication interface output. Therefore, it is necessary to switch the serial bus according to the device mounted on the functional module so that the master device can manage the corresponding device. For example, if the master device supports I 2 C bus and SMBus bus, the master device is mounted according to the serial interface of the functional module 2 C device or SMBus device to flexibly switch I 2 C bus or SMBus bus.

[0004] Currently, when switching serial buses, a bus selection control chip is typically used to implement bus switching. For example, a 2:1 bus expansion multiplexer is used to implement bus switching. Its input interface is connected to two serial buses (respectively designated as Bus 1 and Bus 2) derived from a master device, and its control interface is connected to the master device, which can control it to perform bus switching. When the control interface is at a low level, the output bus is equivalent to a direct connection to Bus 1. When the control interface is at a high level, the output bus is equivalent to a direct connection to Bus 2, thereby achieving bus switching. However, although bus selection control chips can achieve bus switching, they are expensive and unsuitable for large-scale use in some simple electronic circuit systems.

[0005] In addition, some systems use programmable logic devices (PLDs) to implement bus switching. Because PLDs have multiple flexible IO interfaces, they can be flexibly configured according to specific needs. When multiple serial buses are connected to a PLD, internal logic code is designed to select one of the two or more input channels as the primary control bus. Compared to proprietary bus selection chips, PLDs offer flexible bus selection. For example, when the control interface of a proprietary bus selection chip is pulled low, only one of the two input buses is fixedly selected. However, with PLDs, by modifying the logic code, any input bus can be selected as the primary control bus based on the state of the external control signal. For example, if the external control interface signal is low, bus 1 is selected by default. By re-downloading the modified logic code, bus 2 can be selected by default when the control interface signal is low. This allows for flexible design based on different application scenarios without changing the hardware. However, while using PLDs to implement dual-bus channel switching is flexible and easy to use, it requires the design of logic driver code, which increases the complexity of the system design. Furthermore, the reliability of the logic code can affect the stability of the entire system. Summary of the Invention

[0006] The purpose of the present invention is to provide a dual-channel serial bus switching system that can realize bus switching without using a dedicated bus switching chip and designing logic driving code. At the same time, it also provides a method for the dual-channel serial bus switching system to realize dual-channel serial bus switching.

[0007] To achieve the above object, the present invention proposes a dual serial bus switching system based on a single-pole double-throw analog switch, the dual serial bus switching system comprising:

[0008] A first single-pole double-throw analog switch is used for switching a clock signal;

[0009] A second single-pole double-throw analog switch is used for switching data signals;

[0010] The first serial bus and the second serial bus each include a clock signal line and a data signal line;

[0011] a master device connected to an input end of a first single-pole double-throw analog switch via clock signal lines of a first serial bus and a second serial bus, respectively, and connected to an input end of a second single-pole double-throw analog switch via data signal lines of the first serial bus and the second serial bus, respectively, and configured to control the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch simultaneously when switching the first serial bus, so that the first single-pole double-throw analog switch outputs the clock signal of the first serial bus and the second single-pole double-throw analog switch outputs the data signal of the first serial bus; and to control the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch simultaneously when switching the second serial bus, so that the first single-pole double-throw analog switch outputs the clock signal of the second serial bus and the second single-pole double-throw analog switch outputs the data signal of the second serial bus;

[0012] The slave device is connected to the output ends of the first single-pole double-throw analog switch and the output end of the second single-pole double-throw analog switch respectively.

[0013] Preferably, the first single-pole double-throw analog switch and the second single-pole double-throw analog switch each include a first input interface, a second input interface, and an output interface; the master device is connected to the first input interface of the first single-pole double-throw analog switch via a clock signal line of a first serial bus, is connected to the first input interface of the second single-pole double-throw analog switch via a data signal line, is connected to the second input interface of the first single-pole double-throw analog switch via a clock signal line of a second serial bus, and is connected to the second input interface of the second single-pole double-throw analog switch via a data signal line.

[0014] Preferably, the main device has a control signal output interface, the first single-pole double-throw analog switch and the second single-pole double-throw analog switch both have a control signal input interface, and the control signal input interfaces of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch are both connected to the control signal output interface of the main device.

[0015] Preferably, the first serial bus and the second serial bus can both be selected from I 2 C. One of SMBus and CAN buses.

[0016] Preferably, the main device is a CPU.

[0017] The present invention also discloses a dual-channel serial bus switching method, which includes the following steps:

[0018] When switching the first serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to simultaneously switch signals, the first single-pole double-throw analog switch outputs the clock signal of the first serial bus, and the second single-pole double-throw analog switch outputs the data signal of the first serial bus;

[0019] When switching the second serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch signals simultaneously. The first single-pole double-throw analog switch outputs the clock signal of the second serial bus, and the second single-pole double-throw analog switch outputs the data signal of the second serial bus.

[0020] Preferably, the clock signal line and the data signal line of the first serial bus are respectively connected to the first input interface of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch, and the clock signal line and the data signal line of the second serial bus are respectively connected to the second input interface of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch.

[0021] Preferably, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to perform signal switching simultaneously through the same control signal.

[0022] Preferably, the first serial bus and the second serial bus can both be selected from I 2 C. One of SMBus and CAN buses.

[0023] Preferably, the main device is a CPU.

[0024] The beneficial effects of the present invention are:

[0025] The present invention uses a single-pole, double-throw (SPDT) analog switch to switch serial buses, eliminating the need for a dedicated bus switching chip and logic driver code. This simplifies the hardware design of a two-wire bus switching system and reduces hardware design costs. Furthermore, due to the low latency and fast switching characteristics of the SPDT analog switch, the synchronization of clock and data signals is not affected during serial bus switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural block diagram of a dual serial bus switching system according to an embodiment of the present invention;

[0027] Figure 2 FIG. 1 is a schematic diagram of a dual serial bus switching method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention.

[0029] The present invention discloses a dual-channel serial bus switching system based on a single-pole double-throw analog switch, which can realize bus switching without using a dedicated bus switching chip or designing a logic drive code.

[0030] like Figure 1Figure 1 shows a dual serial bus switching system based on a single-pole double-throw analog switch according to an embodiment of the present invention. The system includes a first serial bus, a second serial bus, a first single-pole double-throw analog switch, a second single-pole double-throw analog switch, a master device, and a slave device. Specifically, the first serial bus and the second serial bus are both used for information transmission and include clock signal lines and data signal lines. The data signal lines are used for data transmission, and the clock signal lines are used to control the data signal lines for data transmission.

[0031] The first single-pole double-throw analog switch (SPDT) and the second single-pole double-throw analog switch (SDPT) are used for signal switching, and both have a first input interface (CH1), a second input interface (CH2), a control signal input interface (CTR) and an output interface (OUT). The first single-pole double-throw analog switch is used for switching clock signals, and the second single-pole double-throw analog switch is used for switching data signals.

[0032] The master device is used to manage slave devices through a serial bus and control switching between buses. It has a first serial bus interface (Bus1), a second serial bus interface (Bus2) and a control signal output interface (GPIO). The first serial bus interface of the master device is connected to the first single-pole double-throw analog switch and the second single-pole double-throw analog switch respectively through the first serial bus, and the second serial bus interface is connected to the first single-pole double-throw analog switch and the second single-pole double-throw analog switch respectively through the second serial bus. The control signal output interface (GPIO) is connected to the first single-pole double-throw analog switch and the second single-pole double-throw analog switch respectively, that is, the first serial bus interface is connected to the first input interface of the first single-pole double-throw analog switch through the clock signal line of the first serial bus, and the data signal line is connected to the first input interface of the second single-pole double-throw analog switch. The second serial bus interface is connected to the second input interface of the first single-pole double-throw analog switch through the clock signal line of the second serial bus, and the data signal line is connected to the second input interface of the second single-pole double-throw analog switch. The control signal output interface is connected to the control signal input interface of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch respectively.

[0033] The slave device is connected to the first single-pole double-throw analog switch and the output interface of the first single-pole double-throw analog switch respectively.

[0034] During implementation, when switching the first serial bus, the master device inputs the first bus switching signal to both the first single-pole double-throw analog switch and the second single-pole double-throw analog switch via the control signal output interface. After the first single-pole double-throw analog switch receives the first bus switching signal via its control signal input interface, the first single-pole double-throw analog switch switches the clock signal, causing it to output the clock signal of the first serial bus. Simultaneously, after the second single-pole double-throw analog switch receives the first bus switching signal via its control signal input interface, the second single-pole double-throw analog switch switches the data signal, causing it to externally output the data signal of the first serial bus, thereby switching the output bus to the first serial bus.

[0035] When switching the second serial bus, the master device inputs the second bus switching signal to both the first single-pole double-throw analog switch and the second single-pole double-throw analog switch via the control signal output interface. After the first single-pole double-throw analog switch receives the second bus switching signal via its control signal input interface, the first single-pole double-throw analog switch switches the clock signal, thereby outputting the clock signal of the second serial bus to the outside. Simultaneously, after the second single-pole double-throw analog switch receives the second bus switching signal via its control signal input interface, the second single-pole double-throw analog switch switches the data signal, thereby outputting the data signal of the second serial bus to the outside. This completes the switching of the output bus to the second serial bus.

[0036] In this embodiment, the control signal input interfaces of the first SPDT analog switch and the second SPDT analog switch are respectively connected to the control signal output interface of the master device. That is, the first SPDT analog switch and the second SPDT analog switch are controlled by the same control signal. The master device can control the first SPDT analog switch and the second SPDT analog switch to switch signals simultaneously, thereby ensuring the timing of the serial bus. Of course, in other embodiments, the control signal input interfaces of the first SPDT analog switch and the second SPDT analog switch can be respectively connected to different control signal output interfaces on the master device, but the master device must be able to control the first SPDT analog switch and the second SPDT analog switch to switch signals simultaneously.

[0037] Furthermore, in this embodiment, the first serial bus can be selected from I 2 The second serial bus may be selected from one of I2C (Inter-Integrated Circuit), SMBus (System Management Bus), and CAN (Controller Area Network). Similarly, the second serial bus may also be selected from one of I2C, SMBus, and CAN. The selection may be made according to actual needs during implementation.

[0038] Furthermore, in this embodiment, the master device is preferably a CPU. Of course, in other embodiments, other chips or modules that can manage and support the serial bus can also be selected.

[0039] like Figure 2 As shown, the present invention also discloses a method for implementing dual serial bus switching by the dual serial bus switching system, comprising the following steps:

[0040] When switching the first serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to simultaneously switch signals, the first single-pole double-throw analog switch outputs the clock signal of the first serial bus, and the second single-pole double-throw analog switch outputs the data signal of the first serial bus;

[0041] When switching the second serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch signals simultaneously. The first single-pole double-throw analog switch outputs the clock signal of the second serial bus, and the second single-pole double-throw analog switch outputs the data signal of the second serial bus.

[0042] Specifically, when the dual-channel serial bus switching system switches the first serial bus, the master device inputs the first bus switching signal to both the first single-pole double-throw analog switch and the second single-pole double-throw analog switch via the control signal output interface. After the first single-pole double-throw analog switch receives the first bus switching signal via its control signal input interface, the first single-pole double-throw analog switch switches the clock signal, thereby outputting the clock signal of the first serial bus. Simultaneously, after the second single-pole double-throw analog switch receives the first bus switching signal via its control signal input interface, the second single-pole double-throw analog switch switches the data signal, thereby outputting the data signal of the first serial bus to the outside world. This achieves the switching of the output bus to the first serial bus.

[0043] When the dual-channel serial bus switching system switches the second serial bus, the master device inputs the second bus switching signal to both the first single-pole double-throw analog switch and the second single-pole double-throw analog switch via the control signal output interface. After the first single-pole double-throw analog switch receives the second bus switching signal via its control signal input interface, it switches the clock signal, thereby outputting the clock signal of the second serial bus to the outside. Simultaneously, after the second single-pole double-throw analog switch receives the second bus switching signal via its control signal input interface, it switches the data signal, thereby outputting the data signal of the second serial bus to the outside. This completes the switching of the output bus to the second serial bus.

[0044] The present invention uses a single-pole, double-throw (SPDT) analog switch to switch serial buses, eliminating the need for a dedicated bus switching chip and logic driver code. This simplifies the hardware design of a two-wire bus switching system and reduces hardware design costs. Furthermore, due to the low latency and fast switching characteristics of the SPDT analog switch, the synchronization of clock and data signals is not affected during serial bus switching.

[0045] The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and are covered by the claims of this patent application.

Claims

1. A dual serial bus switching system based on a single-pole double-throw analog switch, characterized in that: The dual serial bus switching system includes: A first single-pole double-throw analog switch is used for switching a clock signal; A second single-pole double-throw analog switch is used for switching data signals; The first serial bus and the second serial bus each include a clock signal line and a data signal line; a master device connected to an input end of a first single-pole double-throw analog switch via clock signal lines of a first serial bus and a second serial bus, respectively, and connected to an input end of a second single-pole double-throw analog switch via data signal lines of the first serial bus and the second serial bus, respectively, and configured to control the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch simultaneously when switching the first serial bus, so that the first single-pole double-throw analog switch outputs the clock signal of the first serial bus and the second single-pole double-throw analog switch outputs the data signal of the first serial bus; and to control the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch simultaneously when switching the second serial bus, so that the first single-pole double-throw analog switch outputs the clock signal of the second serial bus and the second single-pole double-throw analog switch outputs the data signal of the second serial bus; The slave device is connected to the output ends of the first single-pole double-throw analog switch and the output end of the second single-pole double-throw analog switch respectively.

2. The dual serial bus switching system according to claim 1, wherein: The first single-pole double-throw analog switch and the second single-pole double-throw analog switch each include a first input interface, a second input interface, and an output interface; the master device is connected to the first input interface of the first single-pole double-throw analog switch via a clock signal line of a first serial bus, is connected to the first input interface of the second single-pole double-throw analog switch via a data signal line, is connected to the second input interface of the first single-pole double-throw analog switch via a clock signal line of a second serial bus, and is connected to the second input interface of the second single-pole double-throw analog switch via a data signal line.

3. The dual serial bus switching system according to claim 1, wherein: The master device has a control signal output interface, the first single-pole double-throw analog switch and the second single-pole double-throw analog switch both have a control signal input interface, and the control signal input interfaces of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch are both connected to the control signal output interface of the master device.

4. The dual serial bus switching system according to claim 1, wherein: The first serial bus and the second serial bus can both be selected from I 2 C. One of SMBus and CAN buses.

5. The dual serial bus switching system according to claim 1, wherein: The main device is a CPU.

6. A dual serial bus switching method based on the dual serial bus switching system according to claim 1, characterized in that: The dual serial bus switching method comprises the following steps: When switching the first serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to simultaneously switch signals, the first single-pole double-throw analog switch outputs the clock signal of the first serial bus, and the second single-pole double-throw analog switch outputs the data signal of the first serial bus; When switching the second serial bus, the master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch to switch signals simultaneously. The first single-pole double-throw analog switch outputs the clock signal of the second serial bus, and the second single-pole double-throw analog switch outputs the data signal of the second serial bus.

7. The dual serial bus switching method according to claim 6, wherein: The clock signal line and data signal line of the first serial bus are respectively connected to the first input interface of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch, and the clock signal line and data signal line of the second serial bus are respectively connected to the second input interface of the first single-pole double-throw analog switch and the second single-pole double-throw analog switch.

8. The dual serial bus switching method according to claim 6, wherein: The master device controls the first single-pole double-throw analog switch and the second single-pole double-throw analog switch through the same control signal to perform signal switching simultaneously.

9. The dual serial bus switching method according to claim 6, wherein: The first serial bus and the second serial bus can both be selected from I 2 C. One of SMBus and CAN buses.

10. The dual serial bus switching method according to claim 6, wherein: The main device is a CPU.

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