Processor of isomorphic dual computing system and operating method of isomorphic dual computing system

Abstract

A processor of a homogeneous dual computing system with trusted computing functionality. The processor includes a trusted core, a general core, and a shared cache. The trusted core has access to an isolated memory on a system memory. The general core is homogeneous with the trusted core and is prohibited from accessing the isolated memory. The shared cache is shared by the trusted core and the general core. In response to a cache flush instruction initiated by the general core, the trusted core initiates a second cache write back instruction different from a first cache write back instruction to cause isolated data in the shared cache related to the isolated memory to be written back to the isolated memory before being flushed.

Description

Technical Field

[0001] This invention relates to a trusted computing method. Background Technology

[0002] Trusted computing enhances computer security through hardware partitioning. For example, a computer's system memory can be partitioned into isolated memory areas, accessible only to authorized trusted platforms.

[0003] Ensuring the security of isolated data in isolated storage is an important issue in this technical field. Summary of the Invention

[0004] This invention provides a homogeneous dual-computing system, using two identical cores on the same processor to provide trusted computing and general computing. The core used for trusted computing is called the trusted core. The core used for general computing is called the general core. The shared cache (e.g., the lowest level cache LLC) of the general core and the trusted core may contain isolated data accessible only to the trusted core. This invention specifically proposes a protection scheme for the isolated data on the shared cache. In particular, this invention protects the isolated data on the cache system from being lost due to cache flushing operations of the general core.

[0005] A processor implemented according to one embodiment of the present invention includes a trusted core, a general core, and a shared cache. The trusted core has permission to access isolated memory on system memory. The general core is isomorphic to the trusted core and is prohibited from accessing the isolated memory. The shared cache is shared by the trusted core and the general core. In response to a cache refresh instruction initiated by the general core, the trusted core initiates a second cache write-back instruction, different from a first cache write-back instruction, causing the isolated data related to the isolated memory in the shared cache to be written back to the isolated memory before being refreshed. The first cache write-back instruction is not in response to the cache refresh instruction of the general core. The first cache write-back instruction is used to write all cache lines of the shared cache back to system memory.

[0006] In one implementation, according to the second cache write-back instruction, the shared cache polls all cache lines of the shared cache, compares the system memory address corresponding to each cache line, and determines whether it falls within the address range of the isolated memory, thereby determining the isolated data.

[0007] In one implementation, based on the cache refresh instruction, the general core acquires control of the processor and notifies the trusted core to initiate the second cache write-back instruction. After the trusted core completes the second cache write-back instruction, it notifies the general core that the isolated data in the shared cache has been written back to the isolated memory.

[0008] In one implementation, the general core notifies the trusted core via an internal interrupt to initiate the second cache write-back instruction. After completing the second cache write-back instruction, the trusted core issues an interrupt and synchronizes with the general core for isolated data write-back, indicating that the isolated data in the shared cache has been written back to the isolated memory. After the isolated data write-back synchronization, the general core instructs the trusted core to perform a first cache refresh synchronization. After the first cache refresh synchronization, the general core refreshes the shared cache. After refreshing the shared cache, the general core instructs the trusted core to perform a second cache refresh synchronization. After the second cache refresh synchronization, the general core and the trusted core each refresh their own internal cache. After the internal cache refresh, the general core and the trusted core perform a third cache refresh synchronization. After the third cache refresh synchronization, the general core notifies the chipset through a special cycle that the processor's cache system has been refreshed. After this special cycle, the general core relinquishes control of the processor.

[0009] Based on the foregoing concept, the present invention also provides an embodiment of a homogeneous dual computing system operation method, comprising: planning multiple cores of a processor, granting a trusted core permission to access isolated memory on the system memory, and prohibiting a general core homogeneous with the trusted core from accessing the isolated memory, wherein the trusted core and the general core share a shared cache; and responding to a cache refresh instruction initiated by the general core, causing the trusted core to initiate a second cache write-back instruction different from the first cache write-back instruction, so that the isolated data related to the isolated memory in the shared cache is written back to the isolated memory before being refreshed.

[0010] The following detailed description of the invention is illustrated with specific examples and accompanying drawings. Attached Figure Description

[0011] Figure 1 Illustrated explanation of the concept of isolated memory;

[0012] Figure 2A According to one embodiment of the present invention, a homogeneous dual computing system implemented with a single-chip processor is illustrated.

[0013] Figure 2B According to one embodiment of the present invention, a homogeneous dual-computing system implemented with a dual-chip processor is illustrated.

[0014] Figure 3 According to one embodiment of the present invention, the actions of each core after a general core initiates the cache refresh instruction INVD are illustrated.

[0015] Figure 4 According to one embodiment of the present invention, the hardware of processor 400 is illustrated, showing how the cache refresh instruction INVD initiated by a general core 402 operates; and

[0016] Figure 5 The flowchart illustrates, according to one embodiment of the present invention, how the trusted core 406 initiates and executes the second cache write-back refresh instruction WBINVD_S. Detailed Implementation

[0017] The following description illustrates various embodiments of the present invention. This description introduces the basic concepts of the invention and is not intended to limit its scope. The actual scope of the invention should be defined in accordance with the claims.

[0018] Figure 1 This diagram illustrates the concept of isolated memory. A computer 100 with trusted computing capabilities includes multiple normal cores 102_1 to 102_N, a trusted core 104, and system memory (such as dynamic random access memory DRAM, etc.) 106, and is correspondingly designed with a trusted basic input / output system (trusted BIOS) 108 and trusted firmware 110. One of the normal cores 102_1…102_N can act as a bootstrap processor (BSP) to load and run the host operating system 112. The trusted core 104 runs the trusted operating system 114. The system memory 106 is partitioned, including isolated memory 116, shared memory 118, and other memory 120. As shown in the diagram, isolated data in the isolated memory 116 is only accessible to the trusted operating system 114, and is specifically prohibited from being accessed by the host operating system 112. The general cores 102_1 to 102_N running the main operating system 112 and the trusted core 104 can communicate via shared memory 118. Other memory 120 is used by the general cores 102_1 to 102_N for internal operations. The trusted core 104 can also use (e.g., read-only) other memory 120 when performing internal operations.

[0019] In particular, the general cores 102_1…102_N and the trusted core 104 in this invention are multiple cores provided by the same processor. The computer system constructed in this way is called a homogeneous dual-computing system; the trusted core 104 has the same architecture as the general cores 102_1…102_N. The homogeneous dual-computing system is characterized by the trusted core and the general core sharing a cache. The shared cache may simultaneously store isolated data and general non-isolated data. How to manage the shared cache is an important issue.

[0020] The processor can be a single-die processor; the trusted core 104 and the general cores 102_1…102_N are fabricated on the same chip. Generally, the core with the highest core number in the single chip is the trusted core 104 by default, but the manufacturer can also choose the trusted core 104 according to its needs.

[0021] Figure 2A This invention illustrates a homogeneous dual-computing system implemented with a single-chip processor according to one embodiment of the present invention. The single-chip processor 202 has multiple cores, core0 to coreN. Each core (core0 to coreN) has its own in-core cache (including a first-level cache L1 and a second-level cache PL2), and shares a last-level cache LLC. They access system memory 106 through a Host Interconnect Fabric (HIF) structure. Core N is selected as the trusted core 104, running trusted firmware 110. The remaining cores, core0 to core N-1, are the aforementioned multiple general cores 102_# (# being a number), with core0 being the master core (BSP), running a trusted basic input / output system 108. The last-level cache LLC is the shared cache between the general cores core0…core N-1 and the trusted core 104.

[0022] In system memory 106, the isolated data stored in isolation memory 116 may be cached in the lowest level cache LLC, allowing only trusted cores implemented by core N to access it, but may be flushed by cache refresh instructions (INVD instructions) initiated by general cores core0…core N-1. This invention specifically proposes a solution to this phenomenon.

[0023] In another implementation, the processor is a multi-chip processor. Each chip has multiple cores. Each chip has a temporarily planned on-chip trusted core and an on-chip master core (BSP) to securely link between sockets and dies. Once the chip links are established, all chips uniformly provide the system trusted core and the system master core, which are securely loaded and run the trusted operating system 114 and the master operating system 112, respectively. Generally, the core with the highest number among the highest-numbered chips is selected as the system trusted core, but the manufacturer can also select the system trusted core according to customer needs. The system trusted core and the system master core may be provided by different chips.

[0024] Figure 2BThis invention illustrates a homogeneous dual-computing system implemented with a dual-chip processor according to one embodiment. The dual chips 212 and 214 implementing the processor each have multiple cores, core0 to coreN. Before linking, chip 212 must be initialized independently of chip 214. Chip 212 temporarily uses coreN as the trusted on-chip core, running trusted firmware 110, and temporarily uses core0 as the master on-chip core (BSP), running trusted basic input / output system 108, establishing a slot / chip link. Similarly, chip 214 temporarily uses coreN as the trusted on-chip core, running trusted firmware 110, and temporarily uses core0 as the master on-chip core (BSP), running trusted basic input / output system 108, establishing a slot / chip link. In this way, the link between chips 212 and 214 is established. After linking, core0 on chip 212 is selected as the system master core, and coreN on chip 214 is selected as the system trusted core, loading the main operating system and the trusted operating system, respectively. On chip 214, the lowest level cache LLC is a shared cache between the general cores core0...coreN-1 and the system trusted core coreN.

[0025] In system memory 106, the isolated data stored in isolation memory 116 may be cached in the last-level cache LLC on chip 214, accessible only to the trusted system core implemented by core N of chip 214, but may be cleared by cache refresh instructions (INVD instructions) initiated by the general cores core0...coreN-1 of chip 214. This invention specifically proposes a solution to this phenomenon.

[0026] Compared to the first cache write-back instruction used in general techniques, this invention proposes a second cache write-back instruction. The first cache write-back instruction is typically denoted as WBINVD, which writes all cache data back to system memory and then flushes the cache (i.e., invalidates all data in the system cache). The second cache write-back instruction proposed in this invention will be labeled WBINVD_S. A general core sharing a cache with the trusted core may issue a cache refresh instruction INVD; this invention instructs the trusted core to initiate the second cache write-back instruction WBINVD_S before responding to such a cache refresh instruction INVD, first writing the isolated cache data back to the isolated memory to prevent the isolated data from being flushed before being written back and thus lost.

[0027] Figure 3 According to one embodiment of the present invention, the actions of each core after a general core initiates the cache refresh instruction INVD are illustrated. The rightmost column of the illustration represents the actions of the trusted core, and the columns to its left correspond to a general core that initiated INVD and a general core that did not initiate INVD, all of which share the cache with the trusted core.

[0028] In step S302, the general core that initiated the cache refresh instruction INVD acquires ownership; this core is referred to as the controlling core. Some resources within the processor are shared by multiple cores. Each core must acquire ownership before accessing these shared resources to prevent errors caused by multiple cores accessing them simultaneously. For example, if two cores are writing to a shared resource at the same time, the core with ownership can write to the shared resource first. For instance, the instruction "request for ownership" can make the cache exclusive to that core.

[0029] In step S304, the master core sends an internal interrupt, which is received by other cores.

[0030] In step S306, after receiving the internal interrupt from the master core, the trusted core initiates and executes the second cache write-back instruction WBINVD_S taught in this invention. The cached isolated data is written back to the isolated memory on the system memory, preventing the isolated data from being erased and lost before being written back to the isolated memory.

[0031] In step S308, the trusted core synchronizes with the general cores sharing the cache, indicating that the second cache write-back instruction WBINVD_S has been completed. This is called isolation data write-back synchronization. Each core then knows that the isolation data has been safely written back to the isolation memory.

[0032] In step S310, all cores perform the first synchronization of cache refresh to ensure that all cores are ready to perform cache refresh.

[0033] In step S312, the master core refreshes the shared cache (e.g., the lowest level cache LLC), invalidating the cache lines directly. Other general cores and trusted cores then skip to the next synchronization procedure.

[0034] Step S314: All cores perform a second synchronization of cache refresh, indicating that the cache refresh of the shared cache (LLC) is complete.

[0035] In step S316, all cores refresh their own kernel cache.

[0036] Step S318: All cores perform a third synchronization of cache refresh, indicating that the cache in all cores has been refreshed.

[0037] In step S320, the main control core informs the chipset that the refresh of the entire cache system (including the shared cache LLC and the internal cache of each core) has ended through a special cycle.

[0038] Step S322: The master core relinquishes control. For example, the cache is deactivated from its dedicated state.

[0039] Figure 3 The technology ensures that isolated data in a cache system will not be lost when a general core in the shared cache initiates a cache refresh instruction.

[0040] Figure 4 This invention illustrates the hardware of a processor 400 according to one embodiment of the present invention, showing how the cache refresh instruction INVD initiated by a general core 402 operates. The illustration only simply shows one general core. In actual implementation (e.g.) Figure 2A , Figure 2B The processor may have more than two cores, or it may be a multi-chip solution providing multiple cores. As described in Figures 2A and 2B, after power-on and connection establishment, the entire system will have only one trusted core (called the system trusted core), and the rest will be general cores. Figure 4 The simplified version only identifies a trusted core and a general core.

[0041] The cache refresh instruction INVD initiated by core 402 is decoded by decoder 404, triggering an internal interrupt and notifying trusted core 406. Upon receiving the interrupt, trusted core 406 initiates a second cache write-back instruction WBINVD_S. This second cache write-back instruction WBINVD_S is decoded by decoder 408, and then polls the cache lines in the lowest-level cache 414 via the memory order buffer (MOB) 410 and the core cache 412. Specifically, the polling of the lowest-level cache 414 in response to the second cache write-back instruction WBINVD_S is to locate the isolated data 420 associated with the isolated memory 418 of system memory 416.

[0042] In one implementation, the system memory address corresponding to the cache line is compared to see if it falls within the address range of the isolated memory 418. The found isolated data 420 is written back to the isolated memory 418 on the system memory 416. After the trusted core 406 completes the write-back of the isolated data 420, it can issue an interrupt to synchronize the general core 402 with the trusted core 406. The general core 402 can then continue the cache refresh operation. The general core 402 can refresh the last-level cache 414 through the memory sorted cache (MOB) 422 and the core cache 424, making the cache contents therein completely invalid. Then, the general core 402 and the trusted core 406 can each refresh the core cache 424 and 412, respectively, making the cache contents therein completely invalid. The general core 402 can notify the chipset 426 at a special period that the cache refresh is complete.

[0043] Figure 5 The flowchart illustrates, according to one embodiment of the present invention, how the trusted core 406 initiates and executes the second cache write-back refresh instruction WBINVD_S.

[0044] In step S502, the trusted core 406 receives an internal interrupt triggered by the corresponding cache refresh instruction INVD from another core (the general core 402 that shares a cache with the trusted core).

[0045] In step S504, the trusted core 406 initiates and decodes the second cache write-back refresh instruction WBINVD_S. Then, the shared cache (414) polls all its cache lines in the second cache write-back refresh instruction WBINVD_S executed by the trusted core 406.

[0046] In step S506, the shared cache (414) polls its own cache lines to determine whether the currently inspected cache line belongs to the isolated data related to the isolated memory 418 on the system memory 416 (address determination may be used). If not, the shared cache (414) determines in step S508 whether the polling of the shared cache (414) has ended. If there are still cache lines that have not been confirmed, the process returns to step S506. If all cache lines of the shared cache (414) have been confirmed, the trusted core 406 initiates the isolated data write-back synchronization in step S510, notifying the general core 402 that the second cache write-back refresh instruction WBINVD_S has been completed.

[0047] If step S506 determines that the currently inspected cache line belongs to the isolated data related to the isolated memory 418 on the system memory 416, the trusted core 406 writes the isolated data (e.g., 420) back to the isolated memory 418 in step S512. Next, the shared cache (414) determines in step S514 whether the polling of the shared cache 414 has ended. If there are still unacknowledged cache lines, the process returns to step S506. If all cache lines in the shared cache 414 have been acknowledged, the trusted core 406 initiates the isolated data write-back synchronization in step S510, notifying the general core 402 that the second cache write-back refresh instruction WBINVD_S has been completed.

[0048] Compared to the second cache write-back and refresh instruction WBINVD_S of this invention, the first cache write-back and refresh instruction WBINVD, spontaneously generated by the trusted core 406, writes all cache contents back before refreshing the cache system. Data outside of isolated data 420 in the shared cache 414 is also included in the write-back.

[0049] In one implementation, the trusted core 406 is a newly added identifier that distinguishes between the first cache write-back refresh instruction WBINVD generated spontaneously and the second cache write-back refresh instruction WBINVD_S generated by the corresponding INVD interrupt of other cores.

[0050] Generally, core 402 provides microcode for the cache refresh instruction INVD. It needs to have the ability to issue an interrupt to trusted core 406, causing trusted core 406 to initiate the second cache write-back refresh instruction WBINVD_S.

[0051] The trusted core 406 also needs to design microcode for the second cache write-back refresh instruction WBINVD_S to implement the write-back of isolated data 420 in the shared cache 414.

[0052] The above concepts can also realize a homogeneous dual computing system operation method, including: planning multiple cores of a processor, giving a trusted core the right to access an isolated memory on a system memory, and prohibiting a general core that is homogeneous with the trusted core from accessing the isolated memory, wherein the trusted core and the general core share a shared cache; and responding to a cache refresh instruction initiated by the general core, causing the trusted core to initiate a second cache write-back instruction different from a first cache write-back instruction, so that the isolated data related to the isolated memory in the shared cache is written back to the isolated memory before being refreshed.

[0053] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0054] [Symbol Explanation]

[0055] 100: Calculator

[0056] 102_1…_N、402: General core

[0057] 104, 406: Trusted Cores

[0058] 106, 416: System memory

[0059] 108: Trusted Basic Input / Output System

[0060] 110: Trusted Firmware

[0061] 112: Main Operating System

[0062] 114: Trusted Operating System

[0063] 116, 418: Isolated memory

[0064] 118: Shared Memory

[0065] 120: Other memory

[0066] 202: Single Chip

[0067] 212, 214: Chips

[0068] 400: Processor

[0069] 404, 408: Decoder

[0070] 410, 422: Memory sorting cache

[0071] 412, 424: In-core cache

[0072] 414. LLC: Lowest Level Cache

[0073] 420: Isolation Data

[0074] 426: Chipset

[0075] core0…coreN: Cores

[0076] INVD: Cache refresh instruction

[0077] L1: Level 1 cache

[0078] PL2: Level 2 cache

[0079] S302…S322、S502…S510: Steps

[0080] WBINVD_S: Second cache write-back instruction

[0081] [Biomaterial Storage]

[0082] none

Claims

1. A processor for establishing a homogeneous dual-computing system, comprising: A trusted kernel has the authority to access an isolated memory above the system memory; A regular core, isomorphic to this trusted core, is prohibited from accessing the isolated memory; as well as A shared cache is shared by the trusted core and the general core; in: In response to the cache refresh instruction initiated by the general core, the trusted core initiates a second cache write-back instruction, different from the first cache write-back instruction, so that the isolated data related to the isolated memory in the shared cache is written back to the isolated memory before being refreshed, and data other than the isolated data is written back; and The first cache write-back instruction is not in response to the cache refresh instruction of the general core, and the first cache write-back instruction is used to write all cache lines of the shared cache back to system memory. According to the cache refresh instruction, the general core takes control of the processor and notifies the trusted core to initiate the second cache write-back instruction; as well as After the trusted core completes the second cache write-back instruction, it notifies the general core that the isolated data in the shared cache has been written back to the isolated memory.

2. The processor of claim 1, wherein: According to the second cache write-back instruction, the shared cache polls the shared cache, compares the system memory address corresponding to each cache line, and determines whether it falls within the address range of the isolated memory, thereby determining the isolated data.

3. The processor of claim 1, wherein: This general core includes the first core's internal cache; This trusted core includes a second in-core cache; as well as When the cache refresh instruction is executed, the refresh of the shared cache by the general core occurs earlier than the refresh of the cache within the first core and the cache within the second core.

4. The processor of claim 1, wherein: The general core notifies the trusted core to initiate the second cache write-back instruction via an internal interrupt; After the trusted core completes the second cache write-back instruction, it issues an interrupt to synchronize with the general core for an isolated data write-back, indicating that the isolated data in the shared cache has been written back to the isolated memory. After the isolated data is written back and synchronized, the general core instructs the trusted core to perform the first synchronization of cache refresh together; as well as After the first synchronization of the cache refresh, the general core refreshes the shared cache.

5. The processor of claim 4, wherein: After the general core refreshes the shared cache, the trusted core performs a second synchronization cache refresh; and After the cache is refreshed in the second synchronization, the general core refreshes its own cache in the first core, and the trusted core refreshes its own cache in the second core.

6. The processor of claim 5, wherein: After the general core refreshes the cache within the first core and the trusted core refreshes the cache within the second core, the general core and the trusted core perform a third synchronization of cache refresh, indicating that the cache within the first core and the cache within the second core have been refreshed.

7. The processor of claim 6, wherein: After the cache is refreshed in the third synchronization, the general core notifies a chipset, through a special cycle, that a cache system including the shared cache, the first core cache, and the second core cache has completed the refresh.

8. The processor of claim 7, wherein: After this special cycle, the general core releases control of the processor.

9. A method for operating a homogeneous dual computing system, comprising: A processor is configured with multiple cores, where a trusted core has access to isolated memory on system memory, while general cores isomorphic to the trusted core are prohibited from accessing the isolated memory. The trusted core and the general cores share a shared cache. In response to a cache refresh instruction initiated by the general core, the trusted core initiates a second cache write-back instruction, different from a first cache write-back instruction. This ensures that the isolated data in the shared cache related to the isolated memory is written back to the isolated memory before being refreshed, while data other than the isolated data is written back. Specifically, the first cache write-back instruction is not in response to the cache refresh instruction of the general core, and the first cache write-back instruction is used to write all cache lines of the shared cache back to system memory. Based on the cache refresh instruction, the general core acquires control of the processor and notifies the trusted core to initiate the second cache write-back instruction; and After the trusted core completes the second cache write-back instruction, it notifies the general core that the isolated data in the shared cache has been written back to the isolated memory.

10. The method of operating a homogeneous dual computing system as claimed in claim 9, further comprising: According to the second cache write-back instruction, the shared cache is instructed to poll all cache lines of the shared cache, compare the system memory address corresponding to each cache line, and determine whether it falls within the address range of the isolated memory, thereby determining the isolated data.

11. The method of operating a homogeneous dual computing system as claimed in claim 9, wherein: The general core includes a first-core in-core cache; The trusted core includes a second in-core cache; as well as When the cache refresh instruction is executed, the refresh of the shared cache by the general core occurs earlier than the refresh of the cache within the first core and the cache within the second core.

12. The method of operating a homogeneous dual computing system as claimed in claim 9, wherein: The general core notifies the trusted core to initiate the second cache write-back instruction via an internal interrupt; After the trusted core completes the second cache write-back instruction, it issues an interrupt to synchronize with the general core for an isolated data write-back, indicating that the isolated data in the shared cache has been written back to the isolated memory. After the isolated data is written back and synchronized, the general core instructs the trusted core to perform the first synchronization of cache refresh together; as well as After the first synchronization of the cache refresh, the general core refreshes the shared cache.

13. The method of operating a homogeneous dual computing system as claimed in claim 12, wherein: After the general core refreshes the shared cache, the trusted core is instructed to perform a second synchronization of cache refresh. as well as After the cache is refreshed in the second synchronization, the general core refreshes its own cache in the first core, and the trusted core refreshes its own cache in the second core.

14. The method of operating a homogeneous dual computing system as claimed in claim 13, wherein: After the general core refreshes the cache within the first core and the trusted core refreshes the cache within the second core, the general core and the trusted core perform a third synchronization of cache refresh, indicating that the cache within the first core and the cache within the second core have been refreshed.

15. The method of operating a homogeneous dual computing system as claimed in claim 14, wherein: After the cache is refreshed in the third synchronization, the general core notifies a chipset, through a special cycle, that a cache system including the shared cache, the first core cache, and the second core cache has completed the refresh.

16. The method of operating a homogeneous dual computing system as claimed in claim 15, wherein: After this special cycle, the general core releases control of the processor.

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