Pixel Circuit and Its Driving Method

Abstract

An embodiment of the present invention discloses a pixel circuit and a driving method thereof. The pixel circuit includes: a data writing module, a storage module, a leakage current control module, and a driving transistor; the data writing module is configured to write a data voltage to the gate of the driving transistor during a data writing stage; the storage module is configured to store the gate voltage of the driving transistor; the leakage current control module is connected between a reset voltage terminal and a first terminal of the storage module, and a control signal is input to the control terminal of the leakage current control module. The leakage current control module is configured to control the magnitude of the leakage current between the first terminal of the storage module and the reset voltage terminal in response to the control signal during a light emitting stage, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module; the driving transistor is configured to generate a driving current in response to its own gate voltage to drive a light emitting device to emit light. This solution realizes a driving method combining digital driving and analog driving, which helps to reduce the driving difficulty while improving the display effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof. Background Art

[0002] With the continuous development of display technologies, display panels are increasingly widely used, and people's requirements for the performance of display panels are also getting higher and higher. The pixel circuit in a display panel is used to drive a light-emitting device to emit light for display. Currently, existing pixel circuits are difficult to be applicable to displays with high resolution and high refresh rate, and the generation method of the driving signal of the pixel circuit is relatively complex. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel circuit and a driving method thereof to improve the display effect and reduce the driving difficulty.

[0004] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a data writing module, a storage module, a leakage current control module, and a driving transistor;

[0005] The data writing module is configured to write a data voltage to the gate of the driving transistor during a data writing stage;

[0006] A first end of the storage module is connected to the gate of the driving transistor, and a second end is connected to a fixed voltage. The storage module is configured to store the gate voltage of the driving transistor;

[0007] The leakage current control module is connected between a reset voltage terminal and the first end of the storage module. A control terminal of the leakage current control module is connected to a control signal. The leakage current control module is configured to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal in response to the control signal during a light-emitting stage, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module;

[0008] The driving transistor is configured to generate a driving current in response to its own gate voltage to drive a light-emitting device to emit light.

[0009] Optionally, the leakage current control module includes at least two transistors connected in series between the reset voltage terminal and the first end of the storage module, and the channel width-to-length ratios of the at least two transistors are all different;

[0010] The gate of each of the at least two transistors serves as the control terminal of the leakage current control module and is connected to a corresponding control signal. Each transistor is configured to be turned on or off in response to the corresponding control signal and to leak current when turned off.

[0011] Optionally, the at least two transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the channel width-to-length ratios of at least two of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are different;

[0012] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected in series between the reset voltage terminal and the first end of the storage module, and the gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are respectively connected to different control signals.

[0013] Optionally, from the first transistor to the eighth transistor, the channel width-to-length ratio of each transistor increases in sequence;

[0014] Preferably, from the first transistor to the eighth transistor, the ratio of the channel width-to-length ratios of each transistor is 1:2:4:8:16:32:64:128.

[0015] Optionally, each transistor of the at least two transistors is respectively connected with a switch unit and a storage unit at its gate, so as to access the control signal through the switch unit and store the gate voltage through the storage unit.

[0016] Optionally, the leakage current control module includes a leakage control transistor, the gate of the leakage control transistor is connected to the control signal, the first pole of the leakage control transistor is connected to the reset voltage terminal, the second pole of the leakage control transistor is connected to the first end of the storage module, and the channel width-to-length ratio of the leakage control transistor is adjustable.

[0017] Optionally, the leakage current control module is further configured to be turned on in response to the control signal during the initialization phase, and write the reset voltage of the reset voltage terminal into the gate of the driving transistor.

[0018] Optionally, it further includes a first light emission control module, a second light emission control module, and a compensation module;

[0019] The first light emission control module is connected between the power supply voltage terminal and the first pole of the driving transistor, the second light emission control module is connected between the second pole of the driving transistor and the light emitting device, and both the first light emission control module and the second light emission control module are configured to control the light emission phase;

[0020] The compensation module is connected between the second pole and the gate of the driving transistor, and the compensation module is used to compensate the threshold voltage of the driving transistor.

[0021] In a second aspect, an embodiment of the present invention further provides a driving method for a pixel circuit, where the pixel circuit includes: a data writing module, a storage module, a leakage current control module, and a driving transistor; a first end of the storage module is connected to the gate of the driving transistor, and a second end is connected to a fixed voltage, and the storage module is used to store the gate voltage of the driving transistor; the leakage current control module is connected between a reset voltage terminal and the first end of the storage module, and a control terminal of the leakage current control module is connected to a control signal;

[0022] The driving method for the pixel circuit includes:

[0023] In a data writing stage, a data voltage is written to the gate of the driving transistor through the data writing module;

[0024] In a light emitting stage, the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal is controlled by the leakage current control module in response to the control signal, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module, and a driving current is generated by the driving transistor in response to its own gate voltage to drive a light emitting device to emit light.

[0025] Optionally, the leakage current control module includes at least two transistors, the at least two transistors are connected in series between the reset voltage terminal and the first end of the storage module, and the channel width-to-length ratios of the at least two transistors are different; the gate of each of the at least two transistors serves as the control terminal of the leakage current control module;

[0026] The driving method for the pixel circuit includes:

[0027] In an initialization stage, corresponding control signals are applied to the gates of the at least two transistors to control the at least two transistors to conduct in response to the corresponding control signals, and the reset voltage of the reset voltage terminal is written to the gate of the driving transistor;

[0028] In a light emitting stage, corresponding control signals are applied to the gates of the at least two transistors to control the at least two transistors to conduct or turn off in response to the corresponding control signals, so as to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal;

[0029] Preferably, the driving method for the pixel circuit further includes:

[0030] The magnitude of the leakage current between the first end of the storage module and the reset voltage terminal is controlled by adjusting the magnitude of the reset voltage.

[0031] In the pixel circuit and its driving method provided by the embodiments of the present invention, during the data writing stage, a data voltage is written to the gate of the driving transistor through the data writing module, and at the same time, the gate voltage of the driving transistor is stored through the storage module. During the light emitting stage, the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal is controlled by the leakage current control module, so as to control the discharge time of the voltage stored in the storage module and the gate voltage of the driving transistor changing from the data voltage to the reset voltage, thereby controlling the time for the driving transistor to generate a driving current in response to its gate voltage, and controlling the light emitting time of the light emitting device, achieving the control of the light emitting brightness of the light emitting device and the display gray level of the display panel. Compared with the prior art, in this solution, the data voltage is written to the pixel circuit only once within one frame, without dividing the data of one frame into multiple sub-frames for writing, which helps to save the data writing time and can be applied to display devices with high resolution and high refresh rate. In different frames, different data voltages can be written to the pixel circuit to achieve analog driving. By controlling the leakage current between the first end of the storage module and the reset voltage terminal, the light emitting time of the light emitting device is controlled, thereby controlling the light emitting brightness to achieve digital driving, without generating complex pulse width modulation signals to control the light emitting time. In summary, the pixel circuit in this solution realizes a driving method combining digital driving and analog driving, which helps to improve the display effect while reducing the driving difficulty. Description of the Drawings

[0032] Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0033] Figure 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of the discharge curve of a storage capacitor provided by an embodiment of the present invention;

[0036] Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0037] Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0038] Figure 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0039] Figure 8 It is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention;

[0040] Figure 9 It is a schematic flow chart of a driving method for a pixel circuit provided by an embodiment of the present invention. Detailed implementation manners

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that for the sake of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0042] As described in the background art, existing pixel circuits are difficult to be applied to displays with high resolution and high refresh rate, and the generation method of the driving signal of the pixel circuit is relatively complex. After research by the inventor, the reasons for the above problems are as follows. Traditional digital driving pixel circuits usually divide a frame of display image into multiple sub-frames for display, and form various display gray levels by combining time-sharing writing and clearing data voltages. However, this display mode has poor display effects at high resolution and high refresh rate, making traditional digital driving pixel circuits inapplicable to display devices with high resolution and high refresh rate. Subsequently, pixel circuits combining digital driving and analog driving have been developed. Such pixel circuits use pulse width modulation signals (such as triangular wave signals or ramp signals) as driving signals to control the light-emitting duration of light-emitting devices, thereby controlling the display gray level. However, the generation methods of pulse width modulation signals such as triangular waves and ramps are relatively complex.

[0043] In view of the above problems, an embodiment of the present invention provides a pixel circuit, which can be applied to a display panel. Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Refer to Figure 1, the pixel circuit includes: a data writing module 10, a storage module 20, a leakage current control module 30, and a driving transistor DT; the data writing module 10 is configured to write a data voltage Vdata to the gate of the driving transistor DT during a data writing phase; a first end of the storage module 20 is connected to the gate of the driving transistor DT, and a second end is connected to a fixed voltage, and the storage module 20 is configured to store the gate voltage of the driving transistor DT; the leakage current control module 30 is connected between a reset voltage terminal and the first end of the storage module 20, and a control end of the leakage current control module 30 is connected to a control signal VG, and the leakage current control module 30 is configured to control the magnitude of the leakage current between the first end of the storage module 20 and the reset voltage terminal in response to the control signal VG during a light emitting phase, so as to control the magnitude of the gate voltage of the driving transistor DT stored in the storage module 20; the driving transistor DT is configured to generate a driving current in response to its own gate voltage to drive a light emitting device D1 to emit light.

[0044] There can be various connection manners for each module in the pixel circuit. Exemplarily, refer to Figure 1 , a first end of the data writing module 10 is connected to the data voltage Vdata, a second end is connected to the gate of the driving transistor DT, and a control end is connected to a scan signal VScan. A first pole of the driving transistor DT is connected to a first power supply voltage VDD, a second pole of the driving transistor DT is connected to a first pole of the light emitting device D1, and a second pole of the light emitting device D1 is connected to a second power supply voltage VSS. The light emitting device D1 can be an organic light emitting diode (OLED), the first pole of the light emitting device D1 can be the anode of the OLED, and the second pole of the light emitting device D1 can be the cathode of the OLED. The fixed voltage connected to the second end of the storage module 20 can be a power supply voltage, such as the first power supply voltage VDD. The reset voltage terminal is connected to a reset voltage VLOW.

[0045] The data writing module 10 is turned on or off in response to the scan signal VScan at its control end, and writes the data voltage Vdata to the gate of the driving transistor DT when it is turned on. The leakage current control module 30 is turned on or off in response to the control signal VG at its control end, and writes the reset voltage VLOW to the first end of the storage module 20 and the gate of the driving transistor DT when the leakage current control module 30 is turned on. The leakage current control module 30 can also control the magnitude of its own leakage current in response to the control signal VG at its control end, that is, control the magnitude of the leakage current between the first end of the storage module 20 and the reset voltage terminal. For example, when the control signal VG connected to the control end of the leakage current control module 30 is different, the magnitude of the leakage current generated by the leakage current control module 30 is also different.

[0046] Next, in combination with Figure 1The working principle of the pixel circuit will be described. The working phases of the pixel circuit include a data writing phase and a light emitting phase. In the data writing phase, the data writing module 10 is turned on in response to the scan signal VScan at its control terminal, and writes the data voltage Vdata to the gate of the driving transistor DT. Meanwhile, the storage module 20 stores the gate voltage of the driving transistor DT. In the light emitting phase, the first power supply voltage VDD is written to the first pole of the light emitting device D1 through the driving transistor DT, and the second power supply voltage VSS is written to the second pole of the light emitting device D1. The driving transistor DT generates a corresponding driving current according to its gate voltage to drive the light emitting device D1 to emit light. In the light emitting phase, according to different display gray levels, different control signals VG can be applied to the control terminal of the leakage current control module 30, so that the leakage current control module 30 generates a leakage current corresponding to the control signal VG between the first end of the storage module 20 and the reset voltage terminal to discharge the storage module 20. Optionally, the potential of the data voltage Vdata is higher than the potential of the reset voltage VLOW. During the process of discharging the storage module 20 through the leakage current generated by the leakage current control module 30, the voltage stored in the storage module 20 and the gate voltage of the driving transistor DT both gradually change from the data voltage Vdata to the reset voltage VLOW. When the leakage currents generated by the leakage current control module 30 are different, the time for the voltage stored in the storage module 20 and the gate voltage of the driving transistor DT to change from the data voltage Vdata to the reset voltage VLOW is different, and the time for the driving transistor DT to generate a driving current in response to its gate voltage is also different, so that the maintaining time of the driving current flowing through the light emitting device D1 is also different. When the maintaining time of the driving current of the light emitting device D1 is different, the light emitting time of the light emitting device D1 is different, and the light emitting brightness of the light emitting device D1 is also different. Therefore, by controlling the leakage current between the first end of the storage module 20 and the reset voltage terminal through the leakage current control module 30, the discharging time of the storage module 20 can be controlled to control the light emitting time of the light emitting device D1, thereby realizing the control of the light emitting brightness of the light emitting device D1. The display panel includes multiple rows of pixel circuits. By controlling the writing of the data voltage Vdata to the pixel circuits row by row and controlling the magnitude of the leakage currents generated by the leakage current control modules 30 in each row of pixel circuits, it helps to achieve the display of different gray levels.

[0047] In the technical solution of the embodiment of the present invention, in the data writing stage, a data voltage is written to the gate of the driving transistor through a data writing module, and at the same time, the gate voltage of the driving transistor is stored through a storage module. In the light emitting stage, the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal is controlled by a leakage current control module, so as to control the discharge time of the voltage stored in the storage module and the gate voltage of the driving transistor changing from the data voltage to the reset voltage, thereby controlling the time for the driving transistor to generate a driving current in response to its gate voltage, and controlling the light emitting time of the light emitting device, realizing the control of the light emitting brightness of the light emitting device and the display gray level of the display panel. Compared with the prior art, in this solution, the data voltage is written to the pixel circuit only once within a frame, without dividing the data of a frame into multiple sub-frames for writing, which helps to save the data writing time and can be applied to display devices with high resolution and high refresh rate. In different frames, different data voltages can be written to the pixel circuit to achieve analog driving. By controlling the leakage current between the first end of the storage module and the reset voltage terminal, the light emitting time of the light emitting device is controlled, so as to control the light emitting brightness and achieve digital driving, without generating a complex pulse width modulation signal to control the light emitting time. In summary, the pixel circuit in this solution realizes a driving method combining digital driving and analog driving, which helps to improve the display effect while reducing the driving difficulty.

[0048] Continue to refer to Figure 1 , optionally, on the basis of the above embodiment, the working stage of the pixel circuit further includes an initialization stage before the data writing stage. The leakage current control module 30 is further configured to be turned on in response to the control signal VG in the initialization stage, and write the reset voltage VLOW of the reset voltage terminal to the gate of the driving transistor DT. Exemplarily, the potential of the reset voltage VLOW is set to be lower than the potential of the data voltage Vdata. For example, the reset voltage VLOW in the initialization stage can be a negative value, such as -10V. In the initialization stage, by writing the reset voltage VLOW to the gate of the driving transistor DT, the gate voltage of the driving transistor DT and the voltage of the first end of the storage module 20 can be initialized before the data writing stage, which helps to clear the residual charge of the previous frame display image, thereby improving the display effect.

[0049] Figure 2 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer to Figure 2, optionally, the leakage current control module 30 includes at least two transistors, the at least two transistors are connected in series between the reset voltage terminal and the first terminal of the storage module 20, and the channel width-to-length ratios of at least two transistors in the leakage current control module 30 are different; the gate of each transistor in the leakage current control module 30 serves as the control terminal of the leakage current control module 30 and is connected to the corresponding control signal, and each transistor is configured to turn on or off in response to the corresponding control signal, and there is leakage current when the transistor is turned off.

[0050] The transistors in the leakage current control module 30 may be thin film transistors. When the leakage current control module 30 includes only two transistors, the channel width-to-length ratios of the two transistors are different. When the leakage current control module 30 includes more than two transistors, the channel width-to-length ratios of some transistors may be the same, but at least two transistors have different channel width-to-length ratios.

[0051] Figure 2 Schematically shows the case where the leakage current control module 30 includes eight transistors. Taking the Figure 2 shown pixel circuit as an example, this embodiment will be described. Optionally, the at least two transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are connected in series between the reset voltage terminal and the first terminal of the storage module 20, and the gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are respectively connected to different control signals.

[0052] Among them, the channel width-to-length ratios of at least two of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are different. Exemplarily, the channel width-to-length ratios of seven of the first transistor T1 to the eighth transistor T8 can be set to be the same, and the channel width-to-length ratio of the other transistor is different from that of the other transistors; or, the channel width-to-length ratios of six of the first transistor T1 to the eighth transistor T8 can be set to be the same, the channel width-to-length ratio of one of the other transistors is different from that of the six transistors, and the channel width-to-length ratio of the remaining one transistor is different from that of all the other transistors; or, the channel width-to-length ratios of the first transistor T1 to the eighth transistor T8 can also be set to be all different. It can be understood that there are also various implementation manners to make the channel width-to-length ratios of at least two of the first transistor T1 to the eighth transistor T8 different, which will not be listed one by one here.

[0053] Specifically, the gate of the first transistor T1 is connected to the control signal VG1, the gate of the second transistor T2 is connected to the control signal VG2, the gate of the third transistor T3 is connected to the control signal VG3, the gate of the fourth transistor T4 is connected to the control signal VG4, the gate of the fifth transistor T5 is connected to the control signal VG5, the gate of the sixth transistor T6 is connected to the control signal VG6, the gate of the seventh transistor T7 is connected to the control signal VG7, and the gate of the eighth transistor T8 is connected to the control signal VG8. Each of the first transistor T1 to the eighth transistor T8 can be turned on or off in response to the control signal applied to its own gate. It can be known from the characteristics of the thin-film transistor that when a control signal is applied to the gate of the transistor to make it in the off state and there is a voltage difference between the first pole and the second pole of the transistor, the transistor cannot be completely turned off, and there is still a leakage current between the first pole and the second pole of the transistor.

[0054] The channel width-to-length ratio of the thin-film transistor is the ratio of the width to the length of the conductive channel of the thin-film transistor. When the voltage difference between the source and the drain of the thin-film transistor is constant, the larger the channel width-to-length ratio of the thin-film transistor, the larger the leakage current of the thin-film transistor, and the smaller the channel width-to-length ratio of the thin-film transistor, the smaller the leakage current of the thin-film transistor. By setting the channel width-to-length ratios of at least two of the first transistor T1 to the eighth transistor T8 to be different, the leakage currents of the transistors with different width-to-length ratios can be made different when the voltage differences between the sources and the drains of the transistors are the same.

[0055] By controlling the conduction or cutoff of each transistor in the leakage current control module 30, the magnitude of the leakage current between the reset voltage terminal and the first terminal of the storage module 20 can be controlled. Exemplarily, the ways to control the conduction or cutoff of each transistor in the leakage current control module 30 include control methods (1) to (9).

[0056] Control method (1): Control the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I1 between the reset voltage terminal and the first terminal of the storage module 20 is the smallest. At this time, there is almost no leakage current between the reset voltage terminal and the first terminal of the storage module 20.

[0057] Control method (2): Control the first transistor T1 to be conductive, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I2 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I1.

[0058] Control method (3): Control the first transistor T1 and the second transistor T2 to be both conductive, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I3 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I2.

[0059] Control method (4): Control the first transistor T1, the second transistor T2, and the third transistor T3 to be all conductive, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I4 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I3.

[0060] Control method (5): Control the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 to be all conductive, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I5 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I4.

[0061] Control method (6): Control the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 to be all conductive, and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all cutoff. The leakage current I6 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I5.

[0062] Control mode (7): Control the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to be all turned on, and the seventh transistor T7 and the eighth transistor T8 to be all turned off. The leakage current I7 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I6.

[0063] Control mode (8): Control the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to be all turned on, and the eighth transistor T8 to be turned off. The leakage current I8 between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I7.

[0064] Control mode (9): Control the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to be all turned on. When the first transistor T1 to the eighth transistor T8 are normally turned on, the current between the reset voltage terminal and the first terminal of the storage module 20 is greater than the leakage current I8.

[0065] Therefore, during the light-emitting stage of the pixel circuit, by controlling the transistors in the leakage current control module 30 through control modes (1) to (9), the magnitude of the leakage current between the reset voltage terminal and the first terminal of the storage module 20 can be controlled, so as to control the light-emitting time of the light-emitting device D1, thereby controlling the light-emitting brightness of the light-emitting device D1 and the display gray level of the display panel. Moreover, by setting the channel width-to-length ratios of the first transistor T1 to the eighth transistor T8, the magnitude of the difference between each of the leakage currents I1 to I8 relative to other leakage currents can be controlled, thereby further controlling the leakage current between the reset voltage terminal and the first terminal of the storage module 20 in control modes (1) to (9), so as to further control the light-emitting brightness of the light-emitting device D1 and enable the display panel to achieve displays of different gray levels.

[0066] It should be noted that Figure 2 Only the case where the leakage current control module 30 includes eight transistors is schematically shown. In practical applications, the number of transistors in the leakage current control module 30 can be set according to actual situations, so as to control the magnitude of the leakage current between the reset voltage terminal and the first terminal of the storage module 20 by controlling the on or off of each transistor in the leakage current control module 30. This embodiment does not limit this.

[0067] Continue to refer to Figure 2, on the basis of the above embodiments, optionally, for the first transistor T1 to the eighth transistor T8, the channel width-to-length ratios of the transistors increase in sequence. Exemplarily, it can be set that for the first transistor T1 to the eighth transistor T8, the channel width-to-length ratios of the transistors increase proportionally in sequence. During the light-emitting stage, when controlling the transistors in the leakage current control module 30 through the control methods (1) to (8) in the above embodiments, the leakage current I1 < I2 < I3 < I4 < I5 < I6 < I7 < I8 between the reset voltage terminal and the first terminal of the storage module 20. On this basis, by setting the channel width-to-length ratios of the first transistor T1 to the eighth transistor T8 to increase proportionally in sequence, it is possible to make the magnitudes of the leakage currents I1 to I8 also approximately increase proportionally in sequence. Correspondingly, according to the control methods (1) to (8), the discharge time of the leakage current control module 30 for the storage module 20 approximately decreases proportionally in sequence, the light-emitting time of the light-emitting device D1 approximately shortens proportionally in sequence, and the light-emitting brightness of the light-emitting device D1 approximately decreases proportionally in sequence. That is, according to the control methods (1) to (8), the light-emitting brightness of the light-emitting device D1 changes from bright to dim, and the corresponding display gray level changes from high to low. Therefore, by setting the channel width-to-length ratios of the first transistor T1 to the eighth transistor T8 to increase in sequence, this solution helps to more precisely control the light-emitting device to emit light at different brightness levels, thereby more precisely controlling the display panel to display at different gray levels to improve the display effect.

[0068] Based on the above embodiments, optionally, the first transistor T1 to the eighth transistor T8 have a channel width-to-length ratio of 1:2:4:8:16:32:64:128. Exemplarily, when the channel width-to-length ratio of the first transistor T1 to the eighth transistor T8 is set to 1:2:4:8:16:32:64:128, and each transistor in the leakage current control module 30 is controlled by the control methods (1) to (8) in the above embodiments during the light-emitting stage, the leakage current I1 corresponding to the control method (1) is the smallest, the light-emitting brightness a1 of the light-emitting device D1 is the brightest, and the display gray level corresponding to the control method (1) can be 255 gray levels. The leakage current I2 corresponding to the control method (2) > I1, the light-emitting brightness a2 of the light-emitting device D1 < a1, and the display gray level corresponding to the control method (2) can be 127 gray levels. The leakage current I3 corresponding to the control method (3) > I2, the light-emitting brightness a3 of the light-emitting device D1 < a2, and the display gray level corresponding to the control method (3) can be 63 gray levels. The leakage current I4 corresponding to the control method (4) > I3, the light-emitting brightness a4 of the light-emitting device D1 < a3, and the display gray level corresponding to the control method (4) can be 31 gray levels. The leakage current I5 corresponding to the control method (5) > I4, the light-emitting brightness a5 of the light-emitting device D1 < a4, and the display gray level corresponding to the control method (5) can be 15 gray levels. The leakage current I6 corresponding to the control method (6) > I5, the light-emitting brightness a6 of the light-emitting device D1 < a5, and the display gray level corresponding to the control method (6) can be 7 gray levels. The leakage current I7 corresponding to the control method (7) > I6, the light-emitting brightness a7 of the light-emitting device D1 < a6, and the display gray level corresponding to the control method (7) can be 3 gray levels. The leakage current I8 corresponding to the control method (8) is the largest, the light-emitting brightness a8 of the light-emitting device D1 is the darkest, and the display gray level corresponding to the control method (8) can be 1 gray level. Therefore, by setting the channel width-to-length ratio of the first transistor T1 to the eighth transistor T8 to 1:2:4:8:16:32:64:128 and controlling the conduction or cutoff of the first transistor T1 to the eighth transistor T8 during the light-emitting stage on this basis, it helps the display panel to achieve different display gray levels from 255 gray levels to 1 gray level.

[0069] Continue to refer to Figure 2 , optionally, the data writing module 10 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the scan signal VScan, the first pole of the ninth transistor T9 is connected to the data voltage Vdata, and the second pole of the ninth transistor T9 is connected to the gate of the driving transistor DT; the storage module 20 includes a storage capacitor Cst. The first pole of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second pole of the storage capacitor Cst is connected to the first power supply voltage VDD.

[0070] Figure 3It is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention. Figure 3 The shown driving timing can be used to drive Figure 2 the pixel circuit shown to work. Figure 2 It schematically shows the case where each transistor in the pixel circuit is an N-channel transistor. In the embodiments of the present invention and the following embodiments, it is taken as an example that each transistor in the pixel circuit is an N-channel transistor. In practical applications, each transistor in the pixel circuit can be either an N-channel transistor or a P-channel transistor. The type of transistor in the pixel circuit can be set according to specific situations, and the embodiments of the present invention do not limit this. The working principle of the pixel circuit provided by the embodiments of the present invention will be described below in combination with Figure 2 and Figure 3 . Exemplarily, the working stages of the pixel circuit include an initialization stage t0, a data writing stage t1, and a light emitting stage t2.

[0071] In the initialization stage t0, the signals of the data voltage Vdata, the scan signal VScan, and the reset voltage VLOW are all low-level signals, and the control signals VG1 to VG8 are all high-level signals. The ninth transistor T9 is turned off, and the first transistor T1 to the eighth transistor T8 are all turned on. The reset voltage VLOW is written into the gate of the driving transistor DT and the first pole of the storage capacitor Cst through the first transistor T1 to the eighth transistor T8, and the gate voltage of the driving transistor DT and the voltage of the first pole of the storage capacitor Cst are initialized.

[0072] In the data writing stage t1, the signals of the data voltage Vdata and the scan signal VScan are both high-level signals, and the other signals are all low-level signals. The first transistor T1 to the eighth transistor T8 are all turned off. The ninth transistor T9 is turned on, and the data voltage Vdata is written into the gate of the driving transistor DT. At the same time, the storage capacitor Cst stores the gate voltage of the driving transistor DT.

[0073] During the light-emitting stage t2, the first power supply voltage VDD is written to the first pole of the light-emitting device D1 through the driving transistor DT, and the second power supply voltage VSS is written to the second pole of the light-emitting device D1. The driving transistor DT generates a corresponding driving current according to its gate voltage to drive the light-emitting device D1 to emit light. During the light-emitting stage t2, by setting the control signals VG1 to VG8 to high-level signals or low-level signals, the on or off states of the first transistor T1 to the eighth transistor T8 can be controlled, so as to control the magnitude of the leakage current between the first pole of the storage capacitor Cst and the reset voltage terminal, thereby controlling the discharge time of the storage capacitor Cst, controlling the time when the driving transistor DT generates a driving current in response to its gate voltage, and controlling the light-emitting time of the light-emitting device D1, and further controlling the light-emitting brightness of the light-emitting device D1. For example, the on or off states of the first transistor T1 to the eighth transistor T8 can be controlled according to the control methods (1) to (8) in the above embodiments to control the light-emitting brightness of the light-emitting device D1. Figure 3 Only the case where the control signal VG1 is a high-level signal and the control signals VG2 to VG8 are all low-level signals during the light-emitting stage t2 is shown. At this time, the first transistor T1 is turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off, corresponding to the control method (2). In practical applications, the control signals VG1 to VG8 can be set according to the gray level to be displayed to control the on or off states of the first transistor T1 to the eighth transistor T8, so as to control the light-emitting device D1 to display the gray level to be displayed with the corresponding light-emitting brightness.

[0074] Exemplarily, when the ratio of the channel width to length of the first transistor T1 to the eighth transistor T8 is set to 1:2:4:8:16:32:64:128, the display gray levels corresponding to the control methods (1) to (8) in the above embodiments can be 255 gray levels, 127 gray levels, 63 gray levels, 31 gray levels, 15 gray levels, 7 gray levels, 3 gray levels, and 1 gray level in sequence. Figure 4 It is a schematic diagram of the discharge curve of a storage capacitor provided by an embodiment of the present invention. Specifically, it can be a schematic diagram of the discharge curve of the storage capacitor Cst during the light-emitting stage t2 under different display gray levels corresponding to the control methods (1) to (8). Among them, the abscissa T represents time, the ordinate V represents the voltage value of the storage capacitor Cst, and L255 to L1 are the discharge curves of the storage capacitor Cst under the 255 gray level to 1 gray level corresponding to the control methods (1) to (8).

[0075] Combined with Figures 2 to 4, from the 255 gray levels to the 1 gray level corresponding to the control modes (1) to (8), the time required for the voltage stored in the storage capacitor Cst to discharge from the maximum value (for example, the data voltage Vdata) to the reset voltage VLOW decreases in sequence, the corresponding light-emitting time of the light-emitting device D1 decreases in sequence, and the light-emitting brightness decreases in sequence. The speed of the discharge time of the storage capacitor Cst is related to the capacitance value of the storage capacitor Cst, the voltage across the storage capacitor Cst, and the impedance of the circuit. The voltage across the storage capacitor Cst is related to the magnitude of the reset voltage VLOW. Therefore, in the initialization stage t0, the potential of the reset voltage VLOW can be set lower, for example, the reset voltage VLOW in the initialization stage t0 is set to -10V, so as to initialize the voltage stored in the storage capacitor Cst and the gate voltage of the driving transistor DT through the reset voltage VLOW. In the light-emitting stage t2, the potential of the reset voltage VLOW can be set higher, and the potential of the reset voltage VLOW is set lower than the voltage of the data voltage Vdata written to the gate of the driving transistor DT, so that there is a voltage difference between the first pole of the storage capacitor Cst and the reset voltage terminal. For example, the reset voltage VLOW in the light-emitting stage t2 is set to -5V, and the data voltage Vdata written to the gate of the driving transistor DT is greater than -5V.

[0076] On the basis of the above solution, optionally, in the light-emitting stage t2, by adjusting the magnitude of the reset voltage VLOW according to the capacitance value of the storage capacitor Cst, it is also possible to control the magnitude of the leakage current between the first pole of the storage capacitor Cst and the reset voltage terminal, and control the discharge time of the storage capacitor Cst, so as to control the magnitude of the display gray level. Exemplarily, when the data voltage Vdata written to the gate of the driving transistor DT and the capacitance value of the storage capacitor Cst are both fixed, if the voltage difference between the first pole of the storage capacitor Cst and the reset voltage terminal is made larger by adjusting the magnitude of the reset voltage VLOW, the leakage current generated by the transistor between the first pole of the storage capacitor Cst and the reset voltage terminal is larger, the time required for the storage capacitor Cst to discharge from the data voltage Vdata to the reset voltage VLOW is shorter, the light-emitting time of the light-emitting device D1 is shorter, the light-emitting brightness is lower, and the display gray level is lower. Similarly, if the voltage difference between the first pole of the storage capacitor Cst and the reset voltage terminal is made smaller by adjusting the magnitude of the reset voltage VLOW, the leakage current generated by the transistor between the first pole of the storage capacitor Cst and the reset voltage terminal is smaller, the time required for the storage capacitor Cst to discharge from the data voltage Vdata to the reset voltage VLOW is longer, the light-emitting time of the light-emitting device D1 is longer, the light-emitting brightness is brighter, and the display gray level is higher. Therefore, by adjusting the magnitude of the reset voltage VLOW, the magnitude of the leakage current between the first pole of the storage capacitor Cst and the reset voltage terminal can be controlled, and further the light-emitting brightness of the light-emitting device D1 and the display gray level of the display panel can be controlled.

[0077] Figure 5 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 5 , optionally, a switch unit 310 and a storage unit 320 are respectively connected to the gate of each transistor in the leakage current control module 30, so as to access a control signal through the switch unit 310 and store the gate voltage through the storage unit 320. Exemplarily, when the leakage current control module 30 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a switch unit 310 is connected to the gate of each transistor to access a control signal through the corresponding switch unit 310. The control ends of different switch units 310 access different switch control signals. For example, the control end of the switch unit 310 connected to the first transistor T1 accesses the switch control signal V1, the control end of the switch unit 310 connected to the second transistor T2 accesses the switch control signal V2, the control end of the switch unit 310 connected to the third transistor T3 accesses the switch control signal V3, the control end of the switch unit 310 connected to the fourth transistor T4 accesses the switch control signal V4, the control end of the switch unit 310 connected to the fifth transistor T5 accesses the switch control signal V5, the control end of the switch unit 310 connected to the sixth transistor T6 accesses the switch control signal V6, the control end of the switch unit 310 connected to the seventh transistor T7 accesses the switch control signal V7, and the control end of the switch unit 310 connected to the eighth transistor T8 accesses the switch control signal V8. Each switch unit 310 is configured to conduct or turn off in response to the switch control signal at its control end, and when conducting, transmit the corresponding control signal of the transistor connected thereto to the gate of the transistor to control the conduction or turn-off of the transistor. A storage unit 320 is also connected to the gate of each transistor. Different transistors are connected to different storage units 320. The first end of each storage unit 320 is connected to the gate of the corresponding transistor, and the second end accesses a fixed voltage, which may be a power supply voltage, such as the first power supply voltage VDD. The storage unit 320 is configured to store the gate voltage of the corresponding transistor to maintain the gate voltage of the transistor.

[0078] Continue to refer to Figure 5, based on the above embodiments, optionally, the switch unit 310 includes transistors, and the storage unit 320 includes capacitors. Exemplarily, the switch unit 310 connected to the first transistor T1 includes a transistor M1, and the storage unit 320 connected to the first transistor T1 includes a first capacitor C1. The switch unit 310 connected to the second transistor T2 includes a transistor M2, and the storage unit 320 connected to the second transistor T2 includes a second capacitor C2. The switch unit 310 connected to the third transistor T3 includes a transistor M3, and the storage unit 320 connected to the third transistor T3 includes a third capacitor C3. The switch unit 310 connected to the fourth transistor T4 includes a transistor M4, and the storage unit 320 connected to the fourth transistor T4 includes a fourth capacitor C4. The switch unit 310 connected to the fifth transistor T5 includes a transistor M5, and the storage unit 320 connected to the fifth transistor T5 includes a fifth capacitor C5. The switch unit 310 connected to the sixth transistor T6 includes a transistor M6, and the storage unit 320 connected to the sixth transistor T6 includes a sixth capacitor C6. The switch unit 310 connected to the seventh transistor T7 includes a transistor M7, and the storage unit 320 connected to the seventh transistor T7 includes a seventh capacitor C7. The switch unit 310 connected to the eighth transistor T8 includes a transistor M8, and the storage unit 320 connected to the eighth transistor T8 includes an eighth capacitor C8. Each of the transistors M1 to M8 is configured to conduct or turn off in response to a switch control signal applied to its gate. Each of the first capacitor C1 to the eighth capacitor C8 is configured to store the gate voltage of the corresponding transistor.

[0079] Figure 5 The pixel circuit shown is similar to Figure 2 the pixel circuit shown in terms of working principle, with the only difference being that Figure 5 each transistor in the leakage current control module 30 shown has a switch unit 310 and a storage unit 320 connected to its gate. The switch unit 310 includes transistors, and the storage unit 320 includes capacitors. Figure 3 The driving timing shown can also be used to drive Figure 5 the pixel circuit shown to operate. Figure 3 The switch control signals V1 to V8 are not shown in . In practical applications, according to the control requirements for the conduction or turn-off of the first transistor T1 to the eighth transistor T8, the switch control signals V1 to V8 can be set accordingly to apply the corresponding control signals to the gates of the first transistor T1 to the eighth transistor T8. Figure 5 The specific working principle of the pixel circuit shown will not be elaborated further.

[0080] Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 6 shows a case where the leakage current control module 30 includes only one transistor, that is,Figure 2 The leakage current control module 30 in the pixel circuit shown can also be composed of only one transistor. Refer to Figure 6 , optionally, the leakage current control module 30 includes a leakage control transistor T0. The gate of the leakage control transistor T0 is connected to a control signal VG. The first pole of the leakage control transistor T0 is connected to a reset voltage terminal. The second pole of the leakage control transistor T0 is connected to the first end of the storage module 20. The channel width-to-length ratio of the leakage control transistor T0 is adjustable.

[0081] Figure 2 and Figure 6 The difference in the working principle of the pixel circuit shown lies in the different control methods of the transistors in the leakage current control module 30. Specifically, in the initialization stage, the leakage control transistor T0 is controlled to conduct, and the reset voltage VLOW is written into the gate of the driving transistor DT and the first pole of the storage capacitor Cst through the leakage control transistor T0, so as to initialize the gate voltage of the driving transistor DT and the voltage of the first pole of the storage capacitor Cst. In the light-emitting stage, the leakage control transistor T0 is controlled to turn off. Since there is a voltage difference between the first pole and the second pole of the leakage control transistor T0, the leakage control transistor T0 cannot be completely turned off, and the leakage control transistor T0 will generate a leakage current. When the voltage difference between the first pole and the second pole of the leakage control transistor T0 is constant, the channel width-to-length ratio of the leakage control transistor T0 is positively correlated with the magnitude of the leakage current generated by it. Therefore, by adjusting the channel width-to-length ratio of the leakage control transistor T0, the magnitude of the leakage current of the leakage control transistor T0 can be adjusted, so as to control the discharge time of the storage capacitor Cst, control the time when the driving transistor DT responds to its gate voltage to generate a driving current, and control the light-emitting time of the light-emitting device D1, and further control the light-emitting brightness of the light-emitting device D1. The technical solution of the embodiment of the present invention, by setting the leakage current control module 30 to include only one leakage control transistor T0 with an adjustable channel width-to-length ratio, helps to simplify the structure of the leakage current control module 30, thereby simplifying the structure of the pixel circuit. By adjusting the channel width-to-length ratio of the leakage control transistor T0, it helps to control the light-emitting brightness of the light-emitting device D1 and the display gray level of the display panel.

[0082] Figure 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 7 , in this embodiment, it is schematically set that the leakage current control module 30 includes a leakage control transistor T0. In other embodiments of the present invention, it can also be set that the leakage current control module 30 includes at least two transistors, for example Figure 2 and Figure 5 the case where the leakage current control module 30 shown includes the first transistor T1 to the eighth transistor T8.

[0083] Continue to refer to Figure 7, optionally, the second power supply voltage terminal is multiplexed as a reset voltage terminal, and the second power supply voltage terminal is connected to a second power supply voltage VSS. The leakage current control module 30 further includes a transistor M0 and a capacitor C0; the gate of the transistor M0 is connected to a switch control signal V0, the first pole is connected to a control signal VG, the second pole is connected to the gate of the leakage control transistor T0, and the transistor M0 is used to conduct or cut off in response to the switch control signal V0, and write the control signal VG to the gate of the leakage control transistor T0 when conducting; the first pole of the capacitor C0 is connected to the gate of the leakage control transistor T0, the second pole of the capacitor C0 is connected to the second power supply voltage VSS, and the capacitor C0 is used to store the gate voltage of the leakage control transistor T0.

[0084] Continue to refer to Figure 7 , optionally, the control terminal of the data writing module 10 is connected to a scan signal VScan, the first terminal is connected to a data voltage Vdata, and the second terminal is connected to the first pole of a driving transistor DT; the pixel circuit further includes a first light emission control module 40, a second light emission control module 50 and a compensation module 60; the first light emission control module 40 is connected between a power supply voltage terminal (such as a first power supply voltage terminal, and the first power supply voltage terminal is connected to a first power supply voltage VDD) and the first pole of the driving transistor DT, the second light emission control module 50 is connected between the second pole of the driving transistor DT and a light emitting device D1, and both the first light emission control module 40 and the second light emission control module 50 are used to control the light emitting stage; the compensation module 60 is connected between the second pole and the gate of the driving transistor DT, and the compensation module 60 is used to compensate the threshold voltage of the driving transistor DT.

[0085] Continue to refer to Figure 7, optionally, the data writing module 10 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the scanning signal VScan, the first pole of the ninth transistor T9 is connected to the data voltage Vdata, and the second pole of the ninth transistor T9 is connected to the gate of the driving transistor DT. The storage module 20 includes a storage capacitor Cst. The first pole of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second pole of the storage capacitor Cst is connected to the first power supply voltage VDD. The first light emission control module 40 includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the light emission control signal EM, the first pole is connected to the first power supply voltage VDD, and the second pole is connected to the first pole of the driving transistor DT. The second light emission control module 50 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is connected to the light emission control signal EM, the first pole of the eleventh transistor T11 is connected to the second pole of the driving transistor DT, and the second pole of the eleventh transistor T11 is connected to the first pole of the light emitting device D1. The compensation module 60 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the scanning signal VScan, the first pole of the twelfth transistor T12 is connected to the second pole of the driving transistor DT, and the second pole of the twelfth transistor T12 is connected to the gate of the driving transistor DT.

[0086] Figure 8 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention. Figure 8 The shown driving timing can be used to drive Figure 7 the shown pixel circuit to work. The following combines Figure 7 and Figure 8 to illustrate the working principle of the pixel circuit provided by the embodiment of the present invention. Exemplarily, the working stages of the pixel circuit include an initialization stage t10, a data writing stage t11, and a light emission stage t12.

[0087] In the initialization stage t10, the signals of the data voltage Vdata, the scanning signal VScan, and the light emission control signal EM are all low-level signals, and the control signal VG and the switch control signal V0 are all high-level signals. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. The transistor M0 and the leakage control transistor T0 are both turned on, and the second power supply voltage VSS is written into the gate of the driving transistor DT and the first pole of the storage capacitor Cst through the leakage control transistor T0 to initialize the gate voltage of the driving transistor DT and the voltage of the first pole of the storage capacitor Cst.

[0088] In the data writing stage t11, the signals of the data voltage Vdata and the scan signal VScan are both high-level signals, and the rest of the signals are all low-level signals. The transistor M0, the leakage control transistor T0, the tenth transistor T10, and the eleventh transistor T11 are all turned off. The ninth transistor T9 and the twelfth transistor T12 are turned on, and the data voltage Vdata is sequentially written into the gate of the driving transistor DT through the ninth transistor T9, the driving transistor DT, and the twelfth transistor T12 to achieve the data voltage writing of the driving transistor DT and the threshold voltage compensation of the driving transistor DT. At the same time, the storage capacitor Cst stores the gate voltage of the driving transistor DT.

[0089] In the light emitting stage t12, the signals of the data voltage Vdata, the scan signal VScan, and the control signal VG are low-level signals, and the switch control signal V0 and the light emitting control signal EM are both high-level signals. The leakage control transistor T0, the ninth transistor T9, and the twelfth transistor T12 are all turned off. The transistor M0, the tenth transistor T10, and the eleventh transistor T11 are all turned on. The first power supply voltage VDD is written into the first pole of the light emitting device D1 through the tenth transistor T10, the driving transistor DT, and the eleventh transistor T11, and the second power supply voltage VSS is written into the second pole of the light emitting device D1. The driving transistor DT generates a corresponding driving current according to its gate voltage to drive the light emitting device D1 to emit light. Since the channel width-to-length ratio of the leakage control transistor T0 is adjustable, in the light emitting stage t12, by adjusting the channel width-to-length ratio of the leakage control transistor T0, the magnitude of the leakage current of the leakage control transistor T0 can be adjusted, so as to control the discharge time of the storage capacitor Cst, control the time for the driving transistor DT to generate a driving current in response to its gate voltage, and control the light emitting time of the light emitting device D1, thereby controlling the light emitting brightness of the light emitting device D1.

[0090] The embodiment of the present invention also provides a driving method for a pixel circuit, which is applicable to driving the pixel circuit provided in any embodiment of the present invention. Figure 9 It is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention. Refer to Figure 9 , the driving method of the pixel circuit includes the following steps:

[0091] S110. In the data writing stage, write a data voltage into the gate of the driving transistor through a data writing module.

[0092] S120. In the light emitting stage, control the magnitude of the leakage current between the first end of the storage module and the reset voltage end through a leakage current control module in response to a control signal, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module, and generate a driving current through the driving transistor in response to its own gate voltage to drive the light emitting device to emit light.

[0093] In the technical solution of the embodiment of the present invention, in the data writing stage, a data voltage is written to the gate of the driving transistor through the data writing module, and at the same time, the gate voltage of the driving transistor is stored through the storage module. In the light emitting stage, the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal is controlled by the leakage current control module, so as to control the voltage stored in the storage module and the discharge time for the gate voltage of the driving transistor to change from the data voltage to the reset voltage, thereby controlling the time for the driving transistor to generate a driving current in response to its gate voltage, and controlling the light emitting time of the light emitting device, achieving the control of the light emitting brightness of the light emitting device and the display gray level of the display panel. Compared with the prior art, in this solution, the data voltage is written to the pixel circuit only once within one frame, without dividing the data of one frame into multiple sub-frames for writing, which helps to save the data writing time and can be applied to display devices with high resolution and high refresh rate. In different frames, different data voltages can be written to the pixel circuit to achieve analog driving. By controlling the leakage current between the first end of the storage module and the reset voltage terminal, the light emitting time of the light emitting device is controlled, thereby controlling the light emitting brightness to achieve digital driving, without generating complex pulse width modulation signals to control the light emitting time. In summary, the pixel circuit in this solution realizes a driving method that combines digital driving and analog driving, which helps to improve the display effect while reducing the driving difficulty.

[0094] Optionally, referring to Figure 2 or Figure 5 , the leakage current control module 30 includes at least two transistors, the at least two transistors are connected in series between the reset voltage terminal and the first end of the storage module 20, and the channel width-to-length ratios of at least two transistors in the leakage current control module 30 are different; the gate of each of the at least two transistors serves as the control terminal of the leakage current control module 30; correspondingly, the driving method of the pixel circuit includes:

[0095] In the initialization stage, corresponding control signals are applied to the gates of the at least two transistors to control the at least two transistors to conduct in response to the corresponding control signals, and the reset voltage of the reset voltage terminal is written to the gate of the driving transistor;

[0096] In the light emitting stage, corresponding control signals are applied to the gates of the at least two transistors to control the at least two transistors to conduct or turn off in response to the corresponding control signals, so as to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal.

[0097] The technical solution of the embodiment of the present invention is applicable to driving the pixel circuits shown in Figure 2 and Figure 5 . The technical principle and the technical effects generated by driving the pixel circuit to work are similar, so they will not be elaborated here.

[0098] Optionally, the driving method of the pixel circuit further includes: controlling the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal by adjusting the magnitude of the reset voltage. Combining Figures 2 to 4 , for example, when the channel width-to-length ratios of the first transistor T1 to the eighth transistor T8 are set in the ratio of 1:2:4:8:16:32:64:128, the display gray levels corresponding to the control modes (1) to (8) in the above embodiments may be 255 gray levels, 127 gray levels, 63 gray levels, 31 gray levels, 15 gray levels, 7 gray levels, 3 gray levels, and 1 gray level in sequence. In the light-emitting stage t2, by adjusting the magnitude of the reset voltage VLOW according to the capacitance value of the storage capacitor Cst, it is also possible to control the magnitude of the leakage current between the first pole of the storage capacitor Cst and the reset voltage terminal, and control the discharge time of the storage capacitor Cst, so as to control the magnitude of the display gray level. When the data voltage Vdata written to the gate of the driving transistor DT and the capacitance value of the storage capacitor Cst are both fixed, if the voltage difference between the first pole of the storage capacitor Cst and the reset voltage terminal is made larger by adjusting the magnitude of the reset voltage VLOW, the leakage current generated by the transistor between the first pole of the storage capacitor Cst and the reset voltage terminal is larger, the time required for the storage capacitor Cst to discharge from the data voltage Vdata to the reset voltage VLOW is shorter, the light-emitting time of the light-emitting device D1 is shorter, the light-emitting brightness is darker, and the display gray level is lower. Similarly, if the voltage difference between the first pole of the storage capacitor Cst and the reset voltage terminal is made smaller by adjusting the magnitude of the reset voltage VLOW, the leakage current generated by the transistor between the first pole of the storage capacitor Cst and the reset voltage terminal is smaller, the time required for the storage capacitor Cst to discharge from the data voltage Vdata to the reset voltage VLOW is longer, the light-emitting time of the light-emitting device D1 is longer, the light-emitting brightness is brighter, and the display gray level is higher. Therefore, by the magnitude of the reset voltage VLOW, it is possible to control the magnitude of the leakage current between the first pole of the storage capacitor Cst and the reset voltage terminal, and further control the light-emitting brightness of the light-emitting device D1 and the display gray level of the display panel.

[0099] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it may further include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, Including: A data writing module, a storage module, a leakage current control module, and a driving transistor; The data writing module is configured to write a data voltage to the gate of the driving transistor during a data writing phase; A first end of the storage module is connected to the gate of the driving transistor, and a second end is connected to a fixed voltage. The storage module is configured to store the gate voltage of the driving transistor; The leakage current control module is connected between a reset voltage terminal and the first end of the storage module. A control terminal of the leakage current control module is connected to a control signal. The leakage current control module is configured to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal in response to the control signal during a light emitting phase, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module; The driving transistor is configured to generate a driving current in response to its own gate voltage to drive a light emitting device to emit light; The leakage current control module includes at least two transistors. The at least two transistors are connected in series between the reset voltage terminal and the first end of the storage module, and the channel width-to-length ratios of the at least two transistors are different; The gate of each of the at least two transistors serves as the control terminal of the leakage current control module and is connected to a corresponding control signal. Each transistor is configured to be turned on or off in response to the corresponding control signal and to leak current when turned off.

2. The pixel circuit according to claim 1, wherein The at least two transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the channel width-to-length ratios of at least two of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are different; The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected in series between the reset voltage terminal and the first end of the storage module, and the gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are respectively connected to different control signals.

3. The pixel circuit according to claim 2, wherein From the first transistor to the eighth transistor, the channel width-to-length ratio of each transistor increases in sequence.

4. The pixel circuit according to claim 3, wherein From the first transistor to the eighth transistor, the ratio of the channel width-to-length ratios of each transistor is 1:2:4:8:16:32:64:

128.

5. The pixel circuit according to claim 2, wherein A switch unit and a storage unit are respectively connected to the gate of each of the at least two transistors, so as to connect to the control signal through the switch unit and store the gate voltage through the storage unit.

6. The pixel circuit according to claim 1, characterized in that, The leakage current control module is further configured to be turned on in response to the control signal during an initialization phase, and write the reset voltage of the reset voltage terminal to the gate of the driving transistor.

7. The pixel circuit according to claim 1, wherein It further includes a first light emitting control module, a second light emitting control module, and a compensation module; The first light emission control module is connected between the power supply voltage terminal and the first pole of the driving transistor, and the second light emission control module is connected between the second pole of the driving transistor and the light emitting device. Both the first light emission control module and the second light emission control module are used to control the light emission stage; The compensation module is connected between the second pole and the gate of the driving transistor, and the compensation module is used to compensate the threshold voltage of the driving transistor.

8. A pixel circuit, characterized in that, Comprising: A data writing module, a storage module, a leakage current control module, and a driving transistor; The data writing module is used to write a data voltage to the gate of the driving transistor during the data writing stage; The first end of the storage module is connected to the gate of the driving transistor, and the second end is connected to a fixed voltage. The storage module is used to store the gate voltage of the driving transistor; The leakage current control module is connected between the reset voltage terminal and the first end of the storage module. The control terminal of the leakage current control module is connected to a control signal. The leakage current control module is used to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal in response to the control signal during the light emission stage, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module; The driving transistor is used to generate a driving current in response to its own gate voltage to drive the light emitting device to emit light; The leakage current control module includes a leakage control transistor. The gate of the leakage control transistor is connected to the control signal. The first pole of the leakage control transistor is connected to the reset voltage terminal. The second pole of the leakage control transistor is connected to the first end of the storage module. The channel width-to-length ratio of the leakage control transistor is adjustable.

9. The pixel circuit according to claim 8, wherein The leakage current control module is further used to conduct in response to the control signal during the initialization stage, and write the reset voltage of the reset voltage terminal to the gate of the driving transistor.

10. The pixel circuit according to claim 8, wherein, Further comprising a first light emission control module, a second light emission control module, and a compensation module; The first light emission control module is connected between the power supply voltage terminal and the first pole of the driving transistor, and the second light emission control module is connected between the second pole of the driving transistor and the light emitting device. Both the first light emission control module and the second light emission control module are used to control the light emission stage; The compensation module is connected between the second pole and the gate of the driving transistor, and the compensation module is used to compensate the threshold voltage of the driving transistor.

11. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: a data writing module, a storage module, a leakage current control module, and a driving transistor; the first end of the storage module is connected to the gate of the driving transistor, and the second end is connected to a fixed voltage. The storage module is used to store the gate voltage of the driving transistor; the leakage current control module is connected between the reset voltage terminal and the first end of the storage module, and the control terminal of the leakage current control module is connected to a control signal; The driving method of the pixel circuit includes: During the data writing stage, write a data voltage to the gate of the driving transistor through the data writing module; In the light-emitting stage, the leakage current control module responds to the control signal to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module, and the driving transistor responds to its own gate voltage to generate a driving current to drive the light-emitting device to emit light; Wherein, the leakage current control module includes at least two transistors, the at least two transistors are connected in series between the reset voltage terminal and the first end of the storage module, and the channel width-to-length ratios of the at least two transistors are different; the gate of each of the at least two transistors serves as the control terminal of the leakage current control module.

12. The driving method of the pixel circuit according to claim 11, wherein The driving method of the pixel circuit includes: In the initialization stage, a corresponding control signal is applied to the gates of the at least two transistors to control the at least two transistors to conduct in response to the corresponding control signal, and the reset voltage of the reset voltage terminal is written into the gate of the driving transistor; In the light-emitting stage, a corresponding control signal is applied to the gates of the at least two transistors to control the at least two transistors to conduct or turn off in response to the corresponding control signal, so as to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal.

13. The driving method of the pixel circuit according to claim 12, wherein The driving method of the pixel circuit further includes: Controlling the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal by adjusting the magnitude of the reset voltage.

14. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: a data writing module, a storage module, a leakage current control module, and a driving transistor; the first end of the storage module is connected to the gate of the driving transistor, the second end is connected to a fixed voltage, and the storage module is used to store the gate voltage of the driving transistor; the leakage current control module is connected between the reset voltage terminal and the first end of the storage module, and the control terminal of the leakage current control module is connected to a control signal; The driving method of the pixel circuit includes: In the data writing stage, the data writing module writes a data voltage to the gate of the driving transistor; In the light-emitting stage, the leakage current control module responds to the control signal to control the magnitude of the leakage current between the first end of the storage module and the reset voltage terminal, so as to control the magnitude of the gate voltage of the driving transistor stored in the storage module, and the driving transistor responds to its own gate voltage to generate a driving current to drive the light-emitting device to emit light; Wherein, the leakage current control module includes a leakage control transistor, the gate of the leakage control transistor is connected to the control signal, the first pole of the leakage control transistor is connected to the reset voltage terminal, the second pole of the leakage control transistor is connected to the first end of the storage module, and the channel width-to-length ratio of the leakage control transistor is adjustable.

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