Delay reduction in spi flash memory devices

Abstract

The present invention relates to latency reduction in SPI flash memory devices. A method can include the steps of receiving a read request in a memory device from a host device coupled to the memory device by an interface, decoding an address of the read request received from the interface, decoding a command of the read request to determine whether the read request is for an aligned address operation, when the read request is determined to be for an aligned address operation, holding the decoded address without modification regardless of the actual alignment of the decoded address, and executing the read request on the memory device as an aligned address operation using the decoded address.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor devices. More specifically, embodiments of this invention relate to memory devices, including both volatile memory devices and non-volatile memory devices (such as flash memory devices). Background Technology

[0002] Non-volatile memory (NVM) is increasingly appearing in applications such as solid-state drives, removable digital image cards, automotive electronics, and home appliances. Flash memory is the dominant NVM technology used today. However, flash memory has limitations, such as relatively high power consumption and relatively low operating speed. Microprocessor performance is highly sensitive to memory latency. Many non-volatile memory devices have relatively slow access times or latency compared to the microprocessor. Furthermore, many implementations of various communication protocols between the microprocessor / host and memory (such as the Serial Peripheral Interface (SPI)) can add even more latency than the memory array itself requires. Summary of the Invention

[0003] One aspect of the present invention provides a method comprising the steps of: a) receiving a read request from a host device in a memory device, the host device being connected to the memory device via an interface; b) decoding an address of the read request received from the interface; c) decoding a command of the read request to determine whether the read request is for an aligned address operation; d) when the read request is determined to be for an aligned address operation, maintaining the decoded address without modification regardless of the actual alignment of the decoded address; and e) executing the read request on the memory device according to the aligned address operation using the decoded address.

[0004] Another aspect of the present invention provides a memory device configured to: a) receive a read request from a host device via an interface; b) decode the address of the read request; c) decode the command of the read request to determine whether the read request is for an aligned address operation; d) when the read request is determined to be for the aligned address operation, retain the decoded address without modification regardless of the actual alignment of the decoded address; and e) execute the read request on the memory device according to the aligned address operation using the decoded address. Attached Figure Description

[0005] Figure 1 This is a schematic block diagram illustrating an example arrangement of a host and memory device according to an embodiment of the present invention.

[0006] Figure 2This is a schematic block diagram of an example memory controller system according to an embodiment of the present invention.

[0007] Figure 3 This is a schematic block diagram of an example memory device according to an embodiment of the present invention.

[0008] Figure 4 This is a schematic block diagram of an example memory device with read request modification control according to an embodiment of the present invention.

[0009] Figure 5 This is a timing diagram of an example read access according to an embodiment of the present invention.

[0010] Figure 6 This is a timing diagram of an example aligned address read access according to an embodiment of the present invention.

[0011] Figure 7 This is a timing diagram of an example of an unaligned address read access according to an embodiment of the present invention.

[0012] Figure 8 This is a timing diagram of an example DWA read access according to an embodiment of the present invention.

[0013] Figure 9 This is a timing diagram of another example of DWA read access according to an embodiment of the present invention.

[0014] Figure 10 This is a timing diagram of an example DWA read access for word access according to an embodiment of the present invention.

[0015] Figure 11 This is a timing diagram of an example DWA read access for byte access according to an embodiment of the present invention.

[0016] Figure 12 This is a timing diagram of an example modified DWA read access for word access according to an embodiment of the present invention.

[0017] Figure 13 This is a timing diagram of an example modified DWA read access for byte access according to an embodiment of the present invention.

[0018] Figure 14 This is a timing diagram of an example modified DWA read access for double-word access according to an embodiment of the present invention.

[0019] Figure 15 This is a flowchart of an example method for controlling read requests according to an embodiment of the present invention. Detailed Implementation

[0020] Reference will now be made in detail to specific embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with preferred embodiments, it will be understood that these preferred embodiments are not intended to limit the invention to these embodiments. Rather, the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the invention to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without these specific details. In other instances, well-known methods, processes, treatments, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the invention.

[0021] Some portions of the following detailed description are presented from the perspective of the processing, procedures, logic blocks, function blocks, processes, schematic symbols, and / or other symbolic representations of operations on data streams, signals, or waveforms within a computer, processor, controller, device, and / or memory. These descriptions and representations are commonly used by those skilled in the art of data processing to effectively convey the substance of their work to others skilled in the art. Typically, although not strictly necessary, the quantities being manipulated take the form of electrical, magnetic, optical, or quantum signals capable of being stored, transmitted, combined, compared, and otherwise manipulated in a computer or data processing system. Primarily for general reasons, referring to these signals as bits, waves, waveforms, streams, values, elements, symbols, characters, items, numbers, etc., sometimes proves convenient.

[0022] Specific implementations may relate to memory devices including volatile memories such as SRAM and DRAM, and non-volatile memories (NVMs) such as flash memory devices, and / or resistive switching memories (e.g., conductive bridged random access memory [CBRAM], resistive RAM [ReRAM], etc.). Specific implementations may include structures and methods for operating flash memory and / or resistive switching memories that can be written (programmed / erased) between one or more resistive and / or capacitive states. In one specific example, a CBRAM memory element may be configured such that the electrical characteristics (e.g., resistance) of the CBRAM memory element can change when a forward or reverse bias voltage greater than a threshold voltage is applied across the electrodes of the CBRAM memory element. In any case, certain implementations are suitable for any type of memory device, specifically NVM devices such as flash memory devices, and in some cases may include resistive switching memory devices.

[0023] Now for reference Figure 1 , Figure 1An example memory device and host arrangement 100 according to an embodiment of the present invention are illustrated. In this example, host 102 may be interfaced with memory device 104 via a serial interface. For example, host 102 may be any suitable controller (e.g., CPU, MCU, general-purpose processor, GPU, DSP, etc.), and memory device 104 may be any type of memory device (e.g., SRAM, DRAM, EEPROM, flash memory, CBRAM, magnetic RAM, ReRAM, etc.). Therefore, memory device 104 may be implemented according to various memory technologies, such as non-volatile types. In some cases, memory device 104 may be a serial flash memory, which may be implemented according to a more conventional non-volatile memory, or according to a CBRAM / ReRAM resistive switching memory.

[0024] Various interface signals, such as those from a Serial Peripheral Interface (SPI), may be included for communication between the host 102 and the memory device 104. For example, a serial clock (SCK) may provide a clock to the device 104 and may be used to control the data flow to the device. The memory device 104 may latch commands, addresses, and input data (e.g., via I / O pins) on the rising edge of SCK, while output data (e.g., via I / O pins) may be clocked out from the memory device 104 via SCK or a data strobe (DS). A chip select (CS) (which may be active low) may be used to select the memory device 104, such as from multiple memory devices sharing a common bus or board, or otherwise as a means of accessing the device. When the chip select signal is de-asserted (e.g., high), the memory device 104 may be deselected and placed in standby mode. Activating the chip select signal (e.g., via a high-to-low transition on CS) may be used to start operation, and returning the chip select signal to a high state may be used to terminate operation. For internal self-timed operations (e.g., programming or erasing cycles), if the assertion chip selection is deselected during operation, the memory device 104 may not enter standby mode until the specific operation is completed.

[0025] In the example interface, data can be provided to and from memory device 104 via I / O signals (e.g., for write operations, other commands, etc.) and (e.g., for read operations, verification operations, etc.). For example, memory device 104 can latch input data on the I / O on the edge of the serial clock SCK, and such input data can be ignored if the device is deselected (e.g., when the chip select signal is de-asserted). Data can also be output from memory device 104 via I / O signals. For example, data output from memory device 104 can be clocked on the edge of DS or SCK for timing consistency, and the output signal can be in a high-impedance state when the device is deselected (e.g., when the chip select signal is de-asserted). For example, input data can be timed on one edge (SDR / STR) or two edges (DDR / DTR) or a combination of both of the SCK used for commands, addresses, or data. Similarly, output data can be timed on one edge (SDR / STR) or two edges (DDR / DTR) of the SCK or DS used for data. Furthermore, the output data can, but is not required to, use the same clock mode as the input data. Additionally, in some devices / arrangements, DS can be an optional signal. Furthermore, although in... Figure 1 The specific examples show 4 or 8 I / O lines, but in some implementations, any number of I / O lines can be supported (e.g., 1, 2, 4, 8, 16, etc.).

[0026] Serial flash memory devices typically include two types of read commands: one without addressing restrictions (e.g., EBhSPI commands); and another with double-word boundary alignment (DWA) addresses (e.g., E7h SPI commands). Due to the internal structure of the flash memory array, the read latency of DWA commands can be shorter than that of read commands without addressing restrictions. In certain implementations, alignment does not have to be set to 4 bytes or double words, but can be any suitable addressable data portion (e.g., 2 bytes, 4 bytes, 8 bytes, 16 bytes, etc.) based on the specific memory array configuration. Other parameters affecting CPU throughput and power consumption (such as the minimum required time between SPI commands or the “gap” between commands) can also depend on the type and length of each specific command.

[0027] Now for reference Figure 2 , Figure 2A schematic block diagram of an example memory controller system according to an embodiment of the present invention is shown. In example 200, a microcontroller unit (MCU) 202 may include a host device 102, a CPU 204, a cache unit 206, and a bus master 208. For example, the MCU 202 may be a system-on-a-chip (SoC), the cache unit 206 may include SRAM, and each bus master 208 may be any device or controller IP capable of controlling an SPI bus. An internal bus that may interface between the host 102, the cache unit 206, and the bus master 208 may include address, data, and control signaling. For example, the interface between the host 102 and the memory device 104 may be an SPI interface.

[0028] Specific implementations are typically applicable to systems operating in In-Place Execution (XiP) mode. In this system, the CPU (e.g., via optional buffer memory) and other bus masters can generate read requests for the SPI master 102, which can then translate these requests into SPI commands sent to the external flash memory device 104. Because these read operations can be used to handle instruction cache misses, CPU throughput and power consumption in such systems can be particularly sensitive to read latency from the flash memory device and the minimum permissible gap between two consecutive commands. Therefore, read commands with aligned addresses (e.g., DWA) can achieve improved system performance (e.g., improved CPU throughput) and reduced power consumption.

[0029] In many SoCs, the SPI master controller can be programmed to generate specific SPI commands in response to read requests from one of the bus masters 208. In most such systems, the commands used are EBh commands or similar commands without address alignment restrictions. This is due to a mixture of aligned and unaligned requests that can arrive in the host 102 from various SoC bus masters 208 and CPU 204 or associated cache units 206. Instruction cache misses are typically aligned with double-word boundaries and are therefore suitable for DWA read operations and / or commands that require minimal gaps between them. However, user software can inject unaligned reads into the flash memory command stream. Furthermore, the CPU may be unable to send different types of read commands to flash memory depending on the alignment of the requested address, or may not be able to perform other optimizations for the SPI commands used for each requested read operation. Additionally, an unaligned transaction to the flash memory device can also be generated as a Direct Memory Access (DMA) engine of the bus master 208.

[0030] Address alignment is a specific property of the E7h DWA command and is typically taken into account during execution of the command on a flash memory device. Along these lines, regardless of the address being transmitted within the command on the SPI bus, the flash memory device can clear the least significant bit (LSB) of the address (e.g., 2 LSBs) to ensure that the returned data is aligned by its address. Therefore, even if most read accesses to the flash memory device are inherently aligned, the system can be forced to use a less efficient read command (e.g., the EBh command) for all read accesses to accommodate those that are not aligned. In certain implementations, a new operating mode for the E7h DWA command can make it possible to use this command instead of the main read command in the system. Implementation of this operating mode may require only a small number of additional gates added to the flash memory device. Additionally, configuration bits (e.g., from the status register) can be included to ensure backward compatibility, such as by enabling the new functionality when the configuration bit is set (e.g., logic "1"). In some implementations, the new operating mode can be used with any specified read command (e.g., the EBh command) to act as an aligned read operation based on configuration bits (e.g., the ALN status bit in the status register).

[0031] Now for reference Figure 3 , Figure 3 A schematic block diagram of an example memory device according to an embodiment of the present invention is shown. Memory device 104 may include interface control and logic 318, which can manage the interface (e.g., an SPI interface) and decode commands and address information from it. Control and protection logic 302 may include control circuitry for reading and writing to the memory array, including address mapping and control for byte access and group addressing / sorting. For example, control and protection logic 302 may include a command decoder, registers for command execution parameters (e.g., read parameters, programming / erasing parameters, etc.), and a controller for command execution.

[0032] I / O buffer and latch 304 can control the input of data from and the output of data to interface control and logic 318. For example, chip-select-based control and clock-based control of data read from memory array 316 can be adapted via I / O buffer and latch 304. That is, the registers / latches in I / O buffer and latch 304 can be controlled by triggering the serial clock SCK during burst read and sequential fetch operations, as described herein. SRAM data buffer 314 can buffer / store data between memory array 316 and I / O buffer and latch 304. Address latch block 306 can receive address information via interface control and logic 318 and can provide latched addresses to X-decoder 308 for row addresses and Y-decoder 310 for column addresses. Address increment can be performed via address latch block 306 and / or control and protection logic 302. Y-decoder 310 can provide column addresses to Y-strobe 312, which may include pass gates, etc., to multiplex I / O lines to / from memory array 316. As discussed above, memory array 316 may include an array of volatile memory cells or non-volatile memory cells (e.g., CBRAM, ReRAM, flash memory, etc.).

[0033] In some arrangements, more than one buffer 314 (e.g., SRAM or other fast access memory) may be provided, such as a buffer for the input path and another buffer for the output path. Alternatively or additionally, multiple buffers may be provided for multi-level buffering. For example, memory device 104 may be configured as a data flash memory device and / or a serial flash memory device. Memory array 316 may be organized into any suitable number of data pages. For example, each page may include 256 or 264 bytes of data. Similarly, buffer 314 may store at least one data page. I / O interface 318 provides an interface connection between memory array 316, buffer 314, and serial data input (SI) and output (SO). For example, I / O interface 318 may be part of SPI or other serial type interfaces and may also support multiple SPI interface modes (e.g., single SPI, QPI, octal, x16 mode, etc.).

[0034] Now for reference Figure 4 , Figure 4 A schematic block diagram of an example memory device with read request modification control according to an embodiment of the present invention is shown. In example 400, memory device 104 may include memory array 316, data path 402 (e.g., Figure 3The system includes a buffer section 314 and I / O interface 318, a controller 404, an address latch 306, and a status register 406. In a particular example, backward compatibility can be supported within a modified DWA read command by using configuration bits from the status register 406. For example, if a DWA command or other specified read command (e.g., EBh) is encountered and the configuration bit is cleared (e.g., logic "0"), then NAND gate 408 and inverter 410 can ensure that the LSB from address latch 306 is cleared before accessing memory array 316. In this arrangement, if no DWA or other specified read command is encountered or if the configuration bit is set (e.g., logic "1"), then the strobe input to NAND gate 408 can be high to allow latched or decoded addresses received from the SPI bus to pass without modification for read access to memory array 316.

[0035] As used herein, an address is considered "modified" if the relationship between the original address and the modification of the address differs and results in accessing data from a different memory address location. For example, if an address is simply remapped or recoded while maintaining the same one-to-one relationship between the original address and the remapped / recoded address (e.g., in a transition from a virtual address to a physical address), this would be considered "no modification." Similarly, performing a NOT operation on individual address bits (e.g., address 0b0101000 becoming 0b1010111) would also be considered "no modification," while clearing the LSB or other predetermined address bits would be considered an address modification. In this way, when an address sent by the CPU is "modified," the address presented to the memory array is different from the original address.

[0036] Specific implementations can be adapted to any type of read operation, such as any SPI protocol mode (e.g., 1-xx, 4-xx, 8-xx, 0-xx, 0-4-4, etc.). In this notation, for example, the first, second, and third digital positions can represent the number of data lines for sending commands, addresses, and data, respectively. In 0-xx or 0-4-4 modes, the opcode can be implicitly included and therefore does not need to be explicitly sent with each SPI read transaction. Since the opcode is lost in the command, the interleaving of EBh and E7h commands that explicitly include the opcode in this case can become time-consuming and inefficient.

[0037] In this way, all XiP read requests can be designed to utilize appropriate read commands (e.g., DWA read command) or other modified read commands (e.g., EBh read command) that have a reduced number of dummy cycles compared to other standard read command options. As a result, read latency can be reduced to improve CPU throughput. This improves overall system performance because the CPU may have to wait less time to service instruction cache misses. It also effectively improves power consumption because the CPU can spend less time waiting for instruction cache misses to be serviced in a suboptimal state.

[0038] Now for reference Figure 5 , Figure 5 A timing diagram of an example read access according to an embodiment of the present invention is shown. Example 500 illustrates a high-performance SPI read command, which is a transaction in XiP mode (sometimes called continuous mode), where the read command is implicit and its format is 0-4-4. Each byte occupies two SCK cycles on four I / O lines. In cycles 0 and 1, the most significant address bytes A23-A16 can be received; in cycles 2 and 3, address bytes A15-A8 can be received; and in cycles 4 and 5, address bytes A7-A0 can be received. Therefore, six cycles can be used to receive the address via four pins. In cycles 6 and 7, mode bytes M7-M0 can be received. Therefore, two cycles can be used to receive the mode bytes via four pins to indicate that the device should remain in XiP mode. For this example read command, the dummy cycles can be cycles 8 to 11. Thus, in this example, four cycles are shown as dummy cycles before starting to output data from the flash memory at the falling edge of clock 11, and an additional 16 cycles can be used to output 8 bytes of buffered line data.

[0039] Now for reference Figure 6 , Figure 6A timing diagram of an example aligned address read access according to an embodiment of the present invention is shown. Example 600 illustrates a similar command in a more schematic manner and adds information regarding access to the internal NVM array (e.g., 316). Here, the requested address is 100h and occupies 6 CLK cycles, the mode byte occupies 2 cycles, and in this example, there are an additional 4 dummy cycles before the requested data is sent at the rising edge of clock 13. Example 600 also shows an internal NVM memory array read access relative to the read request command and the data output on the SPI bus. The first read access brings bytes 100 to 107h (64 bits in total) in 4 cycles, and the second read access also brings bytes 108 to 10Fh in 4 cycles. In this example, 8 bytes of data can be output via an octal (x8 I / O) or double data rate (DDR) four times (x4 I / O) configured SPI bus. In any case, it should be noted that the flash device waits until the data for the second read is almost available before starting to send the first read data on the SPI bus. This is done to ensure that even in unaligned address requests, NVM can support streaming data out in each clock cycle according to the SPI protocol specifications. It should also be noted that the internal NVM array is designed to read a fixed number of bits per access, thus typically equal to the number of sense amplifiers activated within the array for read operations. The example shown primarily features an array that reads 64 bits (8 bytes) per access to the memory array.

[0040] Now for reference Figure 7 , Figure 7 A timing diagram of an example unaligned address read access according to an embodiment of the present invention is shown. Example 700 illustrates what may happen when the requested address is not an aligned address. In this example, an SPI command requests byte 107h. Byte 107h comes from the first internal read in the sequence, but the subsequent byte 108h needs to be fetched from a second internal read. Because the NVM device, waiting for the second read to be almost complete, ensures that byte 108h can be issued immediately after byte 107h (as required by the SPI bus protocol), a "hiccup" is not allowed.

[0041] Now for reference Figure 8 , Figure 8A timing diagram of an example DWA read access according to an embodiment of the present invention is shown. Example 800 illustrates a DWA command (e.g., an E7h command) that requires address alignment (e.g., both LSBs must be 0). As a result, only the first read needs to be performed before output data begins to flow, because there may be no situation where data from a second read is needed prematurely. Therefore, the number of cycles that the host needs to wait for data (e.g., via dummy cycles) can be reduced. In this example, the number of dummy cycles can be reduced from 4 cycles to only 1 cycle.

[0042] Note that although the E7h command specification requires addresses to be aligned, NVM can ensure alignment by zeroing or clearing two LSBs of the address received from the interface, as discussed above. Figure 9 , Figure 10 and Figure 11 Double-word access, word access, and byte access are shown respectively. The address sent on the SPI bus is unaligned, but the data returned from the NVM is for an aligned address. The two LSBs are cleared due to the internal LSB clearing function.

[0043] Now for reference Figure 9 , Figure 9 A timing diagram of another example DWA read access according to an embodiment of the present invention is shown. In example 900, data is requested from address 105h. However, because two LSBs of the address are cleared, the data from address 104h is initially provided as part of a double word on addresses 104h-107h.

[0044] Now for reference Figure 10 , Figure 10 A timing diagram of an example DWA read access for word access according to an embodiment of the present invention is shown. In example 1000, word data addressed to 106h is requested. However, because the two LSBs of the address are cleared, word data from addresses 104h and 105h is incorrectly provided instead.

[0045] Now for reference Figure 11 , Figure 11 A timing diagram of an example DWA read access for byte access according to an embodiment of the present invention is shown. In example 1100, byte data addressed to 103h is requested. However, because the two LSBs of the address are cleared, byte data from address 100h is incorrectly provided instead.

[0046] In a particular implementation, a mode is added to DWA (E7h) and / or another specified read command (e.g., EBh) where the LSB of the address is not cleared by the flash memory device, and a single internal memory array read access is performed before data is sent back to the host device. Furthermore, this mode can be controlled by a configuration bit in a status register (e.g., 406). When the configuration bit is cleared (e.g., by default), E7h or other specified commands can behave in a way that supports backward compatibility and can therefore clear the LSB address bits 0 and 1 at the start of internal operations, such as... Figures 9 to 11 As shown. However, when the configuration bit is set (e.g., 1), as... Figure 12 and Figure 13 As shown, the device can use the address as is without modification, even if the address is unaligned.

[0047] Now for reference Figure 12 , Figure 12 A timing diagram of an example modified DWA read access for word access according to an embodiment of the present invention is shown. In Example 1200, word data addressed to 106h is requested for a read operation. Here, word data from addresses 106h and 107h is provided because the two LSBs of the address are not cleared and the complete address is allowed to pass without modification, wherein only one dummy cycle is included in the read latency.

[0048] Now for reference Figure 13 , Figure 13 A timing diagram of an example modified DWA read access for byte access according to an embodiment of the present invention is shown. In example 1300, byte data addressed to 103h is requested for a read operation. Here, because the two LSBs of the address are not cleared and the complete address is allowed to pass without modification, byte data from address 103h is provided, where only one dummy cycle is included in the read latency.

[0049] Now for reference Figure 14 , Figure 14 A timing diagram of an example modified DWA read access for double-word access according to an embodiment of the present invention is shown. In Example 1400, double-word data addressed to 107h is requested for a read operation. Here, because the two LSBs of the address are not cleared and the complete address is allowed to pass without modification, the first byte of the double-word data from address 107h is provided, with only one dummy cycle included in the read latency. However, in this particular case, the subsequent three bytes corresponding to addresses 108h, 109h, and 10Ah may result in incorrect data reads because the data corresponding to these addresses is not ready in time. Therefore, this represents a case of limited functionality of the modified DWA read command as discussed herein.

[0050] Now for reference Figure 15 , Figure 15 A flowchart illustrating an example method for controlling read requests according to an embodiment of the present invention is shown. In example 1500, at 1502, a DWA read request (or other specified read command) can be received from a host device (e.g., via an SPI interface) in the memory device. In some cases, the process can proceed to 1512, where the read request is executed on the memory device according to a modified DWA read command or other modified read command, thereby performing a single internal memory array read access before data is sent back to the host device and without clearing LSBs in the flash memory device. In other cases, backward compatibility can be supported via 1504. At 1506, a configuration bit can be read from a status register (e.g., 406). If the configuration bit is cleared (1508), the two LSBs of the address can be cleared at 1510 (e.g., set to "0") to maintain backward compatibility. Otherwise, if the configuration bit (1508) is set, a read request can be executed on the memory device at 1512 according to a modified read command (e.g., DWA read command, EBh command, etc.) without clearing the LSB or otherwise modifying the received address.

[0051] In certain implementations, this refers to a single aligned word read that occurs when the LSB of the address is equal to 0 (e.g., see [link]). Figure 12 ), single byte read (for example, see Figure 13 For any number of aligned double words (when both LSBs of the address are equal to 0), the correct operation of a modified read command (e.g., a DWA command) is found. In the first two cases above, a second array read may not be necessary, such as as long as the number of bits read in parallel from the array is 16 or a higher power of 2. Additionally, in the third case above, access to aligned double words inherently satisfies the condition of an unmodified DWA command, whereby both LSBs are equal to 0, and therefore can operate correctly even if the modified command does not clear these LSBs in the flash memory device.

[0052] In any case, modifications to DWA commands in certain implementations can effectively work with most SoCs. In such systems, there are typically three types of sources for read commands from the NVM: cache fill, data read, and DMA read operations. In most systems, cache fill operations can be performed using bursts of 16 bytes or longer, aligned to their natural address boundaries. Data read operations on most RISC CPUs target single data items (e.g., bytes, words, double words), and if the requested data is not address-aligned, it can be split into two accesses. For example, in the ARM architecture, a double-word read of address 103h can be split into two read accesses by the CPU so as not to cross the boundary between addresses 103h and 104h. In some cases, DMA accesses may require long bursts that could start at unaligned addresses and cross alignment boundaries. To overcome these limitations, DMA programming can be modified so that the starting address of the longer burst is aligned. In many systems, this requirement is feasible, and therefore the modified DWA read (E7h) command or the modified EBh command can be used instead of the standard read (EBh) command for read requests.

[0053] Even though the flash memory device will use a much faster array and therefore have fewer dummy cycles, if a conventional quadruple read command (EBh) takes X cycles, then an E7h command targeting only aligned addresses can take Y cycles, where Y is less than X. This is because the alignment instruction does not require a second array read before output data begins to flow from the memory device. Furthermore, this can be avoided by programming the host device to accommodate only aligned address read requests. Figure 14 The diagram illustrates possible error conditions for bad data. Additionally, DMA drivers ensure that double-word accesses are aligned in most cases, and the traditional EBh command can still be supported by the memory device for any flash read operation, making address alignment impractical.

[0054] Thus, by saving two or even three cycles of latency in each NVM read operation, system performance can be improved in terms of both speed and power consumption. For example, in a system where a large number of NVM accesses are used for instruction cache fill operations, a modified DWA command that brings in an 8-byte cache line might take 17 cycles, while a standard EBh command might take 20 cycles. Therefore, a program limited by cache line misses can run faster (e.g., about 18%). The power savings can depend on how much power the CPU might waste while waiting for those extra three cycles. In most systems, the pipeline can remain active (e.g., by processing previous instructions) even while waiting for instructions, so the CPU might continue to consume approximately the same amount of power as it would consume if it weren't waiting for data. If this is the case, the power savings could equal the performance improvement (e.g., 18%). However, if the CPU's pipeline completely drains before those three extra cycles while waiting for data, then the power consumed during those cycles can be reduced accordingly. In this case, the power savings will be smaller and could correspond to the power consumed when the pipeline is exhausted. For example, this can result in a performance improvement of about 18%, and a power improvement of about 5% to about 18%.

[0055] While the examples above include circuitry, operation, and structural implementations of certain memory arrangements and devices, those skilled in the art will recognize that other technologies and / or architectures, as well as other modes of operation, may be used depending on the implementation. Furthermore, those skilled in the art will recognize that other device circuitry arrangements, architectures, elements, etc., may also be used depending on the implementation. The above description of specific embodiments of the invention has been presented for illustrative and descriptive purposes. The description is not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations will be apparent from the above teachings. These embodiments were chosen and described to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention and its various embodiments with various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A method comprising the following steps: a) Receive a read request from a host device in the memory device, the host device being connected to the memory device via an interface; b) Decode the address of the read request received from the interface; c) Decode the command of the read request to determine whether the read request is for an aligned address operation; d) When the read request is determined to be an operation on the aligned address, the decoded address is kept unchanged regardless of the actual alignment of the decoded address; e) By using the decoded address, the read request is executed on the memory device according to the aligned address operation. f) Access the configuration bits on the memory device; as well as g) The hold step and the execution step are performed only when the configuration bit is in the first state and the read request is determined to be an operation for the aligned address.

2. The method according to claim 1, wherein, The address alignment operation is a double-word aligned DWA read operation.

3. The method according to claim 1, further comprising the following step: a) When the configuration bit is in the second state and the read request is performed on the aligned address, a predetermined number of least significant bits (LSBs) are removed from the decoded address to form a modified address; as well as b) When the configuration bit is in the second state, the read request is executed on the memory device according to the aligned address operation using the modified address.

4. The method according to claim 1, wherein, a) The memory device includes non-volatile memory; and b) The interface includes a serial interface.

5. The method according to claim 1, wherein, The step of decoding the command of the read request to determine whether the read request is for the aligned address operation includes: matching the opcode with a predetermined opcode.

6. The method according to claim 1, wherein, The read latency of the aligned address operation is less than the read latency of the operation without address restrictions.

7. The method according to claim 1, wherein, The alignment address operation is a single-byte read operation.

8. The method according to claim 1, wherein, The address alignment operation is a single-aligned word read operation.

9. The method according to claim 1, wherein, The host device is configured to ensure that the start address is aligned for direct memory access DMA operations that include the aligned address operation.

10. A memory device comprising a status register having configuration bits, the memory device being configured to: a) Receive read requests from the host device via the interface; b) Decode the address of the read request; c) Decode the command of the read request to determine whether the read request is for an aligned address operation; d) When the read request is determined to be an operation on the aligned address, the decoded address is preserved without modification, regardless of the actual alignment of the decoded address; and e) By using the decoded address, the read request is executed on the memory device according to the aligned address operation. Specifically, the decoded address is maintained and the read request is executed using the decoded address only when the configuration bit is in the first state and the read request is determined to be an operation on the aligned address.

11. The memory device according to claim 10, wherein, The address alignment operation is a double-word aligned DWA read operation.

12. The memory device according to claim 10, wherein, a) When the configuration bit is in the second state and the read request is performed on the aligned address, a predetermined number of least significant bits (LSBs) are removed from the decoded address to form a modified address; as well as b) When the configuration bit is in the second state, the read request is executed on the memory device according to the aligned address operation using the modified address.

13. The memory device of claim 10, wherein the memory device comprises non-volatile memory, and wherein, The interface includes a serial interface.

14. The memory device according to claim 10, wherein, The command of the read request is decoded to determine whether the read request is for the aligned address by matching the opcode with a predetermined opcode.

15. The memory device according to claim 10, wherein, The read latency of the aligned address operation is less than the read latency of the operation without address restrictions.

16. The memory device according to claim 10, wherein, The alignment address operation is a single-byte read operation.

17. The memory device according to claim 10, wherein, The address alignment operation is a single-aligned word read operation.

18. The memory device according to claim 10, wherein, The host device is configured to ensure that the start address is aligned for direct memory access DMA operations that include the aligned address operation.

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