Frequency of data integrity scans based on probability of data quality change

Abstract

The present disclosure relates to changing the scan frequency of a probabilistic data integrity scan based on data quality. Exemplary methods, apparatus, and systems include receiving a plurality of read operations. The read operations are divided into a current set of read operation sequences and one or more other sets. The size of the current set is a first number of read operations. An intruder read operation is selected from the current set. A data integrity scan is performed on a victim of the intruder, and a first data integrity indicator is determined based on the first data integrity scan. Based on the data integrity indicator, a size of a subsequent set of read operations is set to a second number, the second number being less than the first number.

Description

Technical Field

[0001] The present disclosure relates generally to mitigation of read disturb errors in memory subsystems, and more particularly to determining and using a dynamic data integrity scanning window for a probabilistic data integrity scanning scheme. Background Art

[0002] The memory subsystem may include one or more memory devices storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method comprising: receiving a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations being divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; selecting an intruder read operation from the current set; performing a data integrity scan on a victim of the intruder read operation; determining a data integrity indicator based on the data integrity scan; and setting the size of a subsequent set of read operations to a second number of read operations based on the data integrity indicator, the second number being different from the first number.

[0004] In another aspect, the present disclosure provides a non-transitory computer-readable storage medium comprising instructions, which, when executed by a processing device, cause the processing device to: receive a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations being divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; select an intruder read operation from the current set; perform a data integrity scan on a victim of the intruder read operation; determine a data integrity indicator based on the data integrity scan; and set the size of a subsequent set of read operations to a second number of read operations based on the data integrity indicator, the second number being different from the first number.

[0005] In another aspect, the present disclosure provides a system comprising: a plurality of memory devices; and a processing device operably coupled to the plurality of memory devices to: receive a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations being divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; select an intruder read operation from the current set; perform a data integrity scan on a victim of the intruder read operation; determine a data integrity indicator based on the data integrity scan, wherein the data integrity indicator is an error rate; and set the size of a subsequent set of read operations to a second number of read operations based on the data integrity indicator, the second number being different from the first number. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be understood as limiting the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example of managing a portion of a memory subsystem according to some embodiments of the present disclosure is described.

[0009] Figure 3 Flowchart of an example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure.

[0010] Figure 4 Flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure.

[0011] Figure 5 Flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure.

[0012] Figure 6 Flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure are directed to implementing a probabilistic data integrity scanning scheme in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The die in a package may be assigned to one or more channels for communication with a memory subsystem controller. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0016] Depending on the cell type, a cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states can be represented as binary values, such as "0" and "1", or a combination of such values. There are various types of cells, such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC can store one bit of information and have two logic states.

[0017] Data reliability in memory can decrease as the density of memory devices increases (e.g., as device components scale down in size, when more bits are programmed per cell, etc.). One contributing factor to this reduced reliability is read disturb. Read disturb occurs when a read operation performed on one portion of memory (e.g., a row of cells), often referred to as an aggressor, affects the threshold voltage in another portion of memory (e.g., an adjacent row of cells), often referred to as a victim. Memory devices typically have a limited tolerance for these disturbances. A sufficient amount of read disturb effects, such as a threshold number of read operations performed on adjacent aggressor cells, can change victim cells in other / unread portions of memory to a different logic state than originally programmed, which can result in errors.

[0018] The memory system can track read disturbances by using a counter for each memory sub-portion and reprogramming a given memory sub-portion when the counter reaches a threshold. The probabilistic data integrity scheme consumes less storage by counting or otherwise tracking a set of read operations in a memory portion (e.g., a die, a logic unit, etc.) and performing a limited data integrity scan by checking the error rate of one or more read disturbance victims of randomly selected read operations in each set (also referred to as a window). However, when the set or window size is set to a fixed value based on the worst case reliability of the memory, the data integrity scan frequency of the probabilistic data integrity scheme is higher than the frequency required for the memory portion whose reliability index is better than the worst case. For example, a probabilistic data integrity scan based on the worst case reliability of the memory may result in a decrease in bandwidth (compared to using a read disturbance counter) because not all memory portions are performing at the worst case reliability level, so the frequency of scanning the memory portion is higher than necessary.

[0019] Aspects of the present disclosure address the above and other deficiencies by dynamically selecting a scan frequency for each memory portion based on the reliability of the memory portion. A higher scan frequency is associated with a smaller probabilistic data integrity scan window size, while a lower scan frequency is associated with a larger probabilistic data integrity scan window size. For example, the window size can be selected based on the error rate or other reliability indicator of the memory portion. Thus, a probabilistic data integrity scheme can initiate a data integrity scan based on an actual measure of reliability, thereby reducing the scan frequency and increasing the bandwidth of memory portions with good reliability, while not sacrificing the reliability coverage of those memory portions that represent the worst case.

[0020] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, such as writing data to the memory subsystem 110 and reading data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where programming can be performed on non-volatile memory cells without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Although nonvolatile memory devices such as NAND-type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point nonvolatile memory cell arrays are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] The memory subsystem controller 115 (or controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130 (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0030] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0031] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem 110).

[0032] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit that communicates with the host system 120 via a physical host interface. The host interface circuit may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0033] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0034] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] The memory subsystem 110 includes a data integrity manager 113 that mitigates read disturbs and other data errors. In some embodiments, the controller 115 includes at least a portion of the data integrity manager 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the data integrity manager 113 is part of a host system 120, an application, or an operating system.

[0036] The data integrity manager 113 may implement and manage a read disturb mitigation scheme. For example, the data integrity manager 113 may implement a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme. Additional details regarding the operation of the data integrity manager 113 are described below.

[0037] Figure 2 An example of managing a portion of the memory subsystem 200 according to some embodiments of the present disclosure is illustrated. In one embodiment, the data integrity manager 113 implements a read disturb mitigation scheme for each memory component 210. For example, the data integrity manager 113 may implement a separate probabilistic read disturb mitigation scheme for each LUN.

[0038] The illustration of memory component 210 includes an array of memory cells. To provide a simple explanation, memory 210 shows a small number of memory cells. Embodiments of memory component 210 may include a much larger number of memory cells.

[0039] Each memory unit 210 includes memory cells that the memory subsystem 110 accesses via word lines 215 and bit lines 220. For example, the memory device 130 may read a memory page using word lines 230. Within the page, memory cell 225 is accessed via word lines 230 and bit lines 235. As described above, reading a memory cell may produce a read disturb effect on other memory cells. For example, a read of memory cell 225 (aggressor) may disturb memory cells 240 and 245 (victims). Similarly, a read of other memory cells of word line 230 (aggressors) may disturb other memory cells of word lines 250 and 255 (victims).

[0040] This disturbing effect may increase the error rate of the victim memory cells. In one embodiment, the data integrity manager 113 measures the error rate of the memory portion as a raw bit error rate (RBER). In another embodiment, the data integrity manager 113 may use other measurements to represent the error rate or data reliability, such as a voltage distribution value (e.g., a read threshold voltage distribution). In one embodiment, the data integrity manager 113 compares the current, recent, or average voltage distribution value with an ideal or expected voltage distribution value (e.g., a value generated by a new or unstressed memory), and the difference represents the error rate or other data reliability indication. The data integrity manager 113 may track and mitigate read disturb by tracking read operation traffic in the memory component 210 and checking the error rate of the victim. For example, the data integrity manager 113 may select a read operation for word line 230 as an aggressor for testing read disturb, and perform a read of word lines 250 and 255 to determine the error rate of each word line. In response to detecting that the error rate of a given victim of the memory meets the threshold error rate value, the data integrity manager 113 may migrate data from the victim portion of the memory to a different portion of the memory.

[0041] In one embodiment, the data integrity manager 113 also maintains one or more indicators of data integrity (e.g., RBER or other data reliability values) for performing data integrity scans. For example, the data integrity manager 113 may compare the RBER value of the current data integrity scan to one or more saved maximum RBER values ​​and replace the saved values ​​when the RBER value of the current data integrity scan exceeds the saved values. The data integrity manager 113 uses the saved representative data reliability values ​​to dynamically update the window size of the probabilistic read disturb handling scheme. Reference Figure 3-5 This and other features of the probabilistic read disturb handling scheme are further described.

[0042] Figure 3 Flowchart of an example method 300 for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1The data integrity manager 113 of FIG. 10 is executed. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0043] At operation 305, the processing device initializes or resets a counter for tracking the processing of read operations. For example, the processing device may set the counter to zero to begin tracking the processing of read operations in a set of read operations. In one embodiment, the processing device processes operations in a set of read operation sequences. For example, if a set contains 10,000 read operations, the counter is initialized or reset to a state that allows it to count at least 10,000 read operations. However, the number of operations per set is a dynamic value and is referred to herein as N.

[0044] At operation 310, the processing device receives a read operation request. The read request may be received from one or more host systems and / or generated by another process within the memory subsystem 110. The processing device may receive the read operation request asynchronously, continuously, in batches, etc. In one embodiment, the memory subsystem 110 receives the operation request from one or more host systems 120 and stores the request in a command queue. The processing device may process the read operation from the command queue and / or generated internally in a set of N operations.

[0045] At operation 315, the processing device selects an intruder operation in the current set of operations. When implementing a probabilistic read disturb handling scheme, the processing device may select an intruder in the current set by generating a random number (e.g., a uniform random number) in the range of 1 to N, and identifying the current / last read operation as an intruder when the count of read operations reaches the random number in the current set.

[0046] At operation 320, the processing device performs a read operation. For example, the memory subsystem 110 reads a page of data by accessing memory cells along a word line and returning data to the host system 120 or initiating an internal process of a read request. In addition, the processing device increments a read operation counter. For example, the processing device may increment a counter in response to completing a read operation to track the current position in the sequence of read operations in the current set.

[0047] At operation 325, the processing device determines whether the read operation counter has reached an intruder operation in the set. For example, the processing device may compare the value of the counter with the generated first random number to identify the intruder read operation in the current set. If the counter has not reached a position in the sequence corresponding to the intruder operation, the method 300 returns to operation 320 to continue to perform the next read operation, as described above. If the counter has reached a position in the sequence corresponding to the intruder operation, the method 300 proceeds to operation 330.

[0048] At operation 330, the processing device performs an integrity scan of the selected intruder's victims. For example, the processing device may perform a read of each victim to determine a data integrity indicator for the victim. In one embodiment, this includes checking an error rate of the victim, such as a raw bit error rate (RBER). In another embodiment, determining the data integrity indicator for the victim includes comparing a threshold voltage distribution of the victim / sampled memory portion to an expected voltage distribution. If the error rate of the victim memory location satisfies a folding threshold (e.g., meets or exceeds an error rate threshold), the processing device folds the data at the victim memory location by, for example, error correcting the data and writing the corrected data to a new location.

[0049] At operation 335, the processing device determines whether the data integrity indicator of the victim is greater than one or more current maximum worst values. For example, the processing device may maintain the highest maximum error rate value and the second highest maximum error rate value for the data integrity indicator of the memory portion. However, for another indicator of data integrity, the worst value may not be the maximum value. For example, when using the threshold voltage distribution as an indicator of data reliability, the processing device may compare the "shape" of the measured distribution value / histogram with the ideal value by determining whether the shape is monotonically increasing / decreasing, comparing local minima, comparing the width of the histogram, determining the offset (left / right) of the histogram, etc. As another example, the processing device may compare the "overall" of the threshold voltage distribution / histogram or its portion (e.g., between certain read positions). The nearest histogram overall that satisfies the threshold increase between read positions compared to the ideal overall can be used as an indication of data reliability (or lack of reliability). As another example, the processing device may evaluate the tolerance compared to the threshold error correction limit, and the lower the tolerance measured, the worse the data reliability. For ease of describing the following examples, it should be understood that maximum value may be used interchangeably with worst value.

[0050] If the victim's data integrity indicator is greater than one or more current worst values, then the method 300 proceeds to operation 340. If the victim's data integrity indicator is not greater than the current worst value, then the method 300 proceeds to operation 345.

[0051] The processing device may maintain one or more worst values ​​for each memory sub-portion (e.g., each die / LUN, plane, individual word line segment, word line group, LUN group, block or block group, etc.). In one embodiment, the processing device determines an average or other combination of indicators to reflect the worst value for the memory sub-portion. For example, the processing device may determine a data integrity indicator for each memory block in the LUN and average or combine the data integrity indicators into an indicator for the entire LUN. In one embodiment, based on the granularity of use, the processing device maintains a worst value for each unique sub-portion of the portion of memory. For example, if a worst value is maintained per LUN, then the processing device may maintain a worst value for each memory block, and the same block cannot provide both a worst value and a second difference value.

[0052] At operation 340, the processing device updates one or more worst / maximum values ​​to reflect the new worst / maximum values. For example, when the data integrity indicator of the victim is greater than the current highest maximum value, the processing device downgrades the current highest maximum value to the new second-highest maximum value and sets the data integrity indicator of the victim to the new current highest maximum value. When the data integrity indicator of the victim is greater than the second-highest maximum value (but not the highest maximum value), the processing device sets the data integrity indicator of the victim to the new second-highest maximum value (e.g., replacing the previous value). When the existing worst / maximum value is for the same memory block / sub-portion as the victim, the processing device replaces the worst / maximum value with the data integrity indicator of the victim and, if applicable, may reorder the worst and second difference values.

[0053] At operation 345, the processing device determines whether the current worst / maximum value meets one or more thresholds. For example, the processing device may divide the range of data integrity values ​​into sub-ranges by one or more thresholds, and each sub-range may be associated with a different data integrity scan window size. The processing device determines whether the current maximum value falls within a sub-range by whether the current maximum value exceeds, is equal to, or is lower than a given threshold. The range of data integrity values ​​may, for example, span from a zero error rate to a collapse threshold.

[0054] As a simple example, the range of data integrity values ​​may be divided into two sub-ranges: a low range corresponding to a large data integrity scan window size and a high range corresponding to a small data integrity scan window size. The low range may be defined as error rate values ​​included between zero and a dynamic window threshold, and the high range may be defined as error rate values ​​included between the dynamic window threshold and a collapse threshold.

[0055] In one embodiment, a single dynamic window threshold may divide the sub-ranges, and a current maximum value less than this threshold belongs to a low range, and a current maximum value greater than this threshold belongs to a high range. In another embodiment, two dynamic window thresholds may divide the sub-ranges, and the threshold used may depend on the current sub-range based on the previous maximum value. For example, when the previous maximum value belongs to the low range, a large threshold may be used to trigger a movement from the low range to the high range, while a small threshold may be used to trigger a movement from the high range to the low range. Therefore, different thresholds may more appropriately trigger changes in the size of the data integrity scan window.

[0056] In one embodiment, the processing device implements a dynamic window size that allows the window size to shrink quickly but grow slowly. For example, the processing device may insert a delay (time, number of sets, etc.) before using an updated window size that is smaller than the current window size. This delay may allow subsequent sets to change the worst / maximum values ​​and possibly eliminate the reduction in window size. Thus, the processing device may avoid dramatic fluctuations in window size. In one embodiment, the amount of delay inserted is a function of: (1) the number of program / erase (P / E) cycles performed on the memory or memory portion and / or (2) the block type (SLC, MLC, TLC, etc.). For example, the greater the number of P / E cycles or the greater the density of the blocks, the greater the delay selected by the processing device.

[0057] If the current maximum value satisfies one or more dynamic window thresholds (e.g., will cause the processing device to trigger a change in the size of the data integrity scan window based on the current range of data integrity values), then the method 300 proceeds to operation 350. If the current maximum value does not satisfy one or more thresholds (e.g., the previous range of data integrity values ​​has not changed), then the method proceeds to operation 355.

[0058] At operation 350, the processing device updates the set size for the next set of operations. For example, in response to the current maximum value satisfying a threshold and therefore belonging to a new range of data integrity values, the processing device changes the data integrity scan window size by updating the operand N for each set, starting with the next set, or if delayed, starting with another subsequent set. The current set continues to use the current value of N, and the processing device stores an updated value of N (or increment) to be applied to the next set. Thus, the processing device may reduce the window size to scan more victims when the maximum value of the data integrity indicator increases, and increase the window size to scan fewer victims when the maximum value of the data integrity indicator decreases. In the case where the dynamic window size change is bidirectional, an embodiment may set the initial value of N (e.g., after a power cycle) to a small window size or to a large window size, and allow subsequent sets to dynamically adjust the window size as needed. In one embodiment, the processing device stores the current value of N in a non-volatile memory, and the value of N is used after the power cycle.

[0059] At operation 355, the processing device determines whether the read operation counter has reached the end of the current set. For example, the processing device may compare the value of the counter with the value of N for the current set. If the read operation counter has reached the end of the current set, the method 300 proceeds to operation 305 to reset the counter (e.g., to the value of N for the next set) and process the next read operation set. If the read operation counter has not reached the end of the current set, the method 300 proceeds to operation 360.

[0060] At operation 360, the processing device performs a read operation and increments the read operation counter as described above with reference to operation 325. The method 300 proceeds to operation 355 to again determine whether the read operation counter has reached the end of the current set.

[0061] In one embodiment, the processing device disables the dynamic feature of the data integrity scan window in response to a threshold of a data integrity indicator maximum value being met, a threshold of a data integrity indicator maximum value being met a threshold number of times, a threshold number of program / erase cycles being met, etc. Thus, the processing device bypasses operations 335-350 in a subsequent set.

[0062] Figure 4 4 is a flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The data integrity manager 113 of FIG. 10 is executed. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0063] At operation 405, the processing device receives a fold operation. For example, the processing device may receive a request or operation to copy data to a new location in response to determining that the data integrity indicator satisfies a fold threshold or another internal garbage collection process.

[0064] At operation 410, the processing device determines whether the memory location undergoing the folding operation maps to the current worst / maximum value of the data integrity indicator. For example, in addition to saving the maximum value as described above, the processing device may also save a mapping between the maximum value and the address or other identification of the memory location that has been scanned for data integrity, which determined the maximum value of the data integrity indicator. If the memory location undergoing the folding operation maps to the current maximum value of the data integrity indicator, then the method 400 proceeds to operation 415. If the memory location undergoing the folding operation does not map to the current maximum value of the data integrity indicator, then the method 400 proceeds to operation 420.

[0065] At operation 415, the processing device updates the worst / maximum value in response to the folding operation. For example, if the folding operation maps to the highest maximum value, the processing device will overwrite the highest maximum value with the second worst / second highest maximum value (promoting the second highest value). In one embodiment, the processing device deletes the second highest value, marks it as needing to be updated, or otherwise notes the promotion. As another example, if the folding operation maps to the second highest maximum value, the processing device deletes the second highest value, marks it as needing to be updated, or otherwise notes that the second highest value is no longer valid. In either scenario, the processing device can use a subsequent data integrity scan to add the second maximum value again, as described above. Although the examples described above involve two worst / maximum values, embodiments can maintain and use more than two worst / maximum values.

[0066] At operation 420, the processing device performs a folding operation. For example, the processing device reads data from a source location and writes the data to a target location. This folding operation can be used to reduce the possibility of errors when reading data in the future, free up writable units of memory, etc.

[0067] Figure 5 Flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1 The data integrity manager 113 of FIG. 10 is executed. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] At operation 505, the processing device initializes or resets a counter for tracking the processing of read operations. For example, the processing device may set the counter to zero to begin tracking the processing of read operations in a set of read operations. In one embodiment, the processing device processes operations in a set of read operation sequences. For example, if a set contains 10,000 read operations, the counter is initialized or reset to a state that allows it to count at least 10,000 read operations. However, the number of operations per set is a dynamic value and is referred to herein as N.

[0069] At operation 510, the processing device receives a read operation request. The read request may be received from one or more host systems and / or generated by another process within the memory subsystem 110. The processing device may receive the read operation request asynchronously, continuously, in batches, etc. In one embodiment, the memory subsystem 110 receives the operation request from one or more host systems 120 and stores the request in a command queue. The processing device may process the read operation from the command queue and / or generated internally in a set of N operations.

[0070] At operation 515, the processing device selects an intruder operation in the current set of operations. When implementing a probabilistic read disturb handling scheme, the processing device may select an intruder in the current set by generating a random number (e.g., a uniform random number) in the range of 1 to N, and identifying the current / last read operation as an intruder when the count of read operations reaches the random number in the current set.

[0071] At operation 520, the processing device performs a read operation. For example, the memory subsystem 110 reads a page of data by accessing memory cells along a word line and returning data to the host system 120 or initiating an internal process of a read request. In addition, the processing device increments a read operation counter. For example, the processing device may increment a counter in response to completing a read operation to track the current position in the sequence of read operations in the current set.

[0072] At operation 525, the processing device determines whether the read operation counter has reached an intruder operation in the set. For example, the processing device may compare the value of the counter with the generated first random number to identify the intruder read operation in the current set. If the counter has not reached a position in the sequence corresponding to the intruder operation, the method 500 returns to operation 520 to continue to perform the next read operation, as described above. If the counter has reached a position in the sequence corresponding to the intruder operation, the method 500 proceeds to operation 530.

[0073] At operation 530, the processing device performs an integrity scan of the victims of the selected intruder. For example, the processing device may perform a read of each victim to determine the data integrity indicator of the victim. In one embodiment, this includes checking the error rate of the victim, such as the raw bit error rate (RBER). In another embodiment, determining the data integrity indicator of the victim includes comparing the threshold voltage distribution of the victim / sampled memory portion with the expected voltage distribution. When using the threshold voltage distribution as an indicator of data reliability, the processing device may compare the "shape" of the measured distribution value / histogram with the ideal value by determining whether the shape is monotonically increasing / decreasing, comparing local minima, comparing the width of the histogram, determining the offset (left / right) of the histogram, etc. As another example, the processing device may compare the "population" of the threshold voltage distribution / histogram or its portion (e.g., between certain read positions). The nearest histogram population that satisfies the threshold increase between read positions compared to the ideal population can be used as an indication of data reliability (or lack of reliability). As another example, the processing device may evaluate the tolerance compared to the threshold error correction limit, the lower the measured tolerance, the worse the data reliability. For ease of describing the following examples, it should be understood that maximum value may be used interchangeably with worst value.

[0074] If the error rate of the victim memory location satisfies the folding threshold (eg, meets or exceeds the error rate threshold), the processing device folds the data at the victim memory location by, for example, error correcting the data and writing the corrected data to a new location.

[0075] The processing device may maintain one or more data integrity values ​​for each memory subdivision (e.g., each die / LUN, plane, individual word line segment, word line group, LUN group, block or block group, etc.). In one embodiment, the processing device determines an average or other combination of indicators to reflect the data integrity value of the memory subdivision. For example, the processing device may determine a data integrity indicator for each memory block in a LUN and average or combine the data integrity indicators into an indicator for the entire LUN.

[0076] At operation 535, the processing device determines whether the data integrity indicator of the victim satisfies the hysteresis range. For example, the processing device may use a range of data integrity values ​​for the memory portion, and a data integrity indicator within the range may trigger an update to the data integrity scan frequency. Continuing this example using error rates, error rates below the minimum value of the hysteresis range will not trigger a change in the window size / scan frequency. Additionally, error rates above the maximum value of the hysteresis range may trigger a collapse of the data of the scanned memory portion, as described above, rather than an update to the window size / scan frequency.

[0077] If the victim's data integrity indicator meets / is within the hysteresis range, then method 500 proceeds to operation 540. If the victim's data integrity indicator does not meet / is not within the hysteresis range, then method 500 proceeds to operation 550. In another embodiment, the processing device bypasses operation 535 and proceeds to operation 540.

[0078] At operation 540, the processing device determines a current scaling factor using the data integrity indicator. The processing device may also determine the current scaling factor using the data integrity indicator and a number of program / erase cycles (PEC) of the memory portion. In one embodiment, the processing device uses a weighted formula with the data integrity indicator and the PEC as inputs. For example, a current scaling factor (CSF) may be determined using a formula based on a weighted exponential curve, such as:

[0079]

[0080] W1 and W2 represent different weight values. In one embodiment, W1 and W2 are fixed values. In another embodiment, W1 and W2 are dynamic values ​​based on the ratio of the range of PEC values ​​(between the maximum PEC value and the minimum PEC value) and the default window size corresponding to the range. For example, the following formula can be used to derive the weights:

[0081] W1 = (PEC Max - PEC Min) / (10 × default window size)

[0082] W2 = (PEC Max - PEC Min) / (default window size).

[0083] Reads to the memory subsystem may be distributed by workload. Thus, several blocks / pages in a LUN may have a higher number of reads than other blocks / pages. Thus, error rates (or other indicators of data integrity) may vary significantly, even within a single LUN. Additionally, particular word lines or other memory portions may be more susceptible to data integrity issues than other portions. Folding of blocks or other memory portions may result in significantly reduced error rates (or other indicators of data integrity) for memory portions. In view of these factors, there may be significant differences / variations in the indications of data integrity depending on the selected intruder and the corresponding victim. An embodiment may use a hysteresis scheme to avoid dramatic fluctuations in window size. In one embodiment, a processing device modifies a current scaling factor based on a historical scaling factor (HSF). For example, a processing device may use a recently adapted scaling factor for a window size (as an HSF) as well as a current scaling factor. For example, the following formula may be used to modify the CSF:

[0084] Modified CSF = (W3 x HSF) + (W4 x CSF).

[0085] W3 and W4 represent different weight values. In one embodiment, W3 is greater than W4 (to bias the historical scale factor and reduce the change of the current scale factor), and W3+W4=1. In one embodiment, W3 and W4 are fixed values. In another embodiment, W3 and W4 are dynamic values ​​based on the data integrity indicator. For example, as the data integrity indicator approaches the collapse threshold, W3 will increase and w4 will decrease.

[0086] At operation 545, the processing device updates the set size for the next set of operations. For example, the processing device changes the data integrity scan window size by updating the number of operations N for each set, starting from the next set, or if delayed, from another subsequent set. In one embodiment, the processing device determines the updated value of N by multiplying the CSF (or modified CSF) by the current value of N. The current set continues to use the current value of N, and the processing device stores the updated value of N (or CSF) to be applied to the next set. Therefore, the processing device can reduce the window size to scan more victims when the value of the data integrity indicator increases, and increase the window size to scan fewer victims when the value of the data integrity indicator decreases. In the case where the dynamic window size change is bidirectional, an embodiment can set the initial or default value of N (e.g., after a power cycle) to a small window size or to a large window size, and allow subsequent sets to dynamically adjust the window size as needed. In one embodiment, the default value of N is set based on characterization data of the memory portion (e.g., determined at the time of manufacture or as a result of post-manufacturing testing), the workload type of the memory portion, and / or the number of PECs. In one embodiment, the processing device stores the current value of N in non-volatile memory, and the value of N is used after a power cycle.

[0087] At operation 550, the processing device determines whether the read operation counter has reached the end of the current set. For example, the processing device may compare the value of the counter with the value of N for the current set. If the read operation counter has reached the end of the current set, the method 500 proceeds to operation 505 to reset the counter (e.g., to the value of N for the next set) and process the next read operation set. If the read operation counter has not reached the end of the current set, the method 500 proceeds to operation 560.

[0088] At operation 555, the processing device performs a read operation and increments the read operation counter, as described above with reference to operation 525. The method 500 proceeds to operation 550 to again determine whether the read operation counter has reached the end of the current set.

[0089] Figure 66 is a flowchart of another example method for implementing a dynamic data integrity scanning frequency of a probabilistic data integrity scanning scheme according to some embodiments of the present disclosure. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1 The data integrity manager 113 of FIG. 10 is executed. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0090] At operation 605, the processing device receives a read operation, for example, as described with reference to operation 310 or 510. The processing device divides the read operation into sets of read operations. For example, the processing device may use a counter to track the number of operations N to be executed for each set.

[0091] At operation 610, the processing device selects an intruder read operation in the current set of operations, for example, as described with reference to operations 315 or 515. The processing device may randomly select read operations in the current set to identify one or more victims as subjects for a data integrity scan.

[0092] At operation 615 , the processing device performs a data integrity scan of the victim memory locations. For example, the processing device may perform a read of the victims to check the error rate of each victim, as described above with respect to operation 330 or 530 .

[0093] At operation 620 , a data integrity indicator is determined based on the scan. For example, the processing device determines the RBER or threshold voltage distribution of the victim / sampled memory portion, as described above with respect to operation 330 or 530 .

[0094] At operation 625 , the processing device sets the size of the subsequent set of read operations to a second / different number of read operations based on the data integrity indicator. For example, the processing device may update the set size N of one or more subsequent sets, as described above with respect to operations 350 or 545 .

[0095] While the above examples focus on dynamically selecting a data integrity scan frequency based on a worst data integrity value, other embodiments may dynamically adjust the scan frequency based on a P / E cycle count or similar data reliability indicator. For example, the processing device may compare the current P / E cycle count of a memory portion / sub-portion to one or more thresholds and update the scan frequency for different ranges of P / E cycles.

[0096] Figure 7 An example machine of a computer system 700 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0097] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute an instruction set (or multiple instruction sets) to perform any one or more of the methodologies discussed herein.

[0098] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0099] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 that communicates through a network 720.

[0100] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0101] In one embodiment, instructions 726 include implementing instructions corresponding to a data integrity manager (e.g., Figure 1 The machine-readable storage medium 724 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0102] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are ways for those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. Operations are operations that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. At times, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0103] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0104] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for a given purpose, or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) may perform computer-implemented methods 300-600 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0105] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for these various systems will be presented as shown in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0106] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0107] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: receiving a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; selecting a first intruder read operation from the current set; performing a data integrity scan on a victim of the first intruder's read operation; determining a first data integrity indicator based on the data integrity scan; as well as A subsequent set of read operations is sized to a second number of read operations based on the first data integrity indicator, the second number being different than the first number.

2. The method according to claim 1, further comprising: In response to determining that the first data integrity indicator is greater than a current maximum value of data integrity indicators for a memory subportion, setting the current maximum value to the first data integrity indicator, wherein in response to determining that the current maximum value satisfies a first threshold, setting the size of the subsequent set of read operations to the second number.

3. The method according to claim 2, further comprising: selecting a second intruder read operation from the subsequent set; performing a second data integrity scan on victims of the second intruder read operation from the subsequent set; determining a second data integrity indicator based on the second data integrity scan; as well as In response to determining that the second data integrity indicator is greater than a second maximum value of data integrity indicators for a memory subportion, the second maximum value is set as the second data integrity indicator.

4. The method according to claim 3, further comprising: responsive to collapsing the victim of the first intruder read operation, setting the current maximum value to the second maximum value; as well as In response to determining that the current maximum value no longer satisfies the first threshold, a size of a subsequent set of read operations is set to the first number of read operations.

5. The method according to claim 1, further comprising: A scaling factor is determined using the first data integrity indicator and a number of program-erase cycles for the memory portion, wherein the size of the subsequent set of read operations is set to the second number using the scaling factor. The method of claim 5 , wherein determining the scaling factor is performed in response to determining that the first data integrity indicator is within a hysteresis range.

7. The method according to claim 5, wherein determining the scaling factor comprises: A sum of first and second product values ​​is determined, the first product value being generated by multiplying the historical scale factor value by the first weight, and the second product value being generated by multiplying the current scale factor by the second weight.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; selecting a first intruder read operation from the current set; performing a data integrity scan on a victim of the first intruder's read operation; determining a first data integrity indicator based on the data integrity scan; as well as A subsequent set of read operations is sized to a second number of read operations based on the first data integrity indicator, the second number being different than the first number.

9. The non-transitory computer-readable storage medium of claim 8, wherein the processing device further performs the following operations: In response to determining that the first data integrity indicator is greater than a current maximum value of data integrity indicators for a memory subportion, setting the current maximum value to the first data integrity indicator, wherein in response to determining that the current maximum value satisfies a first threshold, setting the size of the subsequent set of read operations to the second number.

10. The non-transitory computer-readable storage medium of claim 9, wherein the processing device further performs the following operations: selecting a second intruder read operation from the subsequent set; performing a second data integrity scan on victims of the second intruder read operation from the subsequent set; determining a second data integrity indicator based on the second data integrity scan; as well as In response to determining that the second data integrity indicator is greater than a second maximum value of data integrity indicators for a memory subportion, the second maximum value is set as the second data integrity indicator.

11. The non-transitory computer-readable storage medium of claim 10, wherein the processing device further performs the following operations: In response to collapsing the victim of the first aggressor read operation, setting the current maximum value to the second maximum value; and In response to determining that the current maximum value no longer satisfies the first threshold, a size of a subsequent set of read operations is set to the first number of read operations.

12. The non-transitory computer-readable storage medium of claim 8, wherein the processing device further performs the following operations: A scaling factor is determined using the first data integrity indicator and a number of program-erase cycles for the memory portion, wherein the size of the subsequent set of read operations is set to the second number using the scaling factor.

13. The non-transitory computer-readable storage medium of claim 12, wherein determining the scaling factor is performed in response to determining that the first data integrity indicator is within a hysteresis range.

14. The non-transitory computer-readable storage medium of claim 12, the determining the scaling factor comprising: A sum of first and second product values ​​is determined, the first product value being generated by multiplying the historical scale factor value by the first weight, and the second product value being generated by multiplying the current scale factor by the second weight.

15. A system comprising: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices to: receiving a plurality of read operations for a portion of a memory accessed by a memory channel, the plurality of read operations divided into a current set of read operation sequences and one or more other sets of read operation sequences, the current set being sized to a first number of read operations; selecting a first intruder read operation from the current set; performing a data integrity scan on a victim of the first intruder's read operation; determining a first data integrity indicator based on the data integrity scan, wherein the first data integrity indicator is an error rate; as well as A subsequent set of read operations is sized to a second number of read operations based on the first data integrity indicator, the second number being different than the first number.

16. The system of claim 15, wherein the processing device further performs the following operations: In response to determining that the first data integrity indicator is greater than a current maximum value of data integrity indicators for a memory subportion, setting the current maximum value to the first data integrity indicator, wherein in response to determining that the current maximum value satisfies a first threshold, setting the size of the subsequent set of read operations to the second number.

17. The system of claim 16, wherein the processing device further performs the following operations: selecting a second intruder read operation from the subsequent set; performing a second data integrity scan on victims of the second intruder read operation from the subsequent set; determining a second data integrity indicator based on the second data integrity scan; as well as In response to determining that the second data integrity indicator is greater than a second maximum value of data integrity indicators for a memory subportion, the second maximum value is set as the second data integrity indicator.

18. The system of claim 17, wherein the processing device further performs the following operations: In response to collapsing the victim of the first aggressor read operation, setting the current maximum value to the second maximum value; and In response to determining that the current maximum value no longer satisfies the first threshold, a size of a subsequent set of read operations is set to the first number of read operations.

19. The system of claim 15, wherein the processing device further performs the following operations: A scaling factor is determined using the first data integrity indicator and a number of program-erase cycles for the memory portion, wherein the size of the subsequent set of read operations is set to the second number using the scaling factor.

20. The system of claim 19, wherein determining the scaling factor is performed in response to determining that the first data integrity indicator is within a hysteresis range.

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